1 #include "qcom-ipq8064-v1.0.dtsi"
4 model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
5 compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
8 reg = <0x42000000 0x1e000000>;
9 device_type = "memory";
17 reg = <0x41200000 0x300000>;
32 qcom,mode = <GSBI_PROT_I2C_UART>;
40 * The i2c device on gsbi4 should not be enabled.
41 * On ipq806x designs gsbi4 i2c is meant for exclusive
42 * RPM usage. Turning this on in kernel manifests as
43 * i2c failure for the RPM.
48 qcom,mode = <GSBI_PROT_SPI>;
53 spi-max-frequency = <50000000>;
55 pinctrl-0 = <&spi_pins>;
56 pinctrl-names = "default";
58 cs-gpios = <&qcom_pinmux 20 0>;
61 compatible = "s25fl256s1";
64 spi-max-frequency = <50000000>;
68 compatible = "qcom,smem";
94 pinctrl-0 = <&nand_pins>;
95 pinctrl-names = "default";
99 compatible = "qcom,nandcs";
101 nand-ecc-strength = <4>;
102 nand-bus-width = <8>;
103 nand-ecc-step-size = <512>;
106 compatible = "qcom,smem";
114 pinctrl-0 = <&mdio0_pins>;
115 pinctrl-names = "default";
117 phy0: ethernet-phy@0 {
119 qca,ar8327-initvals = <
120 0x00004 0x7600000 /* PAD0_MODE */
121 0x00008 0x1000000 /* PAD5_MODE */
122 0x0000c 0x80 /* PAD6_MODE */
123 0x000e4 0x6a545 /* MAC_POWER_SEL */
124 0x000e0 0xc74164de /* SGMII_CTRL */
125 0x0007c 0x4e /* PORT0_STATUS */
126 0x00094 0x4e /* PORT6_STATUS */
130 phy4: ethernet-phy@4 {
140 pinctrl-0 = <&rgmii2_pins>;
141 pinctrl-names = "default";