target/linux/ipq806x/patches-4.4/115-add-pcie-aux-clk-dts.patch

   1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
   2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
   3 @@ -475,15 +475,21 @@
   4
   5                         clocks = <&gcc PCIE_A_CLK>,
   6                                  <&gcc PCIE_H_CLK>,
   7 -                                <&gcc PCIE_PHY_CLK>;
   8 -                       clock-names = "core", "iface", "phy";
   9 +                                <&gcc PCIE_PHY_CLK>,
  10 +                                <&gcc PCIE_AUX_CLK>,
  11 +                                <&gcc PCIE_ALT_REF_CLK>;
  12 +                       clock-names = "core", "iface", "phy", "aux", "ref";
  13 +
  14 +                       assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
  15 +                       assigned-clock-rates = <100000000>;
  16
  17                         resets = <&gcc PCIE_ACLK_RESET>,
  18                                  <&gcc PCIE_HCLK_RESET>,
  19                                  <&gcc PCIE_POR_RESET>,
  20                                  <&gcc PCIE_PCI_RESET>,
  21 -                                <&gcc PCIE_PHY_RESET>;
  22 -                       reset-names = "axi", "ahb", "por", "pci", "phy";
  23 +                                <&gcc PCIE_PHY_RESET>,
  24 +                                <&gcc PCIE_EXT_RESET>;
  25 +                       reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  26
  27                         pinctrl-0 = <&pcie0_pins>;
  28                         pinctrl-names = "default";
  29 @@ -521,15 +527,21 @@
  30
  31                         clocks = <&gcc PCIE_1_A_CLK>,
  32                                  <&gcc PCIE_1_H_CLK>,
  33 -                                <&gcc PCIE_1_PHY_CLK>;
  34 -                       clock-names = "core", "iface", "phy";
  35 +                                <&gcc PCIE_1_PHY_CLK>,
  36 +                                <&gcc PCIE_1_AUX_CLK>,
  37 +                                <&gcc PCIE_1_ALT_REF_CLK>;
  38 +                       clock-names = "core", "iface", "phy", "aux", "ref";
  39 +
  40 +                       assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
  41 +                       assigned-clock-rates = <100000000>;
  42
  43                         resets = <&gcc PCIE_1_ACLK_RESET>,
  44                                  <&gcc PCIE_1_HCLK_RESET>,
  45                                  <&gcc PCIE_1_POR_RESET>,
  46                                  <&gcc PCIE_1_PCI_RESET>,
  47 -                                <&gcc PCIE_1_PHY_RESET>;
  48 -                       reset-names = "axi", "ahb", "por", "pci", "phy";
  49 +                                <&gcc PCIE_1_PHY_RESET>,
  50 +                                <&gcc PCIE_1_EXT_RESET>;
  51 +                       reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  52
  53                         pinctrl-0 = <&pcie1_pins>;
  54                         pinctrl-names = "default";
  55 @@ -567,15 +579,21 @@
  56
  57                         clocks = <&gcc PCIE_2_A_CLK>,
  58                                  <&gcc PCIE_2_H_CLK>,
  59 -                                <&gcc PCIE_2_PHY_CLK>;
  60 -                       clock-names = "core", "iface", "phy";
  61 +                                <&gcc PCIE_2_PHY_CLK>,
  62 +                                <&gcc PCIE_2_AUX_CLK>,
  63 +                                <&gcc PCIE_2_ALT_REF_CLK>;
  64 +                       clock-names = "core", "iface", "phy", "aux", "ref";
  65 +
  66 +                       assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
  67 +                       assigned-clock-rates = <100000000>;
  68
  69                         resets = <&gcc PCIE_2_ACLK_RESET>,
  70                                  <&gcc PCIE_2_HCLK_RESET>,
  71                                  <&gcc PCIE_2_POR_RESET>,
  72                                  <&gcc PCIE_2_PCI_RESET>,
  73 -                                <&gcc PCIE_2_PHY_RESET>;
  74 -                       reset-names = "axi", "ahb", "por", "pci", "phy";
  75 +                                <&gcc PCIE_2_PHY_RESET>,
  76 +                                <&gcc PCIE_2_EXT_RESET>;
  77 +                       reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
  78
  79                         pinctrl-0 = <&pcie2_pins>;
  80                         pinctrl-names = "default";