target/linux/ipq806x/patches-4.4/710-spi-qup-Make-sure-mode-is-only-determined-once.patch

   1 From 93f99afbc534e00d72d58336061823055ee820f1 Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <andy.gross@linaro.org>
   3 Date: Tue, 12 Apr 2016 09:11:47 -0500
   4 Subject: [PATCH] spi: qup: Make sure mode is only determined once
   5
   6 This patch calculates the mode once.  All decisions on the current
   7 transaction
   8 is made using the mode instead of use_dma
   9
  10 Signed-off-by: Andy Gross <andy.gross@linaro.org>
  11
  12 Change-Id: If3cdd924355e037d77dc8201a72895fac0461aa5
  13 ---
  14  drivers/spi/spi-qup.c | 96 +++++++++++++++++++--------------------------------
  15  1 file changed, 36 insertions(+), 60 deletions(-)
  16
  17 --- a/drivers/spi/spi-qup.c
  18 +++ b/drivers/spi/spi-qup.c
  19 @@ -150,13 +150,20 @@ struct spi_qup {
  20         int                     rx_bytes;
  21         int                     qup_v1;
  22
  23 -       int                     use_dma;
  24 +       int                     mode;
  25         struct dma_slave_config rx_conf;
  26         struct dma_slave_config tx_conf;
  27 -       int mode;
  28  };
  29
  30
  31 +static inline bool spi_qup_is_dma_xfer(int mode)
  32 +{
  33 +       if (mode == QUP_IO_M_MODE_DMOV || mode == QUP_IO_M_MODE_BAM)
  34 +               return true;
  35 +
  36 +       return false;
  37 +}
  38 +
  39  static inline bool spi_qup_is_valid_state(struct spi_qup *controller)
  40  {
  41         u32 opstate = readl_relaxed(controller->base + QUP_STATE);
  42 @@ -427,7 +434,7 @@ static irqreturn_t spi_qup_qup_irq(int i
  43                 error = -EIO;
  44         }
  45
  46 -       if (!controller->use_dma) {
  47 +       if (!spi_qup_is_dma_xfer(controller->mode)) {
  48                 if (opflags & QUP_OP_IN_SERVICE_FLAG)
  49                         spi_qup_fifo_read(controller, xfer);
  50
  51 @@ -446,43 +453,11 @@ static irqreturn_t spi_qup_qup_irq(int i
  52         return IRQ_HANDLED;
  53  }
  54
  55 -static u32
  56 -spi_qup_get_mode(struct spi_master *master, struct spi_transfer *xfer)
  57 -{
  58 -       struct spi_qup *qup = spi_master_get_devdata(master);
  59 -       u32 mode;
  60 -       size_t dma_align = dma_get_cache_alignment();
  61 -
  62 -       qup->w_size = 4;
  63 -
  64 -       if (xfer->bits_per_word <= 8)
  65 -               qup->w_size = 1;
  66 -       else if (xfer->bits_per_word <= 16)
  67 -               qup->w_size = 2;
  68 -
  69 -       qup->n_words = xfer->len / qup->w_size;
  70 -
  71 -       if (!IS_ERR_OR_NULL(master->dma_rx) &&
  72 -                       IS_ALIGNED((size_t)xfer->tx_buf, dma_align) &&
  73 -                       IS_ALIGNED((size_t)xfer->rx_buf, dma_align) &&
  74 -                       !is_vmalloc_addr(xfer->tx_buf) &&
  75 -                       !is_vmalloc_addr(xfer->rx_buf) &&
  76 -                       (xfer->len > 3*qup->in_blk_sz))
  77 -               qup->use_dma = 1;
  78 -
  79 -       if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
  80 -               mode = QUP_IO_M_MODE_FIFO;
  81 -       else
  82 -               mode = QUP_IO_M_MODE_BLOCK;
  83 -
  84 -       return mode;
  85 -}
  86 -
  87  /* set clock freq ... bits per word */
  88  static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
  89  {
  90         struct spi_qup *controller = spi_master_get_devdata(spi->master);
  91 -       u32 config, iomode, mode, control;
  92 +       u32 config, iomode, control;
  93         int ret, n_words;
  94
  95         if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
  96 @@ -503,24 +478,22 @@ static int spi_qup_io_config(struct spi_
  97                 return -EIO;
  98         }
  99
 100 -       controller->mode = mode = spi_qup_get_mode(spi->master, xfer);
 101 +       controller->w_size = DIV_ROUND_UP(xfer->bits_per_word, 8);
 102 +       controller->n_words = xfer->len / controller->w_size;
 103         n_words = controller->n_words;
 104
 105 -       if (mode == QUP_IO_M_MODE_FIFO) {
 106 +       if (n_words <= (controller->in_fifo_sz / sizeof(u32))) {
 107 +               controller->mode = QUP_IO_M_MODE_FIFO;
 108                 writel_relaxed(n_words, controller->base + QUP_MX_READ_CNT);
 109                 writel_relaxed(n_words, controller->base + QUP_MX_WRITE_CNT);
 110                 /* must be zero for FIFO */
 111                 writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
 112                 writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 113                 controller->use_dma = 0;
 114 -       } else if (!controller->use_dma) {
 115 -               writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
 116 -               writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
 117 -               /* must be zero for BLOCK and BAM */
 118 -               writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 119 -               writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 120 -       } else {
 121 -               mode = QUP_IO_M_MODE_BAM;
 122 +       } else if (spi->master->can_dma &&
 123 +           spi->master->can_dma(spi->master, spi, xfer) &&
 124 +           spi->master->cur_msg_mapped) {
 125 +               controller->mode = QUP_IO_M_MODE_BAM;
 126                 writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 127                 writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 128
 129 @@ -541,19 +514,26 @@ static int spi_qup_io_config(struct spi_
 130
 131                         writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 132                 }
 133 +       } else {
 134 +               controller->mode = QUP_IO_M_MODE_BLOCK;
 135 +               writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
 136 +               writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
 137 +               /* must be zero for BLOCK and BAM */
 138 +               writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 139 +               writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 140         }
 141
 142         iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
 143         /* Set input and output transfer mode */
 144         iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
 145
 146 -       if (!controller->use_dma)
 147 +       if (!spi_qup_is_dma_xfer(controller->mode))
 148                 iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
 149         else
 150                 iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
 151
 152 -       iomode |= (mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
 153 -       iomode |= (mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
 154 +       iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
 155 +       iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
 156
 157         writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
 158
 159 @@ -594,7 +574,7 @@ static int spi_qup_io_config(struct spi_
 160         config |= xfer->bits_per_word - 1;
 161         config |= QUP_CONFIG_SPI_MODE;
 162
 163 -       if (controller->use_dma) {
 164 +       if (spi_qup_is_dma_xfer(controller->mode)) {
 165                 if (!xfer->tx_buf)
 166                         config |= QUP_CONFIG_NO_OUTPUT;
 167                 if (!xfer->rx_buf)
 168 @@ -612,7 +592,7 @@ static int spi_qup_io_config(struct spi_
 169                  * status change in BAM mode
 170                  */
 171
 172 -               if (mode == QUP_IO_M_MODE_BAM)
 173 +               if (spi_qup_is_dma_xfer(controller->mode))
 174                         mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
 175
 176                 writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
 177 @@ -646,7 +626,7 @@ static int spi_qup_transfer_one(struct s
 178         controller->tx_bytes = 0;
 179         spin_unlock_irqrestore(&controller->lock, flags);
 180
 181 -       if (controller->use_dma)
 182 +       if (spi_qup_is_dma_xfer(controller->mode))
 183                 ret = spi_qup_do_dma(master, xfer);
 184         else
 185                 ret = spi_qup_do_pio(master, xfer);
 186 @@ -670,7 +650,7 @@ exit:
 187                 ret = controller->error;
 188         spin_unlock_irqrestore(&controller->lock, flags);
 189
 190 -       if (ret && controller->use_dma)
 191 +       if (ret && spi_qup_is_dma_xfer(controller->mode))
 192                 spi_qup_dma_terminate(master, xfer);
 193
 194         return ret;
 195 @@ -681,9 +661,7 @@ static bool spi_qup_can_dma(struct spi_m
 196  {
 197         struct spi_qup *qup = spi_master_get_devdata(master);
 198         size_t dma_align = dma_get_cache_alignment();
 199 -       u32 mode;
 200 -
 201 -       qup->use_dma = 0;
 202 +       int n_words;
 203
 204         if (xfer->rx_buf && (xfer->len % qup->in_blk_sz ||
 205             IS_ERR_OR_NULL(master->dma_rx) ||
 206 @@ -695,12 +673,10 @@ static bool spi_qup_can_dma(struct spi_m
 207             !IS_ALIGNED((size_t)xfer->tx_buf, dma_align)))
 208                 return false;
 209
 210 -       mode = spi_qup_get_mode(master, xfer);
 211 -       if (mode == QUP_IO_M_MODE_FIFO)
 212 +       n_words = xfer->len / DIV_ROUND_UP(xfer->bits_per_word, 8);
 213 +       if (n_words <= (qup->in_fifo_sz / sizeof(u32)))
 214                 return false;
 215
 216 -       qup->use_dma = 1;
 217 -
 218         return true;
 219  }
 220