target/linux/ipq806x/patches-4.9/0010-spi-qup-call-io_config-in-mode-specific-function.patch

   1 From afe108e638a2dd441b11cd2c7b1e0658bb47b5e8 Mon Sep 17 00:00:00 2001
   2 From: Matthew McClintock <mmcclint@codeaurora.org>
   3 Date: Tue, 26 Apr 2016 13:14:45 -0500
   4 Subject: [PATCH 10/69] spi: qup: call io_config in mode specific function
   5
   6 DMA transactions should only only need to call io_config only once, but
   7 block mode might call it several times to setup several transactions so
   8 it can handle reads/writes larger than the max size per transaction, so
   9 we move the call to the do_ functions.
  10
  11 This is just refactoring, there should be no functional change
  12
  13 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
  14 ---
  15  drivers/spi/spi-qup.c | 327 +++++++++++++++++++++++++-------------------------
  16  1 file changed, 166 insertions(+), 161 deletions(-)
  17
  18 --- a/drivers/spi/spi-qup.c
  19 +++ b/drivers/spi/spi-qup.c
  20 @@ -418,13 +418,170 @@ static void spi_qup_dma_terminate(struct
  21                 dmaengine_terminate_all(master->dma_rx);
  22  }
  23
  24 -static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer,
  25 +/* prep qup for another spi transaction of specific type */
  26 +static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
  27 +{
  28 +       struct spi_qup *controller = spi_master_get_devdata(spi->master);
  29 +       u32 config, iomode, control;
  30 +       unsigned long flags;
  31 +
  32 +       reinit_completion(&controller->done);
  33 +       reinit_completion(&controller->dma_tx_done);
  34 +
  35 +       spin_lock_irqsave(&controller->lock, flags);
  36 +       controller->xfer     = xfer;
  37 +       controller->error    = 0;
  38 +       controller->rx_bytes = 0;
  39 +       controller->tx_bytes = 0;
  40 +       spin_unlock_irqrestore(&controller->lock, flags);
  41 +
  42 +       if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
  43 +               dev_err(controller->dev, "cannot set RESET state\n");
  44 +               return -EIO;
  45 +       }
  46 +
  47 +       switch (controller->mode) {
  48 +               case QUP_IO_M_MODE_FIFO:
  49 +                       writel_relaxed(controller->n_words,
  50 +                                      controller->base + QUP_MX_READ_CNT);
  51 +                       writel_relaxed(controller->n_words,
  52 +                                      controller->base + QUP_MX_WRITE_CNT);
  53 +                       /* must be zero for FIFO */
  54 +                       writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
  55 +                       writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
  56 +                       break;
  57 +               case QUP_IO_M_MODE_BAM:
  58 +                       writel_relaxed(controller->n_words,
  59 +                                      controller->base + QUP_MX_INPUT_CNT);
  60 +                       writel_relaxed(controller->n_words,
  61 +                                      controller->base + QUP_MX_OUTPUT_CNT);
  62 +                       /* must be zero for BLOCK and BAM */
  63 +                       writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
  64 +                       writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
  65 +                       if (!controller->qup_v1) {
  66 +                               void __iomem *input_cnt;
  67 +
  68 +                               input_cnt = controller->base + QUP_MX_INPUT_CNT;
  69 +                               /*
  70 +                                * for DMA transfers, both QUP_MX_INPUT_CNT and
  71 +                                * QUP_MX_OUTPUT_CNT must be zero to all cases
  72 +                                * but one. That case is a non-balanced
  73 +                                * transfer when there is only a rx_buf.
  74 +                                */
  75 +                               if (xfer->tx_buf)
  76 +                                       writel_relaxed(0, input_cnt);
  77 +                               else
  78 +                                       writel_relaxed(controller->n_words,
  79 +                                                      input_cnt);
  80 +
  81 +                               writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
  82 +                       }
  83 +                       break;
  84 +               case QUP_IO_M_MODE_BLOCK:
  85 +                       writel_relaxed(controller->n_words,
  86 +                                      controller->base + QUP_MX_INPUT_CNT);
  87 +                       writel_relaxed(controller->n_words,
  88 +                                      controller->base + QUP_MX_OUTPUT_CNT);
  89 +                       /* must be zero for BLOCK and BAM */
  90 +                       writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
  91 +                       writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
  92 +                       break;
  93 +               default:
  94 +                       dev_err(controller->dev, "unknown mode = %d\n",
  95 +                                       controller->mode);
  96 +                       return -EIO;
  97 +       }
  98 +
  99 +       iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
 100 +       /* Set input and output transfer mode */
 101 +       iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
 102 +
 103 +       if (!spi_qup_is_dma_xfer(controller->mode))
 104 +               iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
 105 +       else
 106 +               iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
 107 +
 108 +       iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
 109 +       iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
 110 +
 111 +       writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
 112 +
 113 +       control = readl_relaxed(controller->base + SPI_IO_CONTROL);
 114 +
 115 +       if (spi->mode & SPI_CPOL)
 116 +               control |= SPI_IO_C_CLK_IDLE_HIGH;
 117 +       else
 118 +               control &= ~SPI_IO_C_CLK_IDLE_HIGH;
 119 +
 120 +       writel_relaxed(control, controller->base + SPI_IO_CONTROL);
 121 +
 122 +       config = readl_relaxed(controller->base + SPI_CONFIG);
 123 +
 124 +       if (spi->mode & SPI_LOOP)
 125 +               config |= SPI_CONFIG_LOOPBACK;
 126 +       else
 127 +               config &= ~SPI_CONFIG_LOOPBACK;
 128 +
 129 +       if (spi->mode & SPI_CPHA)
 130 +               config &= ~SPI_CONFIG_INPUT_FIRST;
 131 +       else
 132 +               config |= SPI_CONFIG_INPUT_FIRST;
 133 +
 134 +       /*
 135 +        * HS_MODE improves signal stability for spi-clk high rates,
 136 +        * but is invalid in loop back mode.
 137 +        */
 138 +       if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
 139 +               config |= SPI_CONFIG_HS_MODE;
 140 +       else
 141 +               config &= ~SPI_CONFIG_HS_MODE;
 142 +
 143 +       writel_relaxed(config, controller->base + SPI_CONFIG);
 144 +
 145 +       config = readl_relaxed(controller->base + QUP_CONFIG);
 146 +       config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
 147 +       config |= xfer->bits_per_word - 1;
 148 +       config |= QUP_CONFIG_SPI_MODE;
 149 +
 150 +       if (spi_qup_is_dma_xfer(controller->mode)) {
 151 +               if (!xfer->tx_buf)
 152 +                       config |= QUP_CONFIG_NO_OUTPUT;
 153 +               if (!xfer->rx_buf)
 154 +                       config |= QUP_CONFIG_NO_INPUT;
 155 +       }
 156 +
 157 +       writel_relaxed(config, controller->base + QUP_CONFIG);
 158 +
 159 +       /* only write to OPERATIONAL_MASK when register is present */
 160 +       if (!controller->qup_v1) {
 161 +               u32 mask = 0;
 162 +
 163 +               /*
 164 +                * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
 165 +                * status change in BAM mode
 166 +                */
 167 +
 168 +               if (spi_qup_is_dma_xfer(controller->mode))
 169 +                       mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
 170 +
 171 +               writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
 172 +       }
 173 +
 174 +       return 0;
 175 +}
 176 +
 177 +static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
 178  unsigned long timeout)
 179  {
 180 +       struct spi_master *master = spi->master;
 181         struct spi_qup *qup = spi_master_get_devdata(master);
 182         dma_async_tx_callback rx_done = NULL, tx_done = NULL;
 183         int ret;
 184
 185 +       ret = spi_qup_io_config(spi, xfer);
 186 +       if (ret)
 187 +               return ret;
 188 +
 189         /* before issuing the descriptors, set the QUP to run */
 190         ret = spi_qup_set_state(qup, QUP_STATE_RUN);
 191         if (ret) {
 192 @@ -467,12 +624,17 @@ unsigned long timeout)
 193         return ret;
 194  }
 195
 196 -static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer,
 197 +static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
 198                           unsigned long timeout)
 199  {
 200 +       struct spi_master *master = spi->master;
 201         struct spi_qup *qup = spi_master_get_devdata(master);
 202         int ret;
 203
 204 +       ret = spi_qup_io_config(spi, xfer);
 205 +       if (ret)
 206 +               return ret;
 207 +
 208         ret = spi_qup_set_state(qup, QUP_STATE_RUN);
 209         if (ret) {
 210                 dev_warn(qup->dev, "cannot set RUN state\n");
 211 @@ -619,159 +781,6 @@ static int spi_qup_io_prep(struct spi_de
 212         return 0;
 213  }
 214
 215 -/* prep qup for another spi transaction of specific type */
 216 -static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
 217 -{
 218 -       struct spi_qup *controller = spi_master_get_devdata(spi->master);
 219 -       u32 config, iomode, control;
 220 -       unsigned long flags;
 221 -
 222 -       reinit_completion(&controller->done);
 223 -       reinit_completion(&controller->dma_tx_done);
 224 -
 225 -       spin_lock_irqsave(&controller->lock, flags);
 226 -       controller->xfer     = xfer;
 227 -       controller->error    = 0;
 228 -       controller->rx_bytes = 0;
 229 -       controller->tx_bytes = 0;
 230 -       spin_unlock_irqrestore(&controller->lock, flags);
 231 -
 232 -
 233 -       if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
 234 -               dev_err(controller->dev, "cannot set RESET state\n");
 235 -               return -EIO;
 236 -       }
 237 -
 238 -       switch (controller->mode) {
 239 -               case QUP_IO_M_MODE_FIFO:
 240 -                       writel_relaxed(controller->n_words,
 241 -                                      controller->base + QUP_MX_READ_CNT);
 242 -                       writel_relaxed(controller->n_words,
 243 -                                      controller->base + QUP_MX_WRITE_CNT);
 244 -                       /* must be zero for FIFO */
 245 -                       writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
 246 -                       writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 247 -                       break;
 248 -               case QUP_IO_M_MODE_BAM:
 249 -                       writel_relaxed(controller->n_words,
 250 -                                      controller->base + QUP_MX_INPUT_CNT);
 251 -                       writel_relaxed(controller->n_words,
 252 -                                      controller->base + QUP_MX_OUTPUT_CNT);
 253 -                       /* must be zero for BLOCK and BAM */
 254 -                       writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 255 -                       writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 256 -                       if (!controller->qup_v1) {
 257 -                               void __iomem *input_cnt;
 258 -
 259 -                               input_cnt = controller->base + QUP_MX_INPUT_CNT;
 260 -                               /*
 261 -                                * for DMA transfers, both QUP_MX_INPUT_CNT and
 262 -                                * QUP_MX_OUTPUT_CNT must be zero to all cases
 263 -                                * but one. That case is a non-balanced
 264 -                                * transfer when there is only a rx_buf.
 265 -                                */
 266 -                               if (xfer->tx_buf)
 267 -                                       writel_relaxed(0, input_cnt);
 268 -                               else
 269 -                                       writel_relaxed(controller->n_words,
 270 -                                                      input_cnt);
 271 -
 272 -                               writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
 273 -                       }
 274 -                       break;
 275 -               case QUP_IO_M_MODE_BLOCK:
 276 -                       writel_relaxed(controller->n_words,
 277 -                                      controller->base + QUP_MX_INPUT_CNT);
 278 -                       writel_relaxed(controller->n_words,
 279 -                                      controller->base + QUP_MX_OUTPUT_CNT);
 280 -                       /* must be zero for BLOCK and BAM */
 281 -                       writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
 282 -                       writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
 283 -                       break;
 284 -               default:
 285 -                       dev_err(controller->dev, "unknown mode = %d\n",
 286 -                                       controller->mode);
 287 -                       return -EIO;
 288 -       }
 289 -
 290 -       iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
 291 -       /* Set input and output transfer mode */
 292 -       iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
 293 -
 294 -       if (!spi_qup_is_dma_xfer(controller->mode))
 295 -               iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
 296 -       else
 297 -               iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
 298 -
 299 -       iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
 300 -       iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
 301 -
 302 -       writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
 303 -
 304 -       control = readl_relaxed(controller->base + SPI_IO_CONTROL);
 305 -
 306 -       if (spi->mode & SPI_CPOL)
 307 -               control |= SPI_IO_C_CLK_IDLE_HIGH;
 308 -       else
 309 -               control &= ~SPI_IO_C_CLK_IDLE_HIGH;
 310 -
 311 -       writel_relaxed(control, controller->base + SPI_IO_CONTROL);
 312 -
 313 -       config = readl_relaxed(controller->base + SPI_CONFIG);
 314 -
 315 -       if (spi->mode & SPI_LOOP)
 316 -               config |= SPI_CONFIG_LOOPBACK;
 317 -       else
 318 -               config &= ~SPI_CONFIG_LOOPBACK;
 319 -
 320 -       if (spi->mode & SPI_CPHA)
 321 -               config &= ~SPI_CONFIG_INPUT_FIRST;
 322 -       else
 323 -               config |= SPI_CONFIG_INPUT_FIRST;
 324 -
 325 -       /*
 326 -        * HS_MODE improves signal stability for spi-clk high rates,
 327 -        * but is invalid in loop back mode.
 328 -        */
 329 -       if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
 330 -               config |= SPI_CONFIG_HS_MODE;
 331 -       else
 332 -               config &= ~SPI_CONFIG_HS_MODE;
 333 -
 334 -       writel_relaxed(config, controller->base + SPI_CONFIG);
 335 -
 336 -       config = readl_relaxed(controller->base + QUP_CONFIG);
 337 -       config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
 338 -       config |= xfer->bits_per_word - 1;
 339 -       config |= QUP_CONFIG_SPI_MODE;
 340 -
 341 -       if (spi_qup_is_dma_xfer(controller->mode)) {
 342 -               if (!xfer->tx_buf)
 343 -                       config |= QUP_CONFIG_NO_OUTPUT;
 344 -               if (!xfer->rx_buf)
 345 -                       config |= QUP_CONFIG_NO_INPUT;
 346 -       }
 347 -
 348 -       writel_relaxed(config, controller->base + QUP_CONFIG);
 349 -
 350 -       /* only write to OPERATIONAL_MASK when register is present */
 351 -       if (!controller->qup_v1) {
 352 -               u32 mask = 0;
 353 -
 354 -               /*
 355 -                * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
 356 -                * status change in BAM mode
 357 -                */
 358 -
 359 -               if (spi_qup_is_dma_xfer(controller->mode))
 360 -                       mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
 361 -
 362 -               writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
 363 -       }
 364 -
 365 -       return 0;
 366 -}
 367 -
 368  static int spi_qup_transfer_one(struct spi_master *master,
 369                               struct spi_device *spi,
 370                               struct spi_transfer *xfer)
 371 @@ -784,18 +793,14 @@ static int spi_qup_transfer_one(struct s
 372         if (ret)
 373                 return ret;
 374
 375 -       ret = spi_qup_io_config(spi, xfer);
 376 -       if (ret)
 377 -               return ret;
 378 -
 379         timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
 380         timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
 381         timeout = 100 * msecs_to_jiffies(timeout);
 382
 383         if (spi_qup_is_dma_xfer(controller->mode))
 384 -               ret = spi_qup_do_dma(master, xfer, timeout);
 385 +               ret = spi_qup_do_dma(spi, xfer, timeout);
 386         else
 387 -               ret = spi_qup_do_pio(master, xfer, timeout);
 388 +               ret = spi_qup_do_pio(spi, xfer, timeout);
 389
 390         if (ret)
 391                 goto exit;