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ipq806x: switch to linux 4.14
[openwrt/openwrt.git] / target / linux / ipq806x / patches-4.9 / 0027-clk-qcom-Add-support-for-SMD-RPM-Clocks.patch
1 From 41ee71bae788e1858c0a387d010c342e6bb3f4b0 Mon Sep 17 00:00:00 2001
2 From: Georgi Djakov <georgi.djakov@linaro.org>
3 Date: Wed, 2 Nov 2016 17:56:56 +0200
4 Subject: [PATCH 27/69] clk: qcom: Add support for SMD-RPM Clocks
5
6 This adds initial support for clocks controlled by the Resource
7 Power Manager (RPM) processor on some Qualcomm SoCs, which use
8 the qcom_smd_rpm driver to communicate with RPM.
9 Such platforms are msm8916, apq8084 and msm8974.
10
11 The RPM is a dedicated hardware engine for managing the shared
12 SoC resources in order to keep the lowest power profile. It
13 communicates with other hardware subsystems via shared memory
14 and accepts clock requests, aggregates the requests and turns
15 the clocks on/off or scales them on demand.
16
17 This driver is based on the codeaurora.org driver:
18 https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c
19
20 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
21 ---
22 .../devicetree/bindings/clock/qcom,rpmcc.txt | 36 ++
23 drivers/clk/qcom/Kconfig | 16 +
24 drivers/clk/qcom/Makefile | 1 +
25 drivers/clk/qcom/clk-smd-rpm.c | 571 +++++++++++++++++++++
26 include/dt-bindings/clock/qcom,rpmcc.h | 45 ++
27 5 files changed, 669 insertions(+)
28 create mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
29 create mode 100644 drivers/clk/qcom/clk-smd-rpm.c
30 create mode 100644 include/dt-bindings/clock/qcom,rpmcc.h
31
32 --- /dev/null
33 +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
34 @@ -0,0 +1,36 @@
35 +Qualcomm RPM Clock Controller Binding
36 +------------------------------------------------
37 +The RPM is a dedicated hardware engine for managing the shared
38 +SoC resources in order to keep the lowest power profile. It
39 +communicates with other hardware subsystems via shared memory
40 +and accepts clock requests, aggregates the requests and turns
41 +the clocks on/off or scales them on demand.
42 +
43 +Required properties :
44 +- compatible : shall contain only one of the following. The generic
45 + compatible "qcom,rpmcc" should be also included.
46 +
47 + "qcom,rpmcc-msm8916", "qcom,rpmcc"
48 +
49 +- #clock-cells : shall contain 1
50 +
51 +Example:
52 + smd {
53 + compatible = "qcom,smd";
54 +
55 + rpm {
56 + interrupts = <0 168 1>;
57 + qcom,ipc = <&apcs 8 0>;
58 + qcom,smd-edge = <15>;
59 +
60 + rpm_requests {
61 + compatible = "qcom,rpm-msm8916";
62 + qcom,smd-channels = "rpm_requests";
63 +
64 + rpmcc: clock-controller {
65 + compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
66 + #clock-cells = <1>;
67 + };
68 + };
69 + };
70 + };
71 --- a/drivers/clk/qcom/Kconfig
72 +++ b/drivers/clk/qcom/Kconfig
73 @@ -2,6 +2,9 @@ config QCOM_GDSC
74 bool
75 select PM_GENERIC_DOMAINS if PM
76
77 +config QCOM_RPMCC
78 + bool
79 +
80 config COMMON_CLK_QCOM
81 tristate "Support for Qualcomm's clock controllers"
82 depends on OF
83 @@ -9,6 +12,19 @@ config COMMON_CLK_QCOM
84 select REGMAP_MMIO
85 select RESET_CONTROLLER
86
87 +config QCOM_CLK_SMD_RPM
88 + tristate "RPM over SMD based Clock Controller"
89 + depends on COMMON_CLK_QCOM && QCOM_SMD_RPM
90 + select QCOM_RPMCC
91 + help
92 + The RPM (Resource Power Manager) is a dedicated hardware engine for
93 + managing the shared SoC resources in order to keep the lowest power
94 + profile. It communicates with other hardware subsystems via shared
95 + memory and accepts clock requests, aggregates the requests and turns
96 + the clocks on/off or scales them on demand.
97 + Say Y if you want to support the clocks exposed by the RPM on
98 + platforms such as apq8016, apq8084, msm8974 etc.
99 +
100 config APQ_GCC_8084
101 tristate "APQ8084 Global Clock Controller"
102 select QCOM_GDSC
103 --- a/drivers/clk/qcom/Makefile
104 +++ b/drivers/clk/qcom/Makefile
105 @@ -29,3 +29,4 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm896
106 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
107 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
108 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
109 +obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
110 --- /dev/null
111 +++ b/drivers/clk/qcom/clk-smd-rpm.c
112 @@ -0,0 +1,571 @@
113 +/*
114 + * Copyright (c) 2016, Linaro Limited
115 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
116 + *
117 + * This software is licensed under the terms of the GNU General Public
118 + * License version 2, as published by the Free Software Foundation, and
119 + * may be copied, distributed, and modified under those terms.
120 + *
121 + * This program is distributed in the hope that it will be useful,
122 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
123 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
124 + * GNU General Public License for more details.
125 + */
126 +
127 +#include <linux/clk-provider.h>
128 +#include <linux/err.h>
129 +#include <linux/export.h>
130 +#include <linux/init.h>
131 +#include <linux/kernel.h>
132 +#include <linux/module.h>
133 +#include <linux/mutex.h>
134 +#include <linux/of.h>
135 +#include <linux/of_device.h>
136 +#include <linux/platform_device.h>
137 +#include <linux/soc/qcom/smd-rpm.h>
138 +
139 +#include <dt-bindings/clock/qcom,rpmcc.h>
140 +#include <dt-bindings/mfd/qcom-rpm.h>
141 +
142 +#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
143 +#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
144 +#define QCOM_RPM_SMD_KEY_RATE 0x007a484b
145 +#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45
146 +#define QCOM_RPM_SMD_KEY_STATE 0x54415453
147 +#define QCOM_RPM_SCALING_ENABLE_ID 0x2
148 +
149 +#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \
150 + key) \
151 + static struct clk_smd_rpm _platform##_##_active; \
152 + static struct clk_smd_rpm _platform##_##_name = { \
153 + .rpm_res_type = (type), \
154 + .rpm_clk_id = (r_id), \
155 + .rpm_status_id = (stat_id), \
156 + .rpm_key = (key), \
157 + .peer = &_platform##_##_active, \
158 + .rate = INT_MAX, \
159 + .hw.init = &(struct clk_init_data){ \
160 + .ops = &clk_smd_rpm_ops, \
161 + .name = #_name, \
162 + .parent_names = (const char *[]){ "xo_board" }, \
163 + .num_parents = 1, \
164 + }, \
165 + }; \
166 + static struct clk_smd_rpm _platform##_##_active = { \
167 + .rpm_res_type = (type), \
168 + .rpm_clk_id = (r_id), \
169 + .rpm_status_id = (stat_id), \
170 + .active_only = true, \
171 + .rpm_key = (key), \
172 + .peer = &_platform##_##_name, \
173 + .rate = INT_MAX, \
174 + .hw.init = &(struct clk_init_data){ \
175 + .ops = &clk_smd_rpm_ops, \
176 + .name = #_active, \
177 + .parent_names = (const char *[]){ "xo_board" }, \
178 + .num_parents = 1, \
179 + }, \
180 + }
181 +
182 +#define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \
183 + stat_id, r, key) \
184 + static struct clk_smd_rpm _platform##_##_active; \
185 + static struct clk_smd_rpm _platform##_##_name = { \
186 + .rpm_res_type = (type), \
187 + .rpm_clk_id = (r_id), \
188 + .rpm_status_id = (stat_id), \
189 + .rpm_key = (key), \
190 + .branch = true, \
191 + .peer = &_platform##_##_active, \
192 + .rate = (r), \
193 + .hw.init = &(struct clk_init_data){ \
194 + .ops = &clk_smd_rpm_branch_ops, \
195 + .name = #_name, \
196 + .parent_names = (const char *[]){ "xo_board" }, \
197 + .num_parents = 1, \
198 + }, \
199 + }; \
200 + static struct clk_smd_rpm _platform##_##_active = { \
201 + .rpm_res_type = (type), \
202 + .rpm_clk_id = (r_id), \
203 + .rpm_status_id = (stat_id), \
204 + .active_only = true, \
205 + .rpm_key = (key), \
206 + .branch = true, \
207 + .peer = &_platform##_##_name, \
208 + .rate = (r), \
209 + .hw.init = &(struct clk_init_data){ \
210 + .ops = &clk_smd_rpm_branch_ops, \
211 + .name = #_active, \
212 + .parent_names = (const char *[]){ "xo_board" }, \
213 + .num_parents = 1, \
214 + }, \
215 + }
216 +
217 +#define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \
218 + __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
219 + 0, QCOM_RPM_SMD_KEY_RATE)
220 +
221 +#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \
222 + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \
223 + r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
224 +
225 +#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \
226 + __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
227 + 0, QCOM_RPM_SMD_KEY_STATE)
228 +
229 +#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id) \
230 + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
231 + QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
232 + QCOM_RPM_KEY_SOFTWARE_ENABLE)
233 +
234 +#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \
235 + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
236 + QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
237 + QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
238 +
239 +#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
240 +
241 +struct clk_smd_rpm {
242 + const int rpm_res_type;
243 + const int rpm_key;
244 + const int rpm_clk_id;
245 + const int rpm_status_id;
246 + const bool active_only;
247 + bool enabled;
248 + bool branch;
249 + struct clk_smd_rpm *peer;
250 + struct clk_hw hw;
251 + unsigned long rate;
252 + struct qcom_smd_rpm *rpm;
253 +};
254 +
255 +struct clk_smd_rpm_req {
256 + __le32 key;
257 + __le32 nbytes;
258 + __le32 value;
259 +};
260 +
261 +struct rpm_cc {
262 + struct qcom_rpm *rpm;
263 + struct clk_hw_onecell_data data;
264 + struct clk_hw *hws[];
265 +};
266 +
267 +struct rpm_smd_clk_desc {
268 + struct clk_smd_rpm **clks;
269 + size_t num_clks;
270 +};
271 +
272 +static DEFINE_MUTEX(rpm_smd_clk_lock);
273 +
274 +static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
275 +{
276 + int ret;
277 + struct clk_smd_rpm_req req = {
278 + .key = cpu_to_le32(r->rpm_key),
279 + .nbytes = cpu_to_le32(sizeof(u32)),
280 + .value = cpu_to_le32(INT_MAX),
281 + };
282 +
283 + ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
284 + r->rpm_res_type, r->rpm_clk_id, &req,
285 + sizeof(req));
286 + if (ret)
287 + return ret;
288 + ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
289 + r->rpm_res_type, r->rpm_clk_id, &req,
290 + sizeof(req));
291 + if (ret)
292 + return ret;
293 +
294 + return 0;
295 +}
296 +
297 +static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
298 + unsigned long rate)
299 +{
300 + struct clk_smd_rpm_req req = {
301 + .key = cpu_to_le32(r->rpm_key),
302 + .nbytes = cpu_to_le32(sizeof(u32)),
303 + .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
304 + };
305 +
306 + return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
307 + r->rpm_res_type, r->rpm_clk_id, &req,
308 + sizeof(req));
309 +}
310 +
311 +static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
312 + unsigned long rate)
313 +{
314 + struct clk_smd_rpm_req req = {
315 + .key = cpu_to_le32(r->rpm_key),
316 + .nbytes = cpu_to_le32(sizeof(u32)),
317 + .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
318 + };
319 +
320 + return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
321 + r->rpm_res_type, r->rpm_clk_id, &req,
322 + sizeof(req));
323 +}
324 +
325 +static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
326 + unsigned long *active, unsigned long *sleep)
327 +{
328 + *active = rate;
329 +
330 + /*
331 + * Active-only clocks don't care what the rate is during sleep. So,
332 + * they vote for zero.
333 + */
334 + if (r->active_only)
335 + *sleep = 0;
336 + else
337 + *sleep = *active;
338 +}
339 +
340 +static int clk_smd_rpm_prepare(struct clk_hw *hw)
341 +{
342 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
343 + struct clk_smd_rpm *peer = r->peer;
344 + unsigned long this_rate = 0, this_sleep_rate = 0;
345 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
346 + unsigned long active_rate, sleep_rate;
347 + int ret = 0;
348 +
349 + mutex_lock(&rpm_smd_clk_lock);
350 +
351 + /* Don't send requests to the RPM if the rate has not been set. */
352 + if (!r->rate)
353 + goto out;
354 +
355 + to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
356 +
357 + /* Take peer clock's rate into account only if it's enabled. */
358 + if (peer->enabled)
359 + to_active_sleep(peer, peer->rate,
360 + &peer_rate, &peer_sleep_rate);
361 +
362 + active_rate = max(this_rate, peer_rate);
363 +
364 + if (r->branch)
365 + active_rate = !!active_rate;
366 +
367 + ret = clk_smd_rpm_set_rate_active(r, active_rate);
368 + if (ret)
369 + goto out;
370 +
371 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
372 + if (r->branch)
373 + sleep_rate = !!sleep_rate;
374 +
375 + ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
376 + if (ret)
377 + /* Undo the active set vote and restore it */
378 + ret = clk_smd_rpm_set_rate_active(r, peer_rate);
379 +
380 +out:
381 + if (!ret)
382 + r->enabled = true;
383 +
384 + mutex_unlock(&rpm_smd_clk_lock);
385 +
386 + return ret;
387 +}
388 +
389 +static void clk_smd_rpm_unprepare(struct clk_hw *hw)
390 +{
391 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
392 + struct clk_smd_rpm *peer = r->peer;
393 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
394 + unsigned long active_rate, sleep_rate;
395 + int ret;
396 +
397 + mutex_lock(&rpm_smd_clk_lock);
398 +
399 + if (!r->rate)
400 + goto out;
401 +
402 + /* Take peer clock's rate into account only if it's enabled. */
403 + if (peer->enabled)
404 + to_active_sleep(peer, peer->rate, &peer_rate,
405 + &peer_sleep_rate);
406 +
407 + active_rate = r->branch ? !!peer_rate : peer_rate;
408 + ret = clk_smd_rpm_set_rate_active(r, active_rate);
409 + if (ret)
410 + goto out;
411 +
412 + sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
413 + ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
414 + if (ret)
415 + goto out;
416 +
417 + r->enabled = false;
418 +
419 +out:
420 + mutex_unlock(&rpm_smd_clk_lock);
421 +}
422 +
423 +static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
424 + unsigned long parent_rate)
425 +{
426 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
427 + struct clk_smd_rpm *peer = r->peer;
428 + unsigned long active_rate, sleep_rate;
429 + unsigned long this_rate = 0, this_sleep_rate = 0;
430 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
431 + int ret = 0;
432 +
433 + mutex_lock(&rpm_smd_clk_lock);
434 +
435 + if (!r->enabled)
436 + goto out;
437 +
438 + to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
439 +
440 + /* Take peer clock's rate into account only if it's enabled. */
441 + if (peer->enabled)
442 + to_active_sleep(peer, peer->rate,
443 + &peer_rate, &peer_sleep_rate);
444 +
445 + active_rate = max(this_rate, peer_rate);
446 + ret = clk_smd_rpm_set_rate_active(r, active_rate);
447 + if (ret)
448 + goto out;
449 +
450 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
451 + ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
452 + if (ret)
453 + goto out;
454 +
455 + r->rate = rate;
456 +
457 +out:
458 + mutex_unlock(&rpm_smd_clk_lock);
459 +
460 + return ret;
461 +}
462 +
463 +static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
464 + unsigned long *parent_rate)
465 +{
466 + /*
467 + * RPM handles rate rounding and we don't have a way to
468 + * know what the rate will be, so just return whatever
469 + * rate is requested.
470 + */
471 + return rate;
472 +}
473 +
474 +static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
475 + unsigned long parent_rate)
476 +{
477 + struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
478 +
479 + /*
480 + * RPM handles rate rounding and we don't have a way to
481 + * know what the rate will be, so just return whatever
482 + * rate was set.
483 + */
484 + return r->rate;
485 +}
486 +
487 +static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
488 +{
489 + int ret;
490 + struct clk_smd_rpm_req req = {
491 + .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
492 + .nbytes = cpu_to_le32(sizeof(u32)),
493 + .value = cpu_to_le32(1),
494 + };
495 +
496 + ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
497 + QCOM_SMD_RPM_MISC_CLK,
498 + QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
499 + if (ret) {
500 + pr_err("RPM clock scaling (sleep set) not enabled!\n");
501 + return ret;
502 + }
503 +
504 + ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
505 + QCOM_SMD_RPM_MISC_CLK,
506 + QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
507 + if (ret) {
508 + pr_err("RPM clock scaling (active set) not enabled!\n");
509 + return ret;
510 + }
511 +
512 + pr_debug("%s: RPM clock scaling is enabled\n", __func__);
513 + return 0;
514 +}
515 +
516 +static const struct clk_ops clk_smd_rpm_ops = {
517 + .prepare = clk_smd_rpm_prepare,
518 + .unprepare = clk_smd_rpm_unprepare,
519 + .set_rate = clk_smd_rpm_set_rate,
520 + .round_rate = clk_smd_rpm_round_rate,
521 + .recalc_rate = clk_smd_rpm_recalc_rate,
522 +};
523 +
524 +static const struct clk_ops clk_smd_rpm_branch_ops = {
525 + .prepare = clk_smd_rpm_prepare,
526 + .unprepare = clk_smd_rpm_unprepare,
527 + .round_rate = clk_smd_rpm_round_rate,
528 + .recalc_rate = clk_smd_rpm_recalc_rate,
529 +};
530 +
531 +/* msm8916 */
532 +DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
533 +DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
534 +DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
535 +DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
536 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1);
537 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2);
538 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4);
539 +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5);
540 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1);
541 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2);
542 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);
543 +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);
544 +
545 +static struct clk_smd_rpm *msm8916_clks[] = {
546 + [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
547 + [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
548 + [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
549 + [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
550 + [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
551 + [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
552 + [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
553 + [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
554 + [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
555 + [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
556 + [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
557 + [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
558 + [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
559 + [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
560 + [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
561 + [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
562 + [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
563 + [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
564 + [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
565 + [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
566 + [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
567 + [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
568 + [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
569 + [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
570 +};
571 +
572 +static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
573 + .clks = msm8916_clks,
574 + .num_clks = ARRAY_SIZE(msm8916_clks),
575 +};
576 +
577 +static const struct of_device_id rpm_smd_clk_match_table[] = {
578 + { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
579 + { }
580 +};
581 +MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
582 +
583 +static int rpm_smd_clk_probe(struct platform_device *pdev)
584 +{
585 + struct clk_hw **hws;
586 + struct rpm_cc *rcc;
587 + struct clk_hw_onecell_data *data;
588 + int ret;
589 + size_t num_clks, i;
590 + struct qcom_smd_rpm *rpm;
591 + struct clk_smd_rpm **rpm_smd_clks;
592 + const struct rpm_smd_clk_desc *desc;
593 +
594 + rpm = dev_get_drvdata(pdev->dev.parent);
595 + if (!rpm) {
596 + dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
597 + return -ENODEV;
598 + }
599 +
600 + desc = of_device_get_match_data(&pdev->dev);
601 + if (!desc)
602 + return -EINVAL;
603 +
604 + rpm_smd_clks = desc->clks;
605 + num_clks = desc->num_clks;
606 +
607 + rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
608 + GFP_KERNEL);
609 + if (!rcc)
610 + return -ENOMEM;
611 +
612 + hws = rcc->hws;
613 + data = &rcc->data;
614 + data->num = num_clks;
615 +
616 + for (i = 0; i < num_clks; i++) {
617 + if (!rpm_smd_clks[i]) {
618 + continue;
619 + }
620 +
621 + rpm_smd_clks[i]->rpm = rpm;
622 +
623 + ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
624 + if (ret)
625 + goto err;
626 + }
627 +
628 + ret = clk_smd_rpm_enable_scaling(rpm);
629 + if (ret)
630 + goto err;
631 +
632 + for (i = 0; i < num_clks; i++) {
633 + if (!rpm_smd_clks[i]) {
634 + data->hws[i] = ERR_PTR(-ENOENT);
635 + continue;
636 + }
637 +
638 + ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
639 + if (ret)
640 + goto err;
641 + }
642 +
643 + ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
644 + data);
645 + if (ret)
646 + goto err;
647 +
648 + return 0;
649 +err:
650 + dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
651 + return ret;
652 +}
653 +
654 +static int rpm_smd_clk_remove(struct platform_device *pdev)
655 +{
656 + of_clk_del_provider(pdev->dev.of_node);
657 + return 0;
658 +}
659 +
660 +static struct platform_driver rpm_smd_clk_driver = {
661 + .driver = {
662 + .name = "qcom-clk-smd-rpm",
663 + .of_match_table = rpm_smd_clk_match_table,
664 + },
665 + .probe = rpm_smd_clk_probe,
666 + .remove = rpm_smd_clk_remove,
667 +};
668 +
669 +static int __init rpm_smd_clk_init(void)
670 +{
671 + return platform_driver_register(&rpm_smd_clk_driver);
672 +}
673 +core_initcall(rpm_smd_clk_init);
674 +
675 +static void __exit rpm_smd_clk_exit(void)
676 +{
677 + platform_driver_unregister(&rpm_smd_clk_driver);
678 +}
679 +module_exit(rpm_smd_clk_exit);
680 +
681 +MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
682 +MODULE_LICENSE("GPL v2");
683 +MODULE_ALIAS("platform:qcom-clk-smd-rpm");
684 --- /dev/null
685 +++ b/include/dt-bindings/clock/qcom,rpmcc.h
686 @@ -0,0 +1,45 @@
687 +/*
688 + * Copyright 2015 Linaro Limited
689 + *
690 + * This software is licensed under the terms of the GNU General Public
691 + * License version 2, as published by the Free Software Foundation, and
692 + * may be copied, distributed, and modified under those terms.
693 + *
694 + * This program is distributed in the hope that it will be useful,
695 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
696 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
697 + * GNU General Public License for more details.
698 + */
699 +
700 +#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
701 +#define _DT_BINDINGS_CLK_MSM_RPMCC_H
702 +
703 +/* msm8916 */
704 +#define RPM_SMD_XO_CLK_SRC 0
705 +#define RPM_SMD_XO_A_CLK_SRC 1
706 +#define RPM_SMD_PCNOC_CLK 2
707 +#define RPM_SMD_PCNOC_A_CLK 3
708 +#define RPM_SMD_SNOC_CLK 4
709 +#define RPM_SMD_SNOC_A_CLK 5
710 +#define RPM_SMD_BIMC_CLK 6
711 +#define RPM_SMD_BIMC_A_CLK 7
712 +#define RPM_SMD_QDSS_CLK 8
713 +#define RPM_SMD_QDSS_A_CLK 9
714 +#define RPM_SMD_BB_CLK1 10
715 +#define RPM_SMD_BB_CLK1_A 11
716 +#define RPM_SMD_BB_CLK2 12
717 +#define RPM_SMD_BB_CLK2_A 13
718 +#define RPM_SMD_RF_CLK1 14
719 +#define RPM_SMD_RF_CLK1_A 15
720 +#define RPM_SMD_RF_CLK2 16
721 +#define RPM_SMD_RF_CLK2_A 17
722 +#define RPM_SMD_BB_CLK1_PIN 18
723 +#define RPM_SMD_BB_CLK1_A_PIN 19
724 +#define RPM_SMD_BB_CLK2_PIN 20
725 +#define RPM_SMD_BB_CLK2_A_PIN 21
726 +#define RPM_SMD_RF_CLK1_PIN 22
727 +#define RPM_SMD_RF_CLK1_A_PIN 23
728 +#define RPM_SMD_RF_CLK2_PIN 24
729 +#define RPM_SMD_RF_CLK2_A_PIN 25
730 +
731 +#endif
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