target/linux/ipq806x/patches-4.9/0039-clk-qcom-Add-HFPLL-driver.patch

   1 From patchwork Fri Dec  8 09:42:22 2017
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   5 Subject: [v4,04/12] clk: qcom: Add HFPLL driver
   6 From: Sricharan R <sricharan@codeaurora.org>
   7 X-Patchwork-Id: 10102079
   8 Message-Id: <1512726150-7204-5-git-send-email-sricharan@codeaurora.org>
   9 To: mturquette@baylibre.com, sboyd@codeaurora.org,
  10  devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
  11  linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
  12  viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
  13 Cc: sricharan@codeaurora.org
  14 Date: Fri,  8 Dec 2017 15:12:22 +0530
  15
  16 From: Stephen Boyd <sboyd@codeaurora.org>
  17
  18 On some devices (MSM8974 for example), the HFPLLs are
  19 instantiated within the Krait processor subsystem as separate
  20 register regions. Add a driver for these PLLs so that we can
  21 provide HFPLL clocks for use by the system.
  22
  23 Cc: <devicetree@vger.kernel.org>
  24 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  25 ---
  26  .../devicetree/bindings/clock/qcom,hfpll.txt       |  40 ++++++++
  27  drivers/clk/qcom/Kconfig                           |   8 ++
  28  drivers/clk/qcom/Makefile                          |   1 +
  29  drivers/clk/qcom/hfpll.c                           | 106 +++++++++++++++++++++
  30  4 files changed, 155 insertions(+)
  31  create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
  32  create mode 100644 drivers/clk/qcom/hfpll.c
  33
  34 --- /dev/null
  35 +++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
  36 @@ -0,0 +1,40 @@
  37 +High-Frequency PLL (HFPLL)
  38 +
  39 +PROPERTIES
  40 +
  41 +- compatible:
  42 +       Usage: required
  43 +       Value type: <string>
  44 +       Definition: must be "qcom,hfpll"
  45 +
  46 +- reg:
  47 +       Usage: required
  48 +       Value type: <prop-encoded-array>
  49 +       Definition: address and size of HPLL registers. An optional second
  50 +                   element specifies the address and size of the alias
  51 +                   register region.
  52 +
  53 +- clock-output-names:
  54 +       Usage: required
  55 +       Value type: <string>
  56 +       Definition: Name of the PLL. Typically hfpllX where X is a CPU number
  57 +                   starting at 0. Otherwise hfpll_Y where Y is more specific
  58 +                   such as "l2".
  59 +
  60 +Example:
  61 +
  62 +1) An HFPLL for the L2 cache.
  63 +
  64 +       clock-controller@f9016000 {
  65 +               compatible = "qcom,hfpll";
  66 +               reg = <0xf9016000 0x30>;
  67 +               clock-output-names = "hfpll_l2";
  68 +       };
  69 +
  70 +2) An HFPLL for CPU0. This HFPLL has the alias register region.
  71 +
  72 +       clock-controller@f908a000 {
  73 +               compatible = "qcom,hfpll";
  74 +               reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
  75 +               clock-output-names = "hfpll0";
  76 +       };
  77 --- a/drivers/clk/qcom/Kconfig
  78 +++ b/drivers/clk/qcom/Kconfig
  79 @@ -179,3 +179,11 @@ config MSM_MMCC_8996
  80           Support for the multimedia clock controller on msm8996 devices.
  81           Say Y if you want to support multimedia devices such as display,
  82           graphics, video encode/decode, camera, etc.
  83 +
  84 +config QCOM_HFPLL
  85 +       tristate "High-Frequency PLL (HFPLL) Clock Controller"
  86 +       depends on COMMON_CLK_QCOM
  87 +       help
  88 +         Support for the high-frequency PLLs present on Qualcomm devices.
  89 +         Say Y if you want to support CPU frequency scaling on devices
  90 +         such as MSM8974, APQ8084, etc.
  91 --- a/drivers/clk/qcom/Makefile
  92 +++ b/drivers/clk/qcom/Makefile
  93 @@ -32,3 +32,4 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8
  94  obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
  95  obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
  96  obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
  97 +obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
  98 --- /dev/null
  99 +++ b/drivers/clk/qcom/hfpll.c
 100 @@ -0,0 +1,106 @@
 101 +/*
 102 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
 103 + *
 104 + * This program is free software; you can redistribute it and/or modify
 105 + * it under the terms of the GNU General Public License version 2 and
 106 + * only version 2 as published by the Free Software Foundation.
 107 + *
 108 + * This program is distributed in the hope that it will be useful,
 109 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 110 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 111 + * GNU General Public License for more details.
 112 + */
 113 +
 114 +#include <linux/kernel.h>
 115 +#include <linux/init.h>
 116 +#include <linux/module.h>
 117 +#include <linux/platform_device.h>
 118 +#include <linux/of.h>
 119 +#include <linux/clk.h>
 120 +#include <linux/clk-provider.h>
 121 +#include <linux/regmap.h>
 122 +
 123 +#include "clk-regmap.h"
 124 +#include "clk-hfpll.h"
 125 +
 126 +static const struct hfpll_data hdata = {
 127 +       .mode_reg = 0x00,
 128 +       .l_reg = 0x04,
 129 +       .m_reg = 0x08,
 130 +       .n_reg = 0x0c,
 131 +       .user_reg = 0x10,
 132 +       .config_reg = 0x14,
 133 +       .config_val = 0x430405d,
 134 +       .status_reg = 0x1c,
 135 +       .lock_bit = 16,
 136 +
 137 +       .user_val = 0x8,
 138 +       .user_vco_mask = 0x100000,
 139 +       .low_vco_max_rate = 1248000000,
 140 +       .min_rate = 537600000UL,
 141 +       .max_rate = 2900000000UL,
 142 +};
 143 +
 144 +static const struct of_device_id qcom_hfpll_match_table[] = {
 145 +       { .compatible = "qcom,hfpll" },
 146 +       { }
 147 +};
 148 +MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
 149 +
 150 +static const struct regmap_config hfpll_regmap_config = {
 151 +       .reg_bits       = 32,
 152 +       .reg_stride     = 4,
 153 +       .val_bits       = 32,
 154 +       .max_register   = 0x30,
 155 +       .fast_io        = true,
 156 +};
 157 +
 158 +static int qcom_hfpll_probe(struct platform_device *pdev)
 159 +{
 160 +       struct resource *res;
 161 +       struct device *dev = &pdev->dev;
 162 +       void __iomem *base;
 163 +       struct regmap *regmap;
 164 +       struct clk_hfpll *h;
 165 +       struct clk_init_data init = {
 166 +               .parent_names = (const char *[]){ "xo" },
 167 +               .num_parents = 1,
 168 +               .ops = &clk_ops_hfpll,
 169 +       };
 170 +
 171 +       h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
 172 +       if (!h)
 173 +               return -ENOMEM;
 174 +
 175 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 176 +       base = devm_ioremap_resource(dev, res);
 177 +       if (IS_ERR(base))
 178 +               return PTR_ERR(base);
 179 +
 180 +       regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
 181 +       if (IS_ERR(regmap))
 182 +               return PTR_ERR(regmap);
 183 +
 184 +       if (of_property_read_string_index(dev->of_node, "clock-output-names",
 185 +                                         0, &init.name))
 186 +               return -ENODEV;
 187 +
 188 +       h->d = &hdata;
 189 +       h->clkr.hw.init = &init;
 190 +       spin_lock_init(&h->lock);
 191 +
 192 +       return devm_clk_register_regmap(&pdev->dev, &h->clkr);
 193 +}
 194 +
 195 +static struct platform_driver qcom_hfpll_driver = {
 196 +       .probe          = qcom_hfpll_probe,
 197 +       .driver         = {
 198 +               .name   = "qcom-hfpll",
 199 +               .of_match_table = qcom_hfpll_match_table,
 200 +       },
 201 +};
 202 +module_platform_driver(qcom_hfpll_driver);
 203 +
 204 +MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
 205 +MODULE_LICENSE("GPL v2");
 206 +MODULE_ALIAS("platform:qcom-hfpll");