target/linux/ipq806x/patches-4.9/0045-cpufreq-Add-module-to-register-cpufreq-on-Krait-CPUs.patch

   1 From 42eea6bc2858ab9649cf6931455e391e48939685 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Fri, 20 Mar 2015 23:45:31 -0700
   4 Subject: [PATCH 45/69] cpufreq: Add module to register cpufreq on Krait CPUs
   5
   6 Register a cpufreq-generic device whenever we detect that a
   7 "qcom,krait" compatible CPU is present in DT.
   8
   9 Cc: <devicetree@vger.kernel.org>
  10 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  11 ---
  12  .../devicetree/bindings/arm/msm/qcom,pvs.txt       |  38 ++++
  13  drivers/cpufreq/Kconfig.arm                        |   9 +
  14  drivers/cpufreq/Makefile                           |   1 +
  15  drivers/cpufreq/qcom-cpufreq.c                     | 204 +++++++++++++++++++++
  16  4 files changed, 252 insertions(+)
  17  create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
  18  create mode 100644 drivers/cpufreq/qcom-cpufreq.c
  19
  20 --- /dev/null
  21 +++ b/Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
  22 @@ -0,0 +1,38 @@
  23 +Qualcomm Process Voltage Scaling Tables
  24 +
  25 +The node name is required to be "qcom,pvs". There shall only be one
  26 +such node present in the root of the tree.
  27 +
  28 +PROPERTIES
  29 +
  30 +- qcom,pvs-format-a or qcom,pvs-format-b:
  31 +       Usage: required
  32 +       Value type: <empty>
  33 +       Definition: Indicates the format of qcom,speedX-pvsY-bin-vZ properties.
  34 +                   If qcom,pvs-format-a is used the table is two columns
  35 +                   (frequency and voltage in that order). If qcom,pvs-format-b                     is used the table is three columns (frequency, voltage,
  36 +                   and current in that order).
  37 +
  38 +- qcom,speedX-pvsY-bin-vZ:
  39 +       Usage: required
  40 +       Value type: <prop-encoded-array>
  41 +       Definition: The PVS table corresponding to the speed bin X, pvs bin Y,
  42 +                   and version Z.
  43 +Example:
  44 +
  45 +       qcom,pvs {
  46 +               qcom,pvs-format-a;
  47 +               qcom,speed0-pvs0-bin-v0 =
  48 +                       <  384000000  950000 >,
  49 +                       <  486000000  975000 >,
  50 +                       <  594000000 1000000 >,
  51 +                       <  702000000 1025000 >,
  52 +                       <  810000000 1075000 >,
  53 +                       <  918000000 1100000 >,
  54 +                       < 1026000000 1125000 >,
  55 +                       < 1134000000 1175000 >,
  56 +                       < 1242000000 1200000 >,
  57 +                       < 1350000000 1225000 >,
  58 +                       < 1458000000 1237500 >,
  59 +                       < 1512000000 1250000 >;
  60 +       };
  61 --- a/drivers/cpufreq/Kconfig.arm
  62 +++ b/drivers/cpufreq/Kconfig.arm
  63 @@ -88,6 +88,15 @@ config ARM_OMAP2PLUS_CPUFREQ
  64         depends on ARCH_OMAP2PLUS
  65         default ARCH_OMAP2PLUS
  66
  67 +config ARM_QCOM_CPUFREQ
  68 +       tristate "Qualcomm based"
  69 +       depends on ARCH_QCOM
  70 +       select PM_OPP
  71 +       help
  72 +         This adds the CPUFreq driver for Qualcomm SoC based boards.
  73 +
  74 +         If in doubt, say N.
  75 +
  76  config ARM_S3C_CPUFREQ
  77         bool
  78         help
  79 --- a/drivers/cpufreq/Makefile
  80 +++ b/drivers/cpufreq/Makefile
  81 @@ -62,6 +62,7 @@ obj-$(CONFIG_ARM_MT8173_CPUFREQ)      += mt81
  82  obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)    += omap-cpufreq.o
  83  obj-$(CONFIG_ARM_PXA2xx_CPUFREQ)       += pxa2xx-cpufreq.o
  84  obj-$(CONFIG_PXA3xx)                   += pxa3xx-cpufreq.o
  85 +obj-$(CONFIG_ARM_QCOM_CPUFREQ)         += qcom-cpufreq.o
  86  obj-$(CONFIG_ARM_S3C24XX_CPUFREQ)      += s3c24xx-cpufreq.o
  87  obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o
  88  obj-$(CONFIG_ARM_S3C2410_CPUFREQ)      += s3c2410-cpufreq.o
  89 --- /dev/null
  90 +++ b/drivers/cpufreq/qcom-cpufreq.c
  91 @@ -0,0 +1,204 @@
  92 +/* Copyright (c) 2014, The Linux Foundation. All rights reserved.
  93 + *
  94 + * This program is free software; you can redistribute it and/or modify
  95 + * it under the terms of the GNU General Public License version 2 and
  96 + * only version 2 as published by the Free Software Foundation.
  97 + *
  98 + * This program is distributed in the hope that it will be useful,
  99 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 100 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 101 + * GNU General Public License for more details.
 102 + */
 103 +
 104 +#include <linux/cpu.h>
 105 +#include <linux/err.h>
 106 +#include <linux/init.h>
 107 +#include <linux/io.h>
 108 +#include <linux/kernel.h>
 109 +#include <linux/module.h>
 110 +#include <linux/of.h>
 111 +#include <linux/platform_device.h>
 112 +#include <linux/pm_opp.h>
 113 +#include <linux/slab.h>
 114 +#include <linux/cpufreq-dt.h>
 115 +
 116 +static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver)
 117 +{
 118 +       void __iomem *base;
 119 +       u32 pte_efuse;
 120 +
 121 +       *speed = *pvs = *pvs_ver = 0;
 122 +
 123 +       base = ioremap(0x007000c0, 4);
 124 +       if (!base) {
 125 +               pr_warn("Unable to read efuse data. Defaulting to 0!\n");
 126 +               return;
 127 +       }
 128 +
 129 +       pte_efuse = readl_relaxed(base);
 130 +       iounmap(base);
 131 +
 132 +       *speed = pte_efuse & 0xf;
 133 +       if (*speed == 0xf)
 134 +               *speed = (pte_efuse >> 4) & 0xf;
 135 +
 136 +       if (*speed == 0xf) {
 137 +               *speed = 0;
 138 +               pr_warn("Speed bin: Defaulting to %d\n", *speed);
 139 +       } else {
 140 +               pr_info("Speed bin: %d\n", *speed);
 141 +       }
 142 +
 143 +       *pvs = (pte_efuse >> 10) & 0x7;
 144 +       if (*pvs == 0x7)
 145 +               *pvs = (pte_efuse >> 13) & 0x7;
 146 +
 147 +       if (*pvs == 0x7) {
 148 +               *pvs = 0;
 149 +               pr_warn("PVS bin: Defaulting to %d\n", *pvs);
 150 +       } else {
 151 +               pr_info("PVS bin: %d\n", *pvs);
 152 +       }
 153 +}
 154 +
 155 +static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver)
 156 +{
 157 +       u32 pte_efuse, redundant_sel;
 158 +       void __iomem *base;
 159 +
 160 +       *speed = 0;
 161 +       *pvs = 0;
 162 +       *pvs_ver = 0;
 163 +
 164 +       base = ioremap(0xfc4b80b0, 8);
 165 +       if (!base) {
 166 +               pr_warn("Unable to read efuse data. Defaulting to 0!\n");
 167 +               return;
 168 +       }
 169 +
 170 +       pte_efuse = readl_relaxed(base);
 171 +       redundant_sel = (pte_efuse >> 24) & 0x7;
 172 +       *speed = pte_efuse & 0x7;
 173 +       /* 4 bits of PVS are in efuse register bits 31, 8-6. */
 174 +       *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
 175 +       *pvs_ver = (pte_efuse >> 4) & 0x3;
 176 +
 177 +       switch (redundant_sel) {
 178 +       case 1:
 179 +               *speed = (pte_efuse >> 27) & 0xf;
 180 +               break;
 181 +       case 2:
 182 +               *pvs = (pte_efuse >> 27) & 0xf;
 183 +               break;
 184 +       }
 185 +
 186 +       /* Check SPEED_BIN_BLOW_STATUS */
 187 +       if (pte_efuse & BIT(3)) {
 188 +               pr_info("Speed bin: %d\n", *speed);
 189 +       } else {
 190 +               pr_warn("Speed bin not set. Defaulting to 0!\n");
 191 +               *speed = 0;
 192 +       }
 193 +
 194 +       /* Check PVS_BLOW_STATUS */
 195 +       pte_efuse = readl_relaxed(base + 0x4) & BIT(21);
 196 +       if (pte_efuse) {
 197 +               pr_info("PVS bin: %d\n", *pvs);
 198 +       } else {
 199 +               pr_warn("PVS bin not set. Defaulting to 0!\n");
 200 +               *pvs = 0;
 201 +       }
 202 +
 203 +       pr_info("PVS version: %d\n", *pvs_ver);
 204 +       iounmap(base);
 205 +}
 206 +
 207 +static int __init qcom_cpufreq_populate_opps(void)
 208 +{
 209 +       int len, rows, cols, i, k, speed, pvs, pvs_ver;
 210 +       char table_name[] = "qcom,speedXX-pvsXX-bin-vXX";
 211 +       struct device_node *np;
 212 +       struct device *dev;
 213 +       int cpu = 0;
 214 +
 215 +       np = of_find_node_by_name(NULL, "qcom,pvs");
 216 +       if (!np)
 217 +               return -ENODEV;
 218 +
 219 +       if (of_property_read_bool(np, "qcom,pvs-format-a")) {
 220 +               get_krait_bin_format_a(&speed, &pvs, &pvs_ver);
 221 +               cols = 2;
 222 +       } else if (of_property_read_bool(np, "qcom,pvs-format-b")) {
 223 +               get_krait_bin_format_b(&speed, &pvs, &pvs_ver);
 224 +               cols = 3;
 225 +       } else {
 226 +               return -ENODEV;
 227 +       }
 228 +
 229 +       snprintf(table_name, sizeof(table_name),
 230 +                       "qcom,speed%d-pvs%d-bin-v%d", speed, pvs, pvs_ver);
 231 +
 232 +       if (!of_find_property(np, table_name, &len))
 233 +               return -EINVAL;
 234 +
 235 +       len /= sizeof(u32);
 236 +       if (len % cols || len == 0)
 237 +               return -EINVAL;
 238 +
 239 +       rows = len / cols;
 240 +
 241 +       for (i = 0, k = 0; i < rows; i++) {
 242 +               u32 freq, volt;
 243 +
 244 +               of_property_read_u32_index(np, table_name, k++, &freq);
 245 +               of_property_read_u32_index(np, table_name, k++, &volt);
 246 +               while (k % cols)
 247 +                       k++; /* Skip uA entries if present */
 248 +               for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
 249 +                       dev = get_cpu_device(cpu);
 250 +                       if (!dev)
 251 +                               return -ENODEV;
 252 +                       if (dev_pm_opp_add(dev, freq, volt))
 253 +                               pr_warn("failed to add OPP %u\n", freq);
 254 +               }
 255 +       }
 256 +
 257 +       return 0;
 258 +}
 259 +
 260 +static int __init qcom_cpufreq_driver_init(void)
 261 +{
 262 +       struct cpufreq_dt_platform_data pdata = { .independent_clocks = true };
 263 +       struct platform_device_info devinfo = {
 264 +               .name = "cpufreq-dt",
 265 +               .data = &pdata,
 266 +               .size_data = sizeof(pdata),
 267 +       };
 268 +       struct device *cpu_dev;
 269 +       struct device_node *np;
 270 +       int ret;
 271 +
 272 +       cpu_dev = get_cpu_device(0);
 273 +       if (!cpu_dev)
 274 +               return -ENODEV;
 275 +
 276 +       np = of_node_get(cpu_dev->of_node);
 277 +       if (!np)
 278 +               return -ENOENT;
 279 +
 280 +       if (!of_device_is_compatible(np, "qcom,krait")) {
 281 +               of_node_put(np);
 282 +               return -ENODEV;
 283 +       }
 284 +       of_node_put(np);
 285 +
 286 +       ret = qcom_cpufreq_populate_opps();
 287 +       if (ret)
 288 +               return ret;
 289 +
 290 +       return PTR_ERR_OR_ZERO(platform_device_register_full(&devinfo));
 291 +}
 292 +module_init(qcom_cpufreq_driver_init);
 293 +
 294 +MODULE_DESCRIPTION("Qualcomm CPUfreq driver");
 295 +MODULE_LICENSE("GPL v2");