target/linux/ipq806x/patches-4.9/859-msm-pinctrl-Add-support-to-configure-ipq40xx-GPIO_PU.patch

   1 From e77af7de404eb464f7da9e0daeb8b362cc66a7ba Mon Sep 17 00:00:00 2001
   2 From: Ram Chandra Jangir <rjangir@codeaurora.org>
   3 Date: Tue, 9 May 2017 11:45:00 +0530
   4 Subject: [PATCH] msm: pinctrl: Add support to configure ipq40xx GPIO_PULL bits
   5
   6 GPIO_PULL bits configurations in TLMM_GPIO_CFG register
   7 differs for IPQ40xx from rest of the other qcom SoC's.
   8 This change add support to configure the msm_gpio_pull
   9 bits for ipq40xx, It is required to fix the proper
  10 configurations of gpio-pull bits for nand pins mux.
  11
  12 IPQ40xx SoC:
  13 2'b10: Internal pull up enable.
  14 2'b11: Unsupport
  15
  16 For other SoC's:
  17 2'b10: Keeper
  18 2'b11: Pull-Up
  19
  20 Signed-off-by: Ram Chandra Jangir <rjangir@codeaurora.org>
  21 ---
  22  drivers/pinctrl/qcom/pinctrl-apq8064.c |  1 +
  23  drivers/pinctrl/qcom/pinctrl-apq8084.c |  1 +
  24  drivers/pinctrl/qcom/pinctrl-ipq4019.c |  8 ++++++++
  25  drivers/pinctrl/qcom/pinctrl-ipq8064.c |  1 +
  26  drivers/pinctrl/qcom/pinctrl-mdm9615.c |  1 +
  27  drivers/pinctrl/qcom/pinctrl-msm.c     | 21 ++++++++-------------
  28  drivers/pinctrl/qcom/pinctrl-msm.h     | 19 +++++++++++++++++++
  29  drivers/pinctrl/qcom/pinctrl-msm8660.c |  1 +
  30  drivers/pinctrl/qcom/pinctrl-msm8916.c |  1 +
  31  drivers/pinctrl/qcom/pinctrl-msm8960.c |  1 +
  32  drivers/pinctrl/qcom/pinctrl-msm8x74.c |  1 +
  33  11 files changed, 43 insertions(+), 13 deletions(-)
  34
  35 --- a/drivers/pinctrl/qcom/pinctrl-apq8064.c
  36 +++ b/drivers/pinctrl/qcom/pinctrl-apq8064.c
  37 @@ -597,6 +597,7 @@ static const struct msm_pinctrl_soc_data
  38         .groups = apq8064_groups,
  39         .ngroups = ARRAY_SIZE(apq8064_groups),
  40         .ngpios = NUM_GPIO_PINGROUPS,
  41 +       .gpio_pull = &msm_gpio_pull,
  42  };
  43
  44  static int apq8064_pinctrl_probe(struct platform_device *pdev)
  45 --- a/drivers/pinctrl/qcom/pinctrl-apq8084.c
  46 +++ b/drivers/pinctrl/qcom/pinctrl-apq8084.c
  47 @@ -1206,6 +1206,7 @@ static const struct msm_pinctrl_soc_data
  48         .groups = apq8084_groups,
  49         .ngroups = ARRAY_SIZE(apq8084_groups),
  50         .ngpios = NUM_GPIO_PINGROUPS,
  51 +       .gpio_pull = &msm_gpio_pull,
  52  };
  53
  54  static int apq8084_pinctrl_probe(struct platform_device *pdev)
  55 --- a/drivers/pinctrl/qcom/pinctrl-ipq4019.c
  56 +++ b/drivers/pinctrl/qcom/pinctrl-ipq4019.c
  57 @@ -1531,6 +1531,13 @@ static const struct msm_pingroup ipq4019
  58         PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
  59  };
  60
  61 +static const struct msm_pinctrl_gpio_pull ipq4019_gpio_pull = {
  62 +       .no_pull = 0,
  63 +       .pull_down = 1,
  64 +       .keeper = 0,
  65 +       .pull_up = 2,
  66 +};
  67 +
  68  static const struct msm_pinctrl_soc_data ipq4019_pinctrl = {
  69         .pins = ipq4019_pins,
  70         .npins = ARRAY_SIZE(ipq4019_pins),
  71 @@ -1539,6 +1546,7 @@ static const struct msm_pinctrl_soc_data
  72         .groups = ipq4019_groups,
  73         .ngroups = ARRAY_SIZE(ipq4019_groups),
  74         .ngpios = 100,
  75 +       .gpio_pull = &ipq4019_gpio_pull,
  76  };
  77
  78  static int ipq4019_pinctrl_probe(struct platform_device *pdev)
  79 --- a/drivers/pinctrl/qcom/pinctrl-ipq8064.c
  80 +++ b/drivers/pinctrl/qcom/pinctrl-ipq8064.c
  81 @@ -630,6 +630,7 @@ static const struct msm_pinctrl_soc_data
  82         .groups = ipq8064_groups,
  83         .ngroups = ARRAY_SIZE(ipq8064_groups),
  84         .ngpios = NUM_GPIO_PINGROUPS,
  85 +       .gpio_pull = &msm_gpio_pull,
  86  };
  87
  88  static int ipq8064_pinctrl_probe(struct platform_device *pdev)
  89 --- a/drivers/pinctrl/qcom/pinctrl-mdm9615.c
  90 +++ b/drivers/pinctrl/qcom/pinctrl-mdm9615.c
  91 @@ -444,6 +444,7 @@ static const struct msm_pinctrl_soc_data
  92         .groups = mdm9615_groups,
  93         .ngroups = ARRAY_SIZE(mdm9615_groups),
  94         .ngpios = NUM_GPIO_PINGROUPS,
  95 +       .gpio_pull = &msm_gpio_pull,
  96  };
  97
  98  static int mdm9615_pinctrl_probe(struct platform_device *pdev)
  99 --- a/drivers/pinctrl/qcom/pinctrl-msm.c
 100 +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
 101 @@ -203,11 +203,6 @@ static int msm_config_reg(struct msm_pin
 102         return 0;
 103  }
 104
 105 -#define MSM_NO_PULL    0
 106 -#define MSM_PULL_DOWN  1
 107 -#define MSM_KEEPER     2
 108 -#define MSM_PULL_UP    3
 109 -
 110  static unsigned msm_regval_to_drive(u32 val)
 111  {
 112         return (val + 1) * 2;
 113 @@ -238,16 +233,16 @@ static int msm_config_group_get(struct p
 114         /* Convert register value to pinconf value */
 115         switch (param) {
 116         case PIN_CONFIG_BIAS_DISABLE:
 117 -               arg = arg == MSM_NO_PULL;
 118 +               arg = arg == pctrl->soc->gpio_pull->no_pull;
 119                 break;
 120         case PIN_CONFIG_BIAS_PULL_DOWN:
 121 -               arg = arg == MSM_PULL_DOWN;
 122 +               arg = arg == pctrl->soc->gpio_pull->pull_down;
 123                 break;
 124         case PIN_CONFIG_BIAS_BUS_HOLD:
 125 -               arg = arg == MSM_KEEPER;
 126 +               arg = arg == pctrl->soc->gpio_pull->keeper;
 127                 break;
 128         case PIN_CONFIG_BIAS_PULL_UP:
 129 -               arg = arg == MSM_PULL_UP;
 130 +               arg = arg == pctrl->soc->gpio_pull->pull_up;
 131                 break;
 132         case PIN_CONFIG_DRIVE_STRENGTH:
 133                 arg = msm_regval_to_drive(arg);
 134 @@ -304,16 +299,16 @@ static int msm_config_group_set(struct p
 135                 /* Convert pinconf values to register values */
 136                 switch (param) {
 137                 case PIN_CONFIG_BIAS_DISABLE:
 138 -                       arg = MSM_NO_PULL;
 139 +                       arg = pctrl->soc->gpio_pull->no_pull;
 140                         break;
 141                 case PIN_CONFIG_BIAS_PULL_DOWN:
 142 -                       arg = MSM_PULL_DOWN;
 143 +                       arg = pctrl->soc->gpio_pull->pull_down;
 144                         break;
 145                 case PIN_CONFIG_BIAS_BUS_HOLD:
 146 -                       arg = MSM_KEEPER;
 147 +                       arg = pctrl->soc->gpio_pull->keeper;
 148                         break;
 149                 case PIN_CONFIG_BIAS_PULL_UP:
 150 -                       arg = MSM_PULL_UP;
 151 +                       arg = pctrl->soc->gpio_pull->pull_up;
 152                         break;
 153                 case PIN_CONFIG_DRIVE_STRENGTH:
 154                         /* Check for invalid values */
 155 --- a/drivers/pinctrl/qcom/pinctrl-msm.h
 156 +++ b/drivers/pinctrl/qcom/pinctrl-msm.h
 157 @@ -98,6 +98,16 @@ struct msm_pingroup {
 158  };
 159
 160  /**
 161 + * struct msm_pinctrl_gpio_pull - pinctrl pull value bit field descriptor
 162 + */
 163 +struct msm_pinctrl_gpio_pull {
 164 +       unsigned no_pull;
 165 +       unsigned pull_down;
 166 +       unsigned keeper;
 167 +       unsigned pull_up;
 168 +};
 169 +
 170 +/**
 171   * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
 172   * @pins:       An array describing all pins the pin controller affects.
 173   * @npins:      The number of entries in @pins.
 174 @@ -106,6 +116,7 @@ struct msm_pingroup {
 175   * @groups:     An array describing all pin groups the pin SoC supports.
 176   * @ngroups:    The numbmer of entries in @groups.
 177   * @ngpio:      The number of pingroups the driver should expose as GPIOs.
 178 + * @gpio_pull_val: The pull value bit field descriptor.
 179   */
 180  struct msm_pinctrl_soc_data {
 181         const struct pinctrl_pin_desc *pins;
 182 @@ -115,6 +126,14 @@ struct msm_pinctrl_soc_data {
 183         const struct msm_pingroup *groups;
 184         unsigned ngroups;
 185         unsigned ngpios;
 186 +       const struct msm_pinctrl_gpio_pull *gpio_pull;
 187 +};
 188 +
 189 +static const struct msm_pinctrl_gpio_pull msm_gpio_pull = {
 190 +       .no_pull = 0,
 191 +       .pull_down = 1,
 192 +       .keeper = 2,
 193 +       .pull_up = 3,
 194  };
 195
 196  int msm_pinctrl_probe(struct platform_device *pdev,
 197 --- a/drivers/pinctrl/qcom/pinctrl-msm8660.c
 198 +++ b/drivers/pinctrl/qcom/pinctrl-msm8660.c
 199 @@ -979,6 +979,7 @@ static const struct msm_pinctrl_soc_data
 200         .groups = msm8660_groups,
 201         .ngroups = ARRAY_SIZE(msm8660_groups),
 202         .ngpios = NUM_GPIO_PINGROUPS,
 203 +       .gpio_pull = &msm_gpio_pull,
 204  };
 205
 206  static int msm8660_pinctrl_probe(struct platform_device *pdev)
 207 --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c
 208 +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c
 209 @@ -967,6 +967,7 @@ static const struct msm_pinctrl_soc_data
 210         .groups = msm8916_groups,
 211         .ngroups = ARRAY_SIZE(msm8916_groups),
 212         .ngpios = NUM_GPIO_PINGROUPS,
 213 +       .gpio_pull = &msm_gpio_pull,
 214  };
 215
 216  static int msm8916_pinctrl_probe(struct platform_device *pdev)
 217 --- a/drivers/pinctrl/qcom/pinctrl-msm8960.c
 218 +++ b/drivers/pinctrl/qcom/pinctrl-msm8960.c
 219 @@ -1244,6 +1244,7 @@ static const struct msm_pinctrl_soc_data
 220         .groups = msm8960_groups,
 221         .ngroups = ARRAY_SIZE(msm8960_groups),
 222         .ngpios = NUM_GPIO_PINGROUPS,
 223 +       .gpio_pull = &msm_gpio_pull,
 224  };
 225
 226  static int msm8960_pinctrl_probe(struct platform_device *pdev)
 227 --- a/drivers/pinctrl/qcom/pinctrl-msm8x74.c
 228 +++ b/drivers/pinctrl/qcom/pinctrl-msm8x74.c
 229 @@ -1069,6 +1069,7 @@ static const struct msm_pinctrl_soc_data
 230         .groups = msm8x74_groups,
 231         .ngroups = ARRAY_SIZE(msm8x74_groups),
 232         .ngpios = NUM_GPIO_PINGROUPS,
 233 +       .gpio_pull = &msm_gpio_pull,
 234  };
 235
 236  static int msm8x74_pinctrl_probe(struct platform_device *pdev)