target/linux/ipq806x/patches-5.10/082-ipq8064-dtsi-tweaks.patch

   1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
   2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
   3 @@ -20,7 +20,7 @@
   4                 #address-cells = <1>;
   5                 #size-cells = <0>;
   6
   7 -               cpu@0 {
   8 +               cpu0: cpu@0 {
   9                         compatible = "qcom,krait";
  10                         enable-method = "qcom,kpss-acc-v1";
  11                         device_type = "cpu";
  12 @@ -30,7 +30,7 @@
  13                         qcom,saw = <&saw0>;
  14                 };
  15
  16 -               cpu@1 {
  17 +               cpu1: cpu@1 {
  18                         compatible = "qcom,krait";
  19                         enable-method = "qcom,kpss-acc-v1";
  20                         device_type = "cpu";
  21 @@ -67,7 +67,7 @@
  22                         no-map;
  23                 };
  24
  25 -               smem@41000000 {
  26 +               smem: smem@41000000 {
  27                         reg = <0x41000000 0x200000>;
  28                         no-map;
  29                 };
  30 @@ -128,6 +128,7 @@
  31                         gpio-ranges = <&qcom_pinmux 0 0 69>;
  32                         #gpio-cells = <2>;
  33                         interrupt-controller;
  34 +                       #address-cells = <0>;
  35                         #interrupt-cells = <2>;
  36                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
  37
  38 @@ -155,6 +156,7 @@
  39                                         function = "pcie3_rst";
  40                                         drive-strength = <12>;
  41                                         bias-disable;
  42 +                                       output-low;
  43                                 };
  44                         };
  45
  46 @@ -190,6 +192,7 @@
  47                 intc: interrupt-controller@2000000 {
  48                         compatible = "qcom,msm-qgic2";
  49                         interrupt-controller;
  50 +                       #address-cells = <0>;
  51                         #interrupt-cells = <3>;
  52                         reg = <0x02000000 0x1000>,
  53                               <0x02002000 0x1000>;
  54 @@ -219,21 +222,23 @@
  55                 acc0: clock-controller@2088000 {
  56                         compatible = "qcom,kpss-acc-v1";
  57                         reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
  58 +                       clock-output-names = "acpu0_aux";
  59                 };
  60
  61                 acc1: clock-controller@2098000 {
  62                         compatible = "qcom,kpss-acc-v1";
  63                         reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
  64 +                       clock-output-names = "acpu1_aux";
  65                 };
  66
  67                 saw0: regulator@2089000 {
  68 -                       compatible = "qcom,saw2";
  69 +                       compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  70                         reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
  71                         regulator;
  72                 };
  73
  74                 saw1: regulator@2099000 {
  75 -                       compatible = "qcom,saw2";
  76 +                       compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
  77                         reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
  78                         regulator;
  79                 };
  80 @@ -251,7 +256,7 @@
  81
  82                         syscon-tcsr = <&tcsr>;
  83
  84 -                       serial@12490000 {
  85 +                       gsbi2_serial: serial@12490000 {
  86                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  87                                 reg = <0x12490000 0x1000>,
  88                                       <0x12480000 0x1000>;
  89 @@ -326,7 +331,7 @@
  90
  91                         syscon-tcsr = <&tcsr>;
  92
  93 -                       serial@1a240000 {
  94 +                       gsbi5_serial: serial@1a240000 {
  95                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
  96                                 reg = <0x1a240000 0x1000>,
  97                                       <0x1a200000 0x1000>;
  98 @@ -397,7 +402,7 @@
  99                         status = "disabled";
 100                 };
 101
 102 -               sata@29000000 {
 103 +               sata: sata@29000000 {
 104                         compatible = "qcom,ipq806x-ahci", "generic-ahci";
 105                         reg = <0x29000000 0x180>;
 106
 107 @@ -430,13 +435,35 @@
 108                         reg = <0x00700000 0x1000>;
 109                         #address-cells = <1>;
 110                         #size-cells = <1>;
 111 +
 112 +                       tsens_calib: calib@400 {
 113 +                               reg = <0x400 0xb>;
 114 +                       };
 115 +                       tsens_backup: backup@410 {
 116 +                               reg = <0x410 0xb>;
 117 +                       };
 118 +                       speedbin_efuse: speedbin@0c0 {
 119 +                               reg = <0x0c0 0x4>;
 120 +                       };
 121                 };
 122
 123                 gcc: clock-controller@900000 {
 124 -                       compatible = "qcom,gcc-ipq8064";
 125 +                       compatible = "qcom,gcc-ipq8064", "syscon";
 126                         reg = <0x00900000 0x4000>;
 127                         #clock-cells = <1>;
 128                         #reset-cells = <1>;
 129 +                       #power-domain-cells = <1>;
 130 +
 131 +                       tsens: thermal-sensor@900000 {
 132 +                               compatible = "qcom,ipq8064-tsens";
 133 +
 134 +                               nvmem-cells = <&tsens_calib>, <&tsens_backup>;
 135 +                               nvmem-cell-names = "calib", "calib_backup";
 136 +                               interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
 137 +                               interrupt-names = "uplow";
 138 +                               #thermal-sensor-cells = <1>;
 139 +                               #qcom,sensors = <11>;
 140 +                       };
 141                 };
 142
 143                 tcsr: syscon@1a400000 {
 144 @@ -740,13 +767,13 @@
 145                         qcom,ee = <0>;
 146                 };
 147
 148 -               amba {
 149 -                       compatible = "simple-bus";
 150 +               amba: amba {
 151 +                       compatible = "arm,amba-bus";
 152                         #address-cells = <1>;
 153                         #size-cells = <1>;
 154                         ranges;
 155
 156 -                       sdcc@12400000 {
 157 +                       sdcc1: sdcc@12400000 {
 158                                 status          = "disabled";
 159                                 compatible      = "arm,pl18x", "arm,primecell";
 160                                 arm,primecell-periphid = <0x00051180>;
 161 @@ -760,13 +787,12 @@
 162                                 non-removable;
 163                                 cap-sd-highspeed;
 164                                 cap-mmc-highspeed;
 165 -                               mmc-ddr-1_8v;
 166                                 vmmc-supply = <&vsdcc_fixed>;
 167                                 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
 168                                 dma-names = "tx", "rx";
 169                         };
 170
 171 -                       sdcc@12180000 {
 172 +                       sdcc3: sdcc@12180000 {
 173                                 compatible      = "arm,pl18x", "arm,primecell";
 174                                 arm,primecell-periphid = <0x00051180>;
 175                                 status          = "disabled";