target/linux/ipq806x/patches-5.4/093-7-v5.8-ipq806x-PCI-qcom-Add-ipq8064-rev2-variant.patch

   1 From 8df093fe2ae1717389df0dcdc620c02cc35abb21 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Mon, 15 Jun 2020 23:06:05 +0200
   4 Subject: PCI: qcom: Add ipq8064 rev2 variant
   5
   6 Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit
   7 different offset based on the revision.
   8
   9 Link: https://lore.kernel.org/r/20200615210608.21469-10-ansuelsmth@gmail.com
  10 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  11 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  12 Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  13 ---
  14  drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
  15  1 file changed, 3 insertions(+), 1 deletion(-)
  16
  17 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  18 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  19 @@ -368,7 +368,8 @@ static int qcom_pcie_init_2_1_0(struct q
  20         val &= ~BIT(0);
  21         writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
  22
  23 -       if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
  24 +       if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
  25 +           of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
  26                 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
  27                                PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
  28                                PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
  29 @@ -1328,6 +1329,7 @@ err_pm_runtime_put:
  30  static const struct of_device_id qcom_pcie_match[] = {
  31         { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
  32         { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
  33 +       { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
  34         { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
  35         { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
  36         { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },