target/linux/ipq806x/patches-5.4/095-1-v5.9-phy-qualcomm-add-qcom-ipq806x-dwc-usb-phy-driver.patch

   1 From ef19b117b83466e1c030368101a24367a34be7f0 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Fri, 17 Jul 2020 15:16:31 +0200
   4 Subject: phy: qualcomm: add qcom ipq806x dwc usb phy driver
   5
   6 This has lost in the original push for the dwc3 qcom driver.
   7 This is needed for ipq806x SoC as without this the usb ports
   8 doesn't work at all.
   9
  10 Signed-off-by: Andy Gross <agross@codeaurora.org>
  11 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  12 Tested-by: Jonathan McDowell <noodles@earth.li>
  13 Link: https://lore.kernel.org/r/20200717131635.11076-1-ansuelsmth@gmail.com
  14 Signed-off-by: Vinod Koul <vkoul@kernel.org>
  15 ---
  16
  17 Light modification to Kconfig as some config are missing in kernel 5.4
  18
  19  drivers/phy/qualcomm/Kconfig                |  10 +
  20  drivers/phy/qualcomm/Makefile               |   1 +
  21  drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 571 ++++++++++++++++++++++++++++
  22  3 files changed, 582 insertions(+)
  23  create mode 100644 drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
  24
  25 --- a/drivers/phy/qualcomm/Kconfig
  26 +++ b/drivers/phy/qualcomm/Kconfig
  27 @@ -91,3 +91,13 @@ config PHY_QCOM_USB_HSIC
  28         select GENERIC_PHY
  29         help
  30           Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.
  31 +
  32 +config PHY_QCOM_IPQ806X_USB
  33 +       tristate "Qualcomm IPQ806x DWC3 USB PHY driver"
  34 +       depends on HAS_IOMEM
  35 +       depends on OF && (ARCH_QCOM || COMPILE_TEST)
  36 +       select GENERIC_PHY
  37 +       help
  38 +         This option enables support for the Synopsis PHYs present inside the
  39 +         Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports
  40 +         both HS and SS PHY controllers.
  41 --- a/drivers/phy/qualcomm/Makefile
  42 +++ b/drivers/phy/qualcomm/Makefile
  43 @@ -10,3 +10,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM)               += phy-
  44  obj-$(CONFIG_PHY_QCOM_UFS_20NM)                += phy-qcom-ufs-qmp-20nm.o
  45  obj-$(CONFIG_PHY_QCOM_USB_HS)          += phy-qcom-usb-hs.o
  46  obj-$(CONFIG_PHY_QCOM_USB_HSIC)        += phy-qcom-usb-hsic.o
  47 +obj-$(CONFIG_PHY_QCOM_IPQ806X_USB)             += phy-qcom-ipq806x-usb.o
  48 --- /dev/null
  49 +++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
  50 @@ -0,0 +1,571 @@
  51 +// SPDX-License-Identifier: GPL-2.0-only
  52 +
  53 +#include <linux/clk.h>
  54 +#include <linux/err.h>
  55 +#include <linux/io.h>
  56 +#include <linux/module.h>
  57 +#include <linux/of_device.h>
  58 +#include <linux/phy/phy.h>
  59 +#include <linux/platform_device.h>
  60 +#include <linux/delay.h>
  61 +#include <linux/regmap.h>
  62 +#include <linux/mfd/syscon.h>
  63 +
  64 +/* USB QSCRATCH Hardware registers */
  65 +#define QSCRATCH_GENERAL_CFG           (0x08)
  66 +#define HSUSB_PHY_CTRL_REG             (0x10)
  67 +
  68 +/* PHY_CTRL_REG */
  69 +#define HSUSB_CTRL_DMSEHV_CLAMP                BIT(24)
  70 +#define HSUSB_CTRL_USB2_SUSPEND                BIT(23)
  71 +#define HSUSB_CTRL_UTMI_CLK_EN         BIT(21)
  72 +#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20)
  73 +#define HSUSB_CTRL_USE_CLKCORE         BIT(18)
  74 +#define HSUSB_CTRL_DPSEHV_CLAMP                BIT(17)
  75 +#define HSUSB_CTRL_COMMONONN           BIT(11)
  76 +#define HSUSB_CTRL_ID_HV_CLAMP         BIT(9)
  77 +#define HSUSB_CTRL_OTGSESSVLD_CLAMP    BIT(8)
  78 +#define HSUSB_CTRL_CLAMP_EN            BIT(7)
  79 +#define HSUSB_CTRL_RETENABLEN          BIT(1)
  80 +#define HSUSB_CTRL_POR                 BIT(0)
  81 +
  82 +/* QSCRATCH_GENERAL_CFG */
  83 +#define HSUSB_GCFG_XHCI_REV            BIT(2)
  84 +
  85 +/* USB QSCRATCH Hardware registers */
  86 +#define SSUSB_PHY_CTRL_REG             (0x00)
  87 +#define SSUSB_PHY_PARAM_CTRL_1         (0x04)
  88 +#define SSUSB_PHY_PARAM_CTRL_2         (0x08)
  89 +#define CR_PROTOCOL_DATA_IN_REG                (0x0c)
  90 +#define CR_PROTOCOL_DATA_OUT_REG       (0x10)
  91 +#define CR_PROTOCOL_CAP_ADDR_REG       (0x14)
  92 +#define CR_PROTOCOL_CAP_DATA_REG       (0x18)
  93 +#define CR_PROTOCOL_READ_REG           (0x1c)
  94 +#define CR_PROTOCOL_WRITE_REG          (0x20)
  95 +
  96 +/* PHY_CTRL_REG */
  97 +#define SSUSB_CTRL_REF_USE_PAD         BIT(28)
  98 +#define SSUSB_CTRL_TEST_POWERDOWN      BIT(27)
  99 +#define SSUSB_CTRL_LANE0_PWR_PRESENT   BIT(24)
 100 +#define SSUSB_CTRL_SS_PHY_EN           BIT(8)
 101 +#define SSUSB_CTRL_SS_PHY_RESET                BIT(7)
 102 +
 103 +/* SSPHY control registers - Does this need 0x30? */
 104 +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * (lane))
 105 +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane)        (0x1002 + 0x100 * (lane))
 106 +
 107 +/* SSPHY SoC version specific values */
 108 +#define SSPHY_RX_EQ_VALUE              4 /* Override value for rx_eq */
 109 +/* Override value for transmit preemphasis */
 110 +#define SSPHY_TX_DEEMPH_3_5DB          23
 111 +/* Override value for mpll */
 112 +#define SSPHY_MPLL_VALUE               0
 113 +
 114 +/* QSCRATCH PHY_PARAM_CTRL1 fields */
 115 +#define PHY_PARAM_CTRL1_TX_FULL_SWING_MASK     GENMASK(26, 19)
 116 +#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK     GENMASK(19, 13)
 117 +#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK   GENMASK(13, 7)
 118 +#define PHY_PARAM_CTRL1_LOS_BIAS_MASK          GENMASK(7, 2)
 119 +
 120 +#define PHY_PARAM_CTRL1_MASK                           \
 121 +               (PHY_PARAM_CTRL1_TX_FULL_SWING_MASK |   \
 122 +                PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK |   \
 123 +                PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK | \
 124 +                PHY_PARAM_CTRL1_LOS_BIAS_MASK)
 125 +
 126 +#define PHY_PARAM_CTRL1_TX_FULL_SWING(x)       \
 127 +               (((x) << 20) & PHY_PARAM_CTRL1_TX_FULL_SWING_MASK)
 128 +#define PHY_PARAM_CTRL1_TX_DEEMPH_6DB(x)       \
 129 +               (((x) << 14) & PHY_PARAM_CTRL1_TX_DEEMPH_6DB_MASK)
 130 +#define PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(x)     \
 131 +               (((x) <<  8) & PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB_MASK)
 132 +#define PHY_PARAM_CTRL1_LOS_BIAS(x)    \
 133 +               (((x) <<  3) & PHY_PARAM_CTRL1_LOS_BIAS_MASK)
 134 +
 135 +/* RX OVRD IN HI bits */
 136 +#define RX_OVRD_IN_HI_RX_RESET_OVRD            BIT(13)
 137 +#define RX_OVRD_IN_HI_RX_RX_RESET              BIT(12)
 138 +#define RX_OVRD_IN_HI_RX_EQ_OVRD               BIT(11)
 139 +#define RX_OVRD_IN_HI_RX_EQ_MASK               GENMASK(10, 7)
 140 +#define RX_OVRD_IN_HI_RX_EQ(x)                 ((x) << 8)
 141 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD            BIT(7)
 142 +#define RX_OVRD_IN_HI_RX_EQ_EN                 BIT(6)
 143 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD       BIT(5)
 144 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK       GENMASK(4, 2)
 145 +#define RX_OVRD_IN_HI_RX_RATE_OVRD             BIT(2)
 146 +#define RX_OVRD_IN_HI_RX_RATE_MASK             GENMASK(2, 0)
 147 +
 148 +/* TX OVRD DRV LO register bits */
 149 +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK          GENMASK(6, 0)
 150 +#define TX_OVRD_DRV_LO_PREEMPH_MASK            GENMASK(13, 6)
 151 +#define TX_OVRD_DRV_LO_PREEMPH(x)              ((x) << 7)
 152 +#define TX_OVRD_DRV_LO_EN                      BIT(14)
 153 +
 154 +/* MPLL bits */
 155 +#define SSPHY_MPLL_MASK                                GENMASK(8, 5)
 156 +#define SSPHY_MPLL(x)                          ((x) << 5)
 157 +
 158 +/* SS CAP register bits */
 159 +#define SS_CR_CAP_ADDR_REG                     BIT(0)
 160 +#define SS_CR_CAP_DATA_REG                     BIT(0)
 161 +#define SS_CR_READ_REG                         BIT(0)
 162 +#define SS_CR_WRITE_REG                                BIT(0)
 163 +
 164 +struct usb_phy {
 165 +       void __iomem            *base;
 166 +       struct device           *dev;
 167 +       struct clk              *xo_clk;
 168 +       struct clk              *ref_clk;
 169 +       u32                     rx_eq;
 170 +       u32                     tx_deamp_3_5db;
 171 +       u32                     mpll;
 172 +};
 173 +
 174 +struct phy_drvdata {
 175 +       struct phy_ops  ops;
 176 +       u32             clk_rate;
 177 +};
 178 +
 179 +/**
 180 + * Write register and read back masked value to confirm it is written
 181 + *
 182 + * @base - QCOM DWC3 PHY base virtual address.
 183 + * @offset - register offset.
 184 + * @mask - register bitmask specifying what should be updated
 185 + * @val - value to write.
 186 + */
 187 +static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
 188 +                                         u32 offset,
 189 +                                         const u32 mask, u32 val)
 190 +{
 191 +       u32 write_val, tmp = readl(phy_dwc3->base + offset);
 192 +
 193 +       tmp &= ~mask;           /* retain other bits */
 194 +       write_val = tmp | val;
 195 +
 196 +       writel(write_val, phy_dwc3->base + offset);
 197 +
 198 +       /* Read back to see if val was written */
 199 +       tmp = readl(phy_dwc3->base + offset);
 200 +       tmp &= mask;            /* clear other bits */
 201 +
 202 +       if (tmp != val)
 203 +               dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);
 204 +}
 205 +
 206 +static int wait_for_latch(void __iomem *addr)
 207 +{
 208 +       u32 retry = 10;
 209 +
 210 +       while (true) {
 211 +               if (!readl(addr))
 212 +                       break;
 213 +
 214 +               if (--retry == 0)
 215 +                       return -ETIMEDOUT;
 216 +
 217 +               usleep_range(10, 20);
 218 +       }
 219 +
 220 +       return 0;
 221 +}
 222 +
 223 +/**
 224 + * Write SSPHY register
 225 + *
 226 + * @base - QCOM DWC3 PHY base virtual address.
 227 + * @addr - SSPHY address to write.
 228 + * @val - value to write.
 229 + */
 230 +static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
 231 +                               u32 addr, u32 val)
 232 +{
 233 +       int ret;
 234 +
 235 +       writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
 236 +       writel(SS_CR_CAP_ADDR_REG,
 237 +              phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
 238 +
 239 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
 240 +       if (ret)
 241 +               goto err_wait;
 242 +
 243 +       writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
 244 +       writel(SS_CR_CAP_DATA_REG,
 245 +              phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
 246 +
 247 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
 248 +       if (ret)
 249 +               goto err_wait;
 250 +
 251 +       writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
 252 +
 253 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
 254 +
 255 +err_wait:
 256 +       if (ret)
 257 +               dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
 258 +       return ret;
 259 +}
 260 +
 261 +/**
 262 + * Read SSPHY register.
 263 + *
 264 + * @base - QCOM DWC3 PHY base virtual address.
 265 + * @addr - SSPHY address to read.
 266 + */
 267 +static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
 268 +                              u32 addr, u32 *val)
 269 +{
 270 +       int ret;
 271 +
 272 +       writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
 273 +       writel(SS_CR_CAP_ADDR_REG,
 274 +              phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
 275 +
 276 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
 277 +       if (ret)
 278 +               goto err_wait;
 279 +
 280 +       /*
 281 +        * Due to hardware bug, first read of SSPHY register might be
 282 +        * incorrect. Hence as workaround, SW should perform SSPHY register
 283 +        * read twice, but use only second read and ignore first read.
 284 +        */
 285 +       writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
 286 +
 287 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
 288 +       if (ret)
 289 +               goto err_wait;
 290 +
 291 +       /* throwaway read */
 292 +       readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
 293 +
 294 +       writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
 295 +
 296 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
 297 +       if (ret)
 298 +               goto err_wait;
 299 +
 300 +       *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
 301 +
 302 +err_wait:
 303 +       return ret;
 304 +}
 305 +
 306 +static int qcom_ipq806x_usb_hs_phy_init(struct phy *phy)
 307 +{
 308 +       struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 309 +       int ret;
 310 +       u32 val;
 311 +
 312 +       ret = clk_prepare_enable(phy_dwc3->xo_clk);
 313 +       if (ret)
 314 +               return ret;
 315 +
 316 +       ret = clk_prepare_enable(phy_dwc3->ref_clk);
 317 +       if (ret) {
 318 +               clk_disable_unprepare(phy_dwc3->xo_clk);
 319 +               return ret;
 320 +       }
 321 +
 322 +       /*
 323 +        * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
 324 +        * enable clamping, and disable RETENTION (power-on default is ENABLED)
 325 +        */
 326 +       val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
 327 +               HSUSB_CTRL_RETENABLEN  | HSUSB_CTRL_COMMONONN |
 328 +               HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
 329 +               HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
 330 +               HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
 331 +
 332 +       /* use core clock if external reference is not present */
 333 +       if (!phy_dwc3->xo_clk)
 334 +               val |= HSUSB_CTRL_USE_CLKCORE;
 335 +
 336 +       writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
 337 +       usleep_range(2000, 2200);
 338 +
 339 +       /* Disable (bypass) VBUS and ID filters */
 340 +       writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
 341 +
 342 +       return 0;
 343 +}
 344 +
 345 +static int qcom_ipq806x_usb_hs_phy_exit(struct phy *phy)
 346 +{
 347 +       struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 348 +
 349 +       clk_disable_unprepare(phy_dwc3->ref_clk);
 350 +       clk_disable_unprepare(phy_dwc3->xo_clk);
 351 +
 352 +       return 0;
 353 +}
 354 +
 355 +static int qcom_ipq806x_usb_ss_phy_init(struct phy *phy)
 356 +{
 357 +       struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 358 +       int ret;
 359 +       u32 data;
 360 +
 361 +       ret = clk_prepare_enable(phy_dwc3->xo_clk);
 362 +       if (ret)
 363 +               return ret;
 364 +
 365 +       ret = clk_prepare_enable(phy_dwc3->ref_clk);
 366 +       if (ret) {
 367 +               clk_disable_unprepare(phy_dwc3->xo_clk);
 368 +               return ret;
 369 +       }
 370 +
 371 +       /* reset phy */
 372 +       data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 373 +       writel(data | SSUSB_CTRL_SS_PHY_RESET,
 374 +              phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 375 +       usleep_range(2000, 2200);
 376 +       writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 377 +
 378 +       /* clear REF_PAD if we don't have XO clk */
 379 +       if (!phy_dwc3->xo_clk)
 380 +               data &= ~SSUSB_CTRL_REF_USE_PAD;
 381 +       else
 382 +               data |= SSUSB_CTRL_REF_USE_PAD;
 383 +
 384 +       writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 385 +
 386 +       /* wait for ref clk to become stable, this can take up to 30ms */
 387 +       msleep(30);
 388 +
 389 +       data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
 390 +       writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 391 +
 392 +       /*
 393 +        * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
 394 +        * in HS mode instead of SS mode. Workaround it by asserting
 395 +        * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
 396 +        */
 397 +       ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data);
 398 +       if (ret)
 399 +               goto err_phy_trans;
 400 +
 401 +       data |= (1 << 7);
 402 +       ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data);
 403 +       if (ret)
 404 +               goto err_phy_trans;
 405 +
 406 +       ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data);
 407 +       if (ret)
 408 +               goto err_phy_trans;
 409 +
 410 +       data &= ~0xff0;
 411 +       data |= 0x20;
 412 +       ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data);
 413 +       if (ret)
 414 +               goto err_phy_trans;
 415 +
 416 +       /*
 417 +        * Fix RX Equalization setting as follows
 418 +        * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
 419 +        * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
 420 +        * LANE0.RX_OVRD_IN_HI.RX_EQ set based on SoC version
 421 +        * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
 422 +        */
 423 +       ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
 424 +       if (ret)
 425 +               goto err_phy_trans;
 426 +
 427 +       data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
 428 +       data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
 429 +       data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
 430 +       data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);
 431 +       data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
 432 +       ret = usb_ss_write_phycreg(phy_dwc3,
 433 +                                  SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
 434 +       if (ret)
 435 +               goto err_phy_trans;
 436 +
 437 +       /*
 438 +        * Set EQ and TX launch amplitudes as follows
 439 +        * LANE0.TX_OVRD_DRV_LO.PREEMPH set based on SoC version
 440 +        * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 110
 441 +        * LANE0.TX_OVRD_DRV_LO.EN set to 1.
 442 +        */
 443 +       ret = usb_ss_read_phycreg(phy_dwc3,
 444 +                                 SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
 445 +       if (ret)
 446 +               goto err_phy_trans;
 447 +
 448 +       data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
 449 +       data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);
 450 +       data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
 451 +       data |= 0x6E;
 452 +       data |= TX_OVRD_DRV_LO_EN;
 453 +       ret = usb_ss_write_phycreg(phy_dwc3,
 454 +                                  SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
 455 +       if (ret)
 456 +               goto err_phy_trans;
 457 +
 458 +       data = 0;
 459 +       data &= ~SSPHY_MPLL_MASK;
 460 +       data |= SSPHY_MPLL(phy_dwc3->mpll);
 461 +       usb_ss_write_phycreg(phy_dwc3, 0x30, data);
 462 +
 463 +       /*
 464 +        * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
 465 +        * TX_FULL_SWING [26:20] amplitude to 110
 466 +        * TX_DEEMPH_6DB [19:14] to 32
 467 +        * TX_DEEMPH_3_5DB [13:8] set based on SoC version
 468 +        * LOS_BIAS [7:3] to 9
 469 +        */
 470 +       data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
 471 +
 472 +       data &= ~PHY_PARAM_CTRL1_MASK;
 473 +
 474 +       data |= PHY_PARAM_CTRL1_TX_FULL_SWING(0x6e) |
 475 +               PHY_PARAM_CTRL1_TX_DEEMPH_6DB(0x20) |
 476 +               PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
 477 +               PHY_PARAM_CTRL1_LOS_BIAS(0x9);
 478 +
 479 +       usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
 480 +                              PHY_PARAM_CTRL1_MASK, data);
 481 +
 482 +err_phy_trans:
 483 +       return ret;
 484 +}
 485 +
 486 +static int qcom_ipq806x_usb_ss_phy_exit(struct phy *phy)
 487 +{
 488 +       struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 489 +
 490 +       /* Sequence to put SSPHY in low power state:
 491 +        * 1. Clear REF_PHY_EN in PHY_CTRL_REG
 492 +        * 2. Clear REF_USE_PAD in PHY_CTRL_REG
 493 +        * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
 494 +        */
 495 +       usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
 496 +                              SSUSB_CTRL_SS_PHY_EN, 0x0);
 497 +       usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
 498 +                              SSUSB_CTRL_REF_USE_PAD, 0x0);
 499 +       usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
 500 +                              SSUSB_CTRL_TEST_POWERDOWN, 0x0);
 501 +
 502 +       clk_disable_unprepare(phy_dwc3->ref_clk);
 503 +       clk_disable_unprepare(phy_dwc3->xo_clk);
 504 +
 505 +       return 0;
 506 +}
 507 +
 508 +static const struct phy_drvdata qcom_ipq806x_usb_hs_drvdata = {
 509 +       .ops = {
 510 +               .init           = qcom_ipq806x_usb_hs_phy_init,
 511 +               .exit           = qcom_ipq806x_usb_hs_phy_exit,
 512 +               .owner          = THIS_MODULE,
 513 +       },
 514 +       .clk_rate = 60000000,
 515 +};
 516 +
 517 +static const struct phy_drvdata qcom_ipq806x_usb_ss_drvdata = {
 518 +       .ops = {
 519 +               .init           = qcom_ipq806x_usb_ss_phy_init,
 520 +               .exit           = qcom_ipq806x_usb_ss_phy_exit,
 521 +               .owner          = THIS_MODULE,
 522 +       },
 523 +       .clk_rate = 125000000,
 524 +};
 525 +
 526 +static const struct of_device_id qcom_ipq806x_usb_phy_table[] = {
 527 +       { .compatible = "qcom,ipq806x-usb-phy-hs",
 528 +         .data = &qcom_ipq806x_usb_hs_drvdata },
 529 +       { .compatible = "qcom,ipq806x-usb-phy-ss",
 530 +         .data = &qcom_ipq806x_usb_ss_drvdata },
 531 +       { /* Sentinel */ }
 532 +};
 533 +MODULE_DEVICE_TABLE(of, qcom_ipq806x_usb_phy_table);
 534 +
 535 +static int qcom_ipq806x_usb_phy_probe(struct platform_device *pdev)
 536 +{
 537 +       struct resource *res;
 538 +       resource_size_t size;
 539 +       struct phy *generic_phy;
 540 +       struct usb_phy *phy_dwc3;
 541 +       const struct phy_drvdata *data;
 542 +       struct phy_provider *phy_provider;
 543 +
 544 +       phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
 545 +       if (!phy_dwc3)
 546 +               return -ENOMEM;
 547 +
 548 +       data = of_device_get_match_data(&pdev->dev);
 549 +
 550 +       phy_dwc3->dev = &pdev->dev;
 551 +
 552 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 553 +       if (!res)
 554 +               return -EINVAL;
 555 +       size = resource_size(res);
 556 +       phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
 557 +
 558 +       if (IS_ERR(phy_dwc3->base)) {
 559 +               dev_err(phy_dwc3->dev, "failed to map reg\n");
 560 +               return PTR_ERR(phy_dwc3->base);
 561 +       }
 562 +
 563 +       phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
 564 +       if (IS_ERR(phy_dwc3->ref_clk)) {
 565 +               dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
 566 +               return PTR_ERR(phy_dwc3->ref_clk);
 567 +       }
 568 +
 569 +       clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
 570 +
 571 +       phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
 572 +       if (IS_ERR(phy_dwc3->xo_clk)) {
 573 +               dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
 574 +               phy_dwc3->xo_clk = NULL;
 575 +       }
 576 +
 577 +       /* Parse device node to probe HSIO settings */
 578 +       if (device_property_read_u32(&pdev->dev, "qcom,rx-eq",
 579 +                                    &phy_dwc3->rx_eq))
 580 +               phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
 581 +
 582 +       if (device_property_read_u32(&pdev->dev, "qcom,tx-deamp_3_5db",
 583 +                                    &phy_dwc3->tx_deamp_3_5db))
 584 +               phy_dwc3->rx_eq = SSPHY_TX_DEEMPH_3_5DB;
 585 +
 586 +       if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
 587 +               phy_dwc3->mpll = SSPHY_MPLL_VALUE;
 588 +
 589 +       generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);
 590 +
 591 +       if (IS_ERR(generic_phy))
 592 +               return PTR_ERR(generic_phy);
 593 +
 594 +       phy_set_drvdata(generic_phy, phy_dwc3);
 595 +       platform_set_drvdata(pdev, phy_dwc3);
 596 +
 597 +       phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
 598 +                                                    of_phy_simple_xlate);
 599 +
 600 +       if (IS_ERR(phy_provider))
 601 +               return PTR_ERR(phy_provider);
 602 +
 603 +       return 0;
 604 +}
 605 +
 606 +static struct platform_driver qcom_ipq806x_usb_phy_driver = {
 607 +       .probe          = qcom_ipq806x_usb_phy_probe,
 608 +       .driver         = {
 609 +               .name   = "qcom-ipq806x-usb-phy",
 610 +               .owner  = THIS_MODULE,
 611 +               .of_match_table = qcom_ipq806x_usb_phy_table,
 612 +       },
 613 +};
 614 +
 615 +module_platform_driver(qcom_ipq806x_usb_phy_driver);
 616 +
 617 +MODULE_ALIAS("platform:phy-qcom-ipq806x-usb");
 618 +MODULE_LICENSE("GPL v2");
 619 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 620 +MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
 621 +MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");