target/linux/ipq806x/patches/0021-ARM-dts-qcom-Add-nodes-necessary-for-SMP-boot.patch

   1 From 5a054211d9380cef5a09da7c5e815c827f330a96 Mon Sep 17 00:00:00 2001
   2 From: Rohit Vaswani <rvaswani@codeaurora.org>
   3 Date: Fri, 1 Nov 2013 10:10:40 -0700
   4 Subject: [PATCH 021/182] ARM: dts: qcom: Add nodes necessary for SMP boot
   5
   6 Add the necessary nodes to support SMP on MSM8660, MSM8960, and
   7 MSM8974/APQ8074. While we're here also add in the error
   8 interrupts for the Krait cache error detection.
   9
  10 Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
  11 [sboyd: Split into separate patch, add error interrupts]
  12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  13 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  14 ---
  15  arch/arm/boot/dts/qcom-msm8660.dtsi |   24 ++++++++++++
  16  arch/arm/boot/dts/qcom-msm8960.dtsi |   52 ++++++++++++++++++++++++++
  17  arch/arm/boot/dts/qcom-msm8974.dtsi |   69 +++++++++++++++++++++++++++++++++++
  18  3 files changed, 145 insertions(+)
  19
  20 diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
  21 index 69d6c4e..c52a9e9 100644
  22 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi
  23 +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
  24 @@ -9,6 +9,30 @@
  25         compatible = "qcom,msm8660";
  26         interrupt-parent = <&intc>;
  27
  28 +       cpus {
  29 +               #address-cells = <1>;
  30 +               #size-cells = <0>;
  31 +               compatible = "qcom,scorpion";
  32 +               enable-method = "qcom,gcc-msm8660";
  33 +
  34 +               cpu@0 {
  35 +                       device_type = "cpu";
  36 +                       reg = <0>;
  37 +                       next-level-cache = <&L2>;
  38 +               };
  39 +
  40 +               cpu@1 {
  41 +                       device_type = "cpu";
  42 +                       reg = <1>;
  43 +                       next-level-cache = <&L2>;
  44 +               };
  45 +
  46 +               L2: l2-cache {
  47 +                       compatible = "cache";
  48 +                       cache-level = <2>;
  49 +               };
  50 +       };
  51 +
  52         intc: interrupt-controller@2080000 {
  53                 compatible = "qcom,msm-8660-qgic";
  54                 interrupt-controller;
  55 diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
  56 index ff00282..02231a5 100644
  57 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi
  58 +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
  59 @@ -9,6 +9,36 @@
  60         compatible = "qcom,msm8960";
  61         interrupt-parent = <&intc>;
  62
  63 +       cpus {
  64 +               #address-cells = <1>;
  65 +               #size-cells = <0>;
  66 +               interrupts = <1 14 0x304>;
  67 +               compatible = "qcom,krait";
  68 +               enable-method = "qcom,kpss-acc-v1";
  69 +
  70 +               cpu@0 {
  71 +                       device_type = "cpu";
  72 +                       reg = <0>;
  73 +                       next-level-cache = <&L2>;
  74 +                       qcom,acc = <&acc0>;
  75 +                       qcom,saw = <&saw0>;
  76 +               };
  77 +
  78 +               cpu@1 {
  79 +                       device_type = "cpu";
  80 +                       reg = <1>;
  81 +                       next-level-cache = <&L2>;
  82 +                       qcom,acc = <&acc1>;
  83 +                       qcom,saw = <&saw1>;
  84 +               };
  85 +
  86 +               L2: l2-cache {
  87 +                       compatible = "cache";
  88 +                       cache-level = <2>;
  89 +                       interrupts = <0 2 0x4>;
  90 +               };
  91 +       };
  92 +
  93         intc: interrupt-controller@2000000 {
  94                 compatible = "qcom,msm-qgic2";
  95                 interrupt-controller;
  96 @@ -53,6 +83,28 @@
  97                 #reset-cells = <1>;
  98         };
  99
 100 +       acc0: clock-controller@2088000 {
 101 +               compatible = "qcom,kpss-acc-v1";
 102 +               reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
 103 +       };
 104 +
 105 +       acc1: clock-controller@2098000 {
 106 +               compatible = "qcom,kpss-acc-v1";
 107 +               reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
 108 +       };
 109 +
 110 +       saw0: regulator@2089000 {
 111 +               compatible = "qcom,saw2";
 112 +               reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
 113 +               regulator;
 114 +       };
 115 +
 116 +       saw1: regulator@2099000 {
 117 +               compatible = "qcom,saw2";
 118 +               reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
 119 +               regulator;
 120 +       };
 121 +
 122         serial@16440000 {
 123                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 124                 reg = <0x16440000 0x1000>,
 125 diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
 126 index 9e5dadb..39eebc5 100644
 127 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
 128 +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
 129 @@ -9,6 +9,49 @@
 130         compatible = "qcom,msm8974";
 131         interrupt-parent = <&intc>;
 132
 133 +       cpus {
 134 +               #address-cells = <1>;
 135 +               #size-cells = <0>;
 136 +               interrupts = <1 9 0xf04>;
 137 +               compatible = "qcom,krait";
 138 +               enable-method = "qcom,kpss-acc-v2";
 139 +
 140 +               cpu@0 {
 141 +                       device_type = "cpu";
 142 +                       reg = <0>;
 143 +                       next-level-cache = <&L2>;
 144 +                       qcom,acc = <&acc0>;
 145 +               };
 146 +
 147 +               cpu@1 {
 148 +                       device_type = "cpu";
 149 +                       reg = <1>;
 150 +                       next-level-cache = <&L2>;
 151 +                       qcom,acc = <&acc1>;
 152 +               };
 153 +
 154 +               cpu@2 {
 155 +                       device_type = "cpu";
 156 +                       reg = <2>;
 157 +                       next-level-cache = <&L2>;
 158 +                       qcom,acc = <&acc2>;
 159 +               };
 160 +
 161 +               cpu@3 {
 162 +                       device_type = "cpu";
 163 +                       reg = <3>;
 164 +                       next-level-cache = <&L2>;
 165 +                       qcom,acc = <&acc3>;
 166 +               };
 167 +
 168 +               L2: l2-cache {
 169 +                       compatible = "cache";
 170 +                       cache-level = <2>;
 171 +                       interrupts = <0 2 0x4>;
 172 +                       qcom,saw = <&saw_l2>;
 173 +               };
 174 +       };
 175 +
 176         soc: soc {
 177                 #address-cells = <1>;
 178                 #size-cells = <1>;
 179 @@ -91,6 +134,32 @@
 180                         };
 181                 };
 182
 183 +               saw_l2: regulator@f9012000 {
 184 +                       compatible = "qcom,saw2";
 185 +                       reg = <0xf9012000 0x1000>;
 186 +                       regulator;
 187 +               };
 188 +
 189 +               acc0: clock-controller@f9088000 {
 190 +                       compatible = "qcom,kpss-acc-v2";
 191 +                       reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
 192 +               };
 193 +
 194 +               acc1: clock-controller@f9098000 {
 195 +                       compatible = "qcom,kpss-acc-v2";
 196 +                       reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
 197 +               };
 198 +
 199 +               acc2: clock-controller@f90a8000 {
 200 +                       compatible = "qcom,kpss-acc-v2";
 201 +                       reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
 202 +               };
 203 +
 204 +               acc3: clock-controller@f90b8000 {
 205 +                       compatible = "qcom,kpss-acc-v2";
 206 +                       reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
 207 +               };
 208 +
 209                 restart@fc4ab000 {
 210                         compatible = "qcom,pshold";
 211                         reg = <0xfc4ab000 0x4>;
 212 --
 213 1.7.10.4
 214