target/linux/ipq806x/patches/0040-pinctrl-qcom-Add-definitions-for-IPQ8064.patch

   1 From 9bbd9d7e40944ca95e07f363b68700225beb9bef Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Mon, 14 Apr 2014 22:10:35 -0500
   4 Subject: [PATCH 040/182] pinctrl: qcom: Add definitions for IPQ8064
   5
   6 This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
   7 Qualcomm IPQ8064 platform.
   8
   9 Signed-off-by: Andy Gross <agross@codeaurora.org>
  10 Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
  11 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  12 ---
  13  drivers/pinctrl/Kconfig           |    8 +
  14  drivers/pinctrl/Makefile          |    1 +
  15  drivers/pinctrl/pinctrl-ipq8064.c |  653 +++++++++++++++++++++++++++++++++++++
  16  3 files changed, 662 insertions(+)
  17  create mode 100644 drivers/pinctrl/pinctrl-ipq8064.c
  18
  19 diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
  20 index d34639d..232e6bc 100644
  21 --- a/drivers/pinctrl/Kconfig
  22 +++ b/drivers/pinctrl/Kconfig
  23 @@ -230,6 +230,14 @@ config PINCTRL_APQ8064
  24           This is the pinctrl, pinmux, pinconf and gpiolib driver for the
  25           Qualcomm TLMM block found in the Qualcomm APQ8064 platform.
  26
  27 +config PINCTRL_IPQ8064
  28 +       tristate "Qualcomm IPQ8064 pin controller driver"
  29 +       depends on GPIOLIB && OF
  30 +       select PINCTRL_MSM
  31 +       help
  32 +         This is the pinctrl, pinmux, pinconf and gpiolib driver for the
  33 +         Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
  34 +
  35  config PINCTRL_MSM8X74
  36         tristate "Qualcomm 8x74 pin controller driver"
  37         depends on GPIOLIB && OF && (ARCH_QCOM || COMPILE_TEST)
  38 diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
  39 index 9e1fb67..6b8474a 100644
  40 --- a/drivers/pinctrl/Makefile
  41 +++ b/drivers/pinctrl/Makefile
  42 @@ -39,6 +39,7 @@ obj-$(CONFIG_PINCTRL_IMX25)   += pinctrl-imx25.o
  43  obj-$(CONFIG_PINCTRL_IMX28)    += pinctrl-imx28.o
  44  obj-$(CONFIG_PINCTRL_MSM)      += pinctrl-msm.o
  45  obj-$(CONFIG_PINCTRL_APQ8064)  += pinctrl-apq8064.o
  46 +obj-$(CONFIG_PINCTRL_IPQ8064)  += pinctrl-ipq8064.o
  47  obj-$(CONFIG_PINCTRL_MSM8X74)  += pinctrl-msm8x74.o
  48  obj-$(CONFIG_PINCTRL_NOMADIK)  += pinctrl-nomadik.o
  49  obj-$(CONFIG_PINCTRL_STN8815)  += pinctrl-nomadik-stn8815.o
  50 diff --git a/drivers/pinctrl/pinctrl-ipq8064.c b/drivers/pinctrl/pinctrl-ipq8064.c
  51 new file mode 100644
  52 index 0000000..1700b49
  53 --- /dev/null
  54 +++ b/drivers/pinctrl/pinctrl-ipq8064.c
  55 @@ -0,0 +1,653 @@
  56 +/*
  57 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
  58 + *
  59 + * This program is free software; you can redistribute it and/or modify
  60 + * it under the terms of the GNU General Public License version 2 and
  61 + * only version 2 as published by the Free Software Foundation.
  62 + *
  63 + * This program is distributed in the hope that it will be useful,
  64 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  65 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  66 + * GNU General Public License for more details.
  67 + *
  68 + */
  69 +
  70 +#include <linux/module.h>
  71 +#include <linux/of.h>
  72 +#include <linux/platform_device.h>
  73 +#include <linux/pinctrl/pinctrl.h>
  74 +
  75 +#include "pinctrl-msm.h"
  76 +
  77 +static const struct pinctrl_pin_desc ipq8064_pins[] = {
  78 +       PINCTRL_PIN(0, "GPIO_1"),
  79 +       PINCTRL_PIN(1, "GPIO_1"),
  80 +       PINCTRL_PIN(2, "GPIO_2"),
  81 +       PINCTRL_PIN(3, "GPIO_3"),
  82 +       PINCTRL_PIN(4, "GPIO_4"),
  83 +       PINCTRL_PIN(5, "GPIO_5"),
  84 +       PINCTRL_PIN(6, "GPIO_6"),
  85 +       PINCTRL_PIN(7, "GPIO_7"),
  86 +       PINCTRL_PIN(8, "GPIO_8"),
  87 +       PINCTRL_PIN(9, "GPIO_9"),
  88 +       PINCTRL_PIN(10, "GPIO_10"),
  89 +       PINCTRL_PIN(11, "GPIO_11"),
  90 +       PINCTRL_PIN(12, "GPIO_12"),
  91 +       PINCTRL_PIN(13, "GPIO_13"),
  92 +       PINCTRL_PIN(14, "GPIO_14"),
  93 +       PINCTRL_PIN(15, "GPIO_15"),
  94 +       PINCTRL_PIN(16, "GPIO_16"),
  95 +       PINCTRL_PIN(17, "GPIO_17"),
  96 +       PINCTRL_PIN(18, "GPIO_18"),
  97 +       PINCTRL_PIN(19, "GPIO_19"),
  98 +       PINCTRL_PIN(20, "GPIO_20"),
  99 +       PINCTRL_PIN(21, "GPIO_21"),
 100 +       PINCTRL_PIN(22, "GPIO_22"),
 101 +       PINCTRL_PIN(23, "GPIO_23"),
 102 +       PINCTRL_PIN(24, "GPIO_24"),
 103 +       PINCTRL_PIN(25, "GPIO_25"),
 104 +       PINCTRL_PIN(26, "GPIO_26"),
 105 +       PINCTRL_PIN(27, "GPIO_27"),
 106 +       PINCTRL_PIN(28, "GPIO_28"),
 107 +       PINCTRL_PIN(29, "GPIO_29"),
 108 +       PINCTRL_PIN(30, "GPIO_30"),
 109 +       PINCTRL_PIN(31, "GPIO_31"),
 110 +       PINCTRL_PIN(32, "GPIO_32"),
 111 +       PINCTRL_PIN(33, "GPIO_33"),
 112 +       PINCTRL_PIN(34, "GPIO_34"),
 113 +       PINCTRL_PIN(35, "GPIO_35"),
 114 +       PINCTRL_PIN(36, "GPIO_36"),
 115 +       PINCTRL_PIN(37, "GPIO_37"),
 116 +       PINCTRL_PIN(38, "GPIO_38"),
 117 +       PINCTRL_PIN(39, "GPIO_39"),
 118 +       PINCTRL_PIN(40, "GPIO_40"),
 119 +       PINCTRL_PIN(41, "GPIO_41"),
 120 +       PINCTRL_PIN(42, "GPIO_42"),
 121 +       PINCTRL_PIN(43, "GPIO_43"),
 122 +       PINCTRL_PIN(44, "GPIO_44"),
 123 +       PINCTRL_PIN(45, "GPIO_45"),
 124 +       PINCTRL_PIN(46, "GPIO_46"),
 125 +       PINCTRL_PIN(47, "GPIO_47"),
 126 +       PINCTRL_PIN(48, "GPIO_48"),
 127 +       PINCTRL_PIN(49, "GPIO_49"),
 128 +       PINCTRL_PIN(50, "GPIO_50"),
 129 +       PINCTRL_PIN(51, "GPIO_51"),
 130 +       PINCTRL_PIN(52, "GPIO_52"),
 131 +       PINCTRL_PIN(53, "GPIO_53"),
 132 +       PINCTRL_PIN(54, "GPIO_54"),
 133 +       PINCTRL_PIN(55, "GPIO_55"),
 134 +       PINCTRL_PIN(56, "GPIO_56"),
 135 +       PINCTRL_PIN(57, "GPIO_57"),
 136 +       PINCTRL_PIN(58, "GPIO_58"),
 137 +       PINCTRL_PIN(59, "GPIO_59"),
 138 +       PINCTRL_PIN(60, "GPIO_60"),
 139 +       PINCTRL_PIN(61, "GPIO_61"),
 140 +       PINCTRL_PIN(62, "GPIO_62"),
 141 +       PINCTRL_PIN(63, "GPIO_63"),
 142 +       PINCTRL_PIN(64, "GPIO_64"),
 143 +       PINCTRL_PIN(65, "GPIO_65"),
 144 +       PINCTRL_PIN(66, "GPIO_66"),
 145 +       PINCTRL_PIN(67, "GPIO_67"),
 146 +       PINCTRL_PIN(68, "GPIO_68"),
 147 +
 148 +       PINCTRL_PIN(69, "SDC3_CLK"),
 149 +       PINCTRL_PIN(70, "SDC3_CMD"),
 150 +       PINCTRL_PIN(71, "SDC3_DATA"),
 151 +};
 152 +
 153 +#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
 154 +DECLARE_IPQ_GPIO_PINS(0);
 155 +DECLARE_IPQ_GPIO_PINS(1);
 156 +DECLARE_IPQ_GPIO_PINS(2);
 157 +DECLARE_IPQ_GPIO_PINS(3);
 158 +DECLARE_IPQ_GPIO_PINS(4);
 159 +DECLARE_IPQ_GPIO_PINS(5);
 160 +DECLARE_IPQ_GPIO_PINS(6);
 161 +DECLARE_IPQ_GPIO_PINS(7);
 162 +DECLARE_IPQ_GPIO_PINS(8);
 163 +DECLARE_IPQ_GPIO_PINS(9);
 164 +DECLARE_IPQ_GPIO_PINS(10);
 165 +DECLARE_IPQ_GPIO_PINS(11);
 166 +DECLARE_IPQ_GPIO_PINS(12);
 167 +DECLARE_IPQ_GPIO_PINS(13);
 168 +DECLARE_IPQ_GPIO_PINS(14);
 169 +DECLARE_IPQ_GPIO_PINS(15);
 170 +DECLARE_IPQ_GPIO_PINS(16);
 171 +DECLARE_IPQ_GPIO_PINS(17);
 172 +DECLARE_IPQ_GPIO_PINS(18);
 173 +DECLARE_IPQ_GPIO_PINS(19);
 174 +DECLARE_IPQ_GPIO_PINS(20);
 175 +DECLARE_IPQ_GPIO_PINS(21);
 176 +DECLARE_IPQ_GPIO_PINS(22);
 177 +DECLARE_IPQ_GPIO_PINS(23);
 178 +DECLARE_IPQ_GPIO_PINS(24);
 179 +DECLARE_IPQ_GPIO_PINS(25);
 180 +DECLARE_IPQ_GPIO_PINS(26);
 181 +DECLARE_IPQ_GPIO_PINS(27);
 182 +DECLARE_IPQ_GPIO_PINS(28);
 183 +DECLARE_IPQ_GPIO_PINS(29);
 184 +DECLARE_IPQ_GPIO_PINS(30);
 185 +DECLARE_IPQ_GPIO_PINS(31);
 186 +DECLARE_IPQ_GPIO_PINS(32);
 187 +DECLARE_IPQ_GPIO_PINS(33);
 188 +DECLARE_IPQ_GPIO_PINS(34);
 189 +DECLARE_IPQ_GPIO_PINS(35);
 190 +DECLARE_IPQ_GPIO_PINS(36);
 191 +DECLARE_IPQ_GPIO_PINS(37);
 192 +DECLARE_IPQ_GPIO_PINS(38);
 193 +DECLARE_IPQ_GPIO_PINS(39);
 194 +DECLARE_IPQ_GPIO_PINS(40);
 195 +DECLARE_IPQ_GPIO_PINS(41);
 196 +DECLARE_IPQ_GPIO_PINS(42);
 197 +DECLARE_IPQ_GPIO_PINS(43);
 198 +DECLARE_IPQ_GPIO_PINS(44);
 199 +DECLARE_IPQ_GPIO_PINS(45);
 200 +DECLARE_IPQ_GPIO_PINS(46);
 201 +DECLARE_IPQ_GPIO_PINS(47);
 202 +DECLARE_IPQ_GPIO_PINS(48);
 203 +DECLARE_IPQ_GPIO_PINS(49);
 204 +DECLARE_IPQ_GPIO_PINS(50);
 205 +DECLARE_IPQ_GPIO_PINS(51);
 206 +DECLARE_IPQ_GPIO_PINS(52);
 207 +DECLARE_IPQ_GPIO_PINS(53);
 208 +DECLARE_IPQ_GPIO_PINS(54);
 209 +DECLARE_IPQ_GPIO_PINS(55);
 210 +DECLARE_IPQ_GPIO_PINS(56);
 211 +DECLARE_IPQ_GPIO_PINS(57);
 212 +DECLARE_IPQ_GPIO_PINS(58);
 213 +DECLARE_IPQ_GPIO_PINS(59);
 214 +DECLARE_IPQ_GPIO_PINS(60);
 215 +DECLARE_IPQ_GPIO_PINS(61);
 216 +DECLARE_IPQ_GPIO_PINS(62);
 217 +DECLARE_IPQ_GPIO_PINS(63);
 218 +DECLARE_IPQ_GPIO_PINS(64);
 219 +DECLARE_IPQ_GPIO_PINS(65);
 220 +DECLARE_IPQ_GPIO_PINS(66);
 221 +DECLARE_IPQ_GPIO_PINS(67);
 222 +DECLARE_IPQ_GPIO_PINS(68);
 223 +
 224 +static const unsigned int sdc3_clk_pins[] = { 69 };
 225 +static const unsigned int sdc3_cmd_pins[] = { 70 };
 226 +static const unsigned int sdc3_data_pins[] = { 71 };
 227 +
 228 +#define FUNCTION(fname)                                        \
 229 +       [IPQ_MUX_##fname] = {                           \
 230 +               .name = #fname,                         \
 231 +               .groups = fname##_groups,               \
 232 +               .ngroups = ARRAY_SIZE(fname##_groups),  \
 233 +       }
 234 +
 235 +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
 236 +       {                                               \
 237 +               .name = "gpio" #id,                     \
 238 +               .pins = gpio##id##_pins,                \
 239 +               .npins = ARRAY_SIZE(gpio##id##_pins),   \
 240 +               .funcs = (int[]){                       \
 241 +                       IPQ_MUX_NA, /* gpio mode */     \
 242 +                       IPQ_MUX_##f1,                   \
 243 +                       IPQ_MUX_##f2,                   \
 244 +                       IPQ_MUX_##f3,                   \
 245 +                       IPQ_MUX_##f4,                   \
 246 +                       IPQ_MUX_##f5,                   \
 247 +                       IPQ_MUX_##f6,                   \
 248 +                       IPQ_MUX_##f7,                   \
 249 +                       IPQ_MUX_##f8,                   \
 250 +                       IPQ_MUX_##f9,                   \
 251 +                       IPQ_MUX_##f10,                  \
 252 +               },                                      \
 253 +               .nfuncs = 11,                           \
 254 +               .ctl_reg = 0x1000 + 0x10 * id,          \
 255 +               .io_reg = 0x1004 + 0x10 * id,           \
 256 +               .intr_cfg_reg = 0x1008 + 0x10 * id,     \
 257 +               .intr_status_reg = 0x100c + 0x10 * id,  \
 258 +               .intr_target_reg = 0x400 + 0x4 * id,    \
 259 +               .mux_bit = 2,                           \
 260 +               .pull_bit = 0,                          \
 261 +               .drv_bit = 6,                           \
 262 +               .oe_bit = 9,                            \
 263 +               .in_bit = 0,                            \
 264 +               .out_bit = 1,                           \
 265 +               .intr_enable_bit = 0,                   \
 266 +               .intr_status_bit = 0,                   \
 267 +               .intr_ack_high = 1,                     \
 268 +               .intr_target_bit = 0,                   \
 269 +               .intr_raw_status_bit = 3,               \
 270 +               .intr_polarity_bit = 1,                 \
 271 +               .intr_detection_bit = 2,                \
 272 +               .intr_detection_width = 1,              \
 273 +       }
 274 +
 275 +#define SDC_PINGROUP(pg_name, ctl, pull, drv)          \
 276 +       {                                               \
 277 +               .name = #pg_name,                       \
 278 +               .pins = pg_name##_pins,                 \
 279 +               .npins = ARRAY_SIZE(pg_name##_pins),    \
 280 +               .ctl_reg = ctl,                         \
 281 +               .io_reg = 0,                            \
 282 +               .intr_cfg_reg = 0,                      \
 283 +               .intr_status_reg = 0,                   \
 284 +               .intr_target_reg = 0,                   \
 285 +               .mux_bit = -1,                          \
 286 +               .pull_bit = pull,                       \
 287 +               .drv_bit = drv,                         \
 288 +               .oe_bit = -1,                           \
 289 +               .in_bit = -1,                           \
 290 +               .out_bit = -1,                          \
 291 +               .intr_enable_bit = -1,                  \
 292 +               .intr_status_bit = -1,                  \
 293 +               .intr_target_bit = -1,                  \
 294 +               .intr_raw_status_bit = -1,              \
 295 +               .intr_polarity_bit = -1,                \
 296 +               .intr_detection_bit = -1,               \
 297 +               .intr_detection_width = -1,             \
 298 +       }
 299 +
 300 +enum ipq8064_functions {
 301 +       IPQ_MUX_mdio,
 302 +       IPQ_MUX_mi2s,
 303 +       IPQ_MUX_pdm,
 304 +       IPQ_MUX_ssbi,
 305 +       IPQ_MUX_spmi,
 306 +       IPQ_MUX_audio_pcm,
 307 +       IPQ_MUX_gsbi1,
 308 +       IPQ_MUX_gsbi2,
 309 +       IPQ_MUX_gsbi4,
 310 +       IPQ_MUX_gsbi5,
 311 +       IPQ_MUX_gsbi5_spi_cs1,
 312 +       IPQ_MUX_gsbi5_spi_cs2,
 313 +       IPQ_MUX_gsbi5_spi_cs3,
 314 +       IPQ_MUX_gsbi6,
 315 +       IPQ_MUX_gsbi7,
 316 +       IPQ_MUX_nss_spi,
 317 +       IPQ_MUX_sdc1,
 318 +       IPQ_MUX_spdif,
 319 +       IPQ_MUX_nand,
 320 +       IPQ_MUX_tsif1,
 321 +       IPQ_MUX_tsif2,
 322 +       IPQ_MUX_usb_fs_n,
 323 +       IPQ_MUX_usb_fs,
 324 +       IPQ_MUX_usb2_hsic,
 325 +       IPQ_MUX_rgmii2,
 326 +       IPQ_MUX_sata,
 327 +       IPQ_MUX_pcie1_rst,
 328 +       IPQ_MUX_pcie1_prsnt,
 329 +       IPQ_MUX_pcie1_pwrflt,
 330 +       IPQ_MUX_pcie1_pwren_n,
 331 +       IPQ_MUX_pcie1_pwren,
 332 +       IPQ_MUX_pcie1_clk_req,
 333 +       IPQ_MUX_pcie2_rst,
 334 +       IPQ_MUX_pcie2_prsnt,
 335 +       IPQ_MUX_pcie2_pwrflt,
 336 +       IPQ_MUX_pcie2_pwren_n,
 337 +       IPQ_MUX_pcie2_pwren,
 338 +       IPQ_MUX_pcie2_clk_req,
 339 +       IPQ_MUX_pcie3_rst,
 340 +       IPQ_MUX_pcie3_prsnt,
 341 +       IPQ_MUX_pcie3_pwrflt,
 342 +       IPQ_MUX_pcie3_pwren_n,
 343 +       IPQ_MUX_pcie3_pwren,
 344 +       IPQ_MUX_pcie3_clk_req,
 345 +       IPQ_MUX_ps_hold,
 346 +       IPQ_MUX_NA,
 347 +};
 348 +
 349 +static const char * const mdio_groups[] = {
 350 +       "gpio0", "gpio1", "gpio10", "gpio11",
 351 +};
 352 +
 353 +static const char * const mi2s_groups[] = {
 354 +       "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
 355 +       "gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
 356 +};
 357 +
 358 +static const char * const pdm_groups[] = {
 359 +       "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
 360 +       "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
 361 +       "gpio59",
 362 +};
 363 +
 364 +static const char * const ssbi_groups[] = {
 365 +       "gpio10", "gpio11",
 366 +};
 367 +
 368 +static const char * const spmi_groups[] = {
 369 +       "gpio10", "gpio11",
 370 +};
 371 +
 372 +static const char * const audio_pcm_groups[] = {
 373 +       "gpio14", "gpio15", "gpio16", "gpio17",
 374 +};
 375 +
 376 +static const char * const gsbi1_groups[] = {
 377 +       "gpio51", "gpio52", "gpio53", "gpio54",
 378 +};
 379 +
 380 +static const char * const gsbi2_groups[] = {
 381 +       "gpio22", "gpio23", "gpio24", "gpio25",
 382 +};
 383 +
 384 +static const char * const gsbi4_groups[] = {
 385 +       "gpio10", "gpio11", "gpio12", "gpio13",
 386 +};
 387 +
 388 +static const char * const gsbi5_groups[] = {
 389 +       "gpio18", "gpio19", "gpio20", "gpio21",
 390 +};
 391 +
 392 +static const char * const gsbi5_spi_cs1_groups[] = {
 393 +       "gpio6", "gpio61",
 394 +};
 395 +
 396 +static const char * const gsbi5_spi_cs2_groups[] = {
 397 +       "gpio7", "gpio62",
 398 +};
 399 +
 400 +static const char * const gsbi5_spi_cs3_groups[] = {
 401 +       "gpio2",
 402 +};
 403 +
 404 +static const char * const gsbi6_groups[] = {
 405 +       "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
 406 +       "gpio57", "gpio58",
 407 +};
 408 +
 409 +static const char * const gsbi7_groups[] = {
 410 +       "gpio6", "gpio7", "gpio8", "gpio9",
 411 +};
 412 +
 413 +static const char * const nss_spi_groups[] = {
 414 +       "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
 415 +       "gpio57", "gpio58",
 416 +};
 417 +
 418 +static const char * const sdc1_groups[] = {
 419 +       "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
 420 +       "gpio44", "gpio45", "gpio46", "gpio47",
 421 +};
 422 +
 423 +static const char * const spdif_groups[] = {
 424 +       "gpio_10", "gpio_48",
 425 +};
 426 +
 427 +static const char * const nand_groups[] = {
 428 +       "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
 429 +       "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
 430 +       "gpio46", "gpio47",
 431 +};
 432 +
 433 +static const char * const tsif1_groups[] = {
 434 +       "gpio55", "gpio56", "gpio57", "gpio58",
 435 +};
 436 +
 437 +static const char * const tsif2_groups[] = {
 438 +       "gpio59", "gpio60", "gpio61", "gpio62",
 439 +};
 440 +
 441 +static const char * const usb_fs_n_groups[] = {
 442 +       "gpio6",
 443 +};
 444 +
 445 +static const char * const usb_fs_groups[] = {
 446 +       "gpio6", "gpio7", "gpio8",
 447 +};
 448 +
 449 +static const char * const usb2_hsic_groups[] = {
 450 +       "gpio67", "gpio68",
 451 +};
 452 +
 453 +static const char * const rgmii2_groups[] = {
 454 +       "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
 455 +       "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
 456 +};
 457 +
 458 +static const char * const sata_groups[] = {
 459 +       "gpio10",
 460 +};
 461 +
 462 +static const char * const pcie1_rst_groups[] = {
 463 +       "gpio3",
 464 +};
 465 +
 466 +static const char * const pcie1_prsnt_groups[] = {
 467 +       "gpio3", "gpio11",
 468 +};
 469 +
 470 +static const char * const pcie1_pwren_n_groups[] = {
 471 +       "gpio4", "gpio12",
 472 +};
 473 +
 474 +static const char * const pcie1_pwren_groups[] = {
 475 +       "gpio4", "gpio12",
 476 +};
 477 +
 478 +static const char * const pcie1_pwrflt_groups[] = {
 479 +       "gpio5", "gpio13",
 480 +};
 481 +
 482 +static const char * const pcie1_clk_req_groups[] = {
 483 +       "gpio5",
 484 +};
 485 +
 486 +static const char * const pcie2_rst_groups[] = {
 487 +       "gpio48",
 488 +};
 489 +
 490 +static const char * const pcie2_prsnt_groups[] = {
 491 +       "gpio11", "gpio48",
 492 +};
 493 +
 494 +static const char * const pcie2_pwren_n_groups[] = {
 495 +       "gpio12", "gpio49",
 496 +};
 497 +
 498 +static const char * const pcie2_pwren_groups[] = {
 499 +       "gpio12", "gpio49",
 500 +};
 501 +
 502 +static const char * const pcie2_pwrflt_groups[] = {
 503 +       "gpio13", "gpio50",
 504 +};
 505 +
 506 +static const char * const pcie2_clk_req_groups[] = {
 507 +       "gpio50",
 508 +};
 509 +
 510 +static const char * const pcie3_rst_groups[] = {
 511 +       "gpio63",
 512 +};
 513 +
 514 +static const char * const pcie3_prsnt_groups[] = {
 515 +       "gpio11",
 516 +};
 517 +
 518 +static const char * const pcie3_pwren_n_groups[] = {
 519 +       "gpio12",
 520 +};
 521 +
 522 +static const char * const pcie3_pwren_groups[] = {
 523 +       "gpio12",
 524 +};
 525 +
 526 +static const char * const pcie3_pwrflt_groups[] = {
 527 +       "gpio13",
 528 +};
 529 +
 530 +static const char * const pcie3_clk_req_groups[] = {
 531 +       "gpio65",
 532 +};
 533 +
 534 +static const char * const ps_hold_groups[] = {
 535 +       "gpio26",
 536 +};
 537 +
 538 +static const struct msm_function ipq8064_functions[] = {
 539 +       FUNCTION(mdio),
 540 +       FUNCTION(ssbi),
 541 +       FUNCTION(spmi),
 542 +       FUNCTION(mi2s),
 543 +       FUNCTION(pdm),
 544 +       FUNCTION(audio_pcm),
 545 +       FUNCTION(gsbi1),
 546 +       FUNCTION(gsbi2),
 547 +       FUNCTION(gsbi4),
 548 +       FUNCTION(gsbi5),
 549 +       FUNCTION(gsbi5_spi_cs1),
 550 +       FUNCTION(gsbi5_spi_cs2),
 551 +       FUNCTION(gsbi5_spi_cs3),
 552 +       FUNCTION(gsbi6),
 553 +       FUNCTION(gsbi7),
 554 +       FUNCTION(nss_spi),
 555 +       FUNCTION(sdc1),
 556 +       FUNCTION(spdif),
 557 +       FUNCTION(nand),
 558 +       FUNCTION(tsif1),
 559 +       FUNCTION(tsif2),
 560 +       FUNCTION(usb_fs_n),
 561 +       FUNCTION(usb_fs),
 562 +       FUNCTION(usb2_hsic),
 563 +       FUNCTION(rgmii2),
 564 +       FUNCTION(sata),
 565 +       FUNCTION(pcie1_rst),
 566 +       FUNCTION(pcie1_prsnt),
 567 +       FUNCTION(pcie1_pwren_n),
 568 +       FUNCTION(pcie1_pwren),
 569 +       FUNCTION(pcie1_pwrflt),
 570 +       FUNCTION(pcie1_clk_req),
 571 +       FUNCTION(pcie2_rst),
 572 +       FUNCTION(pcie2_prsnt),
 573 +       FUNCTION(pcie2_pwren_n),
 574 +       FUNCTION(pcie2_pwren),
 575 +       FUNCTION(pcie2_pwrflt),
 576 +       FUNCTION(pcie2_clk_req),
 577 +       FUNCTION(pcie3_rst),
 578 +       FUNCTION(pcie3_prsnt),
 579 +       FUNCTION(pcie3_pwren_n),
 580 +       FUNCTION(pcie3_pwren),
 581 +       FUNCTION(pcie3_pwrflt),
 582 +       FUNCTION(pcie3_clk_req),
 583 +       FUNCTION(ps_hold),
 584 +};
 585 +
 586 +static const struct msm_pingroup ipq8064_groups[] = {
 587 +       PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 588 +       PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 589 +       PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 590 +       PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
 591 +       PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
 592 +       PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
 593 +       PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
 594 +       PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
 595 +       PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
 596 +       PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 597 +       PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
 598 +       PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
 599 +       PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
 600 +       PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
 601 +       PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
 602 +       PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
 603 +       PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
 604 +       PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
 605 +       PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 606 +       PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 607 +       PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 608 +       PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 609 +       PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
 610 +       PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 611 +       PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 612 +       PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 613 +       PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 614 +       PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
 615 +       PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
 616 +       PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
 617 +       PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
 618 +       PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
 619 +       PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 620 +       PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 621 +       PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
 622 +       PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
 623 +       PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 624 +       PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 625 +       PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 626 +       PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 627 +       PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 628 +       PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 629 +       PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 630 +       PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 631 +       PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 632 +       PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 633 +       PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 634 +       PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
 635 +       PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
 636 +       PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
 637 +       PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
 638 +       PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 639 +       PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
 640 +       PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 641 +       PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 642 +       PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
 643 +       PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
 644 +       PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
 645 +       PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
 646 +       PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
 647 +       PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
 648 +       PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
 649 +       PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
 650 +       PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 651 +       PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 652 +       PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 653 +       PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 654 +       PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 655 +       PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
 656 +       SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
 657 +       SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
 658 +       SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
 659 +};
 660 +
 661 +#define NUM_GPIO_PINGROUPS 69
 662 +
 663 +static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
 664 +       .pins = ipq8064_pins,
 665 +       .npins = ARRAY_SIZE(ipq8064_pins),
 666 +       .functions = ipq8064_functions,
 667 +       .nfunctions = ARRAY_SIZE(ipq8064_functions),
 668 +       .groups = ipq8064_groups,
 669 +       .ngroups = ARRAY_SIZE(ipq8064_groups),
 670 +       .ngpios = NUM_GPIO_PINGROUPS,
 671 +};
 672 +
 673 +static int ipq8064_pinctrl_probe(struct platform_device *pdev)
 674 +{
 675 +       return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
 676 +}
 677 +
 678 +static const struct of_device_id ipq8064_pinctrl_of_match[] = {
 679 +       { .compatible = "qcom,ipq8064-pinctrl", },
 680 +       { },
 681 +};
 682 +
 683 +static struct platform_driver ipq8064_pinctrl_driver = {
 684 +       .driver = {
 685 +               .name = "ipq8064-pinctrl",
 686 +               .owner = THIS_MODULE,
 687 +               .of_match_table = ipq8064_pinctrl_of_match,
 688 +       },
 689 +       .probe = ipq8064_pinctrl_probe,
 690 +       .remove = msm_pinctrl_remove,
 691 +};
 692 +
 693 +static int __init ipq8064_pinctrl_init(void)
 694 +{
 695 +       return platform_driver_register(&ipq8064_pinctrl_driver);
 696 +}
 697 +arch_initcall(ipq8064_pinctrl_init);
 698 +
 699 +static void __exit ipq8064_pinctrl_exit(void)
 700 +{
 701 +       platform_driver_unregister(&ipq8064_pinctrl_driver);
 702 +}
 703 +module_exit(ipq8064_pinctrl_exit);
 704 +
 705 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 706 +MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
 707 +MODULE_LICENSE("GPL v2");
 708 +MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);
 709 --
 710 1.7.10.4
 711