target/linux/ipq806x/patches/0091-ARM-dts-qcom-Update-msm8974-apq8074-device-trees.patch

   1 From 63495b04141e60ceb40d4632a41b7cd4a3d23dd2 Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Wed, 28 May 2014 12:01:29 -0500
   4 Subject: [PATCH 091/182] ARM: dts: qcom: Update msm8974/apq8074 device trees
   5
   6 * Move SoC peripherals into an SoC container node
   7 * Move serial enabling into board file (qcom-apq8074-dragonboard.dts)
   8 * Move spi pinctrl into board file
   9 * Cleanup cpu node to match binding spec, enable-method and compatible
  10   should be per cpu, not part of the container
  11 * Drop interrupts property from l2-cache node as its not part of the
  12   binding spec
  13 * Move timer node out of SoC container
  14
  15 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  16 ---
  17  arch/arm/boot/dts/qcom-apq8074-dragonboard.dts |   28 +++++++++++++-
  18  arch/arm/boot/dts/qcom-msm8974.dtsi            |   49 +++++++++---------------
  19  2 files changed, 45 insertions(+), 32 deletions(-)
  20
  21 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
  22 +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
  23 @@ -4,7 +4,11 @@
  24         model = "Qualcomm APQ8074 Dragonboard";
  25         compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
  26
  27 -       soc: soc {
  28 +       soc {
  29 +               serial@f991e000 {
  30 +                       status = "ok";
  31 +               };
  32 +
  33                 sdhci@f9824900 {
  34                         bus-width = <8>;
  35                         non-removable;
  36 @@ -15,5 +19,27 @@
  37                         cd-gpios = <&msmgpio 62 0x1>;
  38                         bus-width = <4>;
  39                 };
  40 +
  41 +
  42 +               pinctrl@fd510000 {
  43 +                       spi8_default: spi8_default {
  44 +                               mosi {
  45 +                                       pins = "gpio45";
  46 +                                       function = "blsp_spi8";
  47 +                               };
  48 +                               miso {
  49 +                                       pins = "gpio46";
  50 +                                       function = "blsp_spi8";
  51 +                               };
  52 +                               cs {
  53 +                                       pins = "gpio47";
  54 +                                       function = "blsp_spi8";
  55 +                               };
  56 +                               clk {
  57 +                                       pins = "gpio48";
  58 +                                       function = "blsp_spi8";
  59 +                               };
  60 +                       };
  61 +               };
  62         };
  63  };
  64 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi
  65 +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
  66 @@ -13,10 +13,10 @@
  67                 #address-cells = <1>;
  68                 #size-cells = <0>;
  69                 interrupts = <1 9 0xf04>;
  70 -               compatible = "qcom,krait";
  71 -               enable-method = "qcom,kpss-acc-v2";
  72
  73                 cpu@0 {
  74 +                       compatible = "qcom,krait";
  75 +                       enable-method = "qcom,kpss-acc-v2";
  76                         device_type = "cpu";
  77                         reg = <0>;
  78                         next-level-cache = <&L2>;
  79 @@ -24,6 +24,8 @@
  80                 };
  81
  82                 cpu@1 {
  83 +                       compatible = "qcom,krait";
  84 +                       enable-method = "qcom,kpss-acc-v2";
  85                         device_type = "cpu";
  86                         reg = <1>;
  87                         next-level-cache = <&L2>;
  88 @@ -31,6 +33,8 @@
  89                 };
  90
  91                 cpu@2 {
  92 +                       compatible = "qcom,krait";
  93 +                       enable-method = "qcom,kpss-acc-v2";
  94                         device_type = "cpu";
  95                         reg = <2>;
  96                         next-level-cache = <&L2>;
  97 @@ -38,6 +42,8 @@
  98                 };
  99
 100                 cpu@3 {
 101 +                       compatible = "qcom,krait";
 102 +                       enable-method = "qcom,kpss-acc-v2";
 103                         device_type = "cpu";
 104                         reg = <3>;
 105                         next-level-cache = <&L2>;
 106 @@ -47,7 +53,6 @@
 107                 L2: l2-cache {
 108                         compatible = "cache";
 109                         cache-level = <2>;
 110 -                       interrupts = <0 2 0x4>;
 111                         qcom,saw = <&saw_l2>;
 112                 };
 113         };
 114 @@ -57,6 +62,15 @@
 115                 interrupts = <1 7 0xf04>;
 116         };
 117
 118 +       timer {
 119 +               compatible = "arm,armv7-timer";
 120 +               interrupts = <1 2 0xf08>,
 121 +                            <1 3 0xf08>,
 122 +                            <1 4 0xf08>,
 123 +                            <1 1 0xf08>;
 124 +               clock-frequency = <19200000>;
 125 +       };
 126 +
 127         soc: soc {
 128                 #address-cells = <1>;
 129                 #size-cells = <1>;
 130 @@ -71,15 +85,6 @@
 131                               <0xf9002000 0x1000>;
 132                 };
 133
 134 -               timer {
 135 -                       compatible = "arm,armv7-timer";
 136 -                       interrupts = <1 2 0xf08>,
 137 -                                    <1 3 0xf08>,
 138 -                                    <1 4 0xf08>,
 139 -                                    <1 1 0xf08>;
 140 -                       clock-frequency = <19200000>;
 141 -               };
 142 -
 143                 timer@f9020000 {
 144                         #address-cells = <1>;
 145                         #size-cells = <1>;
 146 @@ -190,6 +195,7 @@
 147                         interrupts = <0 108 0x0>;
 148                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
 149                         clock-names = "core", "iface";
 150 +                       status = "disabled";
 151                 };
 152
 153                 sdhci@f9824900 {
 154 @@ -229,25 +235,6 @@
 155                         interrupt-controller;
 156                         #interrupt-cells = <2>;
 157                         interrupts = <0 208 0>;
 158 -
 159 -                       spi8_default: spi8_default {
 160 -                               mosi {
 161 -                                       pins = "gpio45";
 162 -                                       function = "blsp_spi8";
 163 -                               };
 164 -                               miso {
 165 -                                       pins = "gpio46";
 166 -                                       function = "blsp_spi8";
 167 -                               };
 168 -                               cs {
 169 -                                       pins = "gpio47";
 170 -                                       function = "blsp_spi8";
 171 -                               };
 172 -                               clk {
 173 -                                       pins = "gpio48";
 174 -                                       function = "blsp_spi8";
 175 -                               };
 176 -                       };
 177                 };
 178         };
 179  };