1 From 3123079878e29eb8c541111e30de4d1bb42ac6f9 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Fri, 16 May 2014 16:07:11 -0700
4 Subject: [PATCH 105/182] clk: qcom: Support display RCG clocks
6 Add support for the DSI/EDP/HDMI RCG clocks. With the proper
7 display driver in place this should allow us to support display
8 clocks on msm8974 based devices.
10 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
11 Signed-off-by: Mike Turquette <mturquette@linaro.org>
13 drivers/clk/qcom/clk-rcg.h | 3 +
14 drivers/clk/qcom/clk-rcg2.c | 299 ++++++++++++++++++++++++++++++++++++++++---
15 2 files changed, 287 insertions(+), 15 deletions(-)
17 --- a/drivers/clk/qcom/clk-rcg.h
18 +++ b/drivers/clk/qcom/clk-rcg.h
19 @@ -155,5 +155,8 @@ struct clk_rcg2 {
20 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, clkr)
22 extern const struct clk_ops clk_rcg2_ops;
23 +extern const struct clk_ops clk_edp_pixel_ops;
24 +extern const struct clk_ops clk_byte_ops;
25 +extern const struct clk_ops clk_pixel_ops;
28 --- a/drivers/clk/qcom/clk-rcg2.c
29 +++ b/drivers/clk/qcom/clk-rcg2.c
31 #include <linux/clk-provider.h>
32 #include <linux/delay.h>
33 #include <linux/regmap.h>
34 +#include <linux/math64.h>
36 #include <asm/div64.h>
38 @@ -225,31 +226,25 @@ static long clk_rcg2_determine_rate(stru
39 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, rate, p_rate, p);
42 -static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
43 +static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
45 - struct clk_rcg2 *rcg = to_clk_rcg2(hw);
46 - const struct freq_tbl *f;
50 - f = find_freq(rcg->freq_tbl, rate);
54 if (rcg->mnd_width && f->n) {
55 mask = BIT(rcg->mnd_width) - 1;
56 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + M_REG,
58 + ret = regmap_update_bits(rcg->clkr.regmap,
59 + rcg->cmd_rcgr + M_REG, mask, f->m);
63 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + N_REG,
64 - mask, ~(f->n - f->m));
65 + ret = regmap_update_bits(rcg->clkr.regmap,
66 + rcg->cmd_rcgr + N_REG, mask, ~(f->n - f->m));
70 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + D_REG,
72 + ret = regmap_update_bits(rcg->clkr.regmap,
73 + rcg->cmd_rcgr + D_REG, mask, ~f->n);
77 @@ -260,14 +255,26 @@ static int __clk_rcg2_set_rate(struct cl
78 cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
79 if (rcg->mnd_width && f->n)
80 cfg |= CFG_MODE_DUAL_EDGE;
81 - ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, mask,
83 + ret = regmap_update_bits(rcg->clkr.regmap,
84 + rcg->cmd_rcgr + CFG_REG, mask, cfg);
88 return update_config(rcg);
91 +static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
93 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
94 + const struct freq_tbl *f;
96 + f = find_freq(rcg->freq_tbl, rate);
100 + return clk_rcg2_configure(rcg, f);
103 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
104 unsigned long parent_rate)
106 @@ -290,3 +297,265 @@ const struct clk_ops clk_rcg2_ops = {
107 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
109 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
116 +static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
117 + { 52, 295 }, /* 119 M */
118 + { 11, 57 }, /* 130.25 M */
119 + { 63, 307 }, /* 138.50 M */
120 + { 11, 50 }, /* 148.50 M */
121 + { 47, 206 }, /* 154 M */
122 + { 31, 100 }, /* 205.25 M */
123 + { 107, 269 }, /* 268.50 M */
127 +static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
128 + { 31, 211 }, /* 119 M */
129 + { 32, 199 }, /* 130.25 M */
130 + { 63, 307 }, /* 138.50 M */
131 + { 11, 60 }, /* 148.50 M */
132 + { 50, 263 }, /* 154 M */
133 + { 31, 120 }, /* 205.25 M */
134 + { 119, 359 }, /* 268.50 M */
138 +static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
139 + unsigned long parent_rate)
141 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
142 + struct freq_tbl f = *rcg->freq_tbl;
143 + const struct frac_entry *frac;
144 + int delta = 100000;
145 + s64 src_rate = parent_rate;
147 + u32 mask = BIT(rcg->hid_width) - 1;
150 + if (src_rate == 810000000)
151 + frac = frac_table_810m;
153 + frac = frac_table_675m;
155 + for (; frac->num; frac++) {
157 + request *= frac->den;
158 + request = div_s64(request, frac->num);
159 + if ((src_rate < (request - delta)) ||
160 + (src_rate > (request + delta)))
163 + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
165 + f.pre_div = hid_div;
166 + f.pre_div >>= CFG_SRC_DIV_SHIFT;
171 + return clk_rcg2_configure(rcg, &f);
177 +static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
178 + unsigned long rate, unsigned long parent_rate, u8 index)
180 + /* Parent index is set statically in frequency table */
181 + return clk_edp_pixel_set_rate(hw, rate, parent_rate);
184 +static long clk_edp_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
185 + unsigned long *p_rate, struct clk **p)
187 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
188 + const struct freq_tbl *f = rcg->freq_tbl;
189 + const struct frac_entry *frac;
190 + int delta = 100000;
191 + s64 src_rate = *p_rate;
193 + u32 mask = BIT(rcg->hid_width) - 1;
196 + /* Force the correct parent */
197 + *p = clk_get_parent_by_index(hw->clk, f->src);
199 + if (src_rate == 810000000)
200 + frac = frac_table_810m;
202 + frac = frac_table_675m;
204 + for (; frac->num; frac++) {
206 + request *= frac->den;
207 + request = div_s64(request, frac->num);
208 + if ((src_rate < (request - delta)) ||
209 + (src_rate > (request + delta)))
212 + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
214 + hid_div >>= CFG_SRC_DIV_SHIFT;
217 + return calc_rate(src_rate, frac->num, frac->den, !!frac->den,
224 +const struct clk_ops clk_edp_pixel_ops = {
225 + .is_enabled = clk_rcg2_is_enabled,
226 + .get_parent = clk_rcg2_get_parent,
227 + .set_parent = clk_rcg2_set_parent,
228 + .recalc_rate = clk_rcg2_recalc_rate,
229 + .set_rate = clk_edp_pixel_set_rate,
230 + .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
231 + .determine_rate = clk_edp_pixel_determine_rate,
233 +EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
235 +static long clk_byte_determine_rate(struct clk_hw *hw, unsigned long rate,
236 + unsigned long *p_rate, struct clk **p)
238 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
239 + const struct freq_tbl *f = rcg->freq_tbl;
240 + unsigned long parent_rate, div;
241 + u32 mask = BIT(rcg->hid_width) - 1;
246 + *p = clk_get_parent_by_index(hw->clk, f->src);
247 + *p_rate = parent_rate = __clk_round_rate(*p, rate);
249 + div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
250 + div = min_t(u32, div, mask);
252 + return calc_rate(parent_rate, 0, 0, 0, div);
255 +static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
256 + unsigned long parent_rate)
258 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
259 + struct freq_tbl f = *rcg->freq_tbl;
261 + u32 mask = BIT(rcg->hid_width) - 1;
263 + div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
264 + div = min_t(u32, div, mask);
268 + return clk_rcg2_configure(rcg, &f);
271 +static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
272 + unsigned long rate, unsigned long parent_rate, u8 index)
274 + /* Parent index is set statically in frequency table */
275 + return clk_byte_set_rate(hw, rate, parent_rate);
278 +const struct clk_ops clk_byte_ops = {
279 + .is_enabled = clk_rcg2_is_enabled,
280 + .get_parent = clk_rcg2_get_parent,
281 + .set_parent = clk_rcg2_set_parent,
282 + .recalc_rate = clk_rcg2_recalc_rate,
283 + .set_rate = clk_byte_set_rate,
284 + .set_rate_and_parent = clk_byte_set_rate_and_parent,
285 + .determine_rate = clk_byte_determine_rate,
287 +EXPORT_SYMBOL_GPL(clk_byte_ops);
289 +static const struct frac_entry frac_table_pixel[] = {
297 +static long clk_pixel_determine_rate(struct clk_hw *hw, unsigned long rate,
298 + unsigned long *p_rate, struct clk **p)
300 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
301 + unsigned long request, src_rate;
302 + int delta = 100000;
303 + const struct freq_tbl *f = rcg->freq_tbl;
304 + const struct frac_entry *frac = frac_table_pixel;
305 + struct clk *parent = *p = clk_get_parent_by_index(hw->clk, f->src);
307 + for (; frac->num; frac++) {
308 + request = (rate * frac->den) / frac->num;
310 + src_rate = __clk_round_rate(parent, request);
311 + if ((src_rate < (request - delta)) ||
312 + (src_rate > (request + delta)))
315 + *p_rate = src_rate;
316 + return (src_rate * frac->num) / frac->den;
322 +static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
323 + unsigned long parent_rate)
325 + struct clk_rcg2 *rcg = to_clk_rcg2(hw);
326 + struct freq_tbl f = *rcg->freq_tbl;
327 + const struct frac_entry *frac = frac_table_pixel;
328 + unsigned long request, src_rate;
329 + int delta = 100000;
330 + u32 mask = BIT(rcg->hid_width) - 1;
332 + struct clk *parent = clk_get_parent_by_index(hw->clk, f.src);
334 + for (; frac->num; frac++) {
335 + request = (rate * frac->den) / frac->num;
337 + src_rate = __clk_round_rate(parent, request);
338 + if ((src_rate < (request - delta)) ||
339 + (src_rate > (request + delta)))
342 + regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
344 + f.pre_div = hid_div;
345 + f.pre_div >>= CFG_SRC_DIV_SHIFT;
350 + return clk_rcg2_configure(rcg, &f);
355 +static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
356 + unsigned long parent_rate, u8 index)
358 + /* Parent index is set statically in frequency table */
359 + return clk_pixel_set_rate(hw, rate, parent_rate);
362 +const struct clk_ops clk_pixel_ops = {
363 + .is_enabled = clk_rcg2_is_enabled,
364 + .get_parent = clk_rcg2_get_parent,
365 + .set_parent = clk_rcg2_set_parent,
366 + .recalc_rate = clk_rcg2_recalc_rate,
367 + .set_rate = clk_pixel_set_rate,
368 + .set_rate_and_parent = clk_pixel_set_rate_and_parent,
369 + .determine_rate = clk_pixel_determine_rate,
371 +EXPORT_SYMBOL_GPL(clk_pixel_ops);