target/linux/ipq806x/patches/0145-phy-qcom-Add-device-tree-bindings-information.patch

   1 From 37258bc8fe832e4c681593a864686f627f6d3455 Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Tue, 10 Jun 2014 13:09:01 -0500
   4 Subject: [PATCH 145/182] phy: qcom: Add device tree bindings information
   5
   6 Add binding spec for Qualcomm SoC PHYs, starting with the SATA PHY on
   7 the IPQ806x family of SoCs.
   8
   9 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  10 ---
  11  Documentation/devicetree/bindings/phy/qcom-phy.txt |   23 ++++++++++++++++++++
  12  1 file changed, 23 insertions(+)
  13  create mode 100644 Documentation/devicetree/bindings/phy/qcom-phy.txt
  14
  15 diff --git a/Documentation/devicetree/bindings/phy/qcom-phy.txt b/Documentation/devicetree/bindings/phy/qcom-phy.txt
  16 new file mode 100644
  17 index 0000000..76bfbd0
  18 --- /dev/null
  19 +++ b/Documentation/devicetree/bindings/phy/qcom-phy.txt
  20 @@ -0,0 +1,23 @@
  21 +Qualcomm IPQ806x SATA PHY Controller
  22 +------------------------------------
  23 +
  24 +SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
  25 +Each SATA PHY controller should have its own node.
  26 +
  27 +Required properties:
  28 +- compatible: compatible list, contains "qcom,ipq806x-sata-phy"
  29 +- reg: offset and length of the SATA PHY register set;
  30 +- #phy-cells: must be zero
  31 +- clocks: must be exactly one entry
  32 +- clock-names: must be "cfg"
  33 +
  34 +Example:
  35 +       sata_phy: sata-phy@1b400000 {
  36 +               compatible = "qcom,ipq806x-sata-phy";
  37 +               reg = <0x1b400000 0x200>;
  38 +
  39 +               clocks = <&gcc SATA_PHY_CFG_CLK>;
  40 +               clock-names = "cfg";
  41 +
  42 +               #phy-cells = <0>;
  43 +       };
  44 --
  45 1.7.10.4
  46