kernel: update 3.14 to 3.14.18
[openwrt/openwrt.git] / target / linux / ipq806x / patches / 0174-clk-qcom-Add-HFPLLs-to-IPQ806X-driver.patch
1 From b9b3815f2a71af88ca68d3524ee4d9b6b4739257 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Wed, 18 Jun 2014 15:57:06 -0700
4 Subject: [PATCH 174/182] clk: qcom: Add HFPLLs to IPQ806X driver
5
6 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
7 ---
8 drivers/clk/qcom/gcc-ipq806x.c | 83 ++++++++++++++++++++++++++++++++++++++++
9 1 file changed, 83 insertions(+)
10
11 --- a/drivers/clk/qcom/gcc-ipq806x.c
12 +++ b/drivers/clk/qcom/gcc-ipq806x.c
13 @@ -30,6 +30,7 @@
14 #include "clk-pll.h"
15 #include "clk-rcg.h"
16 #include "clk-branch.h"
17 +#include "clk-hfpll.h"
18 #include "reset.h"
19
20 static struct clk_pll pll0 = {
21 @@ -102,6 +103,85 @@ static struct clk_regmap pll8_vote = {
22 },
23 };
24
25 +static struct hfpll_data hfpll0_data = {
26 + .mode_reg = 0x3200,
27 + .l_reg = 0x3208,
28 + .m_reg = 0x320c,
29 + .n_reg = 0x3210,
30 + .config_reg = 0x3204,
31 + .status_reg = 0x321c,
32 + .config_val = 0x7845c665,
33 + .droop_reg = 0x3214,
34 + .droop_val = 0x0108c000,
35 + .min_rate = 600000000UL,
36 + .max_rate = 1800000000UL,
37 +};
38 +
39 +static struct clk_hfpll hfpll0 = {
40 + .d = &hfpll0_data,
41 + .clkr.hw.init = &(struct clk_init_data){
42 + .parent_names = (const char *[]){ "pxo" },
43 + .num_parents = 1,
44 + .name = "hfpll0",
45 + .ops = &clk_ops_hfpll,
46 + .flags = CLK_IGNORE_UNUSED,
47 + },
48 + .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
49 +};
50 +
51 +static struct hfpll_data hfpll1_data = {
52 + .mode_reg = 0x3240,
53 + .l_reg = 0x3248,
54 + .m_reg = 0x324c,
55 + .n_reg = 0x3250,
56 + .config_reg = 0x3244,
57 + .status_reg = 0x325c,
58 + .config_val = 0x7845c665,
59 + .droop_reg = 0x3314,
60 + .droop_val = 0x0108c000,
61 + .min_rate = 600000000UL,
62 + .max_rate = 1800000000UL,
63 +};
64 +
65 +static struct clk_hfpll hfpll1 = {
66 + .d = &hfpll1_data,
67 + .clkr.hw.init = &(struct clk_init_data){
68 + .parent_names = (const char *[]){ "pxo" },
69 + .num_parents = 1,
70 + .name = "hfpll1",
71 + .ops = &clk_ops_hfpll,
72 + .flags = CLK_IGNORE_UNUSED,
73 + },
74 + .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
75 +};
76 +
77 +static struct hfpll_data hfpll_l2_data = {
78 + .mode_reg = 0x3300,
79 + .l_reg = 0x3308,
80 + .m_reg = 0x330c,
81 + .n_reg = 0x3310,
82 + .config_reg = 0x3304,
83 + .status_reg = 0x331c,
84 + .config_val = 0x7845c665,
85 + .droop_reg = 0x3314,
86 + .droop_val = 0x0108c000,
87 + .min_rate = 600000000UL,
88 + .max_rate = 1800000000UL,
89 +};
90 +
91 +static struct clk_hfpll hfpll_l2 = {
92 + .d = &hfpll_l2_data,
93 + .clkr.hw.init = &(struct clk_init_data){
94 + .parent_names = (const char *[]){ "pxo" },
95 + .num_parents = 1,
96 + .name = "hfpll_l2",
97 + .ops = &clk_ops_hfpll,
98 + .flags = CLK_IGNORE_UNUSED,
99 + },
100 + .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
101 +};
102 +
103 +
104 static struct clk_pll pll14 = {
105 .l_reg = 0x31c4,
106 .m_reg = 0x31c8,
107 @@ -2878,6 +2958,9 @@ static struct clk_regmap *gcc_ipq806x_cl
108 [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
109 [NSSTCM_CLK] = &nss_tcm_clk.clkr,
110 [NSS_CORE_CLK] = &nss_core_clk,
111 + [PLL9] = &hfpll0.clkr,
112 + [PLL10] = &hfpll1.clkr,
113 + [PLL12] = &hfpll_l2.clkr,
114 };
115
116 static const struct qcom_reset_map gcc_ipq806x_resets[] = {