target/linux/ipq807x/patches-5.15/0006-v5.16-arm64-dts-qcom-Fix-IPQ8074-PCIe-PHY-nodes.patch

   1 From a9ab8f5de2fc752e37918cfd5dcd16d625d9ecb2 Mon Sep 17 00:00:00 2001
   2 From: Shawn Guo <shawn.guo@linaro.org>
   3 Date: Wed, 29 Sep 2021 11:42:51 +0800
   4 Subject: [PATCH] arm64: dts: qcom: Fix IPQ8074 PCIe PHY nodes
   5
   6 IPQ8074 PCIe PHY nodes are broken in the many ways:
   7
   8 - '#address-cells', '#size-cells' and 'ranges' are missing.
   9 - Child phy/lane node is missing, and the child properties like
  10   '#phy-cells' and 'clocks' are mistakenly put into parent node.
  11 - The clocks properties for parent node are missing.
  12
  13 Fix them to get the nodes comply with the bindings schema.
  14
  15 Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
  16 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  17 Link: https://lore.kernel.org/r/20210929034253.24570-9-shawn.guo@linaro.org
  18 ---
  19  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 46 +++++++++++++++++++++------
  20  1 file changed, 36 insertions(+), 10 deletions(-)
  21
  22 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  23 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  24 @@ -174,34 +174,60 @@
  25                         status = "disabled";
  26                 };
  27
  28 -               pcie_phy0: phy@86000 {
  29 +               pcie_qmp0: phy@86000 {
  30                         compatible = "qcom,ipq8074-qmp-pcie-phy";
  31                         reg = <0x00086000 0x1000>;
  32 -                       #phy-cells = <0>;
  33 -                       clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
  34 -                       clock-names = "pipe_clk";
  35 -                       clock-output-names = "pcie20_phy0_pipe_clk";
  36 +                       #address-cells = <1>;
  37 +                       #size-cells = <1>;
  38 +                       ranges;
  39
  40 +                       clocks = <&gcc GCC_PCIE0_AUX_CLK>,
  41 +                               <&gcc GCC_PCIE0_AHB_CLK>;
  42 +                       clock-names = "aux", "cfg_ahb";
  43                         resets = <&gcc GCC_PCIE0_PHY_BCR>,
  44                                 <&gcc GCC_PCIE0PHY_PHY_BCR>;
  45                         reset-names = "phy",
  46                                       "common";
  47                         status = "disabled";
  48 +
  49 +                       pcie_phy0: phy@86200 {
  50 +                               reg = <0x86200 0x16c>,
  51 +                                     <0x86400 0x200>,
  52 +                                     <0x86800 0x4f4>;
  53 +                               #phy-cells = <0>;
  54 +                               #clock-cells = <0>;
  55 +                               clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
  56 +                               clock-names = "pipe0";
  57 +                               clock-output-names = "pcie_0_pipe_clk";
  58 +                       };
  59                 };
  60
  61 -               pcie_phy1: phy@8e000 {
  62 +               pcie_qmp1: phy@8e000 {
  63                         compatible = "qcom,ipq8074-qmp-pcie-phy";
  64                         reg = <0x0008e000 0x1000>;
  65 -                       #phy-cells = <0>;
  66 -                       clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
  67 -                       clock-names = "pipe_clk";
  68 -                       clock-output-names = "pcie20_phy1_pipe_clk";
  69 +                       #address-cells = <1>;
  70 +                       #size-cells = <1>;
  71 +                       ranges;
  72
  73 +                       clocks = <&gcc GCC_PCIE1_AUX_CLK>,
  74 +                               <&gcc GCC_PCIE1_AHB_CLK>;
  75 +                       clock-names = "aux", "cfg_ahb";
  76                         resets = <&gcc GCC_PCIE1_PHY_BCR>,
  77                                 <&gcc GCC_PCIE1PHY_PHY_BCR>;
  78                         reset-names = "phy",
  79                                       "common";
  80                         status = "disabled";
  81 +
  82 +                       pcie_phy1: phy@8e200 {
  83 +                               reg = <0x8e200 0x16c>,
  84 +                                     <0x8e400 0x200>,
  85 +                                     <0x8e800 0x4f4>;
  86 +                               #phy-cells = <0>;
  87 +                               #clock-cells = <0>;
  88 +                               clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
  89 +                               clock-names = "pipe0";
  90 +                               clock-output-names = "pcie_1_pipe_clk";
  91 +                       };
  92                 };
  93
  94                 prng: rng@e3000 {