target/linux/ipq807x/patches-5.15/0034-v6.1-arm64-dts-qcom-ipq8074-fix-PCIe-PHY-serdes-size.patch

   1 From 8f63346a74c8b3e37ffab2c7a2ddb3c08793dcc2 Mon Sep 17 00:00:00 2001
   2 From: Johan Hovold <johan+linaro@kernel.org>
   3 Date: Thu, 15 Sep 2022 16:34:30 +0200
   4 Subject: [PATCH] arm64: dts: qcom: ipq8074: fix PCIe PHY serdes size
   5
   6 The size of the PCIe PHY serdes register region is 0x1c4 and the
   7 corresponding 'reg' property should specifically not include the
   8 adjacent regions that are defined in the child node (e.g. tx and rx).
   9
  10 Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
  11 Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
  12 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  13 Link: https://lore.kernel.org/r/20220915143431.19842-1-johan+linaro@kernel.org
  14 ---
  15  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
  16  1 file changed, 2 insertions(+), 2 deletions(-)
  17
  18 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  19 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  20 @@ -199,7 +199,7 @@
  21
  22                 pcie_qmp0: phy@86000 {
  23                         compatible = "qcom,ipq8074-qmp-pcie-phy";
  24 -                       reg = <0x00086000 0x1000>;
  25 +                       reg = <0x00086000 0x1c4>;
  26                         #address-cells = <1>;
  27                         #size-cells = <1>;
  28                         ranges;
  29 @@ -227,7 +227,7 @@
  30
  31                 pcie_qmp1: phy@8e000 {
  32                         compatible = "qcom,ipq8074-qmp-pcie-phy";
  33 -                       reg = <0x0008e000 0x1000>;
  34 +                       reg = <0x0008e000 0x1c4>;
  35                         #address-cells = <1>;
  36                         #size-cells = <1>;
  37                         ranges;