target/linux/ipq807x/patches-5.15/0070-v6.2-arm64-dts-qcom-ipq8074-align-TLMM-pin-configuration-.patch

   1 From 5f20690f77878b1ba24ec88df01b92d5131a6780 Mon Sep 17 00:00:00 2001
   2 From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
   3 Date: Tue, 8 Nov 2022 15:23:57 +0100
   4 Subject: [PATCH] arm64: dts: qcom: ipq8074: align TLMM pin configuration with
   5  DT schema
   6
   7 DT schema expects TLMM pin configuration nodes to be named with
   8 '-state' suffix and their optional children with '-pins' suffix.
   9
  10 Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  11 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
  12 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  13 Link: https://lore.kernel.org/r/20221108142357.67202-2-krzysztof.kozlowski@linaro.org
  14 ---
  15  arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++-----
  16  1 file changed, 5 insertions(+), 5 deletions(-)
  17
  18 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  19 +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
  20 @@ -318,35 +318,35 @@
  21                         interrupt-controller;
  22                         #interrupt-cells = <0x2>;
  23
  24 -                       serial_4_pins: serial4-pinmux {
  25 +                       serial_4_pins: serial4-state {
  26                                 pins = "gpio23", "gpio24";
  27                                 function = "blsp4_uart1";
  28                                 drive-strength = <8>;
  29                                 bias-disable;
  30                         };
  31
  32 -                       i2c_0_pins: i2c-0-pinmux {
  33 +                       i2c_0_pins: i2c-0-state {
  34                                 pins = "gpio42", "gpio43";
  35                                 function = "blsp1_i2c";
  36                                 drive-strength = <8>;
  37                                 bias-disable;
  38                         };
  39
  40 -                       spi_0_pins: spi-0-pins {
  41 +                       spi_0_pins: spi-0-state {
  42                                 pins = "gpio38", "gpio39", "gpio40", "gpio41";
  43                                 function = "blsp0_spi";
  44                                 drive-strength = <8>;
  45                                 bias-disable;
  46                         };
  47
  48 -                       hsuart_pins: hsuart-pins {
  49 +                       hsuart_pins: hsuart-state {
  50                                 pins = "gpio46", "gpio47", "gpio48", "gpio49";
  51                                 function = "blsp2_uart";
  52                                 drive-strength = <8>;
  53                                 bias-disable;
  54                         };
  55
  56 -                       qpic_pins: qpic-pins {
  57 +                       qpic_pins: qpic-state {
  58                                 pins = "gpio1", "gpio3", "gpio4",
  59                                        "gpio5", "gpio6", "gpio7",
  60                                        "gpio8", "gpio10", "gpio11",