projects / openwrt / openwrt.git / blob
? search:


fb688574d0ffd276bdcd81f8d68ee8670f6c15a9
[openwrt/openwrt.git] / target / linux / ixp4xx / patches-3.14 / 190-cambria_support.patch
1 Index: linux-3.14.25/arch/arm/mach-ixp4xx/Kconfig
2 ===================================================================
3 --- linux-3.14.25.orig/arch/arm/mach-ixp4xx/Kconfig 2014-11-30 15:26:41.488079161 +0100
4 +++ linux-3.14.25/arch/arm/mach-ixp4xx/Kconfig 2014-12-01 07:28:47.406514014 +0100
5 @@ -21,6 +21,14 @@
6 Avila Network Platform. For more information on this platform,
7 see <file:Documentation/arm/IXP4xx>.
8
9 +config MACH_CAMBRIA
10 + bool "Cambria"
11 + select PCI
12 + help
13 + Say 'Y' here if you want your kernel to support the Gateworks
14 + Cambria series. For more information on this platform,
15 + see <file:Documentation/arm/IXP4xx>.
16 +
17 config MACH_LOFT
18 bool "Loft"
19 depends on MACH_AVILA
20 @@ -218,7 +226,7 @@
21
22 config CPU_IXP43X
23 bool
24 - depends on MACH_KIXRP435
25 + depends on MACH_KIXRP435 || MACH_CAMBRIA
26 default y
27
28 config MACH_GTWX5715
29 Index: linux-3.14.25/arch/arm/mach-ixp4xx/Makefile
30 ===================================================================
31 --- linux-3.14.25.orig/arch/arm/mach-ixp4xx/Makefile 2014-11-30 15:26:41.488079161 +0100
32 +++ linux-3.14.25/arch/arm/mach-ixp4xx/Makefile 2014-12-01 07:28:47.406514014 +0100
33 @@ -7,6 +7,7 @@
34
35 obj-pci-$(CONFIG_ARCH_IXDP4XX) += ixdp425-pci.o
36 obj-pci-$(CONFIG_MACH_AVILA) += avila-pci.o
37 +obj-pci-$(CONFIG_MACH_CAMBRIA) += cambria-pci.o
38 obj-pci-$(CONFIG_MACH_IXDPG425) += ixdpg425-pci.o
39 obj-pci-$(CONFIG_ARCH_ADI_COYOTE) += coyote-pci.o
40 obj-pci-$(CONFIG_MACH_GTWX5715) += gtwx5715-pci.o
41 @@ -31,6 +32,7 @@
42
43 obj-$(CONFIG_ARCH_IXDP4XX) += ixdp425-setup.o
44 obj-$(CONFIG_MACH_AVILA) += avila-setup.o
45 +obj-$(CONFIG_MACH_CAMBRIA) += cambria-setup.o
46 obj-$(CONFIG_MACH_IXDPG425) += coyote-setup.o
47 obj-$(CONFIG_ARCH_ADI_COYOTE) += coyote-setup.o
48 obj-$(CONFIG_MACH_GTWX5715) += gtwx5715-setup.o
49 Index: linux-3.14.25/arch/arm/mach-ixp4xx/cambria-pci.c
50 ===================================================================
51 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
52 +++ linux-3.14.25/arch/arm/mach-ixp4xx/cambria-pci.c 2014-11-30 15:26:41.728087272 +0100
53 @@ -0,0 +1,78 @@
54 +/*
55 + * arch/arch/mach-ixp4xx/cambria-pci.c
56 + *
57 + * PCI setup routines for Gateworks Cambria series
58 + *
59 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
60 + *
61 + * based on coyote-pci.c:
62 + * Copyright (C) 2002 Jungo Software Technologies.
63 + * Copyright (C) 2003 MontaVista Softwrae, Inc.
64 + *
65 + * Maintainer: Imre Kaloz <kaloz@openwrt.org>
66 + *
67 + * This program is free software; you can redistribute it and/or modify
68 + * it under the terms of the GNU General Public License version 2 as
69 + * published by the Free Software Foundation.
70 + *
71 + */
72 +
73 +#include <linux/kernel.h>
74 +#include <linux/pci.h>
75 +#include <linux/init.h>
76 +#include <linux/irq.h>
77 +
78 +#include <asm/mach-types.h>
79 +#include <mach/hardware.h>
80 +#include <asm/irq.h>
81 +
82 +#include <asm/mach/pci.h>
83 +
84 +extern void ixp4xx_pci_preinit(void);
85 +extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
86 +extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
87 +
88 +void __init cambria_pci_preinit(void)
89 +{
90 + irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
91 + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
92 + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
93 + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
94 +
95 + ixp4xx_pci_preinit();
96 +}
97 +
98 +static int __init cambria_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
99 +{
100 + if (slot == 1)
101 + return IRQ_IXP4XX_GPIO11;
102 + else if (slot == 2)
103 + return IRQ_IXP4XX_GPIO10;
104 + else if (slot == 3)
105 + return IRQ_IXP4XX_GPIO9;
106 + else if (slot == 4)
107 + return IRQ_IXP4XX_GPIO8;
108 + else if (slot == 6)
109 + return IRQ_IXP4XX_GPIO10;
110 + else if (slot == 15)
111 + return IRQ_IXP4XX_GPIO8;
112 +
113 + else return -1;
114 +}
115 +
116 +struct hw_pci cambria_pci __initdata = {
117 + .nr_controllers = 1,
118 + .preinit = cambria_pci_preinit,
119 + .ops = &ixp4xx_ops,
120 + .setup = ixp4xx_setup,
121 + .map_irq = cambria_map_irq,
122 +};
123 +
124 +int __init cambria_pci_init(void)
125 +{
126 + if (machine_is_cambria())
127 + pci_common_init(&cambria_pci);
128 + return 0;
129 +}
130 +
131 +subsys_initcall(cambria_pci_init);
132 Index: linux-3.14.25/arch/arm/mach-ixp4xx/cambria-setup.c
133 ===================================================================
134 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
135 +++ linux-3.14.25/arch/arm/mach-ixp4xx/cambria-setup.c 2014-11-30 16:06:45.622389213 +0100
136 @@ -0,0 +1,1003 @@
137 +/*
138 + * arch/arm/mach-ixp4xx/cambria-setup.c
139 + *
140 + * Board setup for the Gateworks Cambria series
141 + *
142 + * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
143 + * Copyright (C) 2012 Gateworks Corporation <support@gateworks.com>
144 + *
145 + * based on coyote-setup.c:
146 + * Copyright (C) 2003-2005 MontaVista Software, Inc.
147 + *
148 + * Author: Imre Kaloz <kaloz@openwrt.org>
149 + * Tim Harvey <tharvey@gateworks.com>
150 + */
151 +
152 +#include <linux/device.h>
153 +#include <linux/gpio_keys.h>
154 +#include <linux/gpio.h>
155 +#include <linux/i2c.h>
156 +#include <linux/i2c-gpio.h>
157 +#include <linux/platform_data/at24.h>
158 +#include <linux/i2c/gw_i2c_pld.h>
159 +#include <linux/platform_data/pca953x.h>
160 +#include <linux/if_ether.h>
161 +#include <linux/init.h>
162 +#include <linux/input.h>
163 +#include <linux/kernel.h>
164 +#include <linux/leds.h>
165 +#include <linux/memory.h>
166 +#include <linux/netdevice.h>
167 +#include <linux/serial.h>
168 +#include <linux/serial_8250.h>
169 +#include <linux/slab.h>
170 +#include <linux/socket.h>
171 +#include <linux/types.h>
172 +#include <linux/tty.h>
173 +#include <linux/irq.h>
174 +#include <linux/usb/ehci_pdriver.h>
175 +
176 +#include <mach/hardware.h>
177 +#include <asm/irq.h>
178 +#include <asm/mach-types.h>
179 +#include <asm/mach/arch.h>
180 +#include <asm/mach/flash.h>
181 +#include <asm/setup.h>
182 +
183 +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
184 +
185 +struct cambria_board_info {
186 + unsigned char *model;
187 + void (*setup)(void);
188 +};
189 +
190 +static struct cambria_board_info *cambria_info __initdata;
191 +
192 +static struct flash_platform_data cambria_flash_data = {
193 + .map_name = "cfi_probe",
194 + .width = 2,
195 +};
196 +
197 +static struct resource cambria_flash_resource = {
198 + .flags = IORESOURCE_MEM,
199 +};
200 +
201 +static struct platform_device cambria_flash = {
202 + .name = "IXP4XX-Flash",
203 + .id = 0,
204 + .dev = {
205 + .platform_data = &cambria_flash_data,
206 + },
207 + .num_resources = 1,
208 + .resource = &cambria_flash_resource,
209 +};
210 +
211 +static struct i2c_gpio_platform_data cambria_i2c_gpio_data = {
212 + .sda_pin = 7,
213 + .scl_pin = 6,
214 +};
215 +
216 +static struct platform_device cambria_i2c_gpio = {
217 + .name = "i2c-gpio",
218 + .id = 0,
219 + .dev = {
220 + .platform_data = &cambria_i2c_gpio_data,
221 + },
222 +};
223 +
224 +#ifdef SFP_SERIALID
225 +static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpa_data = {
226 + .sda_pin = 113,
227 + .scl_pin = 112,
228 + .sda_is_open_drain = 0,
229 + .scl_is_open_drain = 0,
230 +};
231 +
232 +static struct platform_device cambria_i2c_gpio_sfpa = {
233 + .name = "i2c-gpio",
234 + .id = 1,
235 + .dev = {
236 + .platform_data = &cambria_i2c_gpio_sfpa_data,
237 + },
238 +};
239 +
240 +static struct i2c_gpio_platform_data cambria_i2c_gpio_sfpb_data = {
241 + .sda_pin = 115,
242 + .scl_pin = 114,
243 + .sda_is_open_drain = 0,
244 + .scl_is_open_drain = 0,
245 +};
246 +
247 +static struct platform_device cambria_i2c_gpio_sfpb = {
248 + .name = "i2c-gpio",
249 + .id = 2,
250 + .dev = {
251 + .platform_data = &cambria_i2c_gpio_sfpb_data,
252 + },
253 +};
254 +#endif // #ifdef SFP_SERIALID
255 +
256 +static struct eth_plat_info cambria_npec_data = {
257 + .phy = 1,
258 + .rxq = 4,
259 + .txreadyq = 21,
260 +};
261 +
262 +static struct eth_plat_info cambria_npea_data = {
263 + .phy = 2,
264 + .rxq = 2,
265 + .txreadyq = 19,
266 +};
267 +
268 +static struct platform_device cambria_npec_device = {
269 + .name = "ixp4xx_eth",
270 + .id = IXP4XX_ETH_NPEC,
271 + .dev.platform_data = &cambria_npec_data,
272 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
273 +};
274 +
275 +static struct platform_device cambria_npea_device = {
276 + .name = "ixp4xx_eth",
277 + .id = IXP4XX_ETH_NPEA,
278 + .dev.platform_data = &cambria_npea_data,
279 + .dev.coherent_dma_mask = DMA_BIT_MASK(32),
280 +};
281 +
282 +static struct resource cambria_uart_resource = {
283 + .start = IXP4XX_UART1_BASE_PHYS,
284 + .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
285 + .flags = IORESOURCE_MEM,
286 +};
287 +
288 +static struct plat_serial8250_port cambria_uart_data[] = {
289 + {
290 + .mapbase = IXP4XX_UART1_BASE_PHYS,
291 + .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
292 + .irq = IRQ_IXP4XX_UART1,
293 + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
294 + .iotype = UPIO_MEM,
295 + .regshift = 2,
296 + .uartclk = IXP4XX_UART_XTAL,
297 + },
298 + { },
299 +};
300 +
301 +static struct platform_device cambria_uart = {
302 + .name = "serial8250",
303 + .id = PLAT8250_DEV_PLATFORM,
304 + .dev = {
305 + .platform_data = cambria_uart_data,
306 + },
307 + .num_resources = 1,
308 + .resource = &cambria_uart_resource,
309 +};
310 +
311 +static struct resource cambria_optional_uart_resources[] = {
312 + {
313 + .start = 0x52000000,
314 + .end = 0x52000fff,
315 + .flags = IORESOURCE_MEM
316 + },
317 + {
318 + .start = 0x53000000,
319 + .end = 0x53000fff,
320 + .flags = IORESOURCE_MEM
321 + },
322 + {
323 + .start = 0x52000000,
324 + .end = 0x52000fff,
325 + .flags = IORESOURCE_MEM
326 + },
327 + {
328 + .start = 0x52000000,
329 + .end = 0x52000fff,
330 + .flags = IORESOURCE_MEM
331 + },
332 + {
333 + .start = 0x52000000,
334 + .end = 0x52000fff,
335 + .flags = IORESOURCE_MEM
336 + },
337 + {
338 + .start = 0x52000000,
339 + .end = 0x52000fff,
340 + .flags = IORESOURCE_MEM
341 + },
342 + {
343 + .start = 0x52000000,
344 + .end = 0x52000fff,
345 + .flags = IORESOURCE_MEM
346 + },
347 + {
348 + .start = 0x53000000,
349 + .end = 0x53000fff,
350 + .flags = IORESOURCE_MEM
351 + }
352 +};
353 +
354 +static struct plat_serial8250_port cambria_optional_uart_data[] = {
355 + {
356 + .flags = UPF_BOOT_AUTOCONF,
357 + .iotype = UPIO_MEM_DELAY,
358 + .regshift = 0,
359 + .uartclk = 1843200,
360 + .rw_delay = 10,
361 + },
362 + {
363 + .flags = UPF_BOOT_AUTOCONF,
364 + .iotype = UPIO_MEM_DELAY,
365 + .regshift = 0,
366 + .uartclk = 1843200,
367 + .rw_delay = 10,
368 + },
369 + {
370 + .flags = UPF_BOOT_AUTOCONF,
371 + .iotype = UPIO_MEM,
372 + .regshift = 0,
373 + .uartclk = 18432000,
374 + },
375 + {
376 + .flags = UPF_BOOT_AUTOCONF,
377 + .iotype = UPIO_MEM,
378 + .regshift = 0,
379 + .uartclk = 18432000,
380 + },
381 + {
382 + .flags = UPF_BOOT_AUTOCONF,
383 + .iotype = UPIO_MEM,
384 + .regshift = 0,
385 + .uartclk = 18432000,
386 + },
387 + {
388 + .flags = UPF_BOOT_AUTOCONF,
389 + .iotype = UPIO_MEM,
390 + .regshift = 0,
391 + .uartclk = 18432000,
392 + },
393 + {
394 + .flags = UPF_BOOT_AUTOCONF,
395 + .iotype = UPIO_MEM,
396 + .regshift = 0,
397 + .uartclk = 18432000,
398 + },
399 + { },
400 +};
401 +
402 +static struct platform_device cambria_optional_uart = {
403 + .name = "serial8250",
404 + .id = PLAT8250_DEV_PLATFORM1,
405 + .dev.platform_data = cambria_optional_uart_data,
406 + .num_resources = 2,
407 + .resource = cambria_optional_uart_resources,
408 +};
409 +
410 +static struct resource cambria_pata_resources[] = {
411 + {
412 + .flags = IORESOURCE_MEM
413 + },
414 + {
415 + .flags = IORESOURCE_MEM,
416 + },
417 + {
418 + .name = "intrq",
419 + .start = IRQ_IXP4XX_GPIO12,
420 + .end = IRQ_IXP4XX_GPIO12,
421 + .flags = IORESOURCE_IRQ,
422 + },
423 +};
424 +
425 +static struct ixp4xx_pata_data cambria_pata_data = {
426 + .cs0_bits = 0xbfff3c03,
427 + .cs1_bits = 0xbfff3c03,
428 +};
429 +
430 +static struct platform_device cambria_pata = {
431 + .name = "pata_ixp4xx_cf",
432 + .id = 0,
433 + .dev.platform_data = &cambria_pata_data,
434 + .num_resources = ARRAY_SIZE(cambria_pata_resources),
435 + .resource = cambria_pata_resources,
436 +};
437 +
438 +static struct gpio_led cambria_gpio_leds[] = {
439 + {
440 + .name = "user",
441 + .gpio = 5,
442 + .active_low = 1,
443 + },
444 + {
445 + .name = "user2",
446 + .gpio = 0,
447 + .active_low = 1,
448 + },
449 + {
450 + .name = "user3",
451 + .gpio = 0,
452 + .active_low = 1,
453 + },
454 + {
455 + .name = "user4",
456 + .gpio = 0,
457 + .active_low = 1,
458 + }
459 +};
460 +
461 +static struct gpio_led_platform_data cambria_gpio_leds_data = {
462 + .num_leds = 1,
463 + .leds = cambria_gpio_leds,
464 +};
465 +
466 +static struct platform_device cambria_gpio_leds_device = {
467 + .name = "leds-gpio",
468 + .id = -1,
469 + .dev.platform_data = &cambria_gpio_leds_data,
470 +};
471 +
472 +static struct resource cambria_gpio_resources[] = {
473 + {
474 + .name = "gpio",
475 + .flags = 0,
476 + },
477 +};
478 +
479 +static struct gpio cambria_gpios_gw2350[] = {
480 + // ARM GPIO
481 +#if 0 // configured from bootloader
482 + { 0, GPIOF_IN, "ARM_DIO0" },
483 + { 1, GPIOF_IN, "ARM_DIO1" },
484 + { 2, GPIOF_IN, "ARM_DIO2" },
485 + { 3, GPIOF_IN, "ARM_DIO3" },
486 + { 4, GPIOF_IN, "ARM_DIO4" },
487 + { 5, GPIOF_IN, "ARM_DIO5" },
488 + { 12, GPIOF_OUT_INIT_HIGH, "WDOGEN#" },
489 +#endif
490 + { 8, GPIOF_IN, "ARM_DIO8" },
491 + { 9, GPIOF_IN, "ARM_DIO9" },
492 +};
493 +
494 +static struct gpio cambria_gpios_gw2358[] = {
495 + // ARM GPIO
496 +#if 0 // configured from bootloader
497 + { 0, GPIOF_IN, "*VINLOW#" },
498 + { 2, GPIOF_IN, "*GPS_PPS" },
499 + { 3, GPIOF_IN, "*GPS_IRQ#" },
500 + { 4, GPIOF_IN, "*RS485_IRQ#" },
501 + { 5, GPIOF_IN, "*SER_EN#" },
502 + { 14, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" },
503 +#endif
504 +};
505 +
506 +static struct gpio cambria_gpios_gw2359[] = {
507 + // ARM GPIO
508 +#if 0 // configured from bootloader
509 + { 0, GPIOF_IN, "*PCA_IRQ#" },
510 + { 1, GPIOF_IN, "ARM_DIO1" },
511 + { 2, GPIOF_IN, "ARM_DIO2" },
512 + { 3, GPIOF_IN, "ARM_DIO3" },
513 + { 4, GPIOF_IN, "ARM_DIO4" },
514 + { 5, GPIOF_IN, "ARM_DIO5" },
515 + { 8, GPIOF_OUT_INIT_HIGH, "*WDOGEN#" },
516 +#endif
517 + { 11, GPIOF_OUT_INIT_HIGH, "*SER_EN" }, // console serial enable
518 + { 12, GPIOF_IN, "*GSC_IRQ#" },
519 + { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"},
520 + // GSC GPIO
521 +#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
522 + {100, GPIOF_IN, "*USER_PB#" },
523 +#endif
524 + {103, GPIOF_OUT_INIT_HIGH, "*5V_EN" }, // 5V aux supply enable
525 + {108, GPIOF_IN, "*SMUXDA0" },
526 + {109, GPIOF_IN, "*SMUXDA1" },
527 + {110, GPIOF_IN, "*SMUXDA2" },
528 + {111, GPIOF_IN, "*SMUXDB0" },
529 + {112, GPIOF_IN, "*SMUXDB1" },
530 + {113, GPIOF_IN, "*SMUXDB2" },
531 + // PCA GPIO
532 + {118, GPIOF_IN, "*USIM2_DET#"}, // USIM2 Detect
533 + {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCI, 0=FP)
534 + {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCI, 0=FP)
535 + {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect
536 + {123, GPIOF_OUT_INIT_HIGH, "*COM1_DTR#" }, // J21/J10
537 + {124, GPIOF_IN, "*COM1_DSR#" }, // J21/J10
538 + {127, GPIOF_IN, "PCA_DIO0" },
539 + {128, GPIOF_IN, "PCA_DIO1" },
540 + {129, GPIOF_IN, "PCA_DIO2" },
541 + {130, GPIOF_IN, "PCA_DIO3" },
542 + {131, GPIOF_IN, "PCA_DIO4" },
543 +};
544 +
545 +static struct gpio cambria_gpios_gw2360[] = {
546 + // ARM GPIO
547 + { 0, GPIOF_IN, "*PCA_IRQ#" },
548 + { 11, GPIOF_OUT_INIT_LOW, "*SER0_EN#" },
549 + { 12, GPIOF_IN, "*GSC_IRQ#" },
550 + { 13, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#"},
551 + // GSC GPIO
552 +#if !(IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
553 + {100, GPIOF_IN, "*USER_PB#" },
554 +#endif
555 + {108, GPIOF_OUT_INIT_LOW, "*ENET1_EN#" }, // ENET1 TX Enable
556 + {109, GPIOF_IN, "*ENET1_PRES#" }, // ENET1 Detect (0=SFP present)
557 + {110, GPIOF_OUT_INIT_LOW, "*ENET2_EN#" }, // ENET2 TX Enable
558 + {111, GPIOF_IN, "*ENET2_PRES#"}, // ENET2 Detect (0=SFP present)
559 + // PCA GPIO
560 + {116, GPIOF_OUT_INIT_HIGH, "*USIM2_LOC"}, // USIM2 Select (1=Loc, 0=Rem)
561 + {117, GPIOF_IN, "*USIM2_DET_LOC#" },// USIM2 Detect (Local Slot)
562 + {118, GPIOF_IN, "*USIM2_DET_REM#" },// USIM2 Detect (Remote Slot)
563 + {120, GPIOF_OUT_INIT_LOW, "*USB1_PCI_SEL"}, // USB1 Select (1=PCIe1, 0=J1)
564 + {121, GPIOF_OUT_INIT_LOW, "*USB2_PCI_SEL"}, // USB2 Select (1=PCIe2, 0=J1)
565 + {122, GPIOF_IN, "*USIM1_DET#"}, // USIM1 Detect
566 + {127, GPIOF_IN, "DIO0" },
567 + {128, GPIOF_IN, "DIO1" },
568 + {129, GPIOF_IN, "DIO2" },
569 + {130, GPIOF_IN, "DIO3" },
570 + {131, GPIOF_IN, "DIO4" },
571 +};
572 +
573 +static struct latch_led cambria_latch_leds[] = {
574 + {
575 + .name = "ledA", /* green led */
576 + .bit = 0,
577 + },
578 + {
579 + .name = "ledB", /* green led */
580 + .bit = 1,
581 + },
582 + {
583 + .name = "ledC", /* green led */
584 + .bit = 2,
585 + },
586 + {
587 + .name = "ledD", /* green led */
588 + .bit = 3,
589 + },
590 + {
591 + .name = "ledE", /* green led */
592 + .bit = 4,
593 + },
594 + {
595 + .name = "ledF", /* green led */
596 + .bit = 5,
597 + },
598 + {
599 + .name = "ledG", /* green led */
600 + .bit = 6,
601 + },
602 + {
603 + .name = "ledH", /* green led */
604 + .bit = 7,
605 + }
606 +};
607 +
608 +static struct latch_led_platform_data cambria_latch_leds_data = {
609 + .num_leds = 8,
610 + .leds = cambria_latch_leds,
611 + .mem = 0x53F40000,
612 +};
613 +
614 +static struct platform_device cambria_latch_leds_device = {
615 + .name = "leds-latch",
616 + .id = -1,
617 + .dev.platform_data = &cambria_latch_leds_data,
618 +};
619 +
620 +static struct resource cambria_usb0_resources[] = {
621 + {
622 + .start = 0xCD000000,
623 + .end = 0xCD000300,
624 + .flags = IORESOURCE_MEM,
625 + },
626 + {
627 + .start = 32,
628 + .flags = IORESOURCE_IRQ,
629 + },
630 +};
631 +
632 +static struct resource cambria_usb1_resources[] = {
633 + {
634 + .start = 0xCE000000,
635 + .end = 0xCE000300,
636 + .flags = IORESOURCE_MEM,
637 + },
638 + {
639 + .start = 33,
640 + .flags = IORESOURCE_IRQ,
641 + },
642 +};
643 +
644 +static u64 ehci_dma_mask = ~(u32)0;
645 +
646 +static struct usb_ehci_pdata cambria_usb_pdata = {
647 + .big_endian_desc = 1,
648 + .big_endian_mmio = 1,
649 + .has_tt = 1,
650 + .caps_offset = 0x100,
651 +};
652 +
653 +static struct platform_device cambria_usb0_device = {
654 + .name = "ehci-platform",
655 + .id = 0,
656 + .resource = cambria_usb0_resources,
657 + .num_resources = ARRAY_SIZE(cambria_usb0_resources),
658 + .dev = {
659 + .dma_mask = &ehci_dma_mask,
660 + .coherent_dma_mask = 0xffffffff,
661 + .platform_data = &cambria_usb_pdata,
662 + },
663 +};
664 +
665 +static struct platform_device cambria_usb1_device = {
666 + .name = "ehci-platform",
667 + .id = 1,
668 + .resource = cambria_usb1_resources,
669 + .num_resources = ARRAY_SIZE(cambria_usb1_resources),
670 + .dev = {
671 + .dma_mask = &ehci_dma_mask,
672 + .coherent_dma_mask = 0xffffffff,
673 + .platform_data = &cambria_usb_pdata,
674 + },
675 +};
676 +
677 +static struct gw_i2c_pld_platform_data gw_i2c_pld_data0 = {
678 + .gpio_base = 16,
679 + .nr_gpio = 8,
680 +};
681 +
682 +static struct gw_i2c_pld_platform_data gw_i2c_pld_data1 = {
683 + .gpio_base = 24,
684 + .nr_gpio = 2,
685 +};
686 +
687 +
688 +static struct gpio_keys_button cambria_gpio_buttons[] = {
689 + {
690 + .desc = "user",
691 + .type = EV_KEY,
692 + .code = BTN_0,
693 + .debounce_interval = 6,
694 + .gpio = 25,
695 + }
696 +};
697 +
698 +static struct gpio_keys_platform_data cambria_gpio_buttons_data = {
699 + .poll_interval = 500,
700 + .nbuttons = 1,
701 + .buttons = cambria_gpio_buttons,
702 +};
703 +
704 +static struct platform_device cambria_gpio_buttons_device = {
705 + .name = "gpio-keys-polled",
706 + .id = -1,
707 + .dev.platform_data = &cambria_gpio_buttons_data,
708 +};
709 +
710 +static struct platform_device *cambria_devices[] __initdata = {
711 + &cambria_i2c_gpio,
712 + &cambria_flash,
713 + &cambria_uart,
714 +};
715 +
716 +static int cambria_register_gpio(struct gpio *array, size_t num)
717 +{
718 + int i, err, ret;
719 +
720 + ret = 0;
721 + for (i = 0; i < num; i++, array++) {
722 + const char *label = array->label;
723 + if (label[0] == '*')
724 + label++;
725 + err = gpio_request_one(array->gpio, array->flags, label);
726 + if (err)
727 + ret = err;
728 + else {
729 + err = gpio_export(array->gpio, array->label[0] != '*');
730 + }
731 + }
732 + return ret;
733 +}
734 +
735 +static void __init cambria_gw23xx_setup(void)
736 +{
737 + cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
738 + (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
739 + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
740 +
741 + platform_device_register(&cambria_npec_device);
742 + platform_device_register(&cambria_npea_device);
743 +}
744 +
745 +static void __init cambria_gw2350_setup(void)
746 +{
747 + *IXP4XX_EXP_CS2 = 0xBFFF3C43;
748 + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
749 + cambria_optional_uart_data[0].mapbase = 0x52FF0000;
750 + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52FF0000, 0x0fff);
751 + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
752 +
753 + *IXP4XX_EXP_CS3 = 0xBFFF3C43;
754 + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
755 + cambria_optional_uart_data[1].mapbase = 0x53FF0000;
756 + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53FF0000, 0x0fff);
757 + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
758 +
759 + cambria_gpio_resources[0].start = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) | (1 << 4) |\
760 + (1 << 5) | (1 << 8) | (1 << 9) | (1 << 12);
761 + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
762 +
763 + platform_device_register(&cambria_optional_uart);
764 + platform_device_register(&cambria_npec_device);
765 + platform_device_register(&cambria_npea_device);
766 +
767 + platform_device_register(&cambria_usb0_device);
768 + platform_device_register(&cambria_usb1_device);
769 +
770 + platform_device_register(&cambria_gpio_leds_device);
771 +
772 + /* gpio config (/sys/class/gpio) */
773 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2350));
774 +}
775 +
776 +static void __init cambria_gw2358_setup(void)
777 +{
778 + *IXP4XX_EXP_CS3 = 0xBFFF3C43; // bit0 = 16bit vs 8bit bus
779 + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
780 + cambria_optional_uart_data[0].mapbase = 0x53FC0000;
781 + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x53FC0000, 0x0fff);
782 + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO3;
783 +
784 + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
785 + cambria_optional_uart_data[1].mapbase = 0x53F80000;
786 + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x53F80000, 0x0fff);
787 + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO4;
788 +
789 + cambria_gpio_resources[0].start = (1 << 14) | (1 << 16) | (1 << 17) | (1 << 18) |\
790 + (1 << 19) | (1 << 20) | (1 << 24) | (1 << 25);
791 + cambria_gpio_resources[0].end = cambria_gpio_resources[0].start;
792 +
793 + platform_device_register(&cambria_optional_uart);
794 +
795 + platform_device_register(&cambria_npec_device);
796 + platform_device_register(&cambria_npea_device);
797 +
798 + platform_device_register(&cambria_usb0_device);
799 + platform_device_register(&cambria_usb1_device);
800 +
801 + platform_device_register(&cambria_pata);
802 +
803 + cambria_gpio_leds[0].gpio = 24;
804 + platform_device_register(&cambria_gpio_leds_device);
805 +
806 + platform_device_register(&cambria_latch_leds_device);
807 +
808 + platform_device_register(&cambria_gpio_buttons_device);
809 +
810 + /* gpio config (/sys/class/gpio) */
811 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2358));
812 +}
813 +
814 +static void __init cambria_gw2359_setup(void)
815 +{
816 +#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE)
817 + /* The mvswitch driver has some hard-coded values which could
818 + * easily be turned into a platform resource if needed. For now they
819 + * match our hardware configuration:
820 + * MV_BASE 0x10 - phy base address
821 + * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module)
822 + * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1)
823 + *
824 + * The mvswitch driver registers a fixup which forces a driver match
825 + * if phy_addr matches MV_BASE
826 + *
827 + * Two static defautl VLAN's are created: WAN port in 1, and all other ports
828 + * in the other.
829 + */
830 + cambria_npea_data.phy = 0x10; // mvswitch driver catches this
831 +#else
832 + // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the genphy driver
833 + cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
834 + // CPU NPE-C is in bridge bypass mode to Port4 PHY@0x14
835 + cambria_npec_data.phy = 0x14;
836 +#endif
837 + platform_device_register(&cambria_npec_device);
838 + platform_device_register(&cambria_npea_device);
839 +
840 + platform_device_register(&cambria_usb0_device);
841 + platform_device_register(&cambria_usb1_device);
842 +
843 + cambria_gpio_leds_data.num_leds = 3;
844 + cambria_gpio_leds[0].name = "user1";
845 + cambria_gpio_leds[0].gpio = 125; // PNLLED1#
846 + cambria_gpio_leds[1].gpio = 126; // PNLLED3#
847 + cambria_gpio_leds[2].gpio = 119; // PNLLED4#
848 + platform_device_register(&cambria_gpio_leds_device);
849 +
850 +#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
851 + cambria_gpio_buttons[0].gpio = 100;
852 + platform_device_register(&cambria_gpio_buttons_device);
853 +#endif
854 +
855 + /* gpio config (/sys/class/gpio) */
856 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2359));
857 +}
858 +
859 +static void __init cambria_gw2360_setup(void)
860 +{
861 + /* The GW2360 has 8 UARTs in addition to the 1 IXP4xxx UART.
862 + * The chip-selects are expanded via a 3-to-8 decoder and CS2
863 + * and they are 8bit devices
864 + */
865 + *IXP4XX_EXP_CS2 = 0xBFFF3C43;
866 + cambria_optional_uart_data[0].mapbase = 0x52000000;
867 + cambria_optional_uart_data[0].membase = (void __iomem *)ioremap(0x52000000, 0x0fff);
868 + cambria_optional_uart_data[0].uartclk = 18432000;
869 + cambria_optional_uart_data[0].iotype = UPIO_MEM;
870 + cambria_optional_uart_data[0].irq = IRQ_IXP4XX_GPIO2;
871 + irq_set_irq_type(IRQ_IXP4XX_GPIO2, IRQ_TYPE_EDGE_RISING);
872 +
873 + cambria_optional_uart_data[1].mapbase = 0x52000008;
874 + cambria_optional_uart_data[1].membase = (void __iomem *)ioremap(0x52000008, 0x0fff);
875 + cambria_optional_uart_data[1].uartclk = 18432000;
876 + cambria_optional_uart_data[1].iotype = UPIO_MEM;
877 + cambria_optional_uart_data[1].irq = IRQ_IXP4XX_GPIO3;
878 + irq_set_irq_type(IRQ_IXP4XX_GPIO3, IRQ_TYPE_EDGE_RISING);
879 +
880 + cambria_optional_uart_data[2].mapbase = 0x52000010;
881 + cambria_optional_uart_data[2].membase = (void __iomem *)ioremap(0x52000010, 0x0fff);
882 + cambria_optional_uart_data[2].uartclk = 18432000;
883 + cambria_optional_uart_data[2].iotype = UPIO_MEM;
884 + cambria_optional_uart_data[2].irq = IRQ_IXP4XX_GPIO4;
885 + irq_set_irq_type(IRQ_IXP4XX_GPIO4, IRQ_TYPE_EDGE_RISING);
886 +
887 + cambria_optional_uart_data[3].mapbase = 0x52000018;
888 + cambria_optional_uart_data[3].membase = (void __iomem *)ioremap(0x52000018, 0x0fff);
889 + cambria_optional_uart_data[3].uartclk = 18432000;
890 + cambria_optional_uart_data[3].iotype = UPIO_MEM;
891 + cambria_optional_uart_data[3].irq = IRQ_IXP4XX_GPIO5;
892 + irq_set_irq_type(IRQ_IXP4XX_GPIO5, IRQ_TYPE_EDGE_RISING);
893 +
894 + cambria_optional_uart_data[4].mapbase = 0x52000020;
895 + cambria_optional_uart_data[4].membase = (void __iomem *)ioremap(0x52000020, 0x0fff);
896 + cambria_optional_uart_data[4].uartclk = 18432000;
897 + cambria_optional_uart_data[4].iotype = UPIO_MEM;
898 + cambria_optional_uart_data[4].irq = IRQ_IXP4XX_GPIO8;
899 + irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_EDGE_RISING);
900 +
901 + cambria_optional_uart_data[5].mapbase = 0x52000028;
902 + cambria_optional_uart_data[5].membase = (void __iomem *)ioremap(0x52000028, 0x0fff);
903 + cambria_optional_uart_data[5].uartclk = 18432000;
904 + cambria_optional_uart_data[5].iotype = UPIO_MEM;
905 + cambria_optional_uart_data[5].irq = IRQ_IXP4XX_GPIO9;
906 + irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_EDGE_RISING);
907 +
908 + cambria_optional_uart_data[6].mapbase = 0x52000030;
909 + cambria_optional_uart_data[6].membase = (void __iomem *)ioremap(0x52000030, 0x0fff);
910 + cambria_optional_uart_data[6].uartclk = 18432000;
911 + cambria_optional_uart_data[6].iotype = UPIO_MEM;
912 + cambria_optional_uart_data[6].irq = IRQ_IXP4XX_GPIO10;
913 + irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_EDGE_RISING);
914 +
915 + cambria_optional_uart.num_resources = 7,
916 + platform_device_register(&cambria_optional_uart);
917 +
918 +#if defined(CONFIG_MVSWITCH_PHY) || defined(CONFIG_MVSWITCH_PHY_MODULE)
919 + /* The mvswitch driver has some hard-coded values which could
920 + * easily be turned into a platform resource if needed. For now they
921 + * match our hardware configuration:
922 + * MV_BASE 0x10 - phy base address
923 + * MV_WANPORT 0 - Port0 (ENET2) is WAN (SFP module)
924 + * MV_CPUPORT 5 - Port5 is CPU NPEA (eth1)
925 + *
926 + * The mvswitch driver registers a fixup which forces a driver match
927 + * if phy_addr matches MV_BASE
928 + *
929 + * Two static defautl VLAN's are created: WAN port in 1, and all other ports
930 + * in the other.
931 + */
932 + cambria_npea_data.phy = 0x10; // mvswitch driver catches this
933 +#else
934 + // Switch Port5 to CPU is MII<->MII (no PHY) - this disables the generic PHY driver
935 + cambria_npea_data.phy = IXP4XX_ETH_PHY_MAX_ADDR;
936 +#endif
937 +
938 + // disable genphy autonegotiation on NPE-C PHY (eth1) as its 100BaseFX
939 + //cambria_npec_data.noautoneg = 1; // disable autoneg
940 + cambria_npec_data.speed_10 = 0; // 100mbps
941 + cambria_npec_data.half_duplex = 0; // full-duplex
942 + platform_device_register(&cambria_npec_device);
943 + platform_device_register(&cambria_npea_device);
944 +
945 + platform_device_register(&cambria_usb0_device);
946 + platform_device_register(&cambria_usb1_device);
947 +
948 + cambria_gpio_leds_data.num_leds = 3;
949 + cambria_gpio_leds[0].name = "user1";
950 + cambria_gpio_leds[0].gpio = 125;
951 + cambria_gpio_leds[1].gpio = 126;
952 + cambria_gpio_leds[2].gpio = 119;
953 + platform_device_register(&cambria_gpio_leds_device);
954 +
955 +#if (IS_ENABLED(CONFIG_KEYBOARD_GPIO_POLLED))
956 + cambria_gpio_buttons[0].gpio = 100;
957 + platform_device_register(&cambria_gpio_buttons_device);
958 +#endif
959 +
960 +#ifdef SFP_SERIALID
961 + /* the SFP modules each have an i2c bus for serial ident via GSC GPIO
962 + * To use these the i2c-gpio driver must be changed to use the _cansleep
963 + * varients of gpio_get_value/gpio_set_value (I don't know why it doesn't
964 + * use that anyway as it doesn't operate in an IRQ context).
965 + * Additionally the i2c-gpio module must set the gpio to output-high prior
966 + * to changing direction to an input to enable internal Pullups
967 + */
968 + platform_device_register(&cambria_i2c_gpio_sfpa);
969 + platform_device_register(&cambria_i2c_gpio_sfpb);
970 +#endif
971 +
972 + /* gpio config (/sys/class/gpio) */
973 + cambria_register_gpio(ARRAY_AND_SIZE(cambria_gpios_gw2360));
974 +}
975 +
976 +static struct cambria_board_info cambria_boards[] __initdata = {
977 + {
978 + .model = "GW2350",
979 + .setup = cambria_gw2350_setup,
980 + }, {
981 + .model = "GW2351",
982 + .setup = cambria_gw2350_setup,
983 + }, {
984 + .model = "GW2358",
985 + .setup = cambria_gw2358_setup,
986 + }, {
987 + .model = "GW2359",
988 + .setup = cambria_gw2359_setup,
989 + }, {
990 + .model = "GW2360",
991 + .setup = cambria_gw2360_setup,
992 + }, {
993 + .model = "GW2371",
994 + .setup = cambria_gw2358_setup,
995 + }
996 +};
997 +
998 +static struct cambria_board_info * __init cambria_find_board_info(char *model)
999 +{
1000 + int i;
1001 + model[6] = '\0';
1002 +
1003 + for (i = 0; i < ARRAY_SIZE(cambria_boards); i++) {
1004 + struct cambria_board_info *info = &cambria_boards[i];
1005 + if (strcmp(info->model, model) == 0)
1006 + return info;
1007 + }
1008 +
1009 + return NULL;
1010 +}
1011 +
1012 +static struct memory_accessor *at24_mem_acc;
1013 +
1014 +static void at24_setup(struct memory_accessor *mem_acc, void *context)
1015 +{
1016 + char mac_addr[ETH_ALEN];
1017 + char model[7];
1018 +
1019 + at24_mem_acc = mem_acc;
1020 +
1021 + /* Read MAC addresses */
1022 + if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x0, 6) == 6) {
1023 + memcpy(&cambria_npec_data.hwaddr, mac_addr, ETH_ALEN);
1024 + }
1025 + if (at24_mem_acc->read(at24_mem_acc, mac_addr, 0x6, 6) == 6) {
1026 + memcpy(&cambria_npea_data.hwaddr, mac_addr, ETH_ALEN);
1027 + }
1028 +
1029 + /* Read the first 6 bytes of the model number */
1030 + if (at24_mem_acc->read(at24_mem_acc, model, 0x20, 6) == 6) {
1031 + cambria_info = cambria_find_board_info(model);
1032 + }
1033 +
1034 +}
1035 +
1036 +static struct at24_platform_data cambria_eeprom_info = {
1037 + .byte_len = 1024,
1038 + .page_size = 16,
1039 + .flags = AT24_FLAG_READONLY,
1040 + .setup = at24_setup,
1041 +};
1042 +
1043 +static struct pca953x_platform_data cambria_pca_data = {
1044 + .gpio_base = 100,
1045 + .irq_base = -1,
1046 +};
1047 +
1048 +static struct pca953x_platform_data cambria_pca2_data = {
1049 + .gpio_base = 116,
1050 + .irq_base = -1,
1051 +};
1052 +
1053 +static struct i2c_board_info __initdata cambria_i2c_board_info[] = {
1054 + {
1055 + I2C_BOARD_INFO("pca9555", 0x23),
1056 + .platform_data = &cambria_pca_data,
1057 + },
1058 + {
1059 + I2C_BOARD_INFO("pca9555", 0x27),
1060 + .platform_data = &cambria_pca2_data,
1061 + },
1062 + {
1063 + I2C_BOARD_INFO("ds1672", 0x68),
1064 + },
1065 + {
1066 + I2C_BOARD_INFO("gsp", 0x29),
1067 + },
1068 + {
1069 + I2C_BOARD_INFO("ad7418", 0x28),
1070 + },
1071 + {
1072 + I2C_BOARD_INFO("24c08", 0x51),
1073 + .platform_data = &cambria_eeprom_info
1074 + },
1075 + {
1076 + I2C_BOARD_INFO("gw_i2c_pld", 0x56),
1077 + .platform_data = &gw_i2c_pld_data0,
1078 + },
1079 + {
1080 + I2C_BOARD_INFO("gw_i2c_pld", 0x57),
1081 + .platform_data = &gw_i2c_pld_data1,
1082 + },
1083 +};
1084 +
1085 +static void __init cambria_init(void)
1086 +{
1087 + ixp4xx_sys_init();
1088 +
1089 + cambria_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
1090 + cambria_flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + SZ_32M - 1;
1091 +
1092 + *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE; // make sure window is writable
1093 + *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
1094 +
1095 + platform_add_devices(ARRAY_AND_SIZE(cambria_devices));
1096 +
1097 + cambria_pata_resources[0].start = 0x53e00000;
1098 + cambria_pata_resources[0].end = 0x53e3ffff;
1099 +
1100 + cambria_pata_resources[1].start = 0x53e40000;
1101 + cambria_pata_resources[1].end = 0x53e7ffff;
1102 +
1103 + cambria_pata_data.cs0_cfg = IXP4XX_EXP_CS3;
1104 + cambria_pata_data.cs1_cfg = IXP4XX_EXP_CS3;
1105 +
1106 + i2c_register_board_info(0, ARRAY_AND_SIZE(cambria_i2c_board_info));
1107 +}
1108 +
1109 +static int __init cambria_model_setup(void)
1110 +{
1111 + if (!machine_is_cambria())
1112 + return 0;
1113 +
1114 + if (cambria_info) {
1115 + printk(KERN_DEBUG "Running on Gateworks Cambria %s\n",
1116 + cambria_info->model);
1117 + cambria_info->setup();
1118 + } else {
1119 + printk(KERN_INFO "Unknown/missing Cambria model number"
1120 + " -- defaults will be used\n");
1121 + cambria_gw23xx_setup();
1122 + }
1123 +
1124 + return 0;
1125 +}
1126 +late_initcall(cambria_model_setup);
1127 +
1128 +MACHINE_START(CAMBRIA, "Gateworks Cambria series")
1129 + /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
1130 + .map_io = ixp4xx_map_io,
1131 + .init_irq = ixp4xx_init_irq,
1132 + .init_time = ixp4xx_timer_init,
1133 + .atag_offset = 0x0100,
1134 + .init_machine = cambria_init,
1135 +#if defined(CONFIG_PCI)
1136 + .dma_zone_size = SZ_64M,
1137 +#endif
1138 + .restart = ixp4xx_restart,
1139 +MACHINE_END
OpenWrt Source Repository