lantiq: add Falcon support
[openwrt/openwrt.git] / target / linux / lantiq / dts / falcon.dtsi
1 / {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "lantiq,falcon";
5
6 cpus {
7 cpu@0 {
8 compatible = "mips,mips34kc";
9 };
10 };
11
12 aliases {
13 serial0 = &serial0;
14 serial1 = &serial1;
15 gpio0 = &gpio0;
16 gpio1 = &gpio1;
17 gpio2 = &gpio2;
18 gpio3 = &gpio3;
19 gpio4 = &gpio4;
20 };
21
22 clocks {
23 compatible = "simple-bus";
24
25 cpu_clk: cpu {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <400000000>;
29 clock-output-names = "cpu";
30 };
31
32 io_clk: io {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <200000000>;
36 clock-output-names = "io";
37 };
38
39 fpi_clk: fpi {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <100000000>;
43 clock-output-names = "fpi";
44 };
45 };
46
47 ebu_cs0: localbus@10000000 {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 compatible = "lantiq,localbus", "simple-bus";
51 reg = <0x10000000 0x4000000>;
52 ranges = <0x0 0x10000000 0x4000000>;
53 };
54 ebu_cs1: localbus@14000000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "lantiq,localbus", "simple-bus";
58 reg = <0x14000000 0x4000000>;
59 ranges = <0x0 0x14000000 0x4000000>;
60 };
61
62 ebu@18000000 {
63 compatible = "lantiq,ebu-falcon";
64 reg = <0x18000000 0x100>;
65 };
66
67 sbs2@1D000000 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "lantiq,sysb2", "simple-bus";
71 reg = <0x1D000000 0x1000000>;
72 ranges = <0x0 0x1D000000 0x1000000>;
73
74 clock_sysgpe: clock-controller@700000 {
75 compatible = "lantiq,sysgpe-falcon";
76 reg = <0x700000 0x100>;
77 #clock-cells = <1>;
78 };
79
80 mps@4000 {
81 compatible = "lantiq,mps-falcon", "lantiq,mps-xrx100";
82 reg = <0x4000 0x1000>;
83 interrupt-parent = <&icu0>;
84 interrupts = <154 155>;
85 lantiq,mbx = <&mpsmbx>;
86 };
87
88 gpio0: gpio@810000 {
89 compatible = "lantiq,falcon-gpio";
90 gpio-controller;
91 #gpio-cells = <2>;
92 interrupt-controller;
93 #interrupt-cells = <2>;
94 interrupt-parent = <&icu0>;
95 interrupts = <44>;
96 reg = <0x810000 0x80>;
97 clocks = <&clock_syseth 16>;
98 };
99
100 gpio2: gpio@810100 {
101 compatible = "lantiq,falcon-gpio";
102 gpio-controller;
103 #gpio-cells = <2>;
104 interrupt-controller;
105 #interrupt-cells = <2>;
106 interrupt-parent = <&icu0>;
107 interrupts = <46>;
108 reg = <0x810100 0x80>;
109 clocks = <&clock_syseth 17>;
110 };
111
112 clock_syseth: clock-controller@B00000 {
113 compatible = "lantiq,syseth-falcon";
114 reg = <0xB00000 0x100>;
115 #clock-cells = <1>;
116 };
117
118 pad@B01000 {
119 compatible = "lantiq,pad-falcon";
120 reg = <0xB01000 0x100>;
121 lantiq,bank = <0>;
122 clocks = <&clock_syseth 20>;
123 };
124
125 pad@B02000 {
126 compatible = "lantiq,pad-falcon";
127 reg = <0xB02000 0x100>;
128 lantiq,bank = <2>;
129 clocks = <&clock_syseth 21>;
130 };
131 };
132
133 fpi@1E000000 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "lantiq,fpi", "simple-bus";
137 reg = <0x1E000000 0x1000000>;
138 ranges = <0x0 0x1E000000 0x1000000>;
139
140 serial1: serial@100B00 {
141 status = "disabled";
142 compatible = "lantiq,asc";
143 reg = <0x100B00 0x100>;
144 interrupt-parent = <&icu0>;
145 interrupts = <112 113 114>;
146 line = <1>;
147 pinctrl-names = "default";
148 pinctrl-0 = <&asc1_pins>;
149 clocks = <&clock_sys1 11>;
150 };
151
152 serial0: serial@100C00 {
153 compatible = "lantiq,asc";
154 reg = <0x100C00 0x100>;
155 interrupt-parent = <&icu0>;
156 interrupts = <104 105 106>;
157 line = <0>;
158 pinctrl-names = "default";
159 pinctrl-0 = <&asc0_pins>;
160 clocks = <&clock_sys1 12>;
161 };
162
163 spi: spi@100D00 {
164 status = "disabled";
165 compatible = "intel,falcon-spi", "intel,xrx100-spi", "lantiq,spi-lantiq-ssc";
166 interrupts = <22 23 24 25>;
167 interrupt-names = "spi_tx", "spi_rx", "spi_err", "spi_frm";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 reg = <0x100D00 0x100>;
171 interrupt-parent = <&icu0>;
172 clocks = <&clock_sys1 13>;
173 base_cs = <1>;
174 num_cs = <2>;
175 };
176
177 gptc@100E00 {
178 compatible = "lantiq,gptc-falcon";
179 reg = <0x100E00 0x100>;
180 };
181
182 i2c: i2c@200000 {
183 status = "disabled";
184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "lantiq,lantiq-i2c";
187 reg = <0x200000 0x10000>;
188 interrupt-parent = <&icu0>;
189 interrupts = <18 19 20 21>;
190 gpios = <&gpio1 7 0 &gpio1 8 0>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&i2c_pins>;
193 clocks = <&clock_sys1 14>;
194 };
195
196 gpio1: gpio@800100 {
197 compatible = "lantiq,falcon-gpio";
198 gpio-controller;
199 #gpio-cells = <2>;
200 interrupt-controller;
201 #interrupt-cells = <2>;
202 interrupt-parent = <&icu0>;
203 interrupts = <45>;
204 reg = <0x800100 0x100>;
205 clocks = <&clock_sys1 16>;
206 };
207
208 gpio3: gpio@800200 {
209 compatible = "lantiq,falcon-gpio";
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
213 #interrupt-cells = <2>;
214 interrupt-parent = <&icu0>;
215 interrupts = <47>;
216 reg = <0x800200 0x100>;
217 clocks = <&clock_sys1 17>;
218 };
219
220 gpio4: gpio@800300 {
221 compatible = "lantiq,falcon-gpio";
222 gpio-controller;
223 #gpio-cells = <2>;
224 interrupt-controller;
225 #interrupt-cells = <2>;
226 interrupt-parent = <&icu0>;
227 interrupts = <48>;
228 reg = <0x800300 0x100>;
229 clocks = <&clock_sys1 18>;
230 };
231
232 pad@800400 {
233 compatible = "lantiq,pad-falcon";
234 reg = <0x800400 0x100>;
235 lantiq,bank = <1>;
236 clocks = <&clock_sys1 20>;
237 };
238
239 pad@800500 {
240 compatible = "lantiq,pad-falcon";
241 reg = <0x800500 0x100>;
242 lantiq,bank = <3>;
243 clocks = <&clock_sys1 21>;
244 };
245
246 pad@800600 {
247 compatible = "lantiq,pad-falcon";
248 reg = <0x800600 0x100>;
249 lantiq,bank = <4>;
250 clocks = <&clock_sys1 22>;
251 };
252
253 status@802000 {
254 compatible = "lantiq,status-falcon";
255 reg = <0x802000 0x80>;
256 };
257
258 clock_sys1: clock-controller@F00000 {
259 compatible = "lantiq,sys1-falcon";
260 reg = <0xF00000 0x100>;
261 #clock-cells = <1>;
262 };
263 };
264
265 sbs0@1F000000 {
266 #address-cells = <1>;
267 #size-cells = <1>;
268 compatible = "simple-bus";
269 reg = <0x1F000000 0x400000>;
270 ranges = <0x0 0x1F000000 0x400000>;
271
272 mpsmbx: mpsmbx@200000 {
273 reg = <0x200000 0x200>;
274 };
275 };
276
277 sbs1@1F700000 {
278
279 };
280
281 biu@1F800000 {
282 #address-cells = <1>;
283 #size-cells = <1>;
284 compatible = "lantiq,biu", "simple-bus";
285 reg = <0x1F800000 0x800000>;
286 ranges = <0x0 0x1F800000 0x800000>;
287
288 icu0: icu@80200 {
289 #interrupt-cells = <1>;
290 interrupt-controller;
291 compatible = "lantiq,icu";
292 reg = <0x80200 0x28
293 0x80228 0x28
294 0x80250 0x28
295 0x80278 0x28
296 0x802a0 0x28>;
297 };
298
299 watchdog@803F0 {
300 compatible = "lantiq,wdt";
301 reg = <0x803F0 0x10>;
302 clocks = <&io_clk>; /* currently no effect */
303 };
304 };
305
306 pinctrl {
307 compatible = "lantiq,pinctrl-falcon";
308 pinctrl-names = "default";
309 pinctrl-0 = <&state_default>;
310
311 state_default: pinctrl0 {
312 /*ntr {
313 lantiq,groups = "ntr8k";
314 lantiq,function = "ntr";
315 };*/
316 hrst {
317 lantiq,groups = "hrst";
318 lantiq,function = "rst";
319 };
320 };
321
322 asc0_pins: asc0 {
323 asc0 {
324 lantiq,groups = "asc0";
325 lantiq,function = "asc";
326 };
327 };
328 asc1_pins: asc1 {
329 asc1 {
330 lantiq,groups = "asc1";
331 lantiq,function = "asc";
332 };
333 };
334 i2c_pins: i2c {
335 i2c {
336 lantiq,groups = "i2c";
337 lantiq,function = "i2c";
338 };
339 };
340 bootled_pins: bootled {
341 bootled {
342 lantiq,groups = "bootled";
343 lantiq,function = "led";
344 };
345 };
346 ntr_ntr8k: ntr8k {
347 ntr8k {
348 lantiq,groups = "ntr8k";
349 lantiq,function = "ntr";
350 };
351 };
352 ntr_pps: pps {
353 pps {
354 lantiq,groups = "pps";
355 lantiq,function = "ntr";
356 };
357 };
358 ntr_gpio: gpio {
359 gpio {
360 lantiq,pins = "io5";
361 lantiq,mux = <1>;
362 lantiq,output = <0>;
363 };
364 };
365 slic_pins: slic {
366 slic {
367 lantiq,groups = "slic";
368 lantiq,function = "slic";
369 };
370 };
371 };
372
373 pinselect-ntr {
374 compatible = "lantiq,onu-ntr","lantiq,pinselect-ntr";
375 pinctrl-names = "ntr8k", "pps", "gpio";
376 pinctrl-0 = <&ntr_ntr8k>;
377 pinctrl-1 = <&ntr_pps>;
378 pinctrl-2 = <&ntr_gpio>;
379 };
380
381 pinselect-asc1 {
382 compatible = "lantiq,onu-asc1","lantiq,pinselect-asc1";
383 pinctrl-names = "default", "asc1";
384 pinctrl-0 = <&slic_pins>;
385 pinctrl-1 = <&asc1_pins>;
386 };
387
388 };