target/linux/lantiq/files-4.14/arch/mips/boot/dts/EASY80920.dtsi

   1 #include "vr9.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
   5
   6 / {
   7         compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9";
   8
   9         chosen {
  10                 bootargs = "console=ttyLTQ0,115200";
  11         };
  12
  13         aliases {
  14                 led-boot = &power;
  15                 led-failsafe = &power;
  16                 led-running = &power;
  17
  18                 led-usb = &led_usb1;
  19                 led-usb2 = &led_usb2;
  20         };
  21
  22         memory@0 {
  23                 reg = <0x0 0x4000000>;
  24         };
  25
  26         gpio-keys-polled {
  27                 compatible = "gpio-keys-polled";
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30                 poll-interval = <100>;
  31 /*              reset {
  32                         label = "reset";
  33                         gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
  34                         linux,code = <KEY_RESTART>;
  35                 };*/
  36                 paging {
  37                         label = "paging";
  38                         gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
  39                         linux,code = <KEY_PHONE>;
  40                 };
  41         };
  42
  43         gpio-leds {
  44                 compatible = "gpio-leds";
  45
  46                 power: power {
  47                         label = "easy80920:green:power";
  48                         gpios = <&stp 9 GPIO_ACTIVE_HIGH>;
  49                         default-state = "keep";
  50                 };
  51                 warning {
  52                         label = "easy80920:green:warning";
  53                         gpios = <&stp 22 GPIO_ACTIVE_HIGH>;
  54                 };
  55                 fxs1 {
  56                         label = "easy80920:green:fxs1";
  57                         gpios = <&stp 21 GPIO_ACTIVE_HIGH>;
  58                 };
  59                 fxs2 {
  60                         label = "easy80920:green:fxs2";
  61                         gpios = <&stp 20 GPIO_ACTIVE_HIGH>;
  62                 };
  63                 fxo {
  64                         label = "easy80920:green:fxo";
  65                         gpios = <&stp 19 GPIO_ACTIVE_HIGH>;
  66                 };
  67                 led_usb1: usb1 {
  68                         label = "easy80920:green:usb1";
  69                         gpios = <&stp 18 GPIO_ACTIVE_HIGH>;
  70                 };
  71                 led_usb2: usb2 {
  72                         label = "easy80920:green:usb2";
  73                         gpios = <&stp 15 GPIO_ACTIVE_HIGH>;
  74                 };
  75                 sd {
  76                         label = "easy80920:green:sd";
  77                         gpios = <&stp 14 GPIO_ACTIVE_HIGH>;
  78                 };
  79                 wps {
  80                         label = "easy80920:green:wps";
  81                         gpios = <&stp 12 GPIO_ACTIVE_HIGH>;
  82                 };
  83         };
  84
  85         usb_vbus: regulator-usb-vbus {
  86                 compatible = "regulator-fixed";
  87
  88                 regulator-name = "USB_VBUS";
  89
  90                 regulator-min-microvolt = <5000000>;
  91                 regulator-max-microvolt = <5000000>;
  92
  93                 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
  94                 enable-active-high;
  95         };
  96 };
  97
  98 &eth0 {
  99         lan: interface@0 {
 100                 compatible = "lantiq,xrx200-pdi";
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103                 reg = <0>;
 104                 lantiq,switch;
 105
 106                 ethernet@4 {
 107                         compatible = "lantiq,xrx200-pdi-port";
 108                         reg = <4>;
 109                         phy-mode = "gmii";
 110                         phy-handle = <&phy13>;
 111                 };
 112                 ethernet@2 {
 113                         compatible = "lantiq,xrx200-pdi-port";
 114                         reg = <2>;
 115                         phy-mode = "gmii";
 116                         phy-handle = <&phy11>;
 117                 };
 118                 ethernet@1 {
 119                         compatible = "lantiq,xrx200-pdi-port";
 120                         reg = <1>;
 121                         phy-mode = "rgmii";
 122                         phy-handle = <&phy1>;
 123                 };
 124                 ethernet@0 {
 125                         compatible = "lantiq,xrx200-pdi-port";
 126                         reg = <0>;
 127                         phy-mode = "rgmii";
 128                         phy-handle = <&phy0>;
 129                 };
 130         };
 131
 132         wan: interface@1 {
 133                 compatible = "lantiq,xrx200-pdi";
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136                 reg = <1>;
 137                 lantiq,wan;
 138
 139                 ethernet@5 {
 140                         compatible = "lantiq,xrx200-pdi-port";
 141                         reg = <5>;
 142                         phy-mode = "rgmii";
 143                         phy-handle = <&phy5>;
 144                 };
 145         };
 146
 147         mdio@0 {
 148                 #address-cells = <1>;
 149                 #size-cells = <0>;
 150                 compatible = "lantiq,xrx200-mdio";
 151                 reg = <0>;
 152
 153                 phy0: ethernet-phy@0 {
 154                         reg = <0x0>;
 155                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 156                 };
 157                 phy1: ethernet-phy@1 {
 158                         reg = <0x1>;
 159                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 160                 };
 161                 phy5: ethernet-phy@5 {
 162                         reg = <0x5>;
 163                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 164                 };
 165                 phy11: ethernet-phy@11 {
 166                         reg = <0x11>;
 167                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 168                 };
 169                 phy13: ethernet-phy@13 {
 170                         reg = <0x13>;
 171                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 172                 };
 173         };
 174 };
 175
 176 &gphy0 {
 177         lantiq,gphy-mode = <GPHY_MODE_GE>;
 178 };
 179
 180 &gphy1 {
 181         lantiq,gphy-mode = <GPHY_MODE_GE>;
 182 };
 183
 184 &gpio {
 185         pinctrl-names = "default";
 186         pinctrl-0 = <&state_default>;
 187
 188         state_default: pinmux {
 189                 exin3 {
 190                         lantiq,groups = "exin3";
 191                         lantiq,function = "exin";
 192                 };
 193                 stp {
 194                         lantiq,groups = "stp";
 195                         lantiq,function = "stp";
 196                 };
 197                 nand {
 198                         lantiq,groups = "nand cle", "nand ale",
 199                                         "nand rd", "nand rdy";
 200                         lantiq,function = "ebu";
 201                 };
 202                 mdio {
 203                         lantiq,groups = "mdio";
 204                         lantiq,function = "mdio";
 205                 };
 206                 pci {
 207                         lantiq,groups = "gnt1", "req1";
 208                         lantiq,function = "pci";
 209                 };
 210                 conf_out {
 211                         lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
 212                                         "io4", "io5", "io6", /* stp */
 213                                         "io21",
 214                                         "io33";
 215                         lantiq,open-drain;
 216                         lantiq,pull = <0>;
 217                         lantiq,output = <1>;
 218                 };
 219                 pcie-rst {
 220                         lantiq,pins = "io38";
 221                         lantiq,pull = <0>;
 222                         lantiq,output = <1>;
 223                 };
 224                 conf_in {
 225                         lantiq,pins = "io39", /* exin3 */
 226                                         "io48"; /* nand rdy */
 227                         lantiq,pull = <2>;
 228                 };
 229         };
 230         pins_spi_default: pins_spi_default {
 231                 spi_in {
 232                         lantiq,groups = "spi_di";
 233                         lantiq,function = "spi";
 234                 };
 235                 spi_out {
 236                         lantiq,groups = "spi_do", "spi_clk",
 237                                 "spi_cs4";
 238                         lantiq,function = "spi";
 239                         lantiq,output = <1>;
 240                 };
 241         };
 242 };
 243
 244 &spi {
 245         pinctrl-names = "default";
 246         pinctrl-0 = <&pins_spi_default>;
 247
 248         status = "okay";
 249
 250         m25p80@4 {
 251                 #address-cells = <1>;
 252                 #size-cells = <1>;
 253                 compatible = "jedec,spi-nor";
 254                 reg = <4 0>;
 255                 spi-max-frequency = <1000000>;
 256
 257                 partitions {
 258                         compatible = "fixed-partitions";
 259                         #address-cells = <1>;
 260                         #size-cells = <1>;
 261
 262                         partition@0 {
 263                                 reg = <0x0 0x20000>;
 264                                 label = "SPI (RO) U-Boot Image";
 265                                 read-only;
 266                         };
 267
 268                         partition@20000 {
 269                                 reg = <0x20000 0x10000>;
 270                                 label = "ENV_MAC";
 271                                 read-only;
 272                         };
 273
 274                         partition@30000 {
 275                                 reg = <0x30000 0x10000>;
 276                                 label = "DPF";
 277                                 read-only;
 278                         };
 279
 280                         partition@40000 {
 281                                 reg = <0x40000 0x10000>;
 282                                 label = "NVRAM";
 283                                 read-only;
 284                         };
 285
 286                         partition@500000 {
 287                                 reg = <0x50000 0x003a0000>;
 288                                 label = "kernel";
 289                         };
 290                 };
 291         };
 292 };
 293
 294 &stp {
 295         status = "okay";
 296
 297         lantiq,shadow = <0xffff>;
 298         lantiq,groups = <0x7>;
 299         lantiq,dsl = <0x3>;
 300         lantiq,phy1 = <0x7>;
 301         lantiq,phy2 = <0x7>;
 302         /* lantiq,rising; */
 303 };
 304
 305 &usb_phy0 {
 306         status = "okay";
 307         phy-supply = <&usb_vbus>;
 308 };
 309
 310 &usb0 {
 311         status = "okay";
 312 };