lantiq: kernel 4.14: cleanup dts files
[openwrt/openwrt.git] / target / linux / lantiq / files-4.14 / arch / mips / boot / dts / TDW89X0.dtsi
1 #include "vr9.dtsi"
2
3 #include <dt-bindings/input/input.h>
4
5 / {
6 compatible = "tplink,tdw89x0", "lantiq,xway", "lantiq,vr9";
7
8 chosen {
9 bootargs = "console=ttyLTQ0,115200";
10 };
11
12 aliases {
13 /* the power led can't be controlled, use the wps led instead */
14 led-boot = &wps;
15 led-failsafe = &wps;
16
17 led-dsl = &dsl;
18 led-internet = &internet;
19 led-wifi = &wifi;
20 led-usb = &led_usb0;
21 led-usb2 = &led_usb2;
22 };
23
24 memory@0 {
25 reg = <0x0 0x4000000>;
26 };
27
28 gphy-xrx200 {
29 compatible = "lantiq,phy-xrx200";
30 firmware = "lantiq/xrx200_phy11g_a22.bin";
31 phys = [ 00 01 ];
32 };
33
34 gpio-keys-polled {
35 compatible = "gpio-keys-polled";
36 #address-cells = <1>;
37 #size-cells = <0>;
38 poll-interval = <100>;
39 reset {
40 label = "reset";
41 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
42 linux,code = <KEY_RESTART>;
43 };
44
45 wifi {
46 label = "wifi";
47 gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
48 linux,code = <KEY_RFKILL>;
49 linux,input-type = <EV_SW>;
50 };
51
52 wps {
53 label = "wps";
54 gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
55 linux,code = <KEY_WPS_BUTTON>;
56 };
57 };
58
59 gpio-leds {
60 compatible = "gpio-leds";
61 /*
62 power is not controllable via gpio
63 */
64 dsl: dsl {
65 label = "tdw89x0:green:dsl";
66 gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
67 };
68 internet: internet {
69 label = "tdw89x0:green:internet";
70 gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
71 };
72
73 led_usb0: usb0 {
74 label = "tdw89x0:green:usb";
75 gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
76 };
77 led_usb2: usb2 {
78 label = "tdw89x0:green:usb2";
79 gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
80 };
81 wps: wps {
82 label = "tdw89x0:green:wps";
83 gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
84 };
85 };
86
87 wifi-leds {
88 compatible = "gpio-leds";
89
90 wifi: wifi {
91 label = "tdw89x0:green:wifi";
92 gpios = <&ath9k 0 GPIO_ACTIVE_HIGH>;
93 };
94 };
95 };
96
97 &eth0 {
98 lan: interface@0 {
99 compatible = "lantiq,xrx200-pdi";
100 #address-cells = <1>;
101 #size-cells = <0>;
102 reg = <0>;
103 mtd-mac-address = <&ath9k_cal 0xf100>;
104 lantiq,switch;
105
106 ethernet@0 {
107 compatible = "lantiq,xrx200-pdi-port";
108 reg = <0>;
109 phy-mode = "rgmii";
110 phy-handle = <&phy0>;
111 // gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
112 };
113 ethernet@5 {
114 compatible = "lantiq,xrx200-pdi-port";
115 reg = <5>;
116 phy-mode = "rgmii";
117 phy-handle = <&phy5>;
118 };
119 ethernet@2 {
120 compatible = "lantiq,xrx200-pdi-port";
121 reg = <2>;
122 phy-mode = "gmii";
123 phy-handle = <&phy11>;
124 };
125 ethernet@3 {
126 compatible = "lantiq,xrx200-pdi-port";
127 reg = <4>;
128 phy-mode = "gmii";
129 phy-handle = <&phy13>;
130 };
131 };
132
133 mdio@0 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "lantiq,xrx200-mdio";
137 reg = <0>;
138
139 phy0: ethernet-phy@0 {
140 reg = <0x0>;
141 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
142 };
143 phy5: ethernet-phy@5 {
144 reg = <0x5>;
145 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
146 };
147 phy11: ethernet-phy@11 {
148 reg = <0x11>;
149 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
150 };
151 phy13: ethernet-phy@13 {
152 reg = <0x13>;
153 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
154 };
155 };
156 };
157
158 &gpio {
159 pinctrl-names = "default";
160 pinctrl-0 = <&state_default>;
161
162 state_default: pinmux {
163 mdio {
164 lantiq,groups = "mdio";
165 lantiq,function = "mdio";
166 };
167 gphy-leds {
168 lantiq,groups = "gphy0 led1", "gphy1 led1";
169 lantiq,function = "gphy";
170 lantiq,pull = <2>;
171 lantiq,open-drain = <0>;
172 lantiq,output = <1>;
173 };
174 phy-rst {
175 lantiq,pins = "io42";
176 lantiq,pull = <0>;
177 lantiq,open-drain = <0>;
178 lantiq,output = <1>;
179 };
180 pcie-rst {
181 lantiq,pins = "io38";
182 lantiq,pull = <0>;
183 lantiq,output = <1>;
184 };
185 };
186 pins_spi_default: pins_spi_default {
187 spi_in {
188 lantiq,groups = "spi_di";
189 lantiq,function = "spi";
190 };
191 spi_out {
192 lantiq,groups = "spi_do", "spi_clk",
193 "spi_cs4";
194 lantiq,function = "spi";
195 lantiq,output = <1>;
196 };
197 };
198 };
199
200 &pcie0 {
201 pcie@0 {
202 reg = <0 0 0 0 0>;
203 #interrupt-cells = <1>;
204 #size-cells = <2>;
205 #address-cells = <3>;
206 device_type = "pci";
207
208 ath9k: wifi@168c,002e {
209 compatible = "pci168c,002e";
210 reg = <0 0 0 0 0>;
211 #gpio-cells = <2>;
212 gpio-controller;
213 qca,no-eeprom;
214 qca,disable-5ghz;
215 mtd-mac-address = <&ath9k_cal 0xf100>;
216 mtd-mac-address-increment = <2>;
217 };
218 };
219 };
220
221 &spi {
222 status = "okay";
223
224 pinctrl-names = "default";
225 pinctrl-0 = <&pins_spi_default>;
226
227 m25p80@4 {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "jedec,spi-nor";
231 reg = <4 0>;
232 spi-max-frequency = <33250000>;
233 m25p,fast-read;
234
235 partitions {
236 compatible = "fixed-partitions";
237 #address-cells = <1>;
238 #size-cells = <1>;
239
240 partition@0 {
241 reg = <0x0 0x20000>;
242 label = "u-boot";
243 read-only;
244 };
245
246 partition@20000 {
247 reg = <0x20000 0x7a0000>;
248 label = "firmware";
249 };
250
251 partition@7c0000 {
252 reg = <0x7c0000 0x10000>;
253 label = "config";
254 read-only;
255 };
256
257 ath9k_cal: partition@7d0000 {
258 reg = <0x7d0000 0x30000>;
259 label = "boardconfig";
260 read-only;
261 };
262 };
263 };
264 };
265
266 &usb0 {
267 status = "okay";
268 gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
269 lantiq,portmask = <0x3>;
270 };
271
272 &usb1 {
273 status = "okay";
274 gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
275 };