lantiq: dts: Add the reset line for the PCI controller
[openwrt/openwrt.git] / target / linux / lantiq / files / arch / mips / boot / dts / lantiq / ar9.dtsi
1 /dts-v1/;
2
3 #include <dt-bindings/gpio/gpio.h>
4
5 / {
6 #address-cells = <1>;
7 #size-cells = <1>;
8 compatible = "lantiq,xway", "lantiq,ar9";
9
10 aliases {
11 serial0 = &asc1;
12 };
13
14 chosen {
15 stdout-path = "serial0:115200n8";
16 };
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu@0 {
23 compatible = "mips,mips34K";
24 reg = <0>;
25 };
26 };
27
28 reboot {
29 compatible = "syscon-reboot";
30
31 regmap = <&rcu0>;
32 offset = <0x10>;
33 mask = <0x40000000>;
34 };
35
36 biu@1f800000 {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "lantiq,biu", "simple-bus";
40 reg = <0x1f800000 0x800000>;
41 ranges = <0x0 0x1f800000 0x7fffff>;
42
43 icu0: icu@80200 {
44 #interrupt-cells = <1>;
45 interrupt-controller;
46 compatible = "lantiq,icu";
47 /* TODO: AR9 should have ICU1 (like VR9) too */
48 reg = <0x80200 0xc8>;
49 };
50
51 watchdog@803f0 {
52 compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt";
53 reg = <0x803f0 0x10>;
54
55 regmap = <&rcu0>;
56 };
57 };
58
59 sram@1f000000 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "lantiq,sram", "simple-bus";
63 reg = <0x1f000000 0x800000>;
64 ranges = <0x0 0x1f000000 0x7fffff>;
65
66 eiu0: eiu@101000 {
67 #interrupt-cells = <1>;
68 interrupt-controller;
69 compatible = "lantiq,eiu-xway";
70 reg = <0x101000 0x1000>;
71 interrupt-parent = <&icu0>;
72 lantiq,eiu-irqs = <166 135 66 40 41 42>;
73 };
74
75 pmu0: pmu@102000 {
76 compatible = "lantiq,pmu-xway";
77 reg = <0x102000 0x1000>;
78 };
79
80 cgu0: cgu@103000 {
81 compatible = "lantiq,cgu-xway";
82 reg = <0x103000 0x1000>;
83 #clock-cells = <1>;
84 };
85
86 rcu0: rcu@203000 {
87 #address-cells = <1>;
88 #size-cells = <1>;
89 compatible = "lantiq,xrx100-rcu", "simple-mfd", "syscon";
90 reg = <0x203000 0x1000>;
91 ranges = <0x0 0x203000 0x100>;
92 big-endian;
93
94 reset: reset-controller@10 {
95 compatible = "lantiq,xrx100-reset", "lantiq,danube-reset";
96 reg = <0x10 4>, <0x14 4>;
97
98 #reset-cells = <2>;
99 };
100
101 usb_phy0: usb2-phy@18 {
102 compatible = "lantiq,xrx100-usb2-phy";
103 reg = <0x18 4>;
104 status = "disabled";
105
106 resets = <&reset 4 4>;
107 reset-names = "ctrl";
108 #phy-cells = <0>;
109 };
110
111 usb_phy1: usb2-phy@34 {
112 compatible = "lantiq,xrx100-usb2-phy";
113 reg = <0x34 4>;
114 status = "disabled";
115
116 resets = <&reset 28 28>;
117 reset-names = "ctrl";
118 #phy-cells = <0>;
119 };
120 };
121 };
122
123 fpi@10000000 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 compatible = "lantiq,fpi", "simple-bus";
127 ranges = <0x0 0x10000000 0xeefffff>;
128 reg = <0x10000000 0xef00000>;
129
130 localbus: localbus@0 {
131 #address-cells = <2>;
132 #size-cells = <1>;
133 ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
134 1 0 0x4000000 0x4000010>; /* addsel1 */
135 compatible = "lantiq,localbus", "simple-bus";
136 };
137
138 gptu@e100a00 {
139 compatible = "lantiq,gptu-xway";
140 reg = <0xe100a00 0x100>;
141 interrupt-parent = <&icu0>;
142 interrupts = <126 127 128 129 130 131>;
143 };
144
145 asc0: serial@e100400 {
146 compatible = "lantiq,asc";
147 reg = <0xe100400 0x400>;
148 interrupt-parent = <&icu0>;
149 interrupts = <104 105 106>;
150 status = "disabled";
151 };
152
153 spi: spi@e100800 {
154 compatible = "lantiq,xrx100-spi";
155 reg = <0xe100800 0x100>;
156 interrupt-parent = <&icu0>;
157 interrupts = <22 23 24>;
158 interrupt-names = "spi_rx", "spi_tx", "spi_err",
159 "spi_frm";
160 #address-cells = <1>;
161 #size-cells = <0>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;
164 status = "disabled";
165 };
166
167 gpio: pinmux@e100b10 {
168 compatible = "lantiq,xrx100-pinctrl";
169 #gpio-cells = <2>;
170 gpio-controller;
171 reg = <0xe100b10 0xa0>;
172
173 mdio_pins: mdio {
174 mux {
175 lantiq,groups = "mdio";
176 lantiq,function = "mdio";
177 };
178 };
179
180 nand_pins: nand {
181 mux-0 {
182 lantiq,groups = "nand cle", "nand ale",
183 "nand rd";
184 lantiq,function = "ebu";
185 lantiq,output = <1>;
186 lantiq,open-drain = <0>;
187 lantiq,pull = <0>;
188 };
189 mux-1 {
190 lantiq,groups = "nand rdy";
191 lantiq,function = "ebu";
192 lantiq,output = <0>;
193 lantiq,pull = <2>;
194 };
195 };
196
197 nand_cs1_pins: nand-cs1 {
198 mux {
199 lantiq,groups = "nand cs1";
200 lantiq,function = "ebu";
201 lantiq,open-drain = <0>;
202 lantiq,pull = <0>;
203 };
204 };
205
206 pci_gnt1_pins: pci-gnt1 {
207 mux {
208 lantiq,groups = "gnt1";
209 lantiq,function = "pci";
210 lantiq,output = <1>;
211 lantiq,open-drain = <0>;
212 lantiq,pull = <0>;
213 };
214 };
215
216 pci_gnt2_pins: pci-gnt2 {
217 mux {
218 lantiq,groups = "gnt2";
219 lantiq,function = "pci";
220 lantiq,output = <1>;
221 lantiq,open-drain = <0>;
222 lantiq,pull = <0>;
223 };
224 };
225
226 pci_gnt3_pins: pci-gnt3 {
227 mux {
228 lantiq,groups = "gnt3";
229 lantiq,function = "pci";
230 lantiq,output = <1>;
231 lantiq,open-drain = <0>;
232 lantiq,pull = <0>;
233 };
234 };
235
236 pci_gnt4_pins: pci-gnt4 {
237 mux {
238 lantiq,groups = "gnt4";
239 lantiq,function = "pci";
240 lantiq,output = <1>;
241 lantiq,open-drain = <0>;
242 lantiq,pull = <0>;
243 };
244 };
245
246 pci_req1_pins: pci-req1 {
247 mux {
248 lantiq,groups = "req1";
249 lantiq,function = "pci";
250 lantiq,output = <0>;
251 lantiq,open-drain = <1>;
252 lantiq,pull = <2>;
253 };
254 };
255
256 pci_req2_pins: pci-req2 {
257 mux {
258 lantiq,groups = "req2";
259 lantiq,function = "pci";
260 lantiq,output = <0>;
261 lantiq,open-drain = <1>;
262 lantiq,pull = <2>;
263 };
264 };
265
266 pci_req3_pins: pci-req3 {
267 mux {
268 lantiq,groups = "req3";
269 lantiq,function = "pci";
270 lantiq,output = <0>;
271 lantiq,open-drain = <1>;
272 lantiq,pull = <2>;
273 };
274 };
275
276 pci_req4_pins: pci-req4 {
277 mux {
278 lantiq,groups = "req4";
279 lantiq,function = "pci";
280 lantiq,output = <0>;
281 lantiq,open-drain = <1>;
282 lantiq,pull = <2>;
283 };
284 };
285
286 spi_pins: spi {
287 mux-0 {
288 lantiq,groups = "spi_di";
289 lantiq,function = "spi";
290 };
291 mux-1 {
292 lantiq,groups = "spi_do", "spi_clk";
293 lantiq,function = "spi";
294 lantiq,output = <1>;
295 };
296 };
297
298 spi_cs4_pins: spi-cs4 {
299 mux {
300 lantiq,groups = "spi_cs4";
301 lantiq,function = "spi";
302 lantiq,output = <1>;
303 };
304 };
305
306 stp_pins: stp {
307 mux {
308 lantiq,groups = "stp";
309 lantiq,function = "stp";
310 lantiq,pull = <0>;
311 lantiq,open-drain = <0>;
312 lantiq,output = <1>;
313 };
314 };
315 };
316
317 stp: stp@e100bb0 {
318 #gpio-cells = <2>;
319 compatible = "lantiq,gpio-stp-xway";
320 gpio-controller;
321 reg = <0xe100bb0 0x40>;
322
323 pinctrl-0 = <&stp_pins>;
324 pinctrl-names = "default";
325
326 status = "disabled";
327 };
328
329 asc1: serial@e100c00 {
330 compatible = "lantiq,asc";
331 reg = <0xe100c00 0x400>;
332 interrupt-parent = <&icu0>;
333 interrupts = <112 113 114>;
334 };
335
336 usb0: usb@e101000 {
337 compatible = "lantiq,arx100-usb";
338 reg = <0xe101000 0x1000
339 0xe120000 0x3f000>;
340 interrupt-parent = <&icu0>;
341 interrupts = <62 91>;
342 dr_mode = "host";
343 phys = <&usb_phy0>;
344 phy-names = "usb2-phy";
345 status = "disabled";
346 };
347
348 usb1: usb@e106000 {
349 compatible = "lantiq,arx100-usb";
350 reg = <0xe106000 0x1000
351 0xe1e0000 0x3f000>;
352 interrupt-parent = <&icu0>;
353 interrupts = <91>;
354 dr_mode = "host";
355 phys = <&usb_phy1>;
356 phy-names = "usb2-phy";
357 status = "disabled";
358 };
359
360 deu@e103100 {
361 compatible = "lantiq,deu-arx100";
362 reg = <0xe103100 0xf00>;
363 };
364
365 dma0: dma@e104100 {
366 compatible = "lantiq,dma-xway";
367 reg = <0xe104100 0x800>;
368 };
369
370 ebu0: ebu@e105300 {
371 compatible = "lantiq,ebu-xway";
372 reg = <0xe105300 0x100>;
373 };
374
375 mei@e116000 {
376 compatible = "lantiq,mei-xway";
377 reg = <0xe116000 0x9c>;
378 interrupt-parent = <&icu0>;
379 interrupts = <63>;
380 };
381
382 gsw: etop@e180000 {
383 compatible = "lantiq,etop-xway";
384 reg = <0xe180000 0x40000
385 0xe108000 0x200>;
386 interrupt-parent = <&icu0>;
387 interrupts = <73 72>;
388 pinctrl-0 = <&mdio_pins>;
389 pinctrl-names = "default";
390 lantiq,tx-burst-length = <8>;
391 lantiq,rx-burst-length = <8>;
392 };
393
394 ppe@e234000 {
395 compatible = "lantiq,ppe-arx100";
396 reg = <0xe234000 0x3ffd>;
397 interrupt-parent = <&icu0>;
398 interrupts = <96>;
399 };
400
401 pci0: pci@e105400 {
402 status = "disabled";
403 #address-cells = <3>;
404 #size-cells = <2>;
405 #interrupt-cells = <1>;
406 compatible = "lantiq,pci-xway";
407 bus-range = <0x0 0x0>;
408 ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
409 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
410 reg = <0x7000000 0x8000 /* config space */
411 0xe105400 0x400>; /* pci bridge */
412 lantiq,bus-clock = <33333333>;
413 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
414 interrupt-map = <0x7000 0 0 1 &icu0 30 1>;
415 req-mask = <0x1>;
416
417 device_type = "pci";
418
419 resets = <&reset0 13 13>;
420 };
421 };
422
423 adsl {
424 compatible = "lantiq,adsl-arx100";
425 };
426 };