target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9.dtsi

   1 /dts-v1/;
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
   5
   6 / {
   7         #address-cells = <1>;
   8         #size-cells = <1>;
   9         compatible = "lantiq,xway", "lantiq,vr9";
  10
  11         aliases {
  12                 serial0 = &asc1;
  13         };
  14
  15         chosen {
  16                 stdout-path = "serial0:115200n8";
  17         };
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu@0 {
  24                         compatible = "mips,mips34Kc";
  25                         reg = <0>;
  26                 };
  27         };
  28
  29         cputemp {
  30                 compatible = "lantiq,cputemp";
  31         };
  32
  33         reboot {
  34                 compatible = "syscon-reboot";
  35
  36                 regmap = <&rcu0>;
  37                 offset = <0x10>;
  38                 mask = <0xe0000000>;
  39         };
  40
  41         biu@1f800000 {
  42                 #address-cells = <1>;
  43                 #size-cells = <1>;
  44                 compatible = "lantiq,biu", "simple-bus";
  45                 reg = <0x1f800000 0x800000>;
  46                 ranges = <0x0 0x1f800000 0x7fffff>;
  47
  48                 icu0: icu@80200 {
  49                         #interrupt-cells = <1>;
  50                         interrupt-controller;
  51                         compatible = "lantiq,icu";
  52                         reg = <0x80200 0xc8     /* icu0 */
  53                                0x80300 0xc8>;   /* icu1 */
  54                 };
  55
  56                 watchdog@803f0 {
  57                         compatible = "lantiq,xrx100-wdt", "lantiq,xrx100-wdt";
  58                         reg = <0x803f0 0x10>;
  59
  60                         regmap = <&rcu0>;
  61                 };
  62         };
  63
  64         sram@1f000000 {
  65                 #address-cells = <1>;
  66                 #size-cells = <1>;
  67                 compatible = "lantiq,sram", "simple-bus";
  68                 reg = <0x1f000000 0x800000>;
  69                 ranges = <0x0 0x1f000000 0x7fffff>;
  70
  71                 eiu0: eiu@101000 {
  72                         #interrupt-cells = <1>;
  73                         interrupt-controller;
  74                         compatible = "lantiq,eiu-xway";
  75                         reg = <0x101000 0x1000>;
  76                         interrupt-parent = <&icu0>;
  77                         lantiq,eiu-irqs = <166 135 66 40 41 42>;
  78                 };
  79
  80                 pmu0: pmu@102000 {
  81                         compatible = "lantiq,pmu-xway";
  82                         reg = <0x102000 0x1000>;
  83                 };
  84
  85                 cgu0: cgu@103000 {
  86                         compatible = "lantiq,cgu-xway";
  87                         reg = <0x103000 0x1000>;
  88                 };
  89
  90                 dcdc@106a00 {
  91                         compatible = "lantiq,dcdc-xrx200";
  92                         reg = <0x106a00 0x200>;
  93                 };
  94
  95                 vmmc: vmmc@107000 {
  96                         status = "disabled";
  97                         compatible = "lantiq,vmmc-xway";
  98                         reg = <0x107000 0x300>;
  99                         interrupt-parent = <&icu0>;
 100                         interrupts = <150 151 152 153 154 155>;
 101                 };
 102
 103                 pcie0_phy: phy@106800 {
 104                         compatible = "lantiq,vrx200-pcie-phy";
 105                         reg = <0x106800 0x100>;
 106                         lantiq,rcu = <&rcu0>;
 107                         lantiq,rcu-endian-offset = <0x4c>;
 108                         lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
 109                         big-endian;
 110                         resets = <&reset0 12 24>, <&reset0 22 22>;
 111                         reset-names = "phy", "pcie";
 112                         #phy-cells = <1>;
 113                 };
 114
 115                 rcu0: rcu@203000 {
 116                         #address-cells = <1>;
 117                         #size-cells = <1>;
 118                         compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
 119                         reg = <0x203000 0x100>;
 120                         ranges = <0x0 0x203000 0x100>;
 121                         big-endian;
 122
 123                         reset0: reset-controller@10 {
 124                                 compatible = "lantiq,xrx200-reset";
 125                                 reg = <0x10 4>, <0x14 4>;
 126
 127                                 #reset-cells = <2>;
 128                         };
 129
 130                         reset1: reset-controller@48 {
 131                                 compatible = "lantiq,xrx200-reset";
 132                                 reg = <0x48 4>, <0x24 4>;
 133
 134                                 #reset-cells = <2>;
 135                         };
 136
 137                         usb_phy0: usb2-phy@18 {
 138                                 compatible = "lantiq,xrx200-usb2-phy";
 139                                 reg = <0x18 4>, <0x38 4>;
 140                                 status = "disabled";
 141
 142                                 resets = <&reset1 4 4>, <&reset0 4 4>;
 143                                 reset-names = "phy", "ctrl";
 144                                 #phy-cells = <0>;
 145                         };
 146
 147                         usb_phy1: usb2-phy@34 {
 148                                 compatible = "lantiq,xrx200-usb2-phy";
 149                                 reg = <0x34 4>, <0x3c 4>;
 150                                 status = "disabled";
 151
 152                                 resets = <&reset1 5 5>, <&reset0 4 4>;
 153                                 reset-names = "phy", "ctrl";
 154                                 #phy-cells = <0>;
 155                         };
 156                 };
 157         };
 158
 159         fpi@10000000 {
 160                 compatible = "lantiq,xrx200-fpi", "simple-bus";
 161                 ranges = <0x0 0x10000000 0xf000000>;
 162                 reg =   <0x1f400000 0x1000>,
 163                         <0x10000000 0xf000000>;
 164                 regmap = <&rcu0>;
 165                 offset-endianness = <0x4c>;
 166                 #address-cells = <1>;
 167                 #size-cells = <1>;
 168
 169                 localbus: localbus@0 {
 170                         #address-cells = <2>;
 171                         #size-cells = <1>;
 172                         ranges = <0 0 0x0 0x3ffffff /* addrsel0 */
 173                                 1 0 0x4000000 0x4000010>; /* addsel1 */
 174                         compatible = "lantiq,localbus", "simple-bus";
 175                 };
 176
 177                 gptu@e100a00 {
 178                         compatible = "lantiq,gptu-xway";
 179                         reg = <0xe100a00 0x100>;
 180                         interrupt-parent = <&icu0>;
 181                         interrupts = <126 127 128 129 130 131>;
 182                 };
 183
 184                 usif: usif@da00000 {
 185                         compatible = "lantiq,usif";
 186                         reg = <0xda00000 0x1000000>;
 187                         interrupt-parent = <&icu0>;
 188                         interrupts = <29 125 107 108 109 110>;
 189                         status = "disabled";
 190                 };
 191
 192                 spi: spi@e100800 {
 193                         compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
 194                         reg = <0xe100800 0x100>;
 195                         interrupt-parent = <&icu0>;
 196                         interrupts = <22 23 24>;
 197                         interrupt-names = "spi_rx", "spi_tx", "spi_err",
 198                                         "spi_frm";
 199                         #address-cells = <1>;
 200                         #size-cells = <0>;
 201                         pinctrl-names = "default";
 202                         pinctrl-0 = <&spi_pins>, <&spi_cs4_pins>;
 203                         status = "disabled";
 204                 };
 205
 206                 gpio: pinmux@e100b10 {
 207                         compatible = "lantiq,xrx200-pinctrl";
 208                         #gpio-cells = <2>;
 209                         gpio-controller;
 210                         gpio-ranges = <&gpio 0 0 50>;
 211                         reg = <0xe100b10 0xa0>;
 212
 213                         gphy0_led0_pins: gphy0-led0 {
 214                                 mux {
 215                                         lantiq,groups = "gphy0 led0";
 216                                         lantiq,function = "gphy";
 217                                         lantiq,open-drain = <0>;
 218                                         lantiq,pull = <2>;
 219                                         lantiq,output = <1>;
 220                                 };
 221                         };
 222
 223                         gphy0_led1_pins: gphy0-led1 {
 224                                 mux {
 225                                         lantiq,groups = "gphy0 led1";
 226                                         lantiq,function = "gphy";
 227                                         lantiq,open-drain = <0>;
 228                                         lantiq,pull = <2>;
 229                                         lantiq,output = <1>;
 230                                 };
 231                         };
 232
 233                         gphy0_led2_pins: gphy0-led2 {
 234                                 mux {
 235                                         lantiq,groups = "gphy0 led2";
 236                                         lantiq,function = "gphy";
 237                                         lantiq,open-drain = <0>;
 238                                         lantiq,pull = <2>;
 239                                         lantiq,output = <1>;
 240                                 };
 241                         };
 242
 243                         gphy1_led0_pins: gphy1-led0 {
 244                                 mux {
 245                                         lantiq,groups = "gphy1 led0";
 246                                         lantiq,function = "gphy";
 247                                         lantiq,open-drain = <0>;
 248                                         lantiq,pull = <2>;
 249                                         lantiq,output = <1>;
 250                                 };
 251                         };
 252
 253                         gphy1_led1_pins: gphy1-led1 {
 254                                 mux {
 255                                         lantiq,groups = "gphy1 led1";
 256                                         lantiq,function = "gphy";
 257                                         lantiq,open-drain = <0>;
 258                                         lantiq,pull = <2>;
 259                                         lantiq,output = <1>;
 260                                 };
 261                         };
 262
 263                         gphy1_led2_pins: gphy1-led2 {
 264                                 mux {
 265                                         lantiq,groups = "gphy1 led2";
 266                                         lantiq,function = "gphy";
 267                                         lantiq,open-drain = <0>;
 268                                         lantiq,pull = <2>;
 269                                         lantiq,output = <1>;
 270                                 };
 271                         };
 272
 273                         mdio_pins: mdio {
 274                                 mux {
 275                                         lantiq,groups = "mdio";
 276                                         lantiq,function = "mdio";
 277                                 };
 278                         };
 279
 280                         nand_pins: nand {
 281                                 mux-0 {
 282                                         lantiq,groups = "nand cle", "nand ale",
 283                                                         "nand rd";
 284                                         lantiq,function = "ebu";
 285                                         lantiq,output = <1>;
 286                                         lantiq,open-drain = <0>;
 287                                         lantiq,pull = <0>;
 288                                 };
 289                                 mux-1 {
 290                                         lantiq,groups = "nand rdy";
 291                                         lantiq,function = "ebu";
 292                                         lantiq,output = <0>;
 293                                         lantiq,pull = <2>;
 294                                 };
 295                         };
 296
 297                         nand_cs1_pins: nand-cs1 {
 298                                 mux {
 299                                         lantiq,groups = "nand cs1";
 300                                         lantiq,function = "ebu";
 301                                         lantiq,open-drain = <0>;
 302                                         lantiq,pull = <0>;
 303                                 };
 304                         };
 305
 306                         pci_gnt1_pins: pci-gnt1 {
 307                                 mux {
 308                                         lantiq,groups = "gnt1";
 309                                         lantiq,function = "pci";
 310                                         lantiq,output = <1>;
 311                                         lantiq,open-drain = <0>;
 312                                         lantiq,pull = <0>;
 313                                 };
 314                         };
 315
 316                         pci_req1_pins: pci-req1 {
 317                                 mux {
 318                                         lantiq,groups = "req1";
 319                                         lantiq,function = "pci";
 320                                         lantiq,output = <0>;
 321                                         lantiq,open-drain = <1>;
 322                                         lantiq,pull = <2>;
 323                                 };
 324                         };
 325
 326                         spi_pins: spi {
 327                                 mux-0 {
 328                                         lantiq,groups = "spi_di";
 329                                         lantiq,function = "spi";
 330                                 };
 331                                 mux-1 {
 332                                         lantiq,groups = "spi_do", "spi_clk";
 333                                         lantiq,function = "spi";
 334                                         lantiq,output = <1>;
 335                                 };
 336                         };
 337
 338                         spi_cs4_pins: spi-cs4 {
 339                                 mux {
 340                                         lantiq,groups = "spi_cs4";
 341                                         lantiq,function = "spi";
 342                                         lantiq,output = <1>;
 343                                 };
 344                         };
 345
 346                         stp_pins: stp {
 347                                 mux {
 348                                         lantiq,groups = "stp";
 349                                         lantiq,function = "stp";
 350                                         lantiq,pull = <0>;
 351                                         lantiq,open-drain = <0>;
 352                                         lantiq,output = <1>;
 353                                 };
 354                         };
 355                 };
 356
 357                 stp: stp@e100bb0 {
 358                         status = "disabled";
 359                         compatible = "lantiq,gpio-stp-xway";
 360                         reg = <0xe100bb0 0x40>;
 361                         #gpio-cells = <2>;
 362                         gpio-controller;
 363
 364                         pinctrl-0 = <&stp_pins>;
 365                         pinctrl-names = "default";
 366
 367                         lantiq,shadow = <0xffffff>;
 368                         lantiq,groups = <0x7>;
 369                         lantiq,dsl = <0x0>;
 370                         lantiq,phy1 = <0x0>;
 371                         lantiq,phy2 = <0x0>;
 372                 };
 373
 374                 asc1: serial@e100c00 {
 375                         compatible = "lantiq,asc";
 376                         reg = <0xe100c00 0x400>;
 377                         interrupt-parent = <&icu0>;
 378                         interrupts = <112 113 114>;
 379                 };
 380
 381                 deu@e103100 {
 382                         compatible = "lantiq,deu-xrx200";
 383                         reg = <0xe103100 0xf00>;
 384                 };
 385
 386                 dma0: dma@e104100 {
 387                         compatible = "lantiq,dma-xway";
 388                         reg = <0xe104100 0x800>;
 389                 };
 390
 391                 ebu0: ebu@e105300 {
 392                         compatible = "lantiq,ebu-xway";
 393                         reg = <0xe105300 0x100>;
 394                 };
 395
 396                 usb0: usb@e101000 {
 397                         #address-cells = <1>;
 398                         #size-cells = <0>;
 399                         status = "disabled";
 400                         compatible = "lantiq,xrx200-usb";
 401                         reg = <0xe101000 0x1000
 402                                 0xe120000 0x3f000>;
 403                         interrupt-parent = <&icu0>;
 404                         interrupts = <62 91>;
 405                         dr_mode = "host";
 406                         phys = <&usb_phy0>;
 407                         phy-names = "usb2-phy";
 408
 409                         ehci_port1: port@1 {
 410                                 reg = <1>;
 411                                 #trigger-source-cells = <0>;
 412                         };
 413                 };
 414
 415                 usb1: usb@e106000 {
 416                         #address-cells = <1>;
 417                         #size-cells = <0>;
 418                         status = "disabled";
 419                         compatible = "lantiq,xrx200-usb";
 420                         reg = <0xe106000 0x1000>;
 421                         interrupt-parent = <&icu0>;
 422                         interrupts = <91>;
 423                         dr_mode = "host";
 424                         phys = <&usb_phy1>;
 425                         phy-names = "usb2-phy";
 426
 427                         ehci_port2: port@1 {
 428                                 reg = <1>;
 429                                 #trigger-source-cells = <0>;
 430                         };
 431                 };
 432
 433                 gswip: switch@e108000 {
 434                         compatible = "lantiq,xrx200-gswip";
 435                         #address-cells = <1>;
 436                         #size-cells = <0>;
 437                         reg = < 0xe108000 0x3000 /* switch */
 438                                 0xe10b100 0x70   /* mdio */
 439                                 0xe10b1d8 0x30   /* mii */
 440                                 >;
 441
 442                         dsa,member = <0 0>;
 443
 444                         gswip_ports: ports {
 445                                 #address-cells = <1>;
 446                                 #size-cells = <0>;
 447
 448                                 port@6 {
 449                                         reg = <0x6>;
 450                                         label = "cpu";
 451                                         ethernet = <&eth0>;
 452                                 };
 453                         };
 454
 455                         gswip_mdio: mdio {
 456                                 #address-cells = <1>;
 457                                 #size-cells = <0>;
 458                                 compatible = "lantiq,xrx200-mdio";
 459                         };
 460
 461                         gphy-fw {
 462                                 compatible = "lantiq,xrx200-gphy-fw", "lantiq,gphy-fw";
 463                                 lantiq,rcu = <&rcu0>;
 464                                 #address-cells = <1>;
 465                                 #size-cells = <0>;
 466
 467                                 gphy0: gphy@20 {
 468                                         reg = <0x20>;
 469
 470                                         resets = <&reset0 31 30>;
 471                                         reset-names = "gphy";
 472                                 };
 473
 474                                 gphy1: gphy@68 {
 475                                         reg = <0x68>;
 476
 477                                         resets = <&reset0 29 28>;
 478                                         reset-names = "gphy";
 479                                 };
 480                         };
 481                 };
 482
 483                 eth0: eth@e10b308 {
 484                         compatible = "lantiq,xrx200-net";
 485                         reg = <0xe10b308 0x30>; /* pmac */
 486                         interrupt-parent = <&icu0>;
 487                         interrupts = <73>, <72>;
 488                         interrupt-names = "tx", "rx";
 489                         resets = <&reset0 21 16>, <&reset0 8 8>, <&reset0 3 3>;
 490                         reset-names = "switch", "ppe", "ppe_dsp";
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493
 494                         fixed-link {
 495                                 speed = <1000>;
 496                                 full-duplex;
 497                         };
 498                 };
 499
 500                 mei@e116000 {
 501                         compatible = "lantiq,mei-xrx200";
 502                         reg = <0xe116000 0x9c>;
 503                         interrupt-parent = <&icu0>;
 504                         interrupts = <63>;
 505                 };
 506
 507                 ppe@e234000 {
 508                         compatible = "lantiq,ppe-xrx200";
 509                         reg = <0xe234000 0x3ffd>;
 510                         interrupt-parent = <&icu0>;
 511                         interrupts = <96>;
 512                         resets = <&reset0 3 3>, <&reset0 11 11>, <&reset0 23 23>;
 513                         reset-names = "dsp", "dfe", "tc";
 514                 };
 515
 516                 pcie0: pcie@d900000 {
 517                         compatible = "lantiq,pcie-xrx200";
 518
 519                         #interrupt-cells = <1>;
 520                         #size-cells = <2>;
 521                         #address-cells = <3>;
 522
 523                         reg = <0xd900000 0x1000>;
 524
 525                         interrupt-parent = <&icu0>;
 526                         interrupts = <161 144>;
 527
 528                         phys = <&pcie0_phy LANTIQ_PCIE_PHY_MODE_36MHZ>;
 529                         phy-names = "pcie";
 530
 531                         resets = <&reset0 22 22>;
 532
 533                         lantiq,rcu = <&rcu0>;
 534
 535                         device_type = "pci";
 536
 537                         gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
 538                 };
 539
 540                 pci0: pci@e105400 {
 541                         status = "disabled";
 542
 543                         #address-cells = <3>;
 544                         #size-cells = <2>;
 545                         #interrupt-cells = <1>;
 546                         compatible = "lantiq,pci-xway";
 547                         bus-range = <0x0 0x0>;
 548                         ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000   /* pci memory */
 549                                 0x1000000 0 0x00000000 0xae00000 0 0x200000>; /* io space */
 550                         reg = <0x7000000 0x8000         /* config space */
 551                                 0xe105400 0x400>;       /* pci bridge */
 552                         lantiq,bus-clock = <33333333>;
 553                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 554                         interrupt-map = <0x7000 0 0 1 &icu0 30 1>; /* slot 14, irq 30 */
 555                         req-mask = <0x1>; /* GNT1 */
 556
 557                         device_type = "pci";
 558                 };
 559         };
 560
 561         vdsl {
 562                 compatible = "lantiq,vdsl-vrx200";
 563         };
 564 };