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[openwrt/openwrt.git] / target / linux / lantiq / patches-3.14 / 0028-NET-lantiq-various-etop-fixes.patch
1 From 870ed9cae083ff8a60a739ef7e74c5a1800533be Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 9 Sep 2014 22:45:34 +0200
4 Subject: [PATCH 28/36] NET: lantiq: various etop fixes
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 drivers/net/ethernet/lantiq_etop.c | 555 +++++++++++++++++++++++++-----------
9 1 file changed, 389 insertions(+), 166 deletions(-)
10
11 diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
12 index fd4b6ae..1712382 100644
13 --- a/drivers/net/ethernet/lantiq_etop.c
14 +++ b/drivers/net/ethernet/lantiq_etop.c
15 @@ -11,7 +11,7 @@
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 - * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
20 + * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
21 */
22
23 #include <linux/kernel.h>
24 @@ -30,11 +30,16 @@
25 #include <linux/mm.h>
26 #include <linux/platform_device.h>
27 #include <linux/ethtool.h>
28 +#include <linux/if_vlan.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31 #include <linux/io.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/module.h>
34 +#include <linux/clk.h>
35 +#include <linux/of_net.h>
36 +#include <linux/of_irq.h>
37 +#include <linux/of_platform.h>
38
39 #include <asm/checksum.h>
40
41 @@ -42,7 +47,7 @@
42 #include <xway_dma.h>
43 #include <lantiq_platform.h>
44
45 -#define LTQ_ETOP_MDIO 0x11804
46 +#define LTQ_ETOP_MDIO_ACC 0x11804
47 #define MDIO_REQUEST 0x80000000
48 #define MDIO_READ 0x40000000
49 #define MDIO_ADDR_MASK 0x1f
50 @@ -51,44 +56,91 @@
51 #define MDIO_REG_OFFSET 0x10
52 #define MDIO_VAL_MASK 0xffff
53
54 -#define PPE32_CGEN 0x800
55 -#define LQ_PPE32_ENET_MAC_CFG 0x1840
56 +#define LTQ_ETOP_MDIO_CFG 0x11800
57 +#define MDIO_CFG_MASK 0x6
58 +
59 +#define LTQ_ETOP_CFG 0x11808
60 +#define LTQ_ETOP_IGPLEN 0x11820
61 +#define LTQ_ETOP_MAC_CFG 0x11840
62
63 #define LTQ_ETOP_ENETS0 0x11850
64 #define LTQ_ETOP_MAC_DA0 0x1186C
65 #define LTQ_ETOP_MAC_DA1 0x11870
66 -#define LTQ_ETOP_CFG 0x16020
67 -#define LTQ_ETOP_IGPLEN 0x16080
68 +
69 +#define MAC_CFG_MASK 0xfff
70 +#define MAC_CFG_CGEN (1 << 11)
71 +#define MAC_CFG_DUPLEX (1 << 2)
72 +#define MAC_CFG_SPEED (1 << 1)
73 +#define MAC_CFG_LINK (1 << 0)
74
75 #define MAX_DMA_CHAN 0x8
76 #define MAX_DMA_CRC_LEN 0x4
77 #define MAX_DMA_DATA_LEN 0x600
78
79 #define ETOP_FTCU BIT(28)
80 -#define ETOP_MII_MASK 0xf
81 -#define ETOP_MII_NORMAL 0xd
82 -#define ETOP_MII_REVERSE 0xe
83 #define ETOP_PLEN_UNDER 0x40
84 -#define ETOP_CGEN 0x800
85 -
86 -/* use 2 static channels for TX/RX */
87 -#define LTQ_ETOP_TX_CHANNEL 1
88 -#define LTQ_ETOP_RX_CHANNEL 6
89 -#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
90 -#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
91 -
92 +#define ETOP_CFG_MII0 0x01
93 +
94 +#define ETOP_CFG_MASK 0xfff
95 +#define ETOP_CFG_FEN0 (1 << 8)
96 +#define ETOP_CFG_SEN0 (1 << 6)
97 +#define ETOP_CFG_OFF1 (1 << 3)
98 +#define ETOP_CFG_REMII0 (1 << 1)
99 +#define ETOP_CFG_OFF0 (1 << 0)
100 +
101 +#define LTQ_GBIT_MDIO_CTL 0xCC
102 +#define LTQ_GBIT_MDIO_DATA 0xd0
103 +#define LTQ_GBIT_GCTL0 0x68
104 +#define LTQ_GBIT_PMAC_HD_CTL 0x8c
105 +#define LTQ_GBIT_P0_CTL 0x4
106 +#define LTQ_GBIT_PMAC_RX_IPG 0xa8
107 +#define LTQ_GBIT_RGMII_CTL 0x78
108 +
109 +#define PMAC_HD_CTL_AS (1 << 19)
110 +#define PMAC_HD_CTL_RXSH (1 << 22)
111 +
112 +/* Switch Enable (0=disable, 1=enable) */
113 +#define GCTL0_SE 0x80000000
114 +/* Disable MDIO auto polling (0=disable, 1=enable) */
115 +#define PX_CTL_DMDIO 0x00400000
116 +
117 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
118 +#define MDC_CLOCK_MASK 0xff000000
119 +#define MDC_CLOCK_OFFSET 24
120 +
121 +/* register information for the gbit's MDIO bus */
122 +#define MDIO_XR9_REQUEST 0x00008000
123 +#define MDIO_XR9_READ 0x00000800
124 +#define MDIO_XR9_WRITE 0x00000400
125 +#define MDIO_XR9_REG_MASK 0x1f
126 +#define MDIO_XR9_ADDR_MASK 0x1f
127 +#define MDIO_XR9_RD_MASK 0xffff
128 +#define MDIO_XR9_REG_OFFSET 0
129 +#define MDIO_XR9_ADDR_OFFSET 5
130 +#define MDIO_XR9_WR_OFFSET 16
131 +
132 +#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
133 + (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
134 +
135 +/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
136 #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
137 #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
138 #define ltq_etop_w32_mask(x, y, z) \
139 ltq_w32_mask(x, y, ltq_etop_membase + (z))
140
141 -#define DRV_VERSION "1.0"
142 +#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
143 +#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
144 +#define ltq_gbit_w32_mask(x, y, z) \
145 + ltq_w32_mask(x, y, ltq_gbit_membase + (z))
146 +
147 +#define DRV_VERSION "1.2"
148
149 static void __iomem *ltq_etop_membase;
150 +static void __iomem *ltq_gbit_membase;
151
152 struct ltq_etop_chan {
153 - int idx;
154 int tx_free;
155 + int irq;
156 struct net_device *netdev;
157 struct napi_struct napi;
158 struct ltq_dma_channel dma;
159 @@ -98,22 +150,35 @@ struct ltq_etop_chan {
160 struct ltq_etop_priv {
161 struct net_device *netdev;
162 struct platform_device *pdev;
163 - struct ltq_eth_data *pldata;
164 struct resource *res;
165
166 struct mii_bus *mii_bus;
167 struct phy_device *phydev;
168
169 - struct ltq_etop_chan ch[MAX_DMA_CHAN];
170 - int tx_free[MAX_DMA_CHAN >> 1];
171 + struct ltq_etop_chan txch;
172 + struct ltq_etop_chan rxch;
173 +
174 + int tx_irq;
175 + int rx_irq;
176 +
177 + const void *mac;
178 + int mii_mode;
179
180 spinlock_t lock;
181 +
182 + struct clk *clk_ppe;
183 + struct clk *clk_switch;
184 + struct clk *clk_ephy;
185 + struct clk *clk_ephycgu;
186 };
187
188 +static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
189 + int phy_reg, u16 phy_data);
190 +
191 static int
192 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
193 {
194 - ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
195 + ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
196 if (!ch->skb[ch->dma.desc])
197 return -ENOMEM;
198 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
199 @@ -148,8 +213,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan *ch)
200 spin_unlock_irqrestore(&priv->lock, flags);
201
202 skb_put(skb, len);
203 + skb->dev = ch->netdev;
204 skb->protocol = eth_type_trans(skb, ch->netdev);
205 netif_receive_skb(skb);
206 + ch->netdev->stats.rx_packets++;
207 + ch->netdev->stats.rx_bytes += len;
208 }
209
210 static int
211 @@ -157,8 +225,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
212 {
213 struct ltq_etop_chan *ch = container_of(napi,
214 struct ltq_etop_chan, napi);
215 + struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
216 int rx = 0;
217 int complete = 0;
218 + unsigned long flags;
219
220 while ((rx < budget) && !complete) {
221 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
222 @@ -172,7 +242,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
223 }
224 if (complete || !rx) {
225 napi_complete(&ch->napi);
226 + spin_lock_irqsave(&priv->lock, flags);
227 ltq_dma_ack_irq(&ch->dma);
228 + spin_unlock_irqrestore(&priv->lock, flags);
229 }
230 return rx;
231 }
232 @@ -184,12 +256,14 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
233 container_of(napi, struct ltq_etop_chan, napi);
234 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
235 struct netdev_queue *txq =
236 - netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
237 + netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
238 unsigned long flags;
239
240 spin_lock_irqsave(&priv->lock, flags);
241 while ((ch->dma.desc_base[ch->tx_free].ctl &
242 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
243 + ch->netdev->stats.tx_packets++;
244 + ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
245 dev_kfree_skb_any(ch->skb[ch->tx_free]);
246 ch->skb[ch->tx_free] = NULL;
247 memset(&ch->dma.desc_base[ch->tx_free], 0,
248 @@ -202,7 +276,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
249 if (netif_tx_queue_stopped(txq))
250 netif_tx_start_queue(txq);
251 napi_complete(&ch->napi);
252 + spin_lock_irqsave(&priv->lock, flags);
253 ltq_dma_ack_irq(&ch->dma);
254 + spin_unlock_irqrestore(&priv->lock, flags);
255 return 1;
256 }
257
258 @@ -210,9 +286,10 @@ static irqreturn_t
259 ltq_etop_dma_irq(int irq, void *_priv)
260 {
261 struct ltq_etop_priv *priv = _priv;
262 - int ch = irq - LTQ_DMA_CH0_INT;
263 -
264 - napi_schedule(&priv->ch[ch].napi);
265 + if (irq == priv->txch.dma.irq)
266 + napi_schedule(&priv->txch.napi);
267 + else
268 + napi_schedule(&priv->rxch.napi);
269 return IRQ_HANDLED;
270 }
271
272 @@ -224,7 +301,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
273 ltq_dma_free(&ch->dma);
274 if (ch->dma.irq)
275 free_irq(ch->dma.irq, priv);
276 - if (IS_RX(ch->idx)) {
277 + if (ch == &priv->txch) {
278 int desc;
279 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
280 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
281 @@ -235,65 +312,133 @@ static void
282 ltq_etop_hw_exit(struct net_device *dev)
283 {
284 struct ltq_etop_priv *priv = netdev_priv(dev);
285 - int i;
286
287 - ltq_pmu_disable(PMU_PPE);
288 - for (i = 0; i < MAX_DMA_CHAN; i++)
289 - if (IS_TX(i) || IS_RX(i))
290 - ltq_etop_free_channel(dev, &priv->ch[i]);
291 + clk_disable(priv->clk_ppe);
292 +
293 + if (of_machine_is_compatible("lantiq,ar9"))
294 + clk_disable(priv->clk_switch);
295 +
296 + if (of_machine_is_compatible("lantiq,ase")) {
297 + clk_disable(priv->clk_ephy);
298 + clk_disable(priv->clk_ephycgu);
299 + }
300 +
301 + ltq_etop_free_channel(dev, &priv->txch);
302 + ltq_etop_free_channel(dev, &priv->rxch);
303 +}
304 +
305 +static void
306 +ltq_etop_gbit_init(struct net_device *dev)
307 +{
308 + struct ltq_etop_priv *priv = netdev_priv(dev);
309 +
310 + clk_enable(priv->clk_switch);
311 +
312 + /* enable gbit port0 on the SoC */
313 + ltq_gbit_w32_mask((1 << 17), (1 << 18), LTQ_GBIT_P0_CTL);
314 +
315 + ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
316 + /* disable MDIO auto polling mode */
317 + ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
318 + /* set 1522 packet size */
319 + ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
320 + /* disable pmac & dmac headers */
321 + ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
322 + LTQ_GBIT_PMAC_HD_CTL);
323 + /* Due to traffic halt when burst length 8,
324 + replace default IPG value with 0x3B */
325 + ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
326 + /* set mdc clock to 2.5 MHz */
327 + ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
328 + LTQ_GBIT_RGMII_CTL);
329 }
330
331 static int
332 ltq_etop_hw_init(struct net_device *dev)
333 {
334 struct ltq_etop_priv *priv = netdev_priv(dev);
335 - int i;
336 + int mii_mode = priv->mii_mode;
337 +
338 + clk_enable(priv->clk_ppe);
339
340 - ltq_pmu_enable(PMU_PPE);
341 + if (of_machine_is_compatible("lantiq,ar9")) {
342 + ltq_etop_gbit_init(dev);
343 + /* force the etops link to the gbit to MII */
344 + mii_mode = PHY_INTERFACE_MODE_MII;
345 + }
346 + ltq_etop_w32_mask(MDIO_CFG_MASK, 0, LTQ_ETOP_MDIO_CFG);
347 + ltq_etop_w32_mask(MAC_CFG_MASK, MAC_CFG_CGEN | MAC_CFG_DUPLEX |
348 + MAC_CFG_SPEED | MAC_CFG_LINK, LTQ_ETOP_MAC_CFG);
349
350 - switch (priv->pldata->mii_mode) {
351 + switch (mii_mode) {
352 case PHY_INTERFACE_MODE_RMII:
353 - ltq_etop_w32_mask(ETOP_MII_MASK,
354 - ETOP_MII_REVERSE, LTQ_ETOP_CFG);
355 + ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_REMII0 | ETOP_CFG_OFF1 |
356 + ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
357 break;
358
359 case PHY_INTERFACE_MODE_MII:
360 - ltq_etop_w32_mask(ETOP_MII_MASK,
361 - ETOP_MII_NORMAL, LTQ_ETOP_CFG);
362 + ltq_etop_w32_mask(ETOP_CFG_MASK, ETOP_CFG_OFF1 |
363 + ETOP_CFG_SEN0 | ETOP_CFG_FEN0, LTQ_ETOP_CFG);
364 break;
365
366 default:
367 + if (of_machine_is_compatible("lantiq,ase")) {
368 + clk_enable(priv->clk_ephy);
369 + /* disable external MII */
370 + ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
371 + /* enable clock for internal PHY */
372 + clk_enable(priv->clk_ephycgu);
373 + /* we need to write this magic to the internal phy to
374 + make it work */
375 + ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
376 + pr_info("Selected EPHY mode\n");
377 + break;
378 + }
379 netdev_err(dev, "unknown mii mode %d\n",
380 - priv->pldata->mii_mode);
381 + mii_mode);
382 return -ENOTSUPP;
383 }
384
385 - /* enable crc generation */
386 - ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
387 + return 0;
388 +}
389 +
390 +static int
391 +ltq_etop_dma_init(struct net_device *dev)
392 +{
393 + struct ltq_etop_priv *priv = netdev_priv(dev);
394 + int tx = priv->tx_irq - LTQ_DMA_ETOP;
395 + int rx = priv->rx_irq - LTQ_DMA_ETOP;
396 + int err;
397
398 ltq_dma_init_port(DMA_PORT_ETOP);
399
400 - for (i = 0; i < MAX_DMA_CHAN; i++) {
401 - int irq = LTQ_DMA_CH0_INT + i;
402 - struct ltq_etop_chan *ch = &priv->ch[i];
403 -
404 - ch->idx = ch->dma.nr = i;
405 -
406 - if (IS_TX(i)) {
407 - ltq_dma_alloc_tx(&ch->dma);
408 - request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
409 - } else if (IS_RX(i)) {
410 - ltq_dma_alloc_rx(&ch->dma);
411 - for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
412 - ch->dma.desc++)
413 - if (ltq_etop_alloc_skb(ch))
414 - return -ENOMEM;
415 - ch->dma.desc = 0;
416 - request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
417 + priv->txch.dma.nr = tx;
418 + ltq_dma_alloc_tx(&priv->txch.dma);
419 + err = request_irq(priv->tx_irq, ltq_etop_dma_irq, 0, "eth_tx", priv);
420 + if (err) {
421 + netdev_err(dev, "failed to allocate tx irq\n");
422 + goto err_out;
423 + }
424 + priv->txch.dma.irq = priv->tx_irq;
425 +
426 + priv->rxch.dma.nr = rx;
427 + ltq_dma_alloc_rx(&priv->rxch.dma);
428 + for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
429 + priv->rxch.dma.desc++) {
430 + if (ltq_etop_alloc_skb(&priv->rxch)) {
431 + netdev_err(dev, "failed to allocate skbs\n");
432 + err = -ENOMEM;
433 + goto err_out;
434 }
435 - ch->dma.irq = irq;
436 }
437 - return 0;
438 + priv->rxch.dma.desc = 0;
439 + err = request_irq(priv->rx_irq, ltq_etop_dma_irq, 0, "eth_rx", priv);
440 + if (err)
441 + netdev_err(dev, "failed to allocate rx irq\n");
442 + else
443 + priv->rxch.dma.irq = priv->rx_irq;
444 +err_out:
445 + return err;
446 }
447
448 static void
449 @@ -309,7 +454,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
450 {
451 struct ltq_etop_priv *priv = netdev_priv(dev);
452
453 - return phy_ethtool_gset(priv->phydev, cmd);
454 + if (priv->phydev)
455 + return phy_ethtool_gset(priv->phydev, cmd);
456 + else
457 + return 0;
458 }
459
460 static int
461 @@ -317,7 +465,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
462 {
463 struct ltq_etop_priv *priv = netdev_priv(dev);
464
465 - return phy_ethtool_sset(priv->phydev, cmd);
466 + if (priv->phydev)
467 + return phy_ethtool_sset(priv->phydev, cmd);
468 + else
469 + return 0;
470 }
471
472 static int
473 @@ -325,7 +476,10 @@ ltq_etop_nway_reset(struct net_device *dev)
474 {
475 struct ltq_etop_priv *priv = netdev_priv(dev);
476
477 - return phy_start_aneg(priv->phydev);
478 + if (priv->phydev)
479 + return phy_start_aneg(priv->phydev);
480 + else
481 + return 0;
482 }
483
484 static const struct ethtool_ops ltq_etop_ethtool_ops = {
485 @@ -336,6 +490,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = {
486 };
487
488 static int
489 +ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
490 + int phy_reg, u16 phy_data)
491 +{
492 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
493 + (phy_data << MDIO_XR9_WR_OFFSET) |
494 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
495 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
496 +
497 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
498 + ;
499 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
500 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
501 + ;
502 + return 0;
503 +}
504 +
505 +static int
506 +ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
507 +{
508 + u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
509 + ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
510 + ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
511 +
512 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
513 + ;
514 + ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
515 + while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
516 + ;
517 + val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
518 + return val;
519 +}
520 +
521 +static int
522 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
523 {
524 u32 val = MDIO_REQUEST |
525 @@ -343,9 +530,9 @@ ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
526 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
527 phy_data;
528
529 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
530 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
531 ;
532 - ltq_etop_w32(val, LTQ_ETOP_MDIO);
533 + ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
534 return 0;
535 }
536
537 @@ -356,12 +543,12 @@ ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
538 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
539 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
540
541 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
542 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
543 ;
544 - ltq_etop_w32(val, LTQ_ETOP_MDIO);
545 - while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
546 + ltq_etop_w32(val, LTQ_ETOP_MDIO_ACC);
547 + while (ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_REQUEST)
548 ;
549 - val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
550 + val = ltq_etop_r32(LTQ_ETOP_MDIO_ACC) & MDIO_VAL_MASK;
551 return val;
552 }
553
554 @@ -376,14 +563,18 @@ ltq_etop_mdio_probe(struct net_device *dev)
555 {
556 struct ltq_etop_priv *priv = netdev_priv(dev);
557 struct phy_device *phydev = NULL;
558 - int phy_addr;
559 -
560 - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
561 - if (priv->mii_bus->phy_map[phy_addr]) {
562 - phydev = priv->mii_bus->phy_map[phy_addr];
563 - break;
564 - }
565 - }
566 + u32 phy_supported = (SUPPORTED_10baseT_Half
567 + | SUPPORTED_10baseT_Full
568 + | SUPPORTED_100baseT_Half
569 + | SUPPORTED_100baseT_Full
570 + | SUPPORTED_Autoneg
571 + | SUPPORTED_MII
572 + | SUPPORTED_TP);
573 +
574 + if (of_machine_is_compatible("lantiq,ase"))
575 + phydev = priv->mii_bus->phy_map[8];
576 + else
577 + phydev = priv->mii_bus->phy_map[0];
578
579 if (!phydev) {
580 netdev_err(dev, "no PHY found\n");
581 @@ -391,21 +582,18 @@ ltq_etop_mdio_probe(struct net_device *dev)
582 }
583
584 phydev = phy_connect(dev, dev_name(&phydev->dev),
585 - &ltq_etop_mdio_link, priv->pldata->mii_mode);
586 + &ltq_etop_mdio_link, priv->mii_mode);
587
588 if (IS_ERR(phydev)) {
589 netdev_err(dev, "Could not attach to PHY\n");
590 return PTR_ERR(phydev);
591 }
592
593 - phydev->supported &= (SUPPORTED_10baseT_Half
594 - | SUPPORTED_10baseT_Full
595 - | SUPPORTED_100baseT_Half
596 - | SUPPORTED_100baseT_Full
597 - | SUPPORTED_Autoneg
598 - | SUPPORTED_MII
599 - | SUPPORTED_TP);
600 + if (of_machine_is_compatible("lantiq,ar9"))
601 + phy_supported |= SUPPORTED_1000baseT_Half
602 + | SUPPORTED_1000baseT_Full;
603
604 + phydev->supported &= phy_supported;
605 phydev->advertising = phydev->supported;
606 priv->phydev = phydev;
607 pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
608 @@ -430,8 +618,13 @@ ltq_etop_mdio_init(struct net_device *dev)
609 }
610
611 priv->mii_bus->priv = dev;
612 - priv->mii_bus->read = ltq_etop_mdio_rd;
613 - priv->mii_bus->write = ltq_etop_mdio_wr;
614 + if (of_machine_is_compatible("lantiq,ar9")) {
615 + priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
616 + priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
617 + } else {
618 + priv->mii_bus->read = ltq_etop_mdio_rd;
619 + priv->mii_bus->write = ltq_etop_mdio_wr;
620 + }
621 priv->mii_bus->name = "ltq_mii";
622 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
623 priv->pdev->name, priv->pdev->id);
624 @@ -480,17 +673,19 @@ static int
625 ltq_etop_open(struct net_device *dev)
626 {
627 struct ltq_etop_priv *priv = netdev_priv(dev);
628 - int i;
629 + unsigned long flags;
630
631 - for (i = 0; i < MAX_DMA_CHAN; i++) {
632 - struct ltq_etop_chan *ch = &priv->ch[i];
633 + napi_enable(&priv->txch.napi);
634 + napi_enable(&priv->rxch.napi);
635 +
636 + spin_lock_irqsave(&priv->lock, flags);
637 + ltq_dma_open(&priv->txch.dma);
638 + ltq_dma_open(&priv->rxch.dma);
639 + spin_unlock_irqrestore(&priv->lock, flags);
640 +
641 + if (priv->phydev)
642 + phy_start(priv->phydev);
643
644 - if (!IS_TX(i) && (!IS_RX(i)))
645 - continue;
646 - ltq_dma_open(&ch->dma);
647 - napi_enable(&ch->napi);
648 - }
649 - phy_start(priv->phydev);
650 netif_tx_start_all_queues(dev);
651 return 0;
652 }
653 @@ -499,18 +694,19 @@ static int
654 ltq_etop_stop(struct net_device *dev)
655 {
656 struct ltq_etop_priv *priv = netdev_priv(dev);
657 - int i;
658 + unsigned long flags;
659
660 netif_tx_stop_all_queues(dev);
661 - phy_stop(priv->phydev);
662 - for (i = 0; i < MAX_DMA_CHAN; i++) {
663 - struct ltq_etop_chan *ch = &priv->ch[i];
664 + if (priv->phydev)
665 + phy_stop(priv->phydev);
666 + napi_disable(&priv->txch.napi);
667 + napi_disable(&priv->rxch.napi);
668 +
669 + spin_lock_irqsave(&priv->lock, flags);
670 + ltq_dma_close(&priv->txch.dma);
671 + ltq_dma_close(&priv->rxch.dma);
672 + spin_unlock_irqrestore(&priv->lock, flags);
673
674 - if (!IS_RX(i) && !IS_TX(i))
675 - continue;
676 - napi_disable(&ch->napi);
677 - ltq_dma_close(&ch->dma);
678 - }
679 return 0;
680 }
681
682 @@ -520,16 +716,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
683 int queue = skb_get_queue_mapping(skb);
684 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
685 struct ltq_etop_priv *priv = netdev_priv(dev);
686 - struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
687 - struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
688 - int len;
689 + struct ltq_dma_desc *desc =
690 + &priv->txch.dma.desc_base[priv->txch.dma.desc];
691 unsigned long flags;
692 u32 byte_offset;
693 + int len;
694
695 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
696
697 - if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
698 - dev_kfree_skb_any(skb);
699 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
700 + priv->txch.skb[priv->txch.dma.desc]) {
701 netdev_err(dev, "tx ring full\n");
702 netif_tx_stop_queue(txq);
703 return NETDEV_TX_BUSY;
704 @@ -537,7 +733,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
705
706 /* dma needs to start on a 16 byte aligned address */
707 byte_offset = CPHYSADDR(skb->data) % 16;
708 - ch->skb[ch->dma.desc] = skb;
709 + priv->txch.skb[priv->txch.dma.desc] = skb;
710
711 dev->trans_start = jiffies;
712
713 @@ -547,11 +743,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
714 wmb();
715 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
716 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
717 - ch->dma.desc++;
718 - ch->dma.desc %= LTQ_DESC_NUM;
719 + priv->txch.dma.desc++;
720 + priv->txch.dma.desc %= LTQ_DESC_NUM;
721 spin_unlock_irqrestore(&priv->lock, flags);
722
723 - if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
724 + if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
725 netif_tx_stop_queue(txq);
726
727 return NETDEV_TX_OK;
728 @@ -566,8 +762,10 @@ ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
729 struct ltq_etop_priv *priv = netdev_priv(dev);
730 unsigned long flags;
731
732 + int max = ETH_HLEN + VLAN_HLEN + new_mtu + ETH_FCS_LEN;
733 +
734 spin_lock_irqsave(&priv->lock, flags);
735 - ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
736 + ltq_etop_w32((ETOP_PLEN_UNDER << 16) | max,
737 LTQ_ETOP_IGPLEN);
738 spin_unlock_irqrestore(&priv->lock, flags);
739 }
740 @@ -631,34 +829,33 @@ ltq_etop_init(struct net_device *dev)
741 struct ltq_etop_priv *priv = netdev_priv(dev);
742 struct sockaddr mac;
743 int err;
744 - bool random_mac = false;
745
746 ether_setup(dev);
747 dev->watchdog_timeo = 10 * HZ;
748 err = ltq_etop_hw_init(dev);
749 if (err)
750 goto err_hw;
751 + err = ltq_etop_dma_init(dev);
752 + if (err)
753 + goto err_hw;
754 +
755 ltq_etop_change_mtu(dev, 1500);
756
757 - memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
758 + if (priv->mac)
759 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
760 if (!is_valid_ether_addr(mac.sa_data)) {
761 pr_warn("etop: invalid MAC, using random\n");
762 - eth_random_addr(mac.sa_data);
763 - random_mac = true;
764 + random_ether_addr(mac.sa_data);
765 }
766
767 err = ltq_etop_set_mac_address(dev, &mac);
768 if (err)
769 goto err_netdev;
770 -
771 - /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
772 - if (random_mac)
773 - dev->addr_assign_type = NET_ADDR_RANDOM;
774 -
775 ltq_etop_set_multicast_list(dev);
776 - err = ltq_etop_mdio_init(dev);
777 - if (err)
778 - goto err_netdev;
779 + if (!ltq_etop_mdio_init(dev))
780 + dev->ethtool_ops = &ltq_etop_ethtool_ops;
781 + else
782 + pr_warn("etop: mdio probe failed\n");;
783 return 0;
784
785 err_netdev:
786 @@ -678,6 +875,9 @@ ltq_etop_tx_timeout(struct net_device *dev)
787 err = ltq_etop_hw_init(dev);
788 if (err)
789 goto err_hw;
790 + err = ltq_etop_dma_init(dev);
791 + if (err)
792 + goto err_hw;
793 dev->trans_start = jiffies;
794 netif_wake_queue(dev);
795 return;
796 @@ -701,14 +901,18 @@ static const struct net_device_ops ltq_eth_netdev_ops = {
797 .ndo_tx_timeout = ltq_etop_tx_timeout,
798 };
799
800 -static int __init
801 -ltq_etop_probe(struct platform_device *pdev)
802 +static int ltq_etop_probe(struct platform_device *pdev)
803 {
804 struct net_device *dev;
805 struct ltq_etop_priv *priv;
806 - struct resource *res;
807 + struct resource *res, *gbit_res, irqres[2];
808 int err;
809 - int i;
810 +
811 + err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
812 + if (err != 2) {
813 + dev_err(&pdev->dev, "failed to get etop irqs\n");
814 + return -EINVAL;
815 + }
816
817 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 if (!res) {
819 @@ -734,30 +938,58 @@ ltq_etop_probe(struct platform_device *pdev)
820 goto err_out;
821 }
822
823 - dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
824 - if (!dev) {
825 - err = -ENOMEM;
826 - goto err_out;
827 + if (of_machine_is_compatible("lantiq,ar9")) {
828 + gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
829 + if (!gbit_res) {
830 + dev_err(&pdev->dev, "failed to get gbit resource\n");
831 + err = -ENOENT;
832 + goto err_out;
833 + }
834 + ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
835 + gbit_res->start, resource_size(gbit_res));
836 + if (!ltq_gbit_membase) {
837 + dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
838 + pdev->id);
839 + err = -ENOMEM;
840 + goto err_out;
841 + }
842 }
843 +
844 + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
845 strcpy(dev->name, "eth%d");
846 dev->netdev_ops = &ltq_eth_netdev_ops;
847 - dev->ethtool_ops = &ltq_etop_ethtool_ops;
848 priv = netdev_priv(dev);
849 priv->res = res;
850 priv->pdev = pdev;
851 - priv->pldata = dev_get_platdata(&pdev->dev);
852 priv->netdev = dev;
853 + priv->tx_irq = irqres[0].start;
854 + priv->rx_irq = irqres[1].start;
855 + priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
856 + of_get_mac_address_mtd(pdev->dev.of_node, priv->mac);
857 +
858 + priv->clk_ppe = clk_get(&pdev->dev, NULL);
859 + if (IS_ERR(priv->clk_ppe))
860 + return PTR_ERR(priv->clk_ppe);
861 + if (of_machine_is_compatible("lantiq,ar9")) {
862 + priv->clk_switch = clk_get(&pdev->dev, "switch");
863 + if (IS_ERR(priv->clk_switch))
864 + return PTR_ERR(priv->clk_switch);
865 + }
866 + if (of_machine_is_compatible("lantiq,ase")) {
867 + priv->clk_ephy = clk_get(&pdev->dev, "ephy");
868 + if (IS_ERR(priv->clk_ephy))
869 + return PTR_ERR(priv->clk_ephy);
870 + priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
871 + if (IS_ERR(priv->clk_ephycgu))
872 + return PTR_ERR(priv->clk_ephycgu);
873 + }
874 +
875 spin_lock_init(&priv->lock);
876
877 - for (i = 0; i < MAX_DMA_CHAN; i++) {
878 - if (IS_TX(i))
879 - netif_napi_add(dev, &priv->ch[i].napi,
880 - ltq_etop_poll_tx, 8);
881 - else if (IS_RX(i))
882 - netif_napi_add(dev, &priv->ch[i].napi,
883 - ltq_etop_poll_rx, 32);
884 - priv->ch[i].netdev = dev;
885 - }
886 + netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
887 + netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
888 + priv->txch.netdev = dev;
889 + priv->rxch.netdev = dev;
890
891 err = register_netdev(dev);
892 if (err)
893 @@ -786,32 +1018,23 @@ ltq_etop_remove(struct platform_device *pdev)
894 return 0;
895 }
896
897 +static const struct of_device_id ltq_etop_match[] = {
898 + { .compatible = "lantiq,etop-xway" },
899 + {},
900 +};
901 +MODULE_DEVICE_TABLE(of, ltq_etop_match);
902 +
903 static struct platform_driver ltq_mii_driver = {
904 + .probe = ltq_etop_probe,
905 .remove = ltq_etop_remove,
906 .driver = {
907 .name = "ltq_etop",
908 .owner = THIS_MODULE,
909 + .of_match_table = ltq_etop_match,
910 },
911 };
912
913 -int __init
914 -init_ltq_etop(void)
915 -{
916 - int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
917 -
918 - if (ret)
919 - pr_err("ltq_etop: Error registering platform driver!");
920 - return ret;
921 -}
922 -
923 -static void __exit
924 -exit_ltq_etop(void)
925 -{
926 - platform_driver_unregister(&ltq_mii_driver);
927 -}
928 -
929 -module_init(init_ltq_etop);
930 -module_exit(exit_ltq_etop);
931 +module_platform_driver(ltq_mii_driver);
932
933 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
934 MODULE_DESCRIPTION("Lantiq SoC ETOP");
935 --
936 1.7.10.4
937
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