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[openwrt/openwrt.git] / target / linux / lantiq / patches-3.14 / 0029-GPIO-MIPS-lantiq-add-gpio-driver-for-falcon-SoC.patch
1 From 7e178ce2e5f3aef38d4bdd2c0e02eae6100d5af4 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 7 Aug 2014 18:22:19 +0200
4 Subject: [PATCH 29/36] GPIO: MIPS: lantiq: add gpio driver for falcon SoC
5
6 Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of
7 up to 32 pads. The GPIO blocks have a per pin IRQs.
8
9 Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
10 Acked-by: John Crispin <blogic@openwrt.org>
11 Cc: linux-mips@linux-mips.org
12 Cc: linux-gpio@vger.kernel.org
13 ---
14 drivers/gpio/Kconfig | 5 +
15 drivers/gpio/Makefile | 1 +
16 drivers/gpio/gpio-falcon.c | 348 ++++++++++++++++++++++++++++++++++++++++++++
17 3 files changed, 354 insertions(+)
18 create mode 100644 drivers/gpio/gpio-falcon.c
19
20 diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
21 index 903f24d..670c064 100644
22 --- a/drivers/gpio/Kconfig
23 +++ b/drivers/gpio/Kconfig
24 @@ -145,6 +145,11 @@ config GPIO_EP93XX
25 depends on ARCH_EP93XX
26 select GPIO_GENERIC
27
28 +config GPIO_FALCON
29 + def_bool y
30 + depends on MIPS && SOC_FALCON
31 + select GPIO_GENERIC
32 +
33 config GPIO_MM_LANTIQ
34 bool "Lantiq Memory mapped GPIOs"
35 depends on LANTIQ && SOC_XWAY
36 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
37 index 5d50179..c92db39 100644
38 --- a/drivers/gpio/Makefile
39 +++ b/drivers/gpio/Makefile
40 @@ -26,6 +26,7 @@ obj-$(CONFIG_GPIO_DAVINCI) += gpio-davinci.o
41 obj-$(CONFIG_GPIO_EM) += gpio-em.o
42 obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o
43 obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o
44 +obj-$(CONFIG_GPIO_FALCON) += gpio-falcon.o
45 obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o
46 obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o
47 obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
48 diff --git a/drivers/gpio/gpio-falcon.c b/drivers/gpio/gpio-falcon.c
49 new file mode 100644
50 index 0000000..ae3bdfb
51 --- /dev/null
52 +++ b/drivers/gpio/gpio-falcon.c
53 @@ -0,0 +1,348 @@
54 +/*
55 + * This program is free software; you can redistribute it and/or modify it
56 + * under the terms of the GNU General Public License version 2 as published
57 + * by the Free Software Foundation.
58 + *
59 + * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
60 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
61 + */
62 +
63 +#include <linux/gpio.h>
64 +#include <linux/interrupt.h>
65 +#include <linux/slab.h>
66 +#include <linux/export.h>
67 +#include <linux/err.h>
68 +#include <linux/module.h>
69 +#include <linux/of.h>
70 +#include <linux/of_irq.h>
71 +#include <linux/pinctrl/pinctrl.h>
72 +#include <linux/pinctrl/consumer.h>
73 +#include <linux/platform_device.h>
74 +
75 +#include <lantiq_soc.h>
76 +
77 +/* Data Output Register */
78 +#define GPIO_OUT 0x00000000
79 +/* Data Input Register */
80 +#define GPIO_IN 0x00000004
81 +/* Direction Register */
82 +#define GPIO_DIR 0x00000008
83 +/* External Interrupt Control Register 0 */
84 +#define GPIO_EXINTCR0 0x00000018
85 +/* External Interrupt Control Register 1 */
86 +#define GPIO_EXINTCR1 0x0000001C
87 +/* IRN Capture Register */
88 +#define GPIO_IRNCR 0x00000020
89 +/* IRN Interrupt Configuration Register */
90 +#define GPIO_IRNCFG 0x0000002C
91 +/* IRN Interrupt Enable Set Register */
92 +#define GPIO_IRNRNSET 0x00000030
93 +/* IRN Interrupt Enable Clear Register */
94 +#define GPIO_IRNENCLR 0x00000034
95 +/* Output Set Register */
96 +#define GPIO_OUTSET 0x00000040
97 +/* Output Cler Register */
98 +#define GPIO_OUTCLR 0x00000044
99 +/* Direction Clear Register */
100 +#define GPIO_DIRSET 0x00000048
101 +/* Direction Set Register */
102 +#define GPIO_DIRCLR 0x0000004C
103 +
104 +/* turn a gpio_chip into a falcon_gpio_port */
105 +#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip)
106 +/* turn a irq_data into a falcon_gpio_port */
107 +#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq))
108 +
109 +#define port_r32(p, reg) ltq_r32(p->port + reg)
110 +#define port_w32(p, val, reg) ltq_w32(val, p->port + reg)
111 +#define port_w32_mask(p, clear, set, reg) \
112 + port_w32(p, (port_r32(p, reg) & ~(clear)) | (set), reg)
113 +
114 +#define MAX_BANKS 5
115 +#define PINS_PER_PORT 32
116 +
117 +struct falcon_gpio_port {
118 + struct gpio_chip gpio_chip;
119 + void __iomem *port;
120 + unsigned int irq_base;
121 + unsigned int chained_irq;
122 + struct clk *clk;
123 + char name[6];
124 +};
125 +
126 +static struct irq_chip falcon_gpio_irq_chip;
127 +
128 +static int falcon_gpio_direction_input(struct gpio_chip *chip,
129 + unsigned int offset)
130 +{
131 + port_w32(ctop(chip), 1 << offset, GPIO_DIRCLR);
132 +
133 + return 0;
134 +}
135 +
136 +static void falcon_gpio_set(struct gpio_chip *chip, unsigned int offset,
137 + int value)
138 +{
139 + if (value)
140 + port_w32(ctop(chip), 1 << offset, GPIO_OUTSET);
141 + else
142 + port_w32(ctop(chip), 1 << offset, GPIO_OUTCLR);
143 +}
144 +
145 +static int falcon_gpio_direction_output(struct gpio_chip *chip,
146 + unsigned int offset, int value)
147 +{
148 + falcon_gpio_set(chip, offset, value);
149 + port_w32(ctop(chip), 1 << offset, GPIO_DIRSET);
150 +
151 + return 0;
152 +}
153 +
154 +static int falcon_gpio_get(struct gpio_chip *chip, unsigned int offset)
155 +{
156 + if ((port_r32(ctop(chip), GPIO_DIR) >> offset) & 1)
157 + return (port_r32(ctop(chip), GPIO_OUT) >> offset) & 1;
158 + else
159 + return (port_r32(ctop(chip), GPIO_IN) >> offset) & 1;
160 +}
161 +
162 +static int falcon_gpio_request(struct gpio_chip *chip, unsigned offset)
163 +{
164 + int gpio = chip->base + offset;
165 +
166 + return pinctrl_request_gpio(gpio);
167 +}
168 +
169 +static void falcon_gpio_free(struct gpio_chip *chip, unsigned offset)
170 +{
171 + int gpio = chip->base + offset;
172 +
173 + pinctrl_free_gpio(gpio);
174 +}
175 +
176 +static int falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
177 +{
178 + return ctop(chip)->irq_base + offset;
179 +}
180 +
181 +static void falcon_gpio_disable_irq(struct irq_data *d)
182 +{
183 + unsigned int offset = d->irq - itop(d)->irq_base;
184 +
185 + port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
186 +}
187 +
188 +static void falcon_gpio_enable_irq(struct irq_data *d)
189 +{
190 + unsigned int offset = d->irq - itop(d)->irq_base;
191 +
192 + port_w32(itop(d), 1 << offset, GPIO_IRNRNSET);
193 +}
194 +
195 +static void falcon_gpio_ack_irq(struct irq_data *d)
196 +{
197 + unsigned int offset = d->irq - itop(d)->irq_base;
198 +
199 + port_w32(itop(d), 1 << offset, GPIO_IRNCR);
200 +}
201 +
202 +static void falcon_gpio_mask_and_ack_irq(struct irq_data *d)
203 +{
204 + unsigned int offset = d->irq - itop(d)->irq_base;
205 +
206 + port_w32(itop(d), 1 << offset, GPIO_IRNENCLR);
207 + port_w32(itop(d), 1 << offset, GPIO_IRNCR);
208 +}
209 +
210 +static int falcon_gpio_irq_type(struct irq_data *d, unsigned int type)
211 +{
212 + unsigned int offset = d->irq - itop(d)->irq_base;
213 + unsigned int mask = 1 << offset;
214 +
215 + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE)
216 + return 0;
217 +
218 + if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) {
219 + /* level triggered */
220 + port_w32_mask(itop(d), 0, mask, GPIO_IRNCFG);
221 + irq_set_chip_and_handler_name(d->irq,
222 + &falcon_gpio_irq_chip, handle_level_irq, "mux");
223 + } else {
224 + /* edge triggered */
225 + port_w32_mask(itop(d), mask, 0, GPIO_IRNCFG);
226 + irq_set_chip_and_handler_name(d->irq,
227 + &falcon_gpio_irq_chip, handle_simple_irq, "mux");
228 + }
229 +
230 + if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
231 + port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
232 + port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR1);
233 + } else {
234 + if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0)
235 + /* positive logic: rising edge, high level */
236 + port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR0);
237 + else
238 + /* negative logic: falling edge, low level */
239 + port_w32_mask(itop(d), 0, mask, GPIO_EXINTCR0);
240 + port_w32_mask(itop(d), mask, 0, GPIO_EXINTCR1);
241 + }
242 +
243 + return gpio_direction_input(itop(d)->gpio_chip.base + offset);
244 +}
245 +
246 +static void falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
247 +{
248 + struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc);
249 + unsigned long irncr;
250 + int offset;
251 +
252 + /* acknowledge interrupt */
253 + irncr = port_r32(gpio_port, GPIO_IRNCR);
254 + port_w32(gpio_port, irncr, GPIO_IRNCR);
255 +
256 + desc->irq_data.chip->irq_ack(&desc->irq_data);
257 +
258 + for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio)
259 + generic_handle_irq(gpio_port->irq_base + offset);
260 +}
261 +
262 +static int falcon_gpio_irq_map(struct irq_domain *d, unsigned int irq,
263 + irq_hw_number_t hw)
264 +{
265 + struct falcon_gpio_port *port = d->host_data;
266 +
267 + irq_set_chip_and_handler_name(irq, &falcon_gpio_irq_chip,
268 + handle_simple_irq, "mux");
269 + irq_set_chip_data(irq, port);
270 +
271 + /* set to negative logic (falling edge, low level) */
272 + port_w32_mask(port, 0, 1 << hw, GPIO_EXINTCR0);
273 + return 0;
274 +}
275 +
276 +static struct irq_chip falcon_gpio_irq_chip = {
277 + .name = "gpio_irq_mux",
278 + .irq_mask = falcon_gpio_disable_irq,
279 + .irq_unmask = falcon_gpio_enable_irq,
280 + .irq_ack = falcon_gpio_ack_irq,
281 + .irq_mask_ack = falcon_gpio_mask_and_ack_irq,
282 + .irq_set_type = falcon_gpio_irq_type,
283 +};
284 +
285 +static const struct irq_domain_ops irq_domain_ops = {
286 + .xlate = irq_domain_xlate_onetwocell,
287 + .map = falcon_gpio_irq_map,
288 +};
289 +
290 +static struct irqaction gpio_cascade = {
291 + .handler = no_action,
292 + .flags = IRQF_DISABLED,
293 + .name = "gpio_cascade",
294 +};
295 +
296 +static int falcon_gpio_probe(struct platform_device *pdev)
297 +{
298 + struct pinctrl_gpio_range *gpio_range;
299 + struct device_node *node = pdev->dev.of_node;
300 + const __be32 *bank = of_get_property(node, "lantiq,bank", NULL);
301 + struct falcon_gpio_port *gpio_port;
302 + struct resource *gpiores, irqres;
303 + int ret, size;
304 +
305 + if (!bank || *bank >= MAX_BANKS)
306 + return -ENODEV;
307 +
308 + size = pinctrl_falcon_get_range_size(*bank);
309 + if (size < 1) {
310 + dev_err(&pdev->dev, "pad not loaded for bank %d\n", *bank);
311 + return size;
312 + }
313 +
314 + gpio_range = devm_kzalloc(&pdev->dev, sizeof(struct pinctrl_gpio_range),
315 + GFP_KERNEL);
316 + if (!gpio_range)
317 + return -ENOMEM;
318 +
319 + gpio_port = devm_kzalloc(&pdev->dev, sizeof(struct falcon_gpio_port),
320 + GFP_KERNEL);
321 + if (!gpio_port)
322 + return -ENOMEM;
323 +
324 + snprintf(gpio_port->name, 6, "gpio%d", *bank);
325 + gpio_port->gpio_chip.label = gpio_port->name;
326 + gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input;
327 + gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output;
328 + gpio_port->gpio_chip.get = falcon_gpio_get;
329 + gpio_port->gpio_chip.set = falcon_gpio_set;
330 + gpio_port->gpio_chip.request = falcon_gpio_request;
331 + gpio_port->gpio_chip.free = falcon_gpio_free;
332 + gpio_port->gpio_chip.base = *bank * PINS_PER_PORT;
333 + gpio_port->gpio_chip.ngpio = size;
334 + gpio_port->gpio_chip.dev = &pdev->dev;
335 +
336 + gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
337 + gpio_port->port = devm_request_and_ioremap(&pdev->dev, gpiores);
338 + if (IS_ERR(gpio_port->port))
339 + return PTR_ERR(gpio_port->port);
340 +
341 + gpio_port->clk = devm_clk_get(&pdev->dev, NULL);
342 + if (IS_ERR(gpio_port->clk))
343 + return PTR_ERR(gpio_port->clk);
344 + clk_activate(gpio_port->clk);
345 +
346 + if (of_irq_to_resource_table(node, &irqres, 1) == 1) {
347 + gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * *bank);
348 + gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq;
349 + gpio_port->chained_irq = irqres.start;
350 + irq_domain_add_legacy(node, size, gpio_port->irq_base, 0,
351 + &irq_domain_ops, gpio_port);
352 + setup_irq(irqres.start, &gpio_cascade);
353 + irq_set_handler_data(irqres.start, gpio_port);
354 + irq_set_chained_handler(irqres.start, falcon_gpio_irq_handler);
355 + }
356 +
357 + ret = gpiochip_add(&gpio_port->gpio_chip);
358 + if (ret)
359 + return ret;
360 +
361 + platform_set_drvdata(pdev, gpio_port);
362 +
363 + gpio_range->name = "FALCON GPIO";
364 + gpio_range->id = *bank;
365 + gpio_range->base = gpio_port->gpio_chip.base;
366 + gpio_range->pin_base = gpio_port->gpio_chip.base;
367 + gpio_range->npins = gpio_port->gpio_chip.ngpio;
368 + gpio_range->gc = &gpio_port->gpio_chip;
369 +
370 + pinctrl_falcon_add_gpio_range(gpio_range);
371 +
372 + return 0;
373 +}
374 +
375 +static const struct of_device_id falcon_gpio_match[] = {
376 + { .compatible = "lantiq,falcon-gpio" },
377 + {},
378 +};
379 +MODULE_DEVICE_TABLE(of, falcon_gpio_match);
380 +
381 +static struct platform_driver falcon_gpio_driver = {
382 + .probe = falcon_gpio_probe,
383 + .driver = {
384 + .name = "gpio-falcon",
385 + .owner = THIS_MODULE,
386 + .of_match_table = falcon_gpio_match,
387 + },
388 +};
389 +
390 +int __init falcon_gpio_init(void)
391 +{
392 + int ret;
393 +
394 + pr_info("FALC(tm) ON GPIO Driver, (C) 2012 Lantiq Deutschland Gmbh\n");
395 + ret = platform_driver_register(&falcon_gpio_driver);
396 + if (ret)
397 + pr_err("falcon_gpio: Error registering platform driver!");
398 + return ret;
399 +}
400 +
401 +subsys_initcall(falcon_gpio_init);
402 --
403 1.7.10.4
404
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