target/linux/lantiq/patches-3.3/0029-NET-MIPS-lantiq-convert-etop-driver-to-clkdev-api.patch

   1 From 118d9f0abd69278cfdd7c5bde4743c0cab9b7618 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 8 Mar 2012 11:23:00 +0100
   4 Subject: [PATCH 29/70] NET: MIPS: lantiq: convert etop driver to clkdev api
   5
   6 Update from old pmu_{dis,en}able() to ckldev api.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 Cc: netdev@vger.kernel.org
  10 ---
  11  drivers/net/ethernet/lantiq_etop.c |   49 ++++++++++++++++++++++++++++++-----
  12  1 files changed, 42 insertions(+), 7 deletions(-)
  13
  14 diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
  15 index ad0fa54..8fbb069 100644
  16 --- a/drivers/net/ethernet/lantiq_etop.c
  17 +++ b/drivers/net/ethernet/lantiq_etop.c
  18 @@ -36,6 +36,7 @@
  19  #include <linux/io.h>
  20  #include <linux/dma-mapping.h>
  21  #include <linux/module.h>
  22 +#include <linux/clk.h>
  23
  24  #include <asm/checksum.h>
  25
  26 @@ -148,6 +149,11 @@ struct ltq_etop_priv {
  27         int tx_free[MAX_DMA_CHAN >> 1];
  28
  29         spinlock_t lock;
  30 +
  31 +       struct clk *clk_ppe;
  32 +       struct clk *clk_switch;
  33 +       struct clk *clk_ephy;
  34 +       struct clk *clk_ephycgu;
  35  };
  36
  37  static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
  38 @@ -281,16 +287,27 @@ ltq_etop_hw_exit(struct net_device *dev)
  39         struct ltq_etop_priv *priv = netdev_priv(dev);
  40         int i;
  41
  42 -       ltq_pmu_disable(PMU_PPE);
  43 +       clk_disable(priv->clk_ppe);
  44 +
  45 +       if (ltq_has_gbit())
  46 +               clk_disable(priv->clk_switch);
  47 +
  48 +       if (ltq_is_ase()) {
  49 +               clk_disable(priv->clk_ephy);
  50 +               clk_disable(priv->clk_ephycgu);
  51 +       }
  52 +
  53         for (i = 0; i < MAX_DMA_CHAN; i++)
  54                 if (IS_TX(i) || IS_RX(i))
  55                         ltq_etop_free_channel(dev, &priv->ch[i]);
  56  }
  57
  58  static void
  59 -ltq_etop_gbit_init(void)
  60 +ltq_etop_gbit_init(struct net_device *dev)
  61  {
  62 -       ltq_pmu_enable(PMU_SWITCH);
  63 +       struct ltq_etop_priv *priv = netdev_priv(dev);
  64 +
  65 +       clk_enable(priv->clk_switch);
  66
  67         ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
  68         /** Disable MDIO auto polling mode */
  69 @@ -313,10 +330,10 @@ ltq_etop_hw_init(struct net_device *dev)
  70         int err = 0;
  71         int i;
  72
  73 -       ltq_pmu_enable(PMU_PPE);
  74 +       clk_enable(priv->clk_ppe);
  75
  76         if (ltq_has_gbit()) {
  77 -               ltq_etop_gbit_init();
  78 +               ltq_etop_gbit_init(dev);
  79                 /* force the etops link to the gbit to MII */
  80                 mii_mode = PHY_INTERFACE_MODE_MII;
  81         }
  82 @@ -334,11 +351,11 @@ ltq_etop_hw_init(struct net_device *dev)
  83
  84         default:
  85                 if (ltq_is_ase()) {
  86 -                       ltq_pmu_enable(PMU_EPHY);
  87 +                       clk_enable(priv->clk_ephy);
  88                         /* disable external MII */
  89                         ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
  90                         /* enable clock for internal PHY */
  91 -                       ltq_cgu_enable(CGU_EPHY);
  92 +                       clk_enable(priv->clk_ephycgu);
  93                         /* we need to write this magic to the internal phy to
  94                            make it work */
  95                         ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
  96 @@ -883,6 +900,24 @@ ltq_etop_probe(struct platform_device *pdev)
  97         priv->pdev = pdev;
  98         priv->pldata = dev_get_platdata(&pdev->dev);
  99         priv->netdev = dev;
 100 +
 101 +       priv->clk_ppe = clk_get(&pdev->dev, NULL);
 102 +       if (IS_ERR(priv->clk_ppe))
 103 +               return PTR_ERR(priv->clk_ppe);
 104 +       if (ltq_has_gbit()) {
 105 +               priv->clk_switch = clk_get(&pdev->dev, "switch");
 106 +               if (IS_ERR(priv->clk_switch))
 107 +                       return PTR_ERR(priv->clk_switch);
 108 +       }
 109 +       if (ltq_is_ase()) {
 110 +               priv->clk_ephy = clk_get(&pdev->dev, "ephy");
 111 +               if (IS_ERR(priv->clk_ephy))
 112 +                       return PTR_ERR(priv->clk_ephy);
 113 +               priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
 114 +               if (IS_ERR(priv->clk_ephycgu))
 115 +                       return PTR_ERR(priv->clk_ephycgu);
 116 +       }
 117 +
 118         spin_lock_init(&priv->lock);
 119
 120         for (i = 0; i < MAX_DMA_CHAN; i++) {
 121 --
 122 1.7.9.1
 123