target/linux/lantiq/patches-3.7/0126-lantiq_etop-Change-MDIO-clock.patch

   1 From 2f9f0ec1ff013934a86a7303c9194f6dc05620c3 Mon Sep 17 00:00:00 2001
   2 From: Sebastian Mayr <sebastian.mayr@student.uibk.ac.at>
   3 Date: Thu, 20 Dec 2012 18:34:45 +0100
   4 Subject: [PATCH 1/2] lantiq_etop: Change MDIO clock
   5
   6 This patch sets the MDC clock to 2.5MHz which fixes the MDIO communication
   7 with the ar8316 switch.
   8 ---
   9  drivers/net/ethernet/lantiq_etop.c | 8 ++++++++
  10  1 file changed, 8 insertions(+)
  11
  12 --- a/drivers/net/ethernet/lantiq_etop.c
  13 +++ b/drivers/net/ethernet/lantiq_etop.c
  14 @@ -83,6 +83,7 @@
  15  #define LTQ_GBIT_PMAC_HD_CTL   0x8c
  16  #define LTQ_GBIT_P0_CTL                0x4
  17  #define LTQ_GBIT_PMAC_RX_IPG   0xa8
  18 +#define LTQ_GBIT_RGMII_CTL     0x78
  19
  20  #define PMAC_HD_CTL_AS         (1 << 19)
  21  #define PMAC_HD_CTL_RXSH       (1 << 22)
  22 @@ -92,6 +93,10 @@
  23  /* Disable MDIO auto polling (0=disable, 1=enable) */
  24  #define PX_CTL_DMDIO           0x00400000
  25
  26 +/* MDC clock divider, clock = 25MHz/((MDC_CLOCK + 1) * 2) */
  27 +#define MDC_CLOCK_MASK         0xff000000
  28 +#define MDC_CLOCK_OFFSET       24
  29 +
  30  /* register information for the gbit's MDIO bus */
  31  #define MDIO_XR9_REQUEST       0x00008000
  32  #define MDIO_XR9_READ          0x00000800
  33 @@ -329,6 +334,9 @@ ltq_etop_gbit_init(struct net_device *de
  34         /* Due to traffic halt when burst length 8,
  35                 replace default IPG value with 0x3B */
  36         ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
  37 +       /* set mdc clock to 2.5 MHz */
  38 +       ltq_gbit_w32_mask(MDC_CLOCK_MASK, 4 << MDC_CLOCK_OFFSET,
  39 +               LTQ_GBIT_RGMII_CTL);
  40  }
  41
  42  static int