target/linux/lantiq/patches-5.4/0111-MIPS-lantiq-dma-reset-correct-number-of-channel.patch

   1 From d31260c2f6a5cdddb052ab7cb09560eb23ce6597 Mon Sep 17 00:00:00 2001
   2 From: Aleksander Jan Bajkowski <olek2@wp.pl>
   3 Date: Thu, 15 Apr 2021 21:28:24 +0200
   4 Subject: [PATCH 2/5] MIPS: lantiq: dma: reset correct number of channel
   5
   6 Different SoCs have a different number of channels, e.g .:
   7 * amazon-se has 10 channels,
   8 * danube+ar9 have 20 channels,
   9 * vr9 has 28 channels,
  10 * ar10 has 24 channels.
  11
  12 We can read the ID register and, depending on the reported
  13 number of channels, reset the appropriate number of channels.
  14
  15 Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl>
  16 ---
  17  arch/mips/lantiq/xway/dma.c | 11 ++++++-----
  18  1 file changed, 6 insertions(+), 5 deletions(-)
  19
  20 --- a/arch/mips/lantiq/xway/dma.c
  21 +++ b/arch/mips/lantiq/xway/dma.c
  22 @@ -30,6 +30,7 @@
  23  #define LTQ_DMA_PCTRL          0x44
  24  #define LTQ_DMA_IRNEN          0xf4
  25
  26 +#define DMA_ID_CHNR            GENMASK(26, 20) /* channel number */
  27  #define DMA_DESCPT             BIT(3)          /* descriptor complete irq */
  28  #define DMA_TX                 BIT(8)          /* TX channel direction */
  29  #define DMA_CHAN_ON            BIT(0)          /* channel on / off bit */
  30 @@ -40,7 +41,6 @@
  31  #define DMA_POLL               BIT(31)         /* turn on channel polling */
  32  #define DMA_CLK_DIV4           BIT(6)          /* polling clock divider */
  33  #define DMA_2W_BURST           BIT(1)          /* 2 word burst length */
  34 -#define DMA_MAX_CHANNEL                20              /* the soc has 20 channels */
  35  #define DMA_ETOP_ENDIANNESS    (0xf << 8) /* endianness swap etop channels */
  36  #define DMA_WEIGHT     (BIT(17) | BIT(16))     /* default channel wheight */
  37
  38 @@ -206,7 +206,7 @@ ltq_dma_init(struct platform_device *pde
  39  {
  40         struct clk *clk;
  41         struct resource *res;
  42 -       unsigned id;
  43 +       unsigned int id, nchannels;
  44         int i;
  45
  46         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  47 @@ -228,17 +228,18 @@ ltq_dma_init(struct platform_device *pde
  48         ltq_dma_w32(0, LTQ_DMA_IRNEN);
  49
  50         /* reset/configure each channel */
  51 -       for (i = 0; i < DMA_MAX_CHANNEL; i++) {
  52 +       id = ltq_dma_r32(LTQ_DMA_ID);
  53 +       nchannels = ((id & DMA_ID_CHNR) >> 20);
  54 +       for (i = 0; i < nchannels; i++) {
  55                 ltq_dma_w32(i, LTQ_DMA_CS);
  56                 ltq_dma_w32(DMA_CHAN_RST, LTQ_DMA_CCTRL);
  57                 ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
  58                 ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
  59         }
  60
  61 -       id = ltq_dma_r32(LTQ_DMA_ID);
  62         dev_info(&pdev->dev,
  63                 "Init done - hw rev: %X, ports: %d, channels: %d\n",
  64 -               id & 0x1f, (id >> 16) & 0xf, id >> 20);
  65 +               id & 0x1f, (id >> 16) & 0xf, nchannels);
  66
  67         return 0;
  68  }