target/linux/lantiq/patches/100-board.patch

   1 --- a/arch/mips/Kconfig
   2 +++ b/arch/mips/Kconfig
   3 @@ -157,6 +157,9 @@
   4
   5           otherwise choose R3000.
   6
   7 +config LANTIQ
   8 +       bool "Lantiq MIPS"
   9 +
  10  config MACH_JAZZ
  11         bool "Jazz family of machines"
  12         select ARC
  13 @@ -729,6 +732,7 @@
  14  source "arch/mips/vr41xx/Kconfig"
  15  source "arch/mips/cavium-octeon/Kconfig"
  16  source "arch/mips/loongson/Kconfig"
  17 +source "arch/mips/lantiq/Kconfig"
  18
  19  endmenu
  20
  21 --- /dev/null
  22 +++ b/arch/mips/lantiq/Kconfig
  23 @@ -0,0 +1,36 @@
  24 +if LANTIQ
  25 +
  26 +config SOC_LANTIQ
  27 +       bool
  28 +       select DMA_NONCOHERENT
  29 +       select IRQ_CPU
  30 +       select CEVT_R4K
  31 +       select CSRC_R4K
  32 +       select SYS_HAS_CPU_MIPS32_R1
  33 +       select SYS_HAS_CPU_MIPS32_R2
  34 +       select SYS_SUPPORTS_BIG_ENDIAN
  35 +       select SYS_SUPPORTS_32BIT_KERNEL
  36 +       select SYS_SUPPORTS_MULTITHREADING
  37 +       select SYS_HAS_EARLY_PRINTK
  38 +       select HW_HAS_PCI
  39 +       select ARCH_REQUIRE_GPIOLIB
  40 +       select SWAP_IO_SPACE
  41 +       select MIPS_MACHINE
  42 +
  43 +choice
  44 +       prompt "SoC Type"
  45 +       default SOC_LANTIQ_XWAY
  46 +
  47 +#config SOC_LANTIQ_FALCON
  48 +#      bool "FALCON"
  49 +#      select SOC_LANTIQ
  50 +
  51 +config SOC_LANTIQ_XWAY
  52 +       bool "XWAY"
  53 +       select SOC_LANTIQ
  54 +endchoice
  55 +
  56 +#source "arch/mips/lantiq/falcon/Kconfig"
  57 +source "arch/mips/lantiq/xway/Kconfig"
  58 +
  59 +endif
  60 --- /dev/null
  61 +++ b/arch/mips/lantiq/Makefile
  62 @@ -0,0 +1,3 @@
  63 +obj-y := irq.o setup.o clk.o prom.o
  64 +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
  65 +obj-$(CONFIG_SOC_LANTIQ_XWAY) += xway/
  66 --- /dev/null
  67 +++ b/arch/mips/lantiq/irq.c
  68 @@ -0,0 +1,218 @@
  69 +/*
  70 + *  This program is free software; you can redistribute it and/or modify it
  71 + *  under the terms of the GNU General Public License version 2 as published
  72 + *  by the Free Software Foundation.
  73 + *
  74 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  75 + */
  76 +
  77 +#include <linux/module.h>
  78 +#include <linux/interrupt.h>
  79 +
  80 +#include <asm/bootinfo.h>
  81 +#include <asm/irq_cpu.h>
  82 +
  83 +#include <lantiq.h>
  84 +#include <irq.h>
  85 +
  86 +#define LQ_ICU_BASE_ADDR       (KSEG1 | 0x1F880200)
  87 +
  88 +#define LQ_ICU_IM0_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0000))
  89 +#define LQ_ICU_IM0_IER         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0008))
  90 +#define LQ_ICU_IM0_IOSR                ((u32 *)(LQ_ICU_BASE_ADDR + 0x0010))
  91 +#define LQ_ICU_IM0_IRSR                ((u32 *)(LQ_ICU_BASE_ADDR + 0x0018))
  92 +#define LQ_ICU_IM0_IMR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0020))
  93 +
  94 +#define LQ_ICU_IM1_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0028))
  95 +#define LQ_ICU_IM2_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0050))
  96 +#define LQ_ICU_IM3_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0078))
  97 +#define LQ_ICU_IM4_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x00A0))
  98 +
  99 +#define LQ_ICU_OFFSET          (LQ_ICU_IM1_ISR - LQ_ICU_IM0_ISR)
 100 +
 101 +#define LQ_EBU_BASE_ADDR       0xBE105300
 102 +#define LQ_EBU_PCC_ISTAT       ((u32 *)(LQ_EBU_BASE_ADDR + 0x00A0))
 103 +
 104 +void
 105 +lq_disable_irq(unsigned int irq_nr)
 106 +{
 107 +       u32 *ier = LQ_ICU_IM0_IER;
 108 +       irq_nr -= INT_NUM_IRQ0;
 109 +       ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 110 +       irq_nr %= INT_NUM_IM_OFFSET;
 111 +       lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
 112 +}
 113 +EXPORT_SYMBOL(lq_disable_irq);
 114 +
 115 +void
 116 +lq_mask_and_ack_irq(unsigned int irq_nr)
 117 +{
 118 +       u32 *ier = LQ_ICU_IM0_IER;
 119 +       u32 *isr = LQ_ICU_IM0_ISR;
 120 +       irq_nr -= INT_NUM_IRQ0;
 121 +       ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 122 +       isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 123 +       irq_nr %= INT_NUM_IM_OFFSET;
 124 +       lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
 125 +       lq_w32((1 << irq_nr), isr);
 126 +}
 127 +EXPORT_SYMBOL(lq_mask_and_ack_irq);
 128 +
 129 +static void
 130 +lq_ack_irq(unsigned int irq_nr)
 131 +{
 132 +       u32 *isr = LQ_ICU_IM0_ISR;
 133 +       irq_nr -= INT_NUM_IRQ0;
 134 +       isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 135 +       irq_nr %= INT_NUM_IM_OFFSET;
 136 +       lq_w32((1 << irq_nr), isr);
 137 +}
 138 +
 139 +void
 140 +lq_enable_irq(unsigned int irq_nr)
 141 +{
 142 +       u32 *ier = LQ_ICU_IM0_IER;
 143 +       irq_nr -= INT_NUM_IRQ0;
 144 +       ier += LQ_ICU_OFFSET  * (irq_nr / INT_NUM_IM_OFFSET);
 145 +       irq_nr %= INT_NUM_IM_OFFSET;
 146 +       lq_w32(lq_r32(ier) | (1 << irq_nr), ier);
 147 +}
 148 +EXPORT_SYMBOL(lq_enable_irq);
 149 +
 150 +static unsigned int
 151 +lq_startup_irq(unsigned int irq)
 152 +{
 153 +       lq_enable_irq(irq);
 154 +       return 0;
 155 +}
 156 +
 157 +static void
 158 +lq_end_irq(unsigned int irq)
 159 +{
 160 +       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 161 +               lq_enable_irq(irq);
 162 +}
 163 +
 164 +static struct irq_chip
 165 +lq_irq_type = {
 166 +       "lq_irq",
 167 +       .startup = lq_startup_irq,
 168 +       .enable = lq_enable_irq,
 169 +       .disable = lq_disable_irq,
 170 +       .unmask = lq_enable_irq,
 171 +       .ack = lq_ack_irq,
 172 +       .mask = lq_disable_irq,
 173 +       .mask_ack = lq_mask_and_ack_irq,
 174 +       .end = lq_end_irq,
 175 +};
 176 +
 177 +static void
 178 +lq_hw_irqdispatch(int module)
 179 +{
 180 +       u32 irq;
 181 +
 182 +       irq = lq_r32(LQ_ICU_IM0_IOSR + (module * LQ_ICU_OFFSET));
 183 +       if (irq == 0)
 184 +               return;
 185 +
 186 +       /* silicon bug causes only the msb set to 1 to be valid. all
 187 +          other bits might be bogus */
 188 +       irq = __fls(irq);
 189 +       do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
 190 +       if ((irq == 22) && (module == 0))
 191 +               lq_w32(lq_r32(LQ_EBU_PCC_ISTAT) | 0x10,
 192 +                       LQ_EBU_PCC_ISTAT);
 193 +}
 194 +
 195 +#define DEFINE_HWx_IRQDISPATCH(x) \
 196 +static void lq_hw ## x ## _irqdispatch(void)\
 197 +{\
 198 +       lq_hw_irqdispatch(x); \
 199 +}
 200 +static void lq_hw5_irqdispatch(void)
 201 +{
 202 +       do_IRQ(MIPS_CPU_TIMER_IRQ);
 203 +}
 204 +DEFINE_HWx_IRQDISPATCH(0)
 205 +DEFINE_HWx_IRQDISPATCH(1)
 206 +DEFINE_HWx_IRQDISPATCH(2)
 207 +DEFINE_HWx_IRQDISPATCH(3)
 208 +DEFINE_HWx_IRQDISPATCH(4)
 209 +/*DEFINE_HWx_IRQDISPATCH(5)*/
 210 +
 211 +asmlinkage void
 212 +plat_irq_dispatch(void)
 213 +{
 214 +       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 215 +       unsigned int i;
 216 +
 217 +       if (pending & CAUSEF_IP7)
 218 +       {
 219 +               do_IRQ(MIPS_CPU_TIMER_IRQ);
 220 +               goto out;
 221 +       } else {
 222 +               for (i = 0; i < 5; i++)
 223 +               {
 224 +                       if (pending & (CAUSEF_IP2 << i))
 225 +                       {
 226 +                               lq_hw_irqdispatch(i);
 227 +                               goto out;
 228 +                       }
 229 +               }
 230 +       }
 231 +       printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
 232 +
 233 +out:
 234 +       return;
 235 +}
 236 +
 237 +static struct irqaction
 238 +cascade = {
 239 +       .handler = no_action,
 240 +       .flags = IRQF_DISABLED,
 241 +       .name = "cascade",
 242 +};
 243 +
 244 +void __init
 245 +arch_init_irq(void)
 246 +{
 247 +       int i;
 248 +
 249 +       for (i = 0; i < 5; i++)
 250 +               lq_w32(0, LQ_ICU_IM0_IER + (i * LQ_ICU_OFFSET));
 251 +
 252 +       mips_cpu_irq_init();
 253 +
 254 +       for (i = 2; i <= 6; i++)
 255 +               setup_irq(i, &cascade);
 256 +
 257 +       if (cpu_has_vint) {
 258 +               printk(KERN_INFO "Setting up vectored interrupts\n");
 259 +               set_vi_handler(2, lq_hw0_irqdispatch);
 260 +               set_vi_handler(3, lq_hw1_irqdispatch);
 261 +               set_vi_handler(4, lq_hw2_irqdispatch);
 262 +               set_vi_handler(5, lq_hw3_irqdispatch);
 263 +               set_vi_handler(6, lq_hw4_irqdispatch);
 264 +               set_vi_handler(7, lq_hw5_irqdispatch);
 265 +       }
 266 +
 267 +       for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
 268 +               set_irq_chip_and_handler(i, &lq_irq_type,
 269 +                       handle_level_irq);
 270 +
 271 +       #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
 272 +       set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
 273 +               IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 274 +       #else
 275 +       set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
 276 +               IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 277 +       #endif
 278 +}
 279 +
 280 +void __cpuinit
 281 +arch_fixup_c0_irqs(void)
 282 +{
 283 +       /* FIXME: check for CPUID and only do fix for specific chips/versions */
 284 +       cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
 285 +       cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
 286 +}
 287 --- /dev/null
 288 +++ b/arch/mips/lantiq/setup.c
 289 @@ -0,0 +1,47 @@
 290 +/*
 291 + *  This program is free software; you can redistribute it and/or modify it
 292 + *  under the terms of the GNU General Public License version 2 as published
 293 + *  by the Free Software Foundation.
 294 + *
 295 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 296 + */
 297 +
 298 +#include <linux/kernel.h>
 299 +#include <linux/module.h>
 300 +#include <linux/io.h>
 301 +#include <linux/ioport.h>
 302 +
 303 +#include <lantiq.h>
 304 +#include <lantiq_regs.h>
 305 +
 306 +void __init
 307 +plat_mem_setup(void)
 308 +{
 309 +       /* assume 16M as default */
 310 +       int memsize = 16;
 311 +       char **envp = (char **) KSEG1ADDR(fw_arg2);
 312 +       u32 status;
 313 +
 314 +       /* make sure to have no "reverse endian" for user mode! */
 315 +       status = read_c0_status();
 316 +       status &= (~(1<<25));
 317 +       write_c0_status(status);
 318 +
 319 +       ioport_resource.start = IOPORT_RESOURCE_START;
 320 +       ioport_resource.end = IOPORT_RESOURCE_END;
 321 +       iomem_resource.start = IOMEM_RESOURCE_START;
 322 +       iomem_resource.end = IOMEM_RESOURCE_END;
 323 +
 324 +       while (*envp)
 325 +       {
 326 +               char *e = (char *)KSEG1ADDR(*envp);
 327 +               if (!strncmp(e, "memsize=", 8))
 328 +               {
 329 +                       e += 8;
 330 +                       memsize = simple_strtoul(e, NULL, 10);
 331 +               }
 332 +               envp++;
 333 +       }
 334 +       memsize *= 1024 * 1024;
 335 +       add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
 336 +}
 337 --- /dev/null
 338 +++ b/arch/mips/lantiq/clk.c
 339 @@ -0,0 +1,141 @@
 340 +/*
 341 + *  This program is free software; you can redistribute it and/or modify it
 342 + *  under the terms of the GNU General Public License version 2 as published
 343 + *  by the Free Software Foundation.
 344 + *
 345 + * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
 346 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 347 + */
 348 +
 349 +#include <linux/io.h>
 350 +#include <linux/module.h>
 351 +#include <linux/init.h>
 352 +#include <linux/kernel.h>
 353 +#include <linux/types.h>
 354 +#include <linux/clk.h>
 355 +#include <linux/err.h>
 356 +#include <linux/list.h>
 357 +
 358 +#include <asm/time.h>
 359 +#include <asm/irq.h>
 360 +#include <asm/div64.h>
 361 +
 362 +#include <lantiq.h>
 363 +#ifdef CONFIG_SOC_LANTIQ_XWAY
 364 +#include <xway.h>
 365 +#endif
 366 +
 367 +extern unsigned long lq_get_cpu_hz(void);
 368 +extern unsigned long lq_get_fpi_hz(void);
 369 +extern unsigned long lq_get_io_region_clock(void);
 370 +
 371 +struct clk {
 372 +       const char *name;
 373 +       unsigned long rate;
 374 +       unsigned long (*get_rate) (void);
 375 +};
 376 +
 377 +static struct clk *cpu_clk = 0;
 378 +static int cpu_clk_cnt = 0;
 379 +
 380 +static unsigned int r4k_offset;
 381 +static unsigned int r4k_cur;
 382 +
 383 +static struct clk cpu_clk_generic[] = {
 384 +       {
 385 +               .name = "cpu",
 386 +               .get_rate = lq_get_cpu_hz,
 387 +       }, {
 388 +               .name = "fpi",
 389 +               .get_rate = lq_get_fpi_hz,
 390 +       }, {
 391 +               .name = "io",
 392 +               .get_rate = lq_get_io_region_clock,
 393 +       },
 394 +};
 395 +
 396 +void
 397 +clk_init(void)
 398 +{
 399 +       int i;
 400 +       cpu_clk = cpu_clk_generic;
 401 +       cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
 402 +       for(i = 0; i < cpu_clk_cnt; i++)
 403 +               printk("%s: %ld\n", cpu_clk[i].name, clk_get_rate(&cpu_clk[i]));
 404 +}
 405 +
 406 +static inline int
 407 +clk_good(struct clk *clk)
 408 +{
 409 +       return clk && !IS_ERR(clk);
 410 +}
 411 +
 412 +unsigned long
 413 +clk_get_rate(struct clk *clk)
 414 +{
 415 +       if (unlikely(!clk_good(clk)))
 416 +               return 0;
 417 +
 418 +       if (clk->rate != 0)
 419 +               return clk->rate;
 420 +
 421 +       if (clk->get_rate != NULL)
 422 +               return clk->get_rate();
 423 +
 424 +       return 0;
 425 +}
 426 +EXPORT_SYMBOL(clk_get_rate);
 427 +
 428 +struct clk*
 429 +clk_get(struct device *dev, const char *id)
 430 +{
 431 +       int i;
 432 +       for(i = 0; i < cpu_clk_cnt; i++)
 433 +               if (!strcmp(id, cpu_clk[i].name))
 434 +                       return &cpu_clk[i];
 435 +       BUG();
 436 +       return ERR_PTR(-ENOENT);
 437 +}
 438 +EXPORT_SYMBOL(clk_get);
 439 +
 440 +void
 441 +clk_put(struct clk *clk)
 442 +{
 443 +       /* not used */
 444 +}
 445 +EXPORT_SYMBOL(clk_put);
 446 +
 447 +static inline u32
 448 +lq_get_counter_resolution(void)
 449 +{
 450 +       u32 res;
 451 +       __asm__ __volatile__(
 452 +               ".set   push\n"
 453 +               ".set   mips32r2\n"
 454 +               ".set   noreorder\n"
 455 +               "rdhwr  %0, $3\n"
 456 +               "ehb\n"
 457 +               ".set pop\n"
 458 +               : "=&r" (res)
 459 +               : /* no input */
 460 +               : "memory");
 461 +       instruction_hazard();
 462 +       return res;
 463 +}
 464 +
 465 +void __init
 466 +plat_time_init(void)
 467 +{
 468 +       struct clk *clk = clk_get(0, "cpu");
 469 +       mips_hpt_frequency = clk_get_rate(clk) / lq_get_counter_resolution();
 470 +       r4k_cur = (read_c0_count() + r4k_offset);
 471 +       write_c0_compare(r4k_cur);
 472 +
 473 +#ifdef CONFIG_SOC_LANTIQ_XWAY
 474 +#define LQ_GPTU_GPT_CLC                        ((u32 *)(LQ_GPTU_BASE_ADDR + 0x0000))
 475 +       lq_pmu_enable(PMU_GPT);
 476 +       lq_pmu_enable(PMU_FPI);
 477 +
 478 +       lq_w32(0x100, LQ_GPTU_GPT_CLC);
 479 +#endif
 480 +}
 481 --- /dev/null
 482 +++ b/arch/mips/lantiq/prom.c
 483 @@ -0,0 +1,118 @@
 484 +/*
 485 + *  This program is free software; you can redistribute it and/or modify it
 486 + *  under the terms of the GNU General Public License version 2 as published
 487 + *  by the Free Software Foundation.
 488 + *
 489 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 490 + */
 491 +
 492 +#include <linux/module.h>
 493 +#include <linux/clk.h>
 494 +#include <asm/bootinfo.h>
 495 +#include <asm/time.h>
 496 +
 497 +#include <lantiq.h>
 498 +
 499 +#include "prom.h"
 500 +
 501 +static struct lq_soc_info soc_info;
 502 +
 503 +/* for Multithreading (APRP) on MIPS34K */
 504 +unsigned long physical_memsize;
 505 +
 506 +/* all access to the ebu must be locked */
 507 +DEFINE_SPINLOCK(ebu_lock);
 508 +EXPORT_SYMBOL_GPL(ebu_lock);
 509 +
 510 +extern void clk_init(void);
 511 +
 512 +unsigned int
 513 +lq_get_cpu_ver(void)
 514 +{
 515 +       return soc_info.rev;
 516 +}
 517 +EXPORT_SYMBOL(lq_get_cpu_ver);
 518 +
 519 +unsigned int
 520 +lq_get_soc_type(void)
 521 +{
 522 +       return soc_info.type;
 523 +}
 524 +EXPORT_SYMBOL(lq_get_soc_type);
 525 +
 526 +const char*
 527 +get_system_type(void)
 528 +{
 529 +       return soc_info.sys_type;
 530 +}
 531 +
 532 +void
 533 +prom_free_prom_memory(void)
 534 +{
 535 +}
 536 +
 537 +#ifdef CONFIG_IMAGE_CMDLINE_HACK
 538 +extern char __image_cmdline[];
 539 +
 540 +static void __init
 541 +prom_init_image_cmdline(void)
 542 +{
 543 +       char *p = __image_cmdline;
 544 +       int replace = 0;
 545 +
 546 +       if (*p == '-') {
 547 +               replace = 1;
 548 +               p++;
 549 +       }
 550 +
 551 +       if (*p == '\0')
 552 +               return;
 553 +
 554 +       if (replace) {
 555 +               strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
 556 +       } else {
 557 +               strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
 558 +               strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
 559 +       }
 560 +}
 561 +#else
 562 +static void __init prom_init_image_cmdline(void) { return; }
 563 +#endif
 564 +
 565 +static void __init
 566 +prom_init_cmdline(void)
 567 +{
 568 +       int argc = fw_arg0;
 569 +       char **argv = (char**)KSEG1ADDR(fw_arg1);
 570 +       int i;
 571 +
 572 +       arcs_cmdline[0] = '\0';
 573 +       if(argc)
 574 +               for (i = 1; i < argc; i++)
 575 +               {
 576 +                       strlcat(arcs_cmdline, (char*)KSEG1ADDR(argv[i]), COMMAND_LINE_SIZE);
 577 +                       if(i + 1 != argc)
 578 +                               strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
 579 +               }
 580 +
 581 +       if (!*arcs_cmdline)
 582 +               strcpy(&(arcs_cmdline[0]),
 583 +                       "console=ttyS1,115200 rootfstype=squashfs,jffs2");
 584 +       prom_init_image_cmdline();
 585 +}
 586 +
 587 +void __init
 588 +prom_init(void)
 589 +{
 590 +       struct clk *clk;
 591 +       lq_soc_detect(&soc_info);
 592 +
 593 +       clk_init();
 594 +       clk = clk_get(0, "cpu");
 595 +       snprintf(soc_info.sys_type, LQ_SYS_TYPE_LEN - 1, "%s rev1.%d %ldMhz",
 596 +               soc_info.name, soc_info.rev, clk_get_rate(clk) / 1000000);
 597 +       soc_info.sys_type[LQ_SYS_TYPE_LEN - 1] = '\0';
 598 +       printk("SoC: %s\n", soc_info.sys_type);
 599 +
 600 +       prom_init_cmdline();
 601 +}
 602 --- /dev/null
 603 +++ b/arch/mips/lantiq/prom.h
 604 @@ -0,0 +1,24 @@
 605 +/*
 606 + *  This program is free software; you can redistribute it and/or modify it
 607 + *  under the terms of the GNU General Public License version 2 as published
 608 + *  by the Free Software Foundation.
 609 + *
 610 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 611 + */
 612 +
 613 +#ifndef _LQ_PROM_H__
 614 +#define _LQ_PROM_H__
 615 +
 616 +#define LQ_SYS_TYPE_LEN        0x100
 617 +
 618 +struct lq_soc_info {
 619 +       unsigned char *name;
 620 +       unsigned int rev;
 621 +       unsigned int partnum;
 622 +       unsigned int type;
 623 +       unsigned char sys_type[LQ_SYS_TYPE_LEN];
 624 +};
 625 +
 626 +void lq_soc_detect(struct lq_soc_info *i);
 627 +
 628 +#endif
 629 --- a/arch/mips/Kbuild.platforms
 630 +++ b/arch/mips/Kbuild.platforms
 631 @@ -11,6 +11,7 @@
 632  platforms += jazz
 633  platforms += jz4740
 634  platforms += lasat
 635 +platforms += lantiq
 636  platforms += loongson
 637  platforms += mipssim
 638  platforms += mti-malta
 639 --- /dev/null
 640 +++ b/arch/mips/lantiq/Platform
 641 @@ -0,0 +1,8 @@
 642 +#
 643 +# Lantiq
 644 +#
 645 +
 646 +platform-$(CONFIG_LANTIQ)      += lantiq/
 647 +cflags-$(CONFIG_LANTIQ)       += -I$(srctree)/arch/mips/include/asm/mach-lantiq
 648 +load-$(CONFIG_LANTIQ)          = 0xffffffff80002000
 649 +cflags-$(CONFIG_SOC_LANTIQ_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway