target/linux/layerscape/patches-4.14/801-sata-support-layerscape.patch

   1 From 918f966af1f0e42ff8ac298e1d7d02e67afcfab4 Mon Sep 17 00:00:00 2001
   2 From: Biwen Li <biwen.li@nxp.com>
   3 Date: Tue, 30 Oct 2018 18:27:42 +0800
   4 Subject: [PATCH 18/40] sata: support layerscape
   5 This is an integrated patch of sata for layerscape
   6
   7 Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
   8 Signed-off-by: Biwen Li <biwen.li@nxp.com>
   9 ---
  10  drivers/ata/ahci_qoriq.c | 12 ++++++++++++
  11  1 file changed, 12 insertions(+)
  12
  13 --- a/drivers/ata/ahci_qoriq.c
  14 +++ b/drivers/ata/ahci_qoriq.c
  15 @@ -35,6 +35,8 @@
  16
  17  /* port register default value */
  18  #define AHCI_PORT_PHY_1_CFG    0xa003fffe
  19 +#define AHCI_PORT_PHY2_CFG     0x28184d1f
  20 +#define AHCI_PORT_PHY3_CFG     0x0e081509
  21  #define AHCI_PORT_TRANS_CFG    0x08000029
  22  #define AHCI_PORT_AXICC_CFG    0x3fffffff
  23
  24 @@ -183,6 +185,8 @@ static int ahci_qoriq_phy_init(struct ah
  25                 writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
  26                                 qpriv->ecc_addr);
  27                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  28 +               writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  29 +               writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  30                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  31                 if (qpriv->is_dmacoherent)
  32                         writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  33 @@ -190,6 +194,8 @@ static int ahci_qoriq_phy_init(struct ah
  34
  35         case AHCI_LS2080A:
  36                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  37 +               writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  38 +               writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  39                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  40                 if (qpriv->is_dmacoherent)
  41                         writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  42 @@ -201,6 +207,8 @@ static int ahci_qoriq_phy_init(struct ah
  43                 writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
  44                                 qpriv->ecc_addr);
  45                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  46 +               writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  47 +               writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  48                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  49                 if (qpriv->is_dmacoherent)
  50                         writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  51 @@ -212,6 +220,8 @@ static int ahci_qoriq_phy_init(struct ah
  52                 writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
  53                        qpriv->ecc_addr);
  54                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  55 +               writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  56 +               writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  57                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  58                 if (qpriv->is_dmacoherent)
  59                         writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  60 @@ -219,6 +229,8 @@ static int ahci_qoriq_phy_init(struct ah
  61
  62         case AHCI_LS2088A:
  63                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  64 +               writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2);
  65 +               writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3);
  66                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  67                 if (qpriv->is_dmacoherent)
  68                         writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);