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[openwrt/openwrt.git] / target / linux / layerscape / patches-4.14 / 807-usb-support-layerscape.patch
1 From ca86ebf3fddbdfa8aecc4b887ef059948ee79621 Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Wed, 17 Apr 2019 18:59:08 +0800
4 Subject: [PATCH] usb: support layerscape
5
6 This is an integrated patch of usb for layerscape
7
8 Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
9 Signed-off-by: Biwen Li <biwen.li@nxp.com>
10 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
11 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
12 Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
13 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
14 Signed-off-by: Li Yang <leoli@freescale.com>
15 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
16 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
17 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
18 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
19 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
20 Signed-off-by: Roger Quadros <rogerq@ti.com>
21 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
22 Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
23 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
24 Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
25 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
26 ---
27 arch/arm64/include/asm/io.h | 28 +++
28 drivers/usb/common/common.c | 50 +++++
29 drivers/usb/core/usb.c | 1 +
30 drivers/usb/dwc3/core.c | 167 ++++++++++++++++
31 drivers/usb/dwc3/core.h | 58 ++++++
32 drivers/usb/dwc3/ep0.c | 4 +-
33 drivers/usb/dwc3/gadget.c | 7 +
34 drivers/usb/dwc3/host.c | 9 +
35 drivers/usb/gadget/udc/fsl_udc_core.c | 46 +++--
36 drivers/usb/gadget/udc/fsl_usb2_udc.h | 16 +-
37 drivers/usb/host/Kconfig | 2 +-
38 drivers/usb/host/ehci-fsl.c | 276 +++++++++++++++++++++++---
39 drivers/usb/host/ehci-fsl.h | 3 +
40 drivers/usb/host/ehci-hub.c | 2 +
41 drivers/usb/host/ehci.h | 3 +
42 drivers/usb/host/fsl-mph-dr-of.c | 11 +
43 drivers/usb/host/xhci-hub.c | 22 ++
44 drivers/usb/host/xhci-plat.c | 16 +-
45 drivers/usb/host/xhci-ring.c | 28 ++-
46 drivers/usb/host/xhci.c | 37 +++-
47 drivers/usb/host/xhci.h | 10 +-
48 drivers/usb/phy/phy-fsl-usb.c | 59 ++++--
49 drivers/usb/phy/phy-fsl-usb.h | 8 +
50 include/linux/usb.h | 1 +
51 include/linux/usb/of.h | 2 +
52 25 files changed, 780 insertions(+), 86 deletions(-)
53
54 --- a/arch/arm64/include/asm/io.h
55 +++ b/arch/arm64/include/asm/io.h
56 @@ -210,6 +210,34 @@ extern void __iomem *ioremap_cache(phys_
57 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
58 #define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
59
60 +/* access ports */
61 +#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
62 +#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
63 +
64 +#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
65 +#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
66 +
67 +#define setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
68 +#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
69 +
70 +/* Clear and set bits in one shot. These macros can be used to clear and
71 + * set multiple bits in a register using a single read-modify-write. These
72 + * macros can also be used to set a multiple-bit bit pattern using a mask,
73 + * by specifying the mask in the 'clear' parameter and the new bit pattern
74 + * in the 'set' parameter.
75 + */
76 +
77 +#define clrsetbits_be32(addr, clear, set) \
78 + iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
79 +#define clrsetbits_le32(addr, clear, set) \
80 + iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
81 +#define clrsetbits_be16(addr, clear, set) \
82 + iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
83 +#define clrsetbits_le16(addr, clear, set) \
84 + iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
85 +#define clrsetbits_8(addr, clear, set) \
86 + iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
87 +
88 #include <asm-generic/io.h>
89
90 /*
91 --- a/drivers/usb/common/common.c
92 +++ b/drivers/usb/common/common.c
93 @@ -105,6 +105,56 @@ static const char *const usb_dr_modes[]
94 [USB_DR_MODE_OTG] = "otg",
95 };
96
97 +/**
98 + * of_usb_get_dr_mode - Get dual role mode for given device_node
99 + * @np: Pointer to the given device_node
100 + *
101 + * The function gets phy interface string from property 'dr_mode',
102 + * and returns the correspondig enum usb_dr_mode
103 + */
104 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
105 +{
106 + const char *dr_mode;
107 + int err, i;
108 +
109 + err = of_property_read_string(np, "dr_mode", &dr_mode);
110 + if (err < 0)
111 + return USB_DR_MODE_UNKNOWN;
112 +
113 + for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
114 + if (!strcmp(dr_mode, usb_dr_modes[i]))
115 + return i;
116 +
117 + return USB_DR_MODE_UNKNOWN;
118 +}
119 +EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
120 +
121 +/**
122 + * of_usb_get_maximum_speed - Get maximum requested speed for a given USB
123 + * controller.
124 + * @np: Pointer to the given device_node
125 + *
126 + * The function gets the maximum speed string from property "maximum-speed",
127 + * and returns the corresponding enum usb_device_speed.
128 + */
129 +enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np)
130 +{
131 + const char *maximum_speed;
132 + int err;
133 + int i;
134 +
135 + err = of_property_read_string(np, "maximum-speed", &maximum_speed);
136 + if (err < 0)
137 + return USB_SPEED_UNKNOWN;
138 +
139 + for (i = 0; i < ARRAY_SIZE(speed_names); i++)
140 + if (strcmp(maximum_speed, speed_names[i]) == 0)
141 + return i;
142 +
143 + return USB_SPEED_UNKNOWN;
144 +}
145 +EXPORT_SYMBOL_GPL(of_usb_get_maximum_speed);
146 +
147 static enum usb_dr_mode usb_get_dr_mode_from_string(const char *str)
148 {
149 int ret;
150 --- a/drivers/usb/core/usb.c
151 +++ b/drivers/usb/core/usb.c
152 @@ -593,6 +593,7 @@ struct usb_device *usb_alloc_dev(struct
153 dev->dev.dma_mask = bus->sysdev->dma_mask;
154 dev->dev.dma_pfn_offset = bus->sysdev->dma_pfn_offset;
155 set_dev_node(&dev->dev, dev_to_node(bus->sysdev));
156 + dev->dev.of_node = bus->controller->of_node;
157 dev->state = USB_STATE_ATTACHED;
158 dev->lpm_disable_count = 1;
159 atomic_set(&dev->urbnum, 0);
160 --- a/drivers/usb/dwc3/core.c
161 +++ b/drivers/usb/dwc3/core.c
162 @@ -103,6 +103,41 @@ static int dwc3_get_dr_mode(struct dwc3
163 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
164 static int dwc3_event_buffers_setup(struct dwc3 *dwc);
165
166 +/*
167 + * dwc3_power_of_all_roothub_ports - Power off all Root hub ports
168 + * @dwc3: Pointer to our controller context structure
169 + */
170 +static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc)
171 +{
172 + int i, port_num;
173 + u32 reg, op_regs_base, offset;
174 + void __iomem *xhci_regs;
175 +
176 + /* xhci regs is not mapped yet, do it temperary here */
177 + if (dwc->xhci_resources[0].start) {
178 + xhci_regs = ioremap(dwc->xhci_resources[0].start,
179 + DWC3_XHCI_REGS_END);
180 + if (IS_ERR(xhci_regs)) {
181 + dev_err(dwc->dev, "Failed to ioremap xhci_regs\n");
182 + return;
183 + }
184 +
185 + op_regs_base = HC_LENGTH(readl(xhci_regs));
186 + reg = readl(xhci_regs + XHCI_HCSPARAMS1);
187 + port_num = HCS_MAX_PORTS(reg);
188 +
189 + for (i = 1; i <= port_num; i++) {
190 + offset = op_regs_base + XHCI_PORTSC_BASE + 0x10*(i-1);
191 + reg = readl(xhci_regs + offset);
192 + reg &= ~PORT_POWER;
193 + writel(reg, xhci_regs + offset);
194 + }
195 +
196 + iounmap(xhci_regs);
197 + } else
198 + dev_err(dwc->dev, "xhci base reg invalid\n");
199 +}
200 +
201 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
202 {
203 u32 reg;
204 @@ -111,6 +146,15 @@ static void dwc3_set_prtcap(struct dwc3
205 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
206 reg |= DWC3_GCTL_PRTCAPDIR(mode);
207 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
208 +
209 + /*
210 + * We have to power off all Root hub ports immediately after DWC3 set
211 + * to host mode to avoid VBUS glitch happen when xhci get reset later.
212 + */
213 + if (dwc->host_vbus_glitches) {
214 + if (mode == DWC3_GCTL_PRTCAP_HOST)
215 + dwc3_power_off_all_roothub_ports(dwc);
216 + }
217 }
218
219 static void __dwc3_set_mode(struct work_struct *work)
220 @@ -766,6 +810,96 @@ static void dwc3_core_setup_global_contr
221 static int dwc3_core_get_phy(struct dwc3 *dwc);
222 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
223
224 +/* set global soc bus configuration registers */
225 +static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
226 +{
227 + struct device *dev = dwc->dev;
228 + u32 *vals;
229 + u32 cfg;
230 + int ntype;
231 + int ret;
232 + int i;
233 +
234 + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
235 +
236 + /*
237 + * Handle property "snps,incr-burst-type-adjustment".
238 + * Get the number of value from this property:
239 + * result <= 0, means this property is not supported.
240 + * result = 1, means INCRx burst mode supported.
241 + * result > 1, means undefined length burst mode supported.
242 + */
243 + ntype = device_property_read_u32_array(dev,
244 + "snps,incr-burst-type-adjustment", NULL, 0);
245 + if (ntype > 0) {
246 + vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
247 + if (!vals) {
248 + dev_err(dev, "Error to get memory\n");
249 + return;
250 + }
251 + /* Get INCR burst type, and parse it */
252 + ret = device_property_read_u32_array(dev,
253 + "snps,incr-burst-type-adjustment", vals, ntype);
254 + if (ret) {
255 + dev_err(dev, "Error to get property\n");
256 + return;
257 + }
258 + *(dwc->incrx_type + 1) = vals[0];
259 + if (ntype > 1) {
260 + *dwc->incrx_type = 1;
261 + for (i = 1; i < ntype; i++) {
262 + if (vals[i] > *(dwc->incrx_type + 1))
263 + *(dwc->incrx_type + 1) = vals[i];
264 + }
265 + } else
266 + *dwc->incrx_type = 0;
267 +
268 + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
269 + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
270 + if (*dwc->incrx_type)
271 + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
272 + switch (*(dwc->incrx_type + 1)) {
273 + case 256:
274 + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
275 + break;
276 + case 128:
277 + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
278 + break;
279 + case 64:
280 + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
281 + break;
282 + case 32:
283 + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
284 + break;
285 + case 16:
286 + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
287 + break;
288 + case 8:
289 + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
290 + break;
291 + case 4:
292 + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
293 + break;
294 + case 1:
295 + break;
296 + default:
297 + dev_err(dev, "Invalid property\n");
298 + break;
299 + }
300 + }
301 +
302 + /* Handle usb snooping */
303 + if (dwc->dma_coherent) {
304 + cfg &= ~DWC3_GSBUSCFG0_SNP_MASK;
305 + cfg |= (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATARD_SHIFT) |
306 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCRD_SHIFT) |
307 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATAWR_SHIFT) |
308 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCWR_SHIFT);
309 + }
310 +
311 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
312 +}
313 +
314 /**
315 * dwc3_core_init - Low-level initialization of DWC3 Core
316 * @dwc: Pointer to our controller context structure
317 @@ -828,6 +962,8 @@ static int dwc3_core_init(struct dwc3 *d
318 /* Adjust Frame Length */
319 dwc3_frame_length_adjustment(dwc);
320
321 + dwc3_set_soc_bus_cfg(dwc);
322 +
323 usb_phy_set_suspend(dwc->usb2_phy, 0);
324 usb_phy_set_suspend(dwc->usb3_phy, 0);
325 ret = phy_power_on(dwc->usb2_generic_phy);
326 @@ -871,6 +1007,22 @@ static int dwc3_core_init(struct dwc3 *d
327 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
328 }
329
330 + if (dwc->dr_mode == USB_DR_MODE_HOST ||
331 + dwc->dr_mode == USB_DR_MODE_OTG) {
332 + reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
333 +
334 + /*
335 + * Enable Auto retry Feature to make the controller operating in
336 + * Host mode on seeing transaction errors(CRC errors or internal
337 + * overrun scenerios) on IN transfers to reply to the device
338 + * with a non-terminating retry ACK (i.e, an ACK transcation
339 + * packet with Retry=1 & Nump != 0)
340 + */
341 + reg |= DWC3_GUCTL_HSTINAUTORETRY;
342 +
343 + dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
344 + }
345 +
346 return 0;
347
348 err4:
349 @@ -1074,6 +1226,8 @@ static void dwc3_get_properties(struct d
350 &hird_threshold);
351 dwc->usb3_lpm_capable = device_property_read_bool(dev,
352 "snps,usb3_lpm_capable");
353 + dwc->dma_coherent = device_property_read_bool(dev,
354 + "dma-coherent");
355
356 dwc->disable_scramble_quirk = device_property_read_bool(dev,
357 "snps,disable_scramble_quirk");
358 @@ -1106,8 +1260,16 @@ static void dwc3_get_properties(struct d
359 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
360 "snps,dis-tx-ipgap-linecheck-quirk");
361
362 + dwc->quirk_reverse_in_out = device_property_read_bool(dev,
363 + "snps,quirk_reverse_in_out");
364 + dwc->quirk_stop_transfer_in_block = device_property_read_bool(dev,
365 + "snps,quirk_stop_transfer_in_block");
366 + dwc->quirk_stop_ep_in_u1 = device_property_read_bool(dev,
367 + "snps,quirk_stop_ep_in_u1");
368 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
369 "snps,tx_de_emphasis_quirk");
370 + dwc->disable_devinit_u1u2_quirk = device_property_read_bool(dev,
371 + "snps,disable_devinit_u1u2");
372 device_property_read_u8(dev, "snps,tx_de_emphasis",
373 &tx_de_emphasis);
374 device_property_read_string(dev, "snps,hsphy_interface",
375 @@ -1115,6 +1277,9 @@ static void dwc3_get_properties(struct d
376 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
377 &dwc->fladj);
378
379 + dwc->host_vbus_glitches = device_property_read_bool(dev,
380 + "snps,host-vbus-glitches");
381 +
382 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
383 dwc->tx_de_emphasis = tx_de_emphasis;
384
385 @@ -1365,12 +1530,14 @@ static int dwc3_resume_common(struct dwc
386
387 switch (dwc->dr_mode) {
388 case USB_DR_MODE_PERIPHERAL:
389 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
390 case USB_DR_MODE_OTG:
391 spin_lock_irqsave(&dwc->lock, flags);
392 dwc3_gadget_resume(dwc);
393 spin_unlock_irqrestore(&dwc->lock, flags);
394 /* FALLTHROUGH */
395 case USB_DR_MODE_HOST:
396 + dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
397 default:
398 /* do nothing */
399 break;
400 --- a/drivers/usb/dwc3/core.h
401 +++ b/drivers/usb/dwc3/core.h
402 @@ -161,6 +161,32 @@
403
404 /* Bit fields */
405
406 +/* Global SoC Bus Configuration Register 0 */
407 +#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */
408 +#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */
409 +#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */
410 +#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */
411 +#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
412 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
413 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
414 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
415 +#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000
416 +#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11)
417 +#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10)
418 +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
419 +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
420 +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
421 +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
422 +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
423 +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
424 +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
425 +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
426 +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
427 +
428 +/* Global SoC Bus Configuration Register 1 */
429 +#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */
430 +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00
431 +
432 /* Global Debug Queue/FIFO Space Available Register */
433 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
434 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
435 @@ -205,6 +231,9 @@
436 #define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
437 #define DWC3_GCTL_DSBLCLKGTNG BIT(0)
438
439 +/* Global User Control Register */
440 +#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
441 +
442 /* Global User Control 1 Register */
443 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
444 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
445 @@ -477,6 +506,14 @@
446 #define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
447 #define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
448
449 +/* Partial XHCI Register and Bit fields for quirk */
450 +#define XHCI_HCSPARAMS1 0x4
451 +#define XHCI_PORTSC_BASE 0x400
452 +#define PORT_POWER (1 << 9)
453 +#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
454 +#define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
455 +#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
456 +
457 /* Structures */
458
459 struct dwc3_trb;
460 @@ -788,6 +825,7 @@ struct dwc3_scratchpad_array {
461 * @regs: base address for our registers
462 * @regs_size: address space size
463 * @fladj: frame length adjustment
464 + * @incrx_type: INCR burst type adjustment
465 * @irq_gadget: peripheral controller's IRQ number
466 * @nr_scratch: number of scratch buffers
467 * @u1u2: only used on revisions <1.83a for workaround
468 @@ -843,6 +881,7 @@ struct dwc3_scratchpad_array {
469 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
470 * @three_stage_setup: set if we perform a three phase setup
471 * @usb3_lpm_capable: set if hadrware supports Link Power Management
472 + * @dma_coherent: set if hadrware supports DMA snoop
473 * @disable_scramble_quirk: set if we enable the disable scramble quirk
474 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
475 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
476 @@ -869,6 +908,13 @@ struct dwc3_scratchpad_array {
477 * 1 - -3.5dB de-emphasis
478 * 2 - No de-emphasis
479 * 3 - Reserved
480 + * @disable_devinit_u1u2_quirk: disable device-initiated U1/U2 request.
481 + * @quirk_reverse_in_out: prevent tx fifo reverse the data direction
482 + * @quirk_stop_transfer_in_block: prevent block transmission from being
483 + * interrupted
484 + * @quirk_stop_ep_in_u1: replace stop commad with disable slot command
485 + * @host-vbus-glitches: set to avoid vbus glitch during
486 + * xhci reset.
487 * @imod_interval: set the interrupt moderation interval in 250ns
488 * increments or 0 to disable.
489 */
490 @@ -921,6 +967,12 @@ struct dwc3 {
491 enum usb_phy_interface hsphy_mode;
492
493 u32 fladj;
494 + /*
495 + * For INCR burst type.
496 + * First field: for undefined length INCR burst type enable.
497 + * Second field: for INCRx burst type enable
498 + */
499 + u32 incrx_type[2];
500 u32 irq_gadget;
501 u32 nr_scratch;
502 u32 u1u2;
503 @@ -1005,6 +1057,7 @@ struct dwc3 {
504 unsigned setup_packet_pending:1;
505 unsigned three_stage_setup:1;
506 unsigned usb3_lpm_capable:1;
507 + unsigned dma_coherent:1;
508
509 unsigned disable_scramble_quirk:1;
510 unsigned u2exit_lfps_quirk:1;
511 @@ -1024,6 +1077,11 @@ struct dwc3 {
512
513 unsigned tx_de_emphasis_quirk:1;
514 unsigned tx_de_emphasis:2;
515 + unsigned disable_devinit_u1u2_quirk:1;
516 + unsigned quirk_reverse_in_out:1;
517 + unsigned quirk_stop_transfer_in_block:1;
518 + unsigned quirk_stop_ep_in_u1:1;
519 + unsigned host_vbus_glitches:1;
520
521 u16 imod_interval;
522 };
523 --- a/drivers/usb/dwc3/ep0.c
524 +++ b/drivers/usb/dwc3/ep0.c
525 @@ -391,7 +391,7 @@ static int dwc3_ep0_handle_u1(struct dwc
526 return -EINVAL;
527
528 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
529 - if (set)
530 + if (set && !dwc->disable_devinit_u1u2_quirk)
531 reg |= DWC3_DCTL_INITU1ENA;
532 else
533 reg &= ~DWC3_DCTL_INITU1ENA;
534 @@ -413,7 +413,7 @@ static int dwc3_ep0_handle_u2(struct dwc
535 return -EINVAL;
536
537 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
538 - if (set)
539 + if (set && !dwc->disable_devinit_u1u2_quirk)
540 reg |= DWC3_DCTL_INITU2ENA;
541 else
542 reg &= ~DWC3_DCTL_INITU2ENA;
543 --- a/drivers/usb/dwc3/gadget.c
544 +++ b/drivers/usb/dwc3/gadget.c
545 @@ -3210,6 +3210,7 @@ int dwc3_gadget_init(struct dwc3 *dwc)
546 {
547 int ret;
548 int irq;
549 + u32 reg;
550
551 irq = dwc3_gadget_get_irq(dwc);
552 if (irq < 0) {
553 @@ -3288,6 +3289,12 @@ int dwc3_gadget_init(struct dwc3 *dwc)
554
555 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
556
557 + if (dwc->disable_devinit_u1u2_quirk) {
558 + reg = dwc3_readl(dwc->regs, DWC3_DCTL);
559 + reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
560 + dwc3_writel(dwc->regs, DWC3_DCTL, reg);
561 + }
562 +
563 return 0;
564
565 err4:
566 --- a/drivers/usb/dwc3/host.c
567 +++ b/drivers/usb/dwc3/host.c
568 @@ -98,6 +98,15 @@ int dwc3_host_init(struct dwc3 *dwc)
569
570 memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
571
572 + if (dwc->quirk_reverse_in_out)
573 + props[prop_idx++].name = "quirk-reverse-in-out";
574 +
575 + if (dwc->quirk_stop_transfer_in_block)
576 + props[prop_idx++].name = "quirk-stop-transfer-in-block";
577 +
578 + if (dwc->quirk_stop_ep_in_u1)
579 + props[prop_idx++].name = "quirk-stop-ep-in-u1";
580 +
581 if (dwc->usb3_lpm_capable)
582 props[prop_idx++].name = "usb3-lpm-capable";
583
584 --- a/drivers/usb/gadget/udc/fsl_udc_core.c
585 +++ b/drivers/usb/gadget/udc/fsl_udc_core.c
586 @@ -198,7 +198,11 @@ __acquires(ep->udc->lock)
587
588 spin_unlock(&ep->udc->lock);
589
590 - usb_gadget_giveback_request(&ep->ep, &req->req);
591 + /* this complete() should a func implemented by gadget layer,
592 + * eg fsg->bulk_in_complete()
593 + */
594 + if (req->req.complete)
595 + usb_gadget_giveback_request(&ep->ep, &req->req);
596
597 spin_lock(&ep->udc->lock);
598 ep->stopped = stopped;
599 @@ -245,10 +249,10 @@ static int dr_controller_setup(struct fs
600 if (udc->pdata->have_sysif_regs) {
601 if (udc->pdata->controller_ver) {
602 /* controller version 1.6 or above */
603 - ctrl = __raw_readl(&usb_sys_regs->control);
604 + ctrl = ioread32be(&usb_sys_regs->control);
605 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
606 ctrl |= USB_CTRL_USB_EN;
607 - __raw_writel(ctrl, &usb_sys_regs->control);
608 + iowrite32be(ctrl, &usb_sys_regs->control);
609 }
610 }
611 portctrl |= PORTSCX_PTS_ULPI;
612 @@ -257,13 +261,14 @@ static int dr_controller_setup(struct fs
613 portctrl |= PORTSCX_PTW_16BIT;
614 /* fall through */
615 case FSL_USB2_PHY_UTMI:
616 + case FSL_USB2_PHY_UTMI_DUAL:
617 if (udc->pdata->have_sysif_regs) {
618 if (udc->pdata->controller_ver) {
619 /* controller version 1.6 or above */
620 - ctrl = __raw_readl(&usb_sys_regs->control);
621 + ctrl = ioread32be(&usb_sys_regs->control);
622 ctrl |= (USB_CTRL_UTMI_PHY_EN |
623 USB_CTRL_USB_EN);
624 - __raw_writel(ctrl, &usb_sys_regs->control);
625 + iowrite32be(ctrl, &usb_sys_regs->control);
626 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
627 PHY CLK to become stable - 10ms*/
628 }
629 @@ -329,22 +334,22 @@ static int dr_controller_setup(struct fs
630 /* Config control enable i/o output, cpu endian register */
631 #ifndef CONFIG_ARCH_MXC
632 if (udc->pdata->have_sysif_regs) {
633 - ctrl = __raw_readl(&usb_sys_regs->control);
634 + ctrl = ioread32be(&usb_sys_regs->control);
635 ctrl |= USB_CTRL_IOENB;
636 - __raw_writel(ctrl, &usb_sys_regs->control);
637 + iowrite32be(ctrl, &usb_sys_regs->control);
638 }
639 #endif
640
641 -#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
642 +#if !defined(CONFIG_NOT_COHERENT_CACHE)
643 /* Turn on cache snooping hardware, since some PowerPC platforms
644 * wholly rely on hardware to deal with cache coherent. */
645
646 if (udc->pdata->have_sysif_regs) {
647 /* Setup Snooping for all the 4GB space */
648 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
649 - __raw_writel(tmp, &usb_sys_regs->snoop1);
650 + iowrite32be(tmp, &usb_sys_regs->snoop1);
651 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
652 - __raw_writel(tmp, &usb_sys_regs->snoop2);
653 + iowrite32be(tmp, &usb_sys_regs->snoop2);
654 }
655 #endif
656
657 @@ -1056,7 +1061,7 @@ static int fsl_ep_fifo_status(struct usb
658 struct ep_queue_head *qh;
659
660 ep = container_of(_ep, struct fsl_ep, ep);
661 - if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
662 + if (!_ep || !ep->ep.desc || (ep_index(ep) == 0))
663 return -ENODEV;
664
665 udc = (struct fsl_udc *)ep->udc;
666 @@ -1598,14 +1603,13 @@ static int process_ep_req(struct fsl_udc
667 struct fsl_req *curr_req)
668 {
669 struct ep_td_struct *curr_td;
670 - int td_complete, actual, remaining_length, j, tmp;
671 + int actual, remaining_length, j, tmp;
672 int status = 0;
673 int errors = 0;
674 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
675 int direction = pipe % 2;
676
677 curr_td = curr_req->head;
678 - td_complete = 0;
679 actual = curr_req->req.length;
680
681 for (j = 0; j < curr_req->dtd_count; j++) {
682 @@ -1650,11 +1654,9 @@ static int process_ep_req(struct fsl_udc
683 status = -EPROTO;
684 break;
685 } else {
686 - td_complete++;
687 break;
688 }
689 } else {
690 - td_complete++;
691 VDBG("dTD transmitted successful");
692 }
693
694 @@ -1697,7 +1699,7 @@ static void dtd_complete_irq(struct fsl_
695 curr_ep = get_ep_by_pipe(udc, i);
696
697 /* If the ep is configured */
698 - if (!curr_ep->ep.name) {
699 + if (strncmp(curr_ep->name, "ep", 2)) {
700 WARNING("Invalid EP?");
701 continue;
702 }
703 @@ -2419,10 +2421,12 @@ static int fsl_udc_probe(struct platform
704 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
705 #endif
706
707 +#ifdef CONFIG_ARCH_MXC
708 /* Initialize USB clocks */
709 ret = fsl_udc_clk_init(pdev);
710 if (ret < 0)
711 goto err_iounmap_noclk;
712 +#endif
713
714 /* Read Device Controller Capability Parameters register */
715 dccparams = fsl_readl(&dr_regs->dccparams);
716 @@ -2462,9 +2466,11 @@ static int fsl_udc_probe(struct platform
717 dr_controller_setup(udc_controller);
718 }
719
720 +#ifdef CONFIG_ARCH_MXC
721 ret = fsl_udc_clk_finalize(pdev);
722 if (ret)
723 goto err_free_irq;
724 +#endif
725
726 /* Setup gadget structure */
727 udc_controller->gadget.ops = &fsl_gadget_ops;
728 @@ -2477,6 +2483,7 @@ static int fsl_udc_probe(struct platform
729 /* Setup gadget.dev and register with kernel */
730 dev_set_name(&udc_controller->gadget.dev, "gadget");
731 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
732 + set_dma_ops(&udc_controller->gadget.dev, pdev->dev.dma_ops);
733
734 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
735 udc_controller->gadget.is_otg = 1;
736 @@ -2528,7 +2535,9 @@ err_free_irq:
737 err_iounmap:
738 if (pdata->exit)
739 pdata->exit(pdev);
740 +#ifdef CONFIG_ARCH_MXC
741 fsl_udc_clk_release();
742 +#endif
743 err_iounmap_noclk:
744 iounmap(dr_regs);
745 err_release_mem_region:
746 @@ -2556,8 +2565,9 @@ static int fsl_udc_remove(struct platfor
747 udc_controller->done = &done;
748 usb_del_gadget_udc(&udc_controller->gadget);
749
750 +#ifdef CONFIG_ARCH_MXC
751 fsl_udc_clk_release();
752 -
753 +#endif
754 /* DR has been stopped in usb_gadget_unregister_driver() */
755 remove_proc_file();
756
757 @@ -2569,7 +2579,7 @@ static int fsl_udc_remove(struct platfor
758 dma_pool_destroy(udc_controller->td_pool);
759 free_irq(udc_controller->irq, udc_controller);
760 iounmap(dr_regs);
761 - if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
762 + if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
763 release_mem_region(res->start, resource_size(res));
764
765 /* free udc --wait for the release() finished */
766 --- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
767 +++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
768 @@ -20,6 +20,10 @@
769 #define USB_MAX_CTRL_PAYLOAD 64
770 #define USB_DR_SYS_OFFSET 0x400
771
772 +#ifdef CONFIG_SOC_LS1021A
773 +#undef CONFIG_ARCH_MXC
774 +#endif
775 +
776 /* USB DR device mode registers (Little Endian) */
777 struct usb_dr_device {
778 /* Capability register */
779 @@ -597,18 +601,6 @@ struct platform_device;
780 int fsl_udc_clk_init(struct platform_device *pdev);
781 int fsl_udc_clk_finalize(struct platform_device *pdev);
782 void fsl_udc_clk_release(void);
783 -#else
784 -static inline int fsl_udc_clk_init(struct platform_device *pdev)
785 -{
786 - return 0;
787 -}
788 -static inline int fsl_udc_clk_finalize(struct platform_device *pdev)
789 -{
790 - return 0;
791 -}
792 -static inline void fsl_udc_clk_release(void)
793 -{
794 -}
795 #endif
796
797 #endif
798 --- a/drivers/usb/host/Kconfig
799 +++ b/drivers/usb/host/Kconfig
800 @@ -165,7 +165,7 @@ config XPS_USB_HCD_XILINX
801
802 config USB_EHCI_FSL
803 tristate "Support for Freescale PPC on-chip EHCI USB controller"
804 - depends on FSL_SOC
805 + depends on USB_EHCI_HCD
806 select USB_EHCI_ROOT_HUB_TT
807 ---help---
808 Variation of ARC USB block used in some Freescale chips.
809 --- a/drivers/usb/host/ehci-fsl.c
810 +++ b/drivers/usb/host/ehci-fsl.c
811 @@ -36,15 +36,126 @@
812 #include <linux/platform_device.h>
813 #include <linux/fsl_devices.h>
814 #include <linux/of_platform.h>
815 +#include <linux/io.h>
816 +
817 +#ifdef CONFIG_PM
818 +#include <linux/suspend.h>
819 +#endif
820
821 #include "ehci.h"
822 #include "ehci-fsl.h"
823
824 +#define FSL_USB_PHY_ADDR 0xffe214000
825 +
826 +struct ccsr_usb_port_ctrl {
827 + u32 ctrl;
828 + u32 drvvbuscfg;
829 + u32 pwrfltcfg;
830 + u32 sts;
831 + u8 res_14[0xc];
832 + u32 bistcfg;
833 + u32 biststs;
834 + u32 abistcfg;
835 + u32 abiststs;
836 + u8 res_30[0x10];
837 + u32 xcvrprg;
838 + u32 anaprg;
839 + u32 anadrv;
840 + u32 anasts;
841 +};
842 +
843 +struct ccsr_usb_phy {
844 + u32 id;
845 + struct ccsr_usb_port_ctrl port1;
846 + u8 res_50[0xc];
847 + u32 tvr;
848 + u32 pllprg[4];
849 + u8 res_70[0x4];
850 + u32 anaccfg;
851 + u32 dbg;
852 + u8 res_7c[0x4];
853 + struct ccsr_usb_port_ctrl port2;
854 + u8 res_dc[0x334];
855 +};
856 +
857 #define DRIVER_DESC "Freescale EHCI Host controller driver"
858 #define DRV_NAME "ehci-fsl"
859
860 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
861
862 +struct ehci_fsl {
863 + struct ehci_hcd ehci;
864 +
865 +#ifdef CONFIG_PM
866 +struct ehci_regs saved_regs;
867 +struct ccsr_usb_phy saved_phy_regs;
868 +/* Saved USB PHY settings, need to restore after deep sleep. */
869 +u32 usb_ctrl;
870 +#endif
871 + /*
872 + * store current hcd state for otg;
873 + * have_hcd is true when host drv al already part of otg framework,
874 + * otherwise false;
875 + * hcd_add is true when otg framework wants to add host
876 + * drv as part of otg;flase when it wants to remove it
877 + */
878 +unsigned have_hcd:1;
879 +unsigned hcd_add:1;
880 +};
881 +
882 +static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
883 +{
884 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
885 +
886 +return container_of(ehci, struct ehci_fsl, ehci);
887 +}
888 +
889 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
890 +static void do_change_hcd(struct work_struct *work)
891 +{
892 + struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
893 + change_hcd_work);
894 + struct usb_hcd *hcd = ehci_to_hcd(ehci);
895 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
896 + void __iomem *non_ehci = hcd->regs;
897 + int retval;
898 +
899 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
900 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
901 + /* host, gadget and otg share same int line */
902 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
903 + if (retval == 0)
904 + ehci_fsl->have_hcd = 1;
905 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
906 + usb_remove_hcd(hcd);
907 + ehci_fsl->have_hcd = 0;
908 + }
909 +}
910 +#endif
911 +
912 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
913 +static void do_change_hcd(struct work_struct *work)
914 +{
915 + struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
916 + change_hcd_work);
917 + struct usb_hcd *hcd = ehci_to_hcd(ehci);
918 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
919 + void __iomem *non_ehci = hcd->regs;
920 + int retval;
921 +
922 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
923 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
924 + /* host, gadget and otg share same int line */
925 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
926 + if (retval == 0)
927 + ehci_fsl->have_hcd = 1;
928 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
929 + usb_remove_hcd(hcd);
930 + ehci_fsl->have_hcd = 0;
931 + }
932 +}
933 +#endif
934 +
935 /* configure so an HC device and id are always provided */
936 /* always called with process context; sleeping is OK */
937
938 @@ -131,6 +242,12 @@ static int fsl_ehci_drv_probe(struct pla
939 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
940 CONTROL_REGISTER_W1C_MASK, 0x4);
941
942 + /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
943 + if (pdata->controller_ver == FSL_USB_VER_2_5 &&
944 + pdata->phy_mode == FSL_USB2_PHY_ULPI)
945 + iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
946 +
947 +
948 /*
949 * Enable UTMI phy and program PTS field in UTMI mode before asserting
950 * controller reset for USB Controller version 2.5
951 @@ -143,16 +260,20 @@ static int fsl_ehci_drv_probe(struct pla
952
953 /* Don't need to set host mode here. It will be done by tdi_reset() */
954
955 - retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
956 + retval = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_NO_SUSPEND);
957 if (retval != 0)
958 goto err2;
959 device_wakeup_enable(hcd->self.controller);
960
961 -#ifdef CONFIG_USB_OTG
962 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
963 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
964 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
965 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
966
967 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
968 +
969 + INIT_WORK(&ehci->change_hcd_work, do_change_hcd);
970 +
971 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
972 hcd, ehci, hcd->usb_phy);
973
974 @@ -168,6 +289,11 @@ static int fsl_ehci_drv_probe(struct pla
975 retval = -ENODEV;
976 goto err2;
977 }
978 +
979 + ehci_fsl->have_hcd = 1;
980 + } else {
981 + dev_err(&pdev->dev, "wrong operating mode\n");
982 + return -ENODEV;
983 }
984 #endif
985 return retval;
986 @@ -181,6 +307,17 @@ static int fsl_ehci_drv_probe(struct pla
987 return retval;
988 }
989
990 +static bool usb_phy_clk_valid(struct usb_hcd *hcd)
991 +{
992 + void __iomem *non_ehci = hcd->regs;
993 + bool ret = true;
994 +
995 + if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
996 + ret = false;
997 +
998 + return ret;
999 +}
1000 +
1001 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
1002 enum fsl_usb2_phy_modes phy_mode,
1003 unsigned int port_offset)
1004 @@ -219,6 +356,21 @@ static int ehci_fsl_setup_phy(struct usb
1005 /* fall through */
1006 case FSL_USB2_PHY_UTMI:
1007 case FSL_USB2_PHY_UTMI_DUAL:
1008 + if (pdata->has_fsl_erratum_a006918) {
1009 + pr_warn("fsl-ehci: USB PHY clock invalid\n");
1010 + return -EINVAL;
1011 + }
1012 +
1013 + /* PHY_CLK_VALID bit is de-featured from all controller
1014 + * versions below 2.4 and is to be checked only for
1015 + * internal UTMI phy
1016 + */
1017 + if (pdata->controller_ver > FSL_USB_VER_2_4 &&
1018 + pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
1019 + pr_err("fsl-ehci: USB PHY clock invalid\n");
1020 + return -EINVAL;
1021 + }
1022 +
1023 if (pdata->have_sysif_regs && pdata->controller_ver) {
1024 /* controller version 1.6 or above */
1025 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
1026 @@ -295,14 +447,9 @@ static int ehci_fsl_usb_setup(struct ehc
1027 return -EINVAL;
1028
1029 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
1030 - unsigned int chip, rev, svr;
1031 -
1032 - svr = mfspr(SPRN_SVR);
1033 - chip = svr >> 16;
1034 - rev = (svr >> 4) & 0xf;
1035
1036 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
1037 - if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
1038 + if (pdata->has_fsl_erratum_14 == 1)
1039 ehci->has_fsl_port_bug = 1;
1040
1041 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
1042 @@ -382,16 +529,56 @@ static int ehci_fsl_setup(struct usb_hcd
1043 return retval;
1044 }
1045
1046 -struct ehci_fsl {
1047 - struct ehci_hcd ehci;
1048 -
1049 #ifdef CONFIG_PM
1050 - /* Saved USB PHY settings, need to restore after deep sleep. */
1051 - u32 usb_ctrl;
1052 -#endif
1053 -};
1054 +void __iomem *phy_reg;
1055
1056 -#ifdef CONFIG_PM
1057 +#ifdef CONFIG_PPC
1058 +/* save usb registers */
1059 +static int ehci_fsl_save_context(struct usb_hcd *hcd)
1060 +{
1061 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1062 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1063 + void __iomem *non_ehci = hcd->regs;
1064 + struct device *dev = hcd->self.controller;
1065 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1066 +
1067 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1068 + phy_reg = ioremap(FSL_USB_PHY_ADDR,
1069 + sizeof(struct ccsr_usb_phy));
1070 + _memcpy_fromio((void *)&ehci_fsl->saved_phy_regs, phy_reg,
1071 + sizeof(struct ccsr_usb_phy));
1072 + }
1073 +
1074 + _memcpy_fromio((void *)&ehci_fsl->saved_regs, ehci->regs,
1075 + sizeof(struct ehci_regs));
1076 + ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
1077 +
1078 + return 0;
1079 +}
1080 +
1081 +/*Restore usb registers */
1082 +static int ehci_fsl_restore_context(struct usb_hcd *hcd)
1083 +{
1084 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1085 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1086 + void __iomem *non_ehci = hcd->regs;
1087 + struct device *dev = hcd->self.controller;
1088 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1089 +
1090 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1091 + if (phy_reg)
1092 + _memcpy_toio(phy_reg,
1093 + (void *)&ehci_fsl->saved_phy_regs,
1094 + sizeof(struct ccsr_usb_phy));
1095 + }
1096 +
1097 + _memcpy_toio(ehci->regs, (void *)&ehci_fsl->saved_regs,
1098 + sizeof(struct ehci_regs));
1099 + iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
1100 +
1101 + return 0;
1102 +}
1103 +#endif
1104
1105 #ifdef CONFIG_PPC_MPC512x
1106 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
1107 @@ -538,26 +725,45 @@ static inline int ehci_fsl_mpc512x_drv_r
1108 }
1109 #endif /* CONFIG_PPC_MPC512x */
1110
1111 -static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
1112 -{
1113 - struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1114 -
1115 - return container_of(ehci, struct ehci_fsl, ehci);
1116 -}
1117 -
1118 static int ehci_fsl_drv_suspend(struct device *dev)
1119 {
1120 struct usb_hcd *hcd = dev_get_drvdata(dev);
1121 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1122 void __iomem *non_ehci = hcd->regs;
1123 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1124 + struct usb_bus host = hcd->self;
1125 +#endif
1126 +
1127 +#ifdef CONFIG_PPC
1128 + suspend_state_t pm_state;
1129 + /* FIXME:Need to port fsl_pm.h before enable below code. */
1130 + /*pm_state = pm_suspend_state();*/
1131 + pm_state = PM_SUSPEND_MEM;
1132 +
1133 +if (pm_state == PM_SUSPEND_MEM)
1134 + ehci_fsl_save_context(hcd);
1135 +#endif
1136
1137 if (of_device_is_compatible(dev->parent->of_node,
1138 "fsl,mpc5121-usb2-dr")) {
1139 return ehci_fsl_mpc512x_drv_suspend(dev);
1140 }
1141
1142 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1143 + if (host.is_otg) {
1144 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1145 +
1146 + /* remove hcd */
1147 + ehci_fsl->hcd_add = 0;
1148 + schedule_work(&ehci->change_hcd_work);
1149 + host.is_otg = 0;
1150 + return 0;
1151 + }
1152 +#endif
1153 +
1154 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
1155 device_may_wakeup(dev));
1156 +
1157 if (!fsl_deep_sleep())
1158 return 0;
1159
1160 @@ -571,12 +777,36 @@ static int ehci_fsl_drv_resume(struct de
1161 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1162 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1163 void __iomem *non_ehci = hcd->regs;
1164 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1165 + struct usb_bus host = hcd->self;
1166 +#endif
1167 +
1168 +#ifdef CONFIG_PPC
1169 + suspend_state_t pm_state;
1170 + /* FIXME:Need to port fsl_pm.h before enable below code.*/
1171 + /* pm_state = pm_suspend_state(); */
1172 + pm_state = PM_SUSPEND_MEM;
1173 +
1174 + if (pm_state == PM_SUSPEND_MEM)
1175 + ehci_fsl_restore_context(hcd);
1176 +#endif
1177
1178 if (of_device_is_compatible(dev->parent->of_node,
1179 "fsl,mpc5121-usb2-dr")) {
1180 return ehci_fsl_mpc512x_drv_resume(dev);
1181 }
1182
1183 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1184 + if (host.is_otg) {
1185 + /* add hcd */
1186 + ehci_fsl->hcd_add = 1;
1187 + schedule_work(&ehci->change_hcd_work);
1188 + usb_hcd_resume_root_hub(hcd);
1189 + host.is_otg = 0;
1190 + return 0;
1191 + }
1192 +#endif
1193 +
1194 ehci_prepare_ports_for_controller_resume(ehci);
1195 if (!fsl_deep_sleep())
1196 return 0;
1197 --- a/drivers/usb/host/ehci-fsl.h
1198 +++ b/drivers/usb/host/ehci-fsl.h
1199 @@ -63,4 +63,7 @@
1200 #define UTMI_PHY_EN (1<<9)
1201 #define ULPI_PHY_CLK_SEL (1<<10)
1202 #define PHY_CLK_VALID (1<<17)
1203 +
1204 +/* Retry count for checking UTMI PHY CLK validity */
1205 +#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
1206 #endif /* _EHCI_FSL_H */
1207 --- a/drivers/usb/host/ehci-hub.c
1208 +++ b/drivers/usb/host/ehci-hub.c
1209 @@ -305,6 +305,8 @@ static int ehci_bus_suspend (struct usb_
1210 USB_PORT_STAT_HIGH_SPEED)
1211 fs_idle_delay = true;
1212 ehci_writel(ehci, t2, reg);
1213 + if (ehci_has_fsl_susp_errata(ehci))
1214 + usleep_range(10000, 20000);
1215 changed = 1;
1216 }
1217 }
1218 --- a/drivers/usb/host/ehci.h
1219 +++ b/drivers/usb/host/ehci.h
1220 @@ -180,6 +180,9 @@ struct ehci_hcd { /* one per controlle
1221 unsigned periodic_count; /* periodic activity count */
1222 unsigned uframe_periodic_max; /* max periodic time per uframe */
1223
1224 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1225 + struct work_struct change_hcd_work;
1226 +#endif
1227
1228 /* list of itds & sitds completed while now_frame was still active */
1229 struct list_head cached_itd_list;
1230 --- a/drivers/usb/host/fsl-mph-dr-of.c
1231 +++ b/drivers/usb/host/fsl-mph-dr-of.c
1232 @@ -229,6 +229,17 @@ static int fsl_usb2_mph_dr_of_probe(stru
1233 pdata->has_fsl_erratum_a005697 =
1234 of_property_read_bool(np, "fsl,usb_erratum-a005697");
1235
1236 + if (of_get_property(np, "fsl,erratum_a006918", NULL))
1237 + pdata->has_fsl_erratum_a006918 = 1;
1238 + else
1239 + pdata->has_fsl_erratum_a006918 = 0;
1240 +
1241 + if (of_get_property(np, "fsl,usb_erratum_14", NULL))
1242 + pdata->has_fsl_erratum_14 = 1;
1243 + else
1244 + pdata->has_fsl_erratum_14 = 0;
1245 +
1246 +
1247 /*
1248 * Determine whether phy_clk_valid needs to be checked
1249 * by reading property in device tree
1250 --- a/drivers/usb/host/xhci-hub.c
1251 +++ b/drivers/usb/host/xhci-hub.c
1252 @@ -689,12 +689,34 @@ void xhci_set_link_state(struct xhci_hcd
1253 int port_id, u32 link_state)
1254 {
1255 u32 temp;
1256 + u32 portpmsc_u2_backup = 0;
1257 +
1258 + /* Backup U2 timeout info before initiating U3 entry erratum A-010131 */
1259 + if (xhci->shared_hcd->speed >= HCD_USB3 &&
1260 + link_state == USB_SS_PORT_LS_U3 &&
1261 + (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
1262 + portpmsc_u2_backup = readl(port_array[port_id] + PORTPMSC);
1263 + portpmsc_u2_backup &= PORT_U2_TIMEOUT_MASK;
1264 + temp = readl(port_array[port_id] + PORTPMSC);
1265 + temp |= PORT_U2_TIMEOUT_MASK;
1266 + writel(temp, port_array[port_id] + PORTPMSC);
1267 + }
1268
1269 temp = readl(port_array[port_id]);
1270 temp = xhci_port_state_to_neutral(temp);
1271 temp &= ~PORT_PLS_MASK;
1272 temp |= PORT_LINK_STROBE | link_state;
1273 writel(temp, port_array[port_id]);
1274 +
1275 + /* Restore U2 timeout info after U3 entry complete */
1276 + if (xhci->shared_hcd->speed >= HCD_USB3 &&
1277 + link_state == USB_SS_PORT_LS_U3 &&
1278 + (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
1279 + temp = readl(port_array[port_id] + PORTPMSC);
1280 + temp &= ~PORT_U2_TIMEOUT_MASK;
1281 + temp |= portpmsc_u2_backup;
1282 + writel(temp, port_array[port_id] + PORTPMSC);
1283 + }
1284 }
1285
1286 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
1287 --- a/drivers/usb/host/xhci-plat.c
1288 +++ b/drivers/usb/host/xhci-plat.c
1289 @@ -263,8 +263,22 @@ static int xhci_plat_probe(struct platfo
1290 goto disable_clk;
1291 }
1292
1293 - if (device_property_read_bool(sysdev, "usb3-lpm-capable"))
1294 + if (device_property_read_bool(sysdev, "usb3-lpm-capable")) {
1295 xhci->quirks |= XHCI_LPM_SUPPORT;
1296 + if (device_property_read_bool(sysdev,
1297 + "snps,dis-u1u2-when-u3-quirk"))
1298 + xhci->quirks |= XHCI_DIS_U1U2_WHEN_U3;
1299 + }
1300 +
1301 + if (device_property_read_bool(&pdev->dev, "quirk-reverse-in-out"))
1302 + xhci->quirks |= XHCI_REVERSE_IN_OUT;
1303 +
1304 + if (device_property_read_bool(&pdev->dev,
1305 + "quirk-stop-transfer-in-block"))
1306 + xhci->quirks |= XHCI_STOP_TRANSFER_IN_BLOCK;
1307 +
1308 + if (device_property_read_bool(&pdev->dev, "quirk-stop-ep-in-u1"))
1309 + xhci->quirks |= XHCI_STOP_EP_IN_U1;
1310
1311 if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
1312 xhci->quirks |= XHCI_BROKEN_PORT_PED;
1313 --- a/drivers/usb/host/xhci-ring.c
1314 +++ b/drivers/usb/host/xhci-ring.c
1315 @@ -1972,10 +1972,12 @@ static int finish_td(struct xhci_hcd *xh
1316 union xhci_trb *ep_trb, struct xhci_transfer_event *event,
1317 struct xhci_virt_ep *ep, int *status)
1318 {
1319 + struct xhci_dequeue_state deq_state;
1320 struct xhci_virt_device *xdev;
1321 struct xhci_ep_ctx *ep_ctx;
1322 struct xhci_ring *ep_ring;
1323 unsigned int slot_id;
1324 + u32 remaining;
1325 u32 trb_comp_code;
1326 int ep_index;
1327
1328 @@ -1998,14 +2000,30 @@ static int finish_td(struct xhci_hcd *xh
1329 if (trb_comp_code == COMP_STALL_ERROR ||
1330 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1331 trb_comp_code)) {
1332 - /* Issue a reset endpoint command to clear the host side
1333 - * halt, followed by a set dequeue command to move the
1334 - * dequeue pointer past the TD.
1335 - * The class driver clears the device side halt later.
1336 + /*erratum A-007463:
1337 + *After transaction error, controller switches control transfer
1338 + *data stage from IN to OUT direction.
1339 */
1340 - xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1341 + remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1342 + if (remaining && xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1343 + trb_comp_code) &&
1344 + (xhci->quirks & XHCI_REVERSE_IN_OUT)) {
1345 + memset(&deq_state, 0, sizeof(deq_state));
1346 + xhci_find_new_dequeue_state(xhci, slot_id,
1347 + ep_index, td->urb->stream_id, td, &deq_state);
1348 + xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
1349 + &deq_state);
1350 + xhci_ring_cmd_db(xhci);
1351 + } else {
1352 + /* Issue a reset endpoint command to clear the host side
1353 + * halt, followed by a set dequeue command to move the
1354 + * dequeue pointer past the TD.
1355 + * The class driver clears the device side halt later.
1356 + */
1357 + xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1358 ep_ring->stream_id, td, ep_trb,
1359 EP_HARD_RESET);
1360 + }
1361 } else {
1362 /* Update ring dequeue pointer */
1363 while (ep_ring->dequeue != td->last_trb)
1364 --- a/drivers/usb/host/xhci.c
1365 +++ b/drivers/usb/host/xhci.c
1366 @@ -1597,13 +1597,38 @@ static int xhci_urb_dequeue(struct usb_h
1367 ret = -ENOMEM;
1368 goto done;
1369 }
1370 - ep->ep_state |= EP_STOP_CMD_PENDING;
1371 - ep->stop_cmd_timer.expires = jiffies +
1372 + /*
1373 + *erratum A-009611: Issuing an End Transfer command on an IN
1374 + *endpoint. when a transfer is in progress on USB blocks the
1375 + *transmission.
1376 + *Workaround: Software must wait for all existing TRBs to
1377 + *complete before issuing End transfer command.
1378 + */
1379 + if ((ep_ring->enqueue == ep_ring->dequeue &&
1380 + (xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) ||
1381 + !(xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) {
1382 + ep->ep_state |= EP_STOP_CMD_PENDING;
1383 + ep->stop_cmd_timer.expires = jiffies +
1384 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1385 - add_timer(&ep->stop_cmd_timer);
1386 - xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1387 - ep_index, 0);
1388 - xhci_ring_cmd_db(xhci);
1389 + add_timer(&ep->stop_cmd_timer);
1390 + xhci_queue_stop_endpoint(xhci, command,
1391 + urb->dev->slot_id,
1392 + ep_index, 0);
1393 + xhci_ring_cmd_db(xhci);
1394 + }
1395 +
1396 + /*
1397 + *erratum A-009668: Stop Endpoint Command does not complete.
1398 + *Workaround: Instead of issuing a Stop Endpoint Command,
1399 + *issue a Disable Slot Command with the corresponding slot ID.
1400 + *Alternately, you can issue an Address Device Command with
1401 + *BSR=1
1402 + */
1403 + if ((urb->dev->speed <= USB_SPEED_HIGH) &&
1404 + (xhci->quirks & XHCI_STOP_EP_IN_U1)) {
1405 + xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
1406 + urb->dev->slot_id);
1407 + }
1408 }
1409 done:
1410 spin_unlock_irqrestore(&xhci->lock, flags);
1411 --- a/drivers/usb/host/xhci.h
1412 +++ b/drivers/usb/host/xhci.h
1413 @@ -1794,7 +1794,7 @@ struct xhci_hcd {
1414 #define XHCI_STATE_DYING (1 << 0)
1415 #define XHCI_STATE_HALTED (1 << 1)
1416 #define XHCI_STATE_REMOVING (1 << 2)
1417 - unsigned long long quirks;
1418 + unsigned long long quirks;
1419 #define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1420 #define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1421 #define XHCI_NEC_HOST BIT_ULL(2)
1422 @@ -1830,6 +1830,9 @@ struct xhci_hcd {
1423 #define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1424 #define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1425 #define XHCI_MISSING_CAS BIT_ULL(24)
1426 +#define XHCI_REVERSE_IN_OUT BIT(32)
1427 +#define XHCI_STOP_TRANSFER_IN_BLOCK BIT(33)
1428 +#define XHCI_STOP_EP_IN_U1 BIT(34)
1429 /* For controller with a broken Port Disable implementation */
1430 #define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1431 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1432 @@ -1838,8 +1841,9 @@ struct xhci_hcd {
1433 #define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1434 #define XHCI_SUSPEND_DELAY BIT_ULL(30)
1435 #define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1436 -#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1437 -#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1438 +#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(35)
1439 +#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(36)
1440 +#define XHCI_DIS_U1U2_WHEN_U3 BIT(37)
1441
1442 unsigned int num_active_eps;
1443 unsigned int limit_active_eps;
1444 --- a/drivers/usb/phy/phy-fsl-usb.c
1445 +++ b/drivers/usb/phy/phy-fsl-usb.c
1446 @@ -1,5 +1,5 @@
1447 /*
1448 - * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
1449 + * Copyright 2007,2008 Freescale Semiconductor, Inc.
1450 *
1451 * Author: Li Yang <LeoLi@freescale.com>
1452 * Jerry Huang <Chang-Ming.Huang@freescale.com>
1453 @@ -470,6 +470,7 @@ void otg_reset_controller(void)
1454 int fsl_otg_start_host(struct otg_fsm *fsm, int on)
1455 {
1456 struct usb_otg *otg = fsm->otg;
1457 + struct usb_bus *host = otg->host;
1458 struct device *dev;
1459 struct fsl_otg *otg_dev =
1460 container_of(otg->usb_phy, struct fsl_otg, phy);
1461 @@ -493,6 +494,7 @@ int fsl_otg_start_host(struct otg_fsm *f
1462 otg_reset_controller();
1463 VDBG("host on......\n");
1464 if (dev->driver->pm && dev->driver->pm->resume) {
1465 + host->is_otg = 1;
1466 retval = dev->driver->pm->resume(dev);
1467 if (fsm->id) {
1468 /* default-b */
1469 @@ -517,8 +519,11 @@ int fsl_otg_start_host(struct otg_fsm *f
1470 else {
1471 VDBG("host off......\n");
1472 if (dev && dev->driver) {
1473 - if (dev->driver->pm && dev->driver->pm->suspend)
1474 + if (dev->driver->pm &&
1475 + dev->driver->pm->suspend) {
1476 + host->is_otg = 1;
1477 retval = dev->driver->pm->suspend(dev);
1478 + }
1479 if (fsm->id)
1480 /* default-b */
1481 fsl_otg_drv_vbus(fsm, 0);
1482 @@ -546,8 +551,17 @@ int fsl_otg_start_gadget(struct otg_fsm
1483 dev = otg->gadget->dev.parent;
1484
1485 if (on) {
1486 - if (dev->driver->resume)
1487 + /* Delay gadget resume to synchronize between host and gadget
1488 + * drivers. Upon role-reversal host drv is shutdown by kernel
1489 + * worker thread. By the time host drv shuts down, controller
1490 + * gets programmed for gadget role. Shutting host drv after
1491 + * this results in controller getting reset, and it stops
1492 + * responding to otg events
1493 + */
1494 + if (dev->driver->resume) {
1495 + msleep(1000);
1496 dev->driver->resume(dev);
1497 + }
1498 } else {
1499 if (dev->driver->suspend)
1500 dev->driver->suspend(dev, otg_suspend_state);
1501 @@ -668,6 +682,10 @@ static void fsl_otg_event(struct work_st
1502 fsl_otg_start_host(fsm, 0);
1503 otg_drv_vbus(fsm, 0);
1504 fsl_otg_start_gadget(fsm, 1);
1505 + } else {
1506 + fsl_otg_start_gadget(fsm, 0);
1507 + otg_drv_vbus(fsm, 1);
1508 + fsl_otg_start_host(fsm, 1);
1509 }
1510 }
1511
1512 @@ -720,6 +738,7 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1513 {
1514 struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
1515 struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
1516 + struct fsl_otg *otg_dev = dev_id;
1517 u32 otg_int_src, otg_sc;
1518
1519 otg_sc = fsl_readl(&usb_dr_regs->otgsc);
1520 @@ -749,18 +768,8 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1521 otg->gadget->is_a_peripheral = !fsm->id;
1522 VDBG("ID int (ID is %d)\n", fsm->id);
1523
1524 - if (fsm->id) { /* switch to gadget */
1525 - schedule_delayed_work(
1526 - &((struct fsl_otg *)dev_id)->otg_event,
1527 - 100);
1528 - } else { /* switch to host */
1529 - cancel_delayed_work(&
1530 - ((struct fsl_otg *)dev_id)->
1531 - otg_event);
1532 - fsl_otg_start_gadget(fsm, 0);
1533 - otg_drv_vbus(fsm, 1);
1534 - fsl_otg_start_host(fsm, 1);
1535 - }
1536 + schedule_delayed_work(&otg_dev->otg_event, 100);
1537 +
1538 return IRQ_HANDLED;
1539 }
1540 }
1541 @@ -920,12 +929,32 @@ int usb_otg_start(struct platform_device
1542 temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
1543 switch (pdata->phy_mode) {
1544 case FSL_USB2_PHY_ULPI:
1545 + if (pdata->controller_ver) {
1546 + /* controller version 1.6 or above */
1547 + setbits32(&p_otg->dr_mem_map->control,
1548 + USB_CTRL_ULPI_PHY_CLK_SEL);
1549 + /*
1550 + * Due to controller issue of PHY_CLK_VALID in ULPI
1551 + * mode, we set USB_CTRL_USB_EN before checking
1552 + * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
1553 + */
1554 + clrsetbits_be32(&p_otg->dr_mem_map->control,
1555 + USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
1556 + }
1557 temp |= PORTSC_PTS_ULPI;
1558 break;
1559 case FSL_USB2_PHY_UTMI_WIDE:
1560 temp |= PORTSC_PTW_16BIT;
1561 /* fall through */
1562 case FSL_USB2_PHY_UTMI:
1563 + if (pdata->controller_ver) {
1564 + /* controller version 1.6 or above */
1565 + setbits32(&p_otg->dr_mem_map->control,
1566 + USB_CTRL_UTMI_PHY_EN);
1567 + /* Delay for UTMI PHY CLK to become stable - 10ms */
1568 + mdelay(FSL_UTMI_PHY_DLY);
1569 + }
1570 + setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
1571 temp |= PORTSC_PTS_UTMI;
1572 /* fall through */
1573 default:
1574 --- a/drivers/usb/phy/phy-fsl-usb.h
1575 +++ b/drivers/usb/phy/phy-fsl-usb.h
1576 @@ -199,6 +199,14 @@
1577 /* control Register Bit Masks */
1578 #define USB_CTRL_IOENB (0x1<<2)
1579 #define USB_CTRL_ULPI_INT0EN (0x1<<0)
1580 +#define USB_CTRL_WU_INT_EN (0x1<<1)
1581 +#define USB_CTRL_LINE_STATE_FILTER__EN (0x1<<3)
1582 +#define USB_CTRL_KEEP_OTG_ON (0x1<<4)
1583 +#define USB_CTRL_OTG_PORT (0x1<<5)
1584 +#define USB_CTRL_PLL_RESET (0x1<<8)
1585 +#define USB_CTRL_UTMI_PHY_EN (0x1<<9)
1586 +#define USB_CTRL_ULPI_PHY_CLK_SEL (0x1<<10)
1587 +#define USB_CTRL_PHY_CLK_VALID (0x1<<17)
1588
1589 /* BCSR5 */
1590 #define BCSR5_INT_USB (0x02)
1591 --- a/include/linux/usb.h
1592 +++ b/include/linux/usb.h
1593 @@ -432,6 +432,7 @@ struct usb_bus {
1594 * for control transfers?
1595 */
1596 u8 otg_port; /* 0, or number of OTG/HNP port */
1597 + unsigned is_otg:1; /* true when host is also otg */
1598 unsigned is_b_host:1; /* true during some HNP roleswitches */
1599 unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */
1600 unsigned no_stop_on_short:1; /*
1601 --- a/include/linux/usb/of.h
1602 +++ b/include/linux/usb/of.h
1603 @@ -11,6 +11,8 @@
1604 #include <linux/usb/otg.h>
1605 #include <linux/usb/phy.h>
1606
1607 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np);
1608 +
1609 #if IS_ENABLED(CONFIG_OF)
1610 enum usb_dr_mode of_usb_get_dr_mode_by_phy(struct device_node *np, int arg0);
1611 bool of_usb_host_tpl_support(struct device_node *np);
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