projects / openwrt / openwrt.git / blob
? search:


3ecec1756e04d5003a19b9b5588c74d1d5ea95b1
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.14 / 812-flexspi-support-layerscape.patch
1 From 9875df1e872eb2b0f9d2d72c9a761a5f03400d9f Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Fri, 19 Apr 2019 13:23:01 +0800
4 Subject: [PATCH] flexspi: support layerscape
5
6 This is an integrated patch of flexspi for layerscape
7
8 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
9 Signed-off-by: Biwen Li <biwen.li@nxp.com>
10 Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
12 Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
13 ---
14 .../devicetree/bindings/mtd/nxp-flexspi.txt | 41 +
15 drivers/mtd/spi-nor/Kconfig | 10 +
16 drivers/mtd/spi-nor/Makefile | 1 +
17 drivers/mtd/spi-nor/nxp-flexspi.c | 1404 +++++++++++++++++
18 drivers/mtd/spi-nor/spi-nor.c | 13 +-
19 include/linux/mtd/cfi.h | 1 +
20 include/linux/mtd/spi-nor.h | 3 +-
21 7 files changed, 1470 insertions(+), 3 deletions(-)
22 create mode 100644 Documentation/devicetree/bindings/mtd/nxp-flexspi.txt
23 create mode 100644 drivers/mtd/spi-nor/nxp-flexspi.c
24
25 --- /dev/null
26 +++ b/Documentation/devicetree/bindings/mtd/nxp-flexspi.txt
27 @@ -0,0 +1,41 @@
28 +* NXP Flex Serial Peripheral Interface(FlexSPI)
29 +
30 +Required properties:
31 + - compatible : Should be "nxp,lx2160a-fspi"
32 + - reg : the first contains the register location and length,
33 + the second contains the memory mapping address and length
34 + - reg-names: Should contain the reg names "FSPI" and "FSPI-memory"
35 + - interrupts : Should contain the interrupt for the device
36 + - clocks : The clocks needed by the FlexSPI controller
37 + - clock-names : Should contain the name of the clocks: "fspi_en" and "fspi"
38 +
39 +Optional properties:
40 + - nxp,fspi-has-second-chip: The controller has two buses, bus A and bus B.
41 + Each bus can be connected with two NOR flashes.
42 + Most of the time, each bus only has one NOR flash
43 + connected, this is the default case.
44 + But if there are two NOR flashes connected to the
45 + bus, you should enable this property.
46 + (Please check the board's schematic.)
47 +Example:
48 +fspi0: flexspi@20c0000 {
49 + compatible = "nxp,lx2160a-fspi";
50 + reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>;
51 + reg-names = "FSPI", "FSPI-memory";
52 + interrupts = <0 25 0x4>; /* Level high type */
53 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
54 + clock-names = "fspi_en", "fspi";
55 +
56 + status = "okay";
57 + nxp,fspi-has-second-chip;
58 + flash0: mt35xu512aba@0 {
59 + reg = <0>;
60 + ....
61 + };
62 +
63 + flash1: mt35xu512aba@1 {
64 + reg = <1>;
65 + ....
66 + };
67 +
68 +};
69 --- a/drivers/mtd/spi-nor/Kconfig
70 +++ b/drivers/mtd/spi-nor/Kconfig
71 @@ -97,6 +97,16 @@ config SPI_NXP_SPIFI
72 Flash. Enable this option if you have a device with a SPIFI
73 controller and want to access the Flash as a mtd device.
74
75 +config SPI_NXP_FLEXSPI
76 + tristate "NXP Flex SPI controller"
77 + help
78 + This enables support for the Flex SPI controller in master mode.
79 + Up to four slave devices can be connected on two buses with two
80 + chipselects each.
81 + This controller does not support generic SPI messages and only
82 + supports the high-level SPI memory interface using SPI-NOR
83 + framework.
84 +
85 config SPI_INTEL_SPI
86 tristate
87
88 --- a/drivers/mtd/spi-nor/Makefile
89 +++ b/drivers/mtd/spi-nor/Makefile
90 @@ -7,6 +7,7 @@ obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-qua
91 obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o
92 obj-$(CONFIG_MTD_MT81xx_NOR) += mtk-quadspi.o
93 obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o
94 +obj-$(CONFIG_SPI_NXP_FLEXSPI) += nxp-flexspi.o
95 obj-$(CONFIG_SPI_INTEL_SPI) += intel-spi.o
96 obj-$(CONFIG_SPI_INTEL_SPI_PCI) += intel-spi-pci.o
97 obj-$(CONFIG_SPI_INTEL_SPI_PLATFORM) += intel-spi-platform.o
98 --- /dev/null
99 +++ b/drivers/mtd/spi-nor/nxp-flexspi.c
100 @@ -0,0 +1,1404 @@
101 +/*
102 + * NXP FSPI(FlexSPI controller) driver.
103 + *
104 + * Copyright 2018 NXP
105 + * Author: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
106 + *
107 + * This program is free software; you can redistribute it and/or modify
108 + * it under the terms of the GNU General Public License as published by
109 + * the Free Software Foundation; either version 2 of the License, or
110 + * (at your option) any later version.
111 + */
112 +#include <linux/kernel.h>
113 +#include <linux/module.h>
114 +#include <linux/interrupt.h>
115 +#include <linux/errno.h>
116 +#include <linux/platform_device.h>
117 +#include <linux/sched.h>
118 +#include <linux/delay.h>
119 +#include <linux/io.h>
120 +#include <linux/clk.h>
121 +#include <linux/err.h>
122 +#include <linux/of.h>
123 +#include <linux/of_device.h>
124 +#include <linux/timer.h>
125 +#include <linux/jiffies.h>
126 +#include <linux/completion.h>
127 +#include <linux/mtd/mtd.h>
128 +#include <linux/mtd/partitions.h>
129 +#include <linux/mtd/spi-nor.h>
130 +#include <linux/mutex.h>
131 +#include <linux/pm_qos.h>
132 +#include <linux/pci.h>
133 +
134 +/* The registers */
135 +#define FSPI_MCR0 0x00
136 +#define FSPI_MCR0_AHB_TIMEOUT_SHIFT 24
137 +#define FSPI_MCR0_AHB_TIMEOUT_MASK (0xFF << FSPI_MCR0_AHB_TIMEOUT_SHIFT)
138 +#define FSPI_MCR0_IP_TIMEOUT_SHIFT 16
139 +#define FSPI_MCR0_IP_TIMEOUT_MASK (0xFF << FSPI_MCR0_IP_TIMEOUT_SHIFT)
140 +#define FSPI_MCR0_LEARN_EN_SHIFT 15
141 +#define FSPI_MCR0_LEARN_EN_MASK (1 << FSPI_MCR0_LEARN_EN_SHIFT)
142 +#define FSPI_MCR0_SCRFRUN_EN_SHIFT 14
143 +#define FSPI_MCR0_SCRFRUN_EN_MASK (1 << FSPI_MCR0_SCRFRUN_EN_SHIFT)
144 +#define FSPI_MCR0_OCTCOMB_EN_SHIFT 13
145 +#define FSPI_MCR0_OCTCOMB_EN_MASK (1 << FSPI_MCR0_OCTCOMB_EN_SHIFT)
146 +#define FSPI_MCR0_DOZE_EN_SHIFT 12
147 +#define FSPI_MCR0_DOZE_EN_MASK (1 << FSPI_MCR0_DOZE_EN_SHIFT)
148 +#define FSPI_MCR0_HSEN_SHIFT 11
149 +#define FSPI_MCR0_HSEN_MASK (1 << FSPI_MCR0_HSEN_SHIFT)
150 +#define FSPI_MCR0_SERCLKDIV_SHIFT 8
151 +#define FSPI_MCR0_SERCLKDIV_MASK (7 << FSPI_MCR0_SERCLKDIV_SHIFT)
152 +#define FSPI_MCR0_ATDF_EN_SHIFT 7
153 +#define FSPI_MCR0_ATDF_EN_MASK (1 << FSPI_MCR0_ATDF_EN_SHIFT)
154 +#define FSPI_MCR0_ARDF_EN_SHIFT 6
155 +#define FSPI_MCR0_ARDF_EN_MASK (1 << FSPI_MCR0_ARDF_EN_SHIFT)
156 +#define FSPI_MCR0_RXCLKSRC_SHIFT 4
157 +#define FSPI_MCR0_RXCLKSRC_MASK (3 << FSPI_MCR0_RXCLKSRC_SHIFT)
158 +#define FSPI_MCR0_END_CFG_SHIFT 2
159 +#define FSPI_MCR0_END_CFG_MASK (3 << FSPI_MCR0_END_CFG_SHIFT)
160 +#define FSPI_MCR0_MDIS_SHIFT 1
161 +#define FSPI_MCR0_MDIS_MASK (1 << FSPI_MCR0_MDIS_SHIFT)
162 +#define FSPI_MCR0_SWRST_SHIFT 0
163 +#define FSPI_MCR0_SWRST_MASK (1 << FSPI_MCR0_SWRST_SHIFT)
164 +
165 +#define FSPI_MCR1 0x04
166 +#define FSPI_MCR1_SEQ_TIMEOUT_SHIFT 16
167 +#define FSPI_MCR1_SEQ_TIMEOUT_MASK \
168 + (0xFFFF << FSPI_MCR1_SEQ_TIMEOUT_SHIFT)
169 +#define FSPI_MCR1_AHB_TIMEOUT_SHIFT 0
170 +#define FSPI_MCR1_AHB_TIMEOUT_MASK \
171 + (0xFFFF << FSPI_MCR1_AHB_TIMEOUT_SHIFT)
172 +
173 +#define FSPI_MCR2 0x08
174 +#define FSPI_MCR2_IDLE_WAIT_SHIFT 24
175 +#define FSPI_MCR2_IDLE_WAIT_MASK (0xFF << FSPI_MCR2_IDLE_WAIT_SHIFT)
176 +#define FSPI_MCR2_SAMEFLASH_SHIFT 15
177 +#define FSPI_MCR2_SAMEFLASH_MASK (1 << FSPI_MCR2_SAMEFLASH_SHIFT)
178 +#define FSPI_MCR2_CLRLRPHS_SHIFT 14
179 +#define FSPI_MCR2_CLRLRPHS_MASK (1 << FSPI_MCR2_CLRLRPHS_SHIFT)
180 +#define FSPI_MCR2_ABRDATSZ_SHIFT 8
181 +#define FSPI_MCR2_ABRDATSZ_MASK (1 << FSPI_MCR2_ABRDATSZ_SHIFT)
182 +#define FSPI_MCR2_ABRLEARN_SHIFT 7
183 +#define FSPI_MCR2_ABRLEARN_MASK (1 << FSPI_MCR2_ABRLEARN_SHIFT)
184 +#define FSPI_MCR2_ABR_READ_SHIFT 6
185 +#define FSPI_MCR2_ABR_READ_MASK (1 << FSPI_MCR2_ABR_READ_SHIFT)
186 +#define FSPI_MCR2_ABRWRITE_SHIFT 5
187 +#define FSPI_MCR2_ABRWRITE_MASK (1 << FSPI_MCR2_ABRWRITE_SHIFT)
188 +#define FSPI_MCR2_ABRDUMMY_SHIFT 4
189 +#define FSPI_MCR2_ABRDUMMY_MASK (1 << FSPI_MCR2_ABRDUMMY_SHIFT)
190 +#define FSPI_MCR2_ABR_MODE_SHIFT 3
191 +#define FSPI_MCR2_ABR_MODE_MASK (1 << FSPI_MCR2_ABR_MODE_SHIFT)
192 +#define FSPI_MCR2_ABRCADDR_SHIFT 2
193 +#define FSPI_MCR2_ABRCADDR_MASK (1 << FSPI_MCR2_ABRCADDR_SHIFT)
194 +#define FSPI_MCR2_ABRRADDR_SHIFT 1
195 +#define FSPI_MCR2_ABRRADDR_MASK (1 << FSPI_MCR2_ABRRADDR_SHIFT)
196 +#define FSPI_MCR2_ABR_CMD_SHIFT 0
197 +#define FSPI_MCR2_ABR_CMD_MASK (1 << FSPI_MCR2_ABR_CMD_SHIFT)
198 +
199 +#define FSPI_AHBCR 0x0c
200 +#define FSPI_AHBCR_RDADDROPT_SHIFT 6
201 +#define FSPI_AHBCR_RDADDROPT_MASK (1 << FSPI_AHBCR_RDADDROPT_SHIFT)
202 +#define FSPI_AHBCR_PREF_EN_SHIFT 5
203 +#define FSPI_AHBCR_PREF_EN_MASK (1 << FSPI_AHBCR_PREF_EN_SHIFT)
204 +#define FSPI_AHBCR_BUFF_EN_SHIFT 4
205 +#define FSPI_AHBCR_BUFF_EN_MASK (1 << FSPI_AHBCR_BUFF_EN_SHIFT)
206 +#define FSPI_AHBCR_CACH_EN_SHIFT 3
207 +#define FSPI_AHBCR_CACH_EN_MASK (1 << FSPI_AHBCR_CACH_EN_SHIFT)
208 +#define FSPI_AHBCR_CLRTXBUF_SHIFT 2
209 +#define FSPI_AHBCR_CLRTXBUF_MASK (1 << FSPI_AHBCR_CLRTXBUF_SHIFT)
210 +#define FSPI_AHBCR_CLRRXBUF_SHIFT 1
211 +#define FSPI_AHBCR_CLRRXBUF_MASK (1 << FSPI_AHBCR_CLRRXBUF_SHIFT)
212 +#define FSPI_AHBCR_PAR_EN_SHIFT 0
213 +#define FSPI_AHBCR_PAR_EN_MASK (1 << FSPI_AHBCR_PAR_EN_SHIFT)
214 +
215 +#define FSPI_INTEN 0x10
216 +#define FSPI_INTEN_SCLKSBWR_SHIFT 9
217 +#define FSPI_INTEN_SCLKSBWR_MASK (1 << FSPI_INTEN_SCLKSBWR_SHIFT)
218 +#define FSPI_INTEN_SCLKSBRD_SHIFT 8
219 +#define FSPI_INTEN_SCLKSBRD_MASK (1 << FSPI_INTEN_SCLKSBRD_SHIFT)
220 +#define FSPI_INTEN_DATALRNFL_SHIFT 7
221 +#define FSPI_INTEN_DATALRNFL_MASK (1 << FSPI_INTEN_DATALRNFL_SHIFT)
222 +#define FSPI_INTEN_IPTXWE_SHIFT 6
223 +#define FSPI_INTEN_IPTXWE_MASK (1 << FSPI_INTEN_IPTXWE_SHIFT)
224 +#define FSPI_INTEN_IPRXWA_SHIFT 5
225 +#define FSPI_INTEN_IPRXWA_MASK (1 << FSPI_INTEN_IPRXWA_SHIFT)
226 +#define FSPI_INTEN_AHBCMDERR_SHIFT 4
227 +#define FSPI_INTEN_AHBCMDERR_MASK (1 << FSPI_INTEN_AHBCMDERR_SHIFT)
228 +#define FSPI_INTEN_IPCMDERR_SHIFT 3
229 +#define FSPI_INTEN_IPCMDERR_MASK (1 << FSPI_INTEN_IPCMDERR_SHIFT)
230 +#define FSPI_INTEN_AHBCMDGE_SHIFT 2
231 +#define FSPI_INTEN_AHBCMDGE_MASK (1 << FSPI_INTEN_AHBCMDGE_SHIFT)
232 +#define FSPI_INTEN_IPCMDGE_SHIFT 1
233 +#define FSPI_INTEN_IPCMDGE_MASK (1 << FSPI_INTEN_IPCMDGE_SHIFT)
234 +#define FSPI_INTEN_IPCMDDONE_SHIFT 0
235 +#define FSPI_INTEN_IPCMDDONE_MASK (1 << FSPI_INTEN_IPCMDDONE_SHIFT)
236 +
237 +#define FSPI_INTR 0x14
238 +#define FSPI_INTR_SCLKSBWR_SHIFT 9
239 +#define FSPI_INTR_SCLKSBWR_MASK (1 << FSPI_INTR_SCLKSBWR_SHIFT)
240 +#define FSPI_INTR_SCLKSBRD_SHIFT 8
241 +#define FSPI_INTR_SCLKSBRD_MASK (1 << FSPI_INTR_SCLKSBRD_SHIFT)
242 +#define FSPI_INTR_DATALRNFL_SHIFT 7
243 +#define FSPI_INTR_DATALRNFL_MASK (1 << FSPI_INTR_DATALRNFL_SHIFT)
244 +#define FSPI_INTR_IPTXWE_SHIFT 6
245 +#define FSPI_INTR_IPTXWE_MASK (1 << FSPI_INTR_IPTXWE_SHIFT)
246 +#define FSPI_INTR_IPRXWA_SHIFT 5
247 +#define FSPI_INTR_IPRXWA_MASK (1 << FSPI_INTR_IPRXWA_SHIFT)
248 +#define FSPI_INTR_AHBCMDERR_SHIFT 4
249 +#define FSPI_INTR_AHBCMDERR_MASK (1 << FSPI_INTR_AHBCMDERR_SHIFT)
250 +#define FSPI_INTR_IPCMDERR_SHIFT 3
251 +#define FSPI_INTR_IPCMDERR_MASK (1 << FSPI_INTR_IPCMDERR_SHIFT)
252 +#define FSPI_INTR_AHBCMDGE_SHIFT 2
253 +#define FSPI_INTR_AHBCMDGE_MASK (1 << FSPI_INTR_AHBCMDGE_SHIFT)
254 +#define FSPI_INTR_IPCMDGE_SHIFT 1
255 +#define FSPI_INTR_IPCMDGE_MASK (1 << FSPI_INTR_IPCMDGE_SHIFT)
256 +#define FSPI_INTR_IPCMDDONE_SHIFT 0
257 +#define FSPI_INTR_IPCMDDONE_MASK (1 << FSPI_INTR_IPCMDDONE_SHIFT)
258 +
259 +#define FSPI_LUTKEY 0x18
260 +#define FSPI_LUTKEY_VALUE 0x5AF05AF0
261 +
262 +#define FSPI_LCKCR 0x1C
263 +#define FSPI_LCKER_LOCK 0x1
264 +#define FSPI_LCKER_UNLOCK 0x2
265 +
266 +#define FSPI_BUFXCR_INVALID_MSTRID 0xe
267 +#define FSPI_AHBRX_BUF0CR0 0x20
268 +#define FSPI_AHBRX_BUF1CR0 0x24
269 +#define FSPI_AHBRX_BUF2CR0 0x28
270 +#define FSPI_AHBRX_BUF3CR0 0x2C
271 +#define FSPI_AHBRX_BUF4CR0 0x30
272 +#define FSPI_AHBRX_BUF5CR0 0x34
273 +#define FSPI_AHBRX_BUF6CR0 0x38
274 +#define FSPI_AHBRX_BUF7CR0 0x3C
275 +#define FSPI_AHBRXBUF0CR7_PREF_SHIFT 31
276 +#define FSPI_AHBRXBUF0CR7_PREF_MASK (1 << FSPI_AHBRXBUF0CR7_PREF_SHIFT)
277 +
278 +#define FSPI_AHBRX_BUF0CR1 0x40
279 +#define FSPI_AHBRX_BUF1CR1 0x44
280 +#define FSPI_AHBRX_BUF2CR1 0x48
281 +#define FSPI_AHBRX_BUF3CR1 0x4C
282 +#define FSPI_AHBRX_BUF4CR1 0x50
283 +#define FSPI_AHBRX_BUF5CR1 0x54
284 +#define FSPI_AHBRX_BUF6CR1 0x58
285 +#define FSPI_AHBRX_BUF7CR1 0x5C
286 +#define FSPI_BUFXCR1_MSID_SHIFT 0
287 +#define FSPI_BUFXCR1_MSID_MASK (0xF << FSPI_BUFXCR1_MSID_SHIFT)
288 +#define FSPI_BUFXCR1_PRIO_SHIFT 8
289 +#define FSPI_BUFXCR1_PRIO_MASK (0x7 << FSPI_BUFXCR1_PRIO_SHIFT)
290 +
291 +#define FSPI_FLSHA1CR0 0x60
292 +#define FSPI_FLSHA2CR0 0x64
293 +#define FSPI_FLSHB1CR0 0x68
294 +#define FSPI_FLSHB2CR0 0x6C
295 +#define FSPI_FLSHXCR0_SZ_SHIFT 10
296 +#define FSPI_FLSHXCR0_SZ_MASK (0x3FFFFF << FSPI_FLSHXCR0_SZ_SHIFT)
297 +
298 +#define FSPI_FLSHA1CR1 0x70
299 +#define FSPI_FLSHA2CR1 0x74
300 +#define FSPI_FLSHB1CR1 0x78
301 +#define FSPI_FLSHB2CR1 0x7C
302 +#define FSPI_FLSHXCR1_CSINTR_SHIFT 16
303 +#define FSPI_FLSHXCR1_CSINTR_MASK \
304 + (0xFFFF << FSPI_FLSHXCR1_CSINTR_SHIFT)
305 +#define FSPI_FLSHXCR1_CAS_SHIFT 11
306 +#define FSPI_FLSHXCR1_CAS_MASK (0xF << FSPI_FLSHXCR1_CAS_SHIFT)
307 +#define FSPI_FLSHXCR1_WA_SHIFT 10
308 +#define FSPI_FLSHXCR1_WA_MASK (1 << FSPI_FLSHXCR1_WA_SHIFT)
309 +#define FSPI_FLSHXCR1_TCSH_SHIFT 5
310 +#define FSPI_FLSHXCR1_TCSH_MASK (0x1F << FSPI_FLSHXCR1_TCSH_SHIFT)
311 +#define FSPI_FLSHXCR1_TCSS_SHIFT 0
312 +#define FSPI_FLSHXCR1_TCSS_MASK (0x1F << FSPI_FLSHXCR1_TCSS_SHIFT)
313 +
314 +#define FSPI_FLSHA1CR2 0x80
315 +#define FSPI_FLSHA2CR2 0x84
316 +#define FSPI_FLSHB1CR2 0x88
317 +#define FSPI_FLSHB2CR2 0x8C
318 +#define FSPI_FLSHXCR2_CLRINSP_SHIFT 24
319 +#define FSPI_FLSHXCR2_CLRINSP_MASK (1 << FSPI_FLSHXCR2_CLRINSP_SHIFT)
320 +#define FSPI_FLSHXCR2_AWRWAIT_SHIFT 16
321 +#define FSPI_FLSHXCR2_AWRWAIT_MASK (0xFF << FSPI_FLSHXCR2_AWRWAIT_SHIFT)
322 +#define FSPI_FLSHXCR2_AWRSEQN_SHIFT 13
323 +#define FSPI_FLSHXCR2_AWRSEQN_MASK (0x7 << FSPI_FLSHXCR2_AWRSEQN_SHIFT)
324 +#define FSPI_FLSHXCR2_AWRSEQI_SHIFT 8
325 +#define FSPI_FLSHXCR2_AWRSEQI_MASK (0xF << FSPI_FLSHXCR2_AWRSEQI_SHIFT)
326 +#define FSPI_FLSHXCR2_ARDSEQN_SHIFT 5
327 +#define FSPI_FLSHXCR2_ARDSEQN_MASK (0x7 << FSPI_FLSHXCR2_ARDSEQN_SHIFT)
328 +#define FSPI_FLSHXCR2_ARDSEQI_SHIFT 0
329 +#define FSPI_FLSHXCR2_ARDSEQI_MASK (0xF << FSPI_FLSHXCR2_ARDSEQI_SHIFT)
330 +
331 +#define FSPI_IPCR0 0xA0
332 +
333 +#define FSPI_IPCR1 0xA4
334 +#define FSPI_IPCR1_IPAREN_SHIFT 31
335 +#define FSPI_IPCR1_IPAREN_MASK (1 << FSPI_IPCR1_IPAREN_SHIFT)
336 +#define FSPI_IPCR1_SEQNUM_SHIFT 24
337 +#define FSPI_IPCR1_SEQNUM_MASK (0xF << FSPI_IPCR1_SEQNUM_SHIFT)
338 +#define FSPI_IPCR1_SEQID_SHIFT 16
339 +#define FSPI_IPCR1_SEQID_MASK (0xF << FSPI_IPCR1_SEQID_SHIFT)
340 +#define FSPI_IPCR1_IDATSZ_SHIFT 0
341 +#define FSPI_IPCR1_IDATSZ_MASK (0xFFFF << FSPI_IPCR1_IDATSZ_SHIFT)
342 +
343 +#define FSPI_IPCMD 0xB0
344 +#define FSPI_IPCMD_TRG_SHIFT 0
345 +#define FSPI_IPCMD_TRG_MASK (1 << FSPI_IPCMD_TRG_SHIFT)
346 +
347 +#define FSPI_DLPR 0xB4
348 +
349 +#define FSPI_IPRXFCR 0xB8
350 +#define FSPI_IPRXFCR_CLR_SHIFT 0
351 +#define FSPI_IPRXFCR_CLR_MASK (1 << FSPI_IPRXFCR_CLR_SHIFT)
352 +#define FSPI_IPRXFCR_DMA_EN_SHIFT 1
353 +#define FSPI_IPRXFCR_DMA_EN_MASK (1 << FSPI_IPRXFCR_DMA_EN_SHIFT)
354 +#define FSPI_IPRXFCR_WMRK_SHIFT 2
355 +#define FSPI_IPRXFCR_WMRK_MASK (0x1F << FSPI_IPRXFCR_WMRK_SHIFT)
356 +
357 +#define FSPI_IPTXFCR 0xBC
358 +#define FSPI_IPTXFCR_CLR_SHIFT 0
359 +#define FSPI_IPTXFCR_CLR_MASK (1 << FSPI_IPTXFCR_CLR_SHIFT)
360 +#define FSPI_IPTXFCR_DMA_EN_SHIFT 1
361 +#define FSPI_IPTXFCR_DMA_EN_MASK (1 << FSPI_IPTXFCR_DMA_EN_SHIFT)
362 +#define FSPI_IPTXFCR_WMRK_SHIFT 2
363 +#define FSPI_IPTXFCR_WMRK_MASK (0x1F << FSPI_IPTXFCR_WMRK_SHIFT)
364 +
365 +#define FSPI_DLLACR 0xC0
366 +#define FSPI_DLLACR_OVRDEN_SHIFT 8
367 +#define FSPI_DLLACR_OVRDEN_MASK (1 << FSPI_DLLACR_OVRDEN_SHIFT)
368 +
369 +#define FSPI_DLLBCR 0xC4
370 +#define FSPI_DLLBCR_OVRDEN_SHIFT 8
371 +#define FSPI_DLLBCR_OVRDEN_MASK (1 << FSPI_DLLBCR_OVRDEN_SHIFT)
372 +
373 +#define FSPI_STS0 0xE0
374 +#define FSPI_STS0_DLPHA_SHIFT 9
375 +#define FSPI_STS0_DLPHA_MASK (0x1F << FSPI_STS0_DLPHA_SHIFT)
376 +#define FSPI_STS0_DLPHB_SHIFT 4
377 +#define FSPI_STS0_DLPHB_MASK (0x1F << FSPI_STS0_DLPHB_SHIFT)
378 +#define FSPI_STS0_CMD_SRC_SHIFT 2
379 +#define FSPI_STS0_CMD_SRC_MASK (3 << FSPI_STS0_CMD_SRC_SHIFT)
380 +#define FSPI_STS0_ARB_IDLE_SHIFT 1
381 +#define FSPI_STS0_ARB_IDLE_MASK (1 << FSPI_STS0_ARB_IDLE_SHIFT)
382 +#define FSPI_STS0_SEQ_IDLE_SHIFT 0
383 +#define FSPI_STS0_SEQ_IDLE_MASK (1 << FSPI_STS0_SEQ_IDLE_SHIFT)
384 +
385 +#define FSPI_STS1 0xE4
386 +#define FSPI_STS1_IP_ERRCD_SHIFT 24
387 +#define FSPI_STS1_IP_ERRCD_MASK (0xF << FSPI_STS1_IP_ERRCD_SHIFT)
388 +#define FSPI_STS1_IP_ERRID_SHIFT 16
389 +#define FSPI_STS1_IP_ERRID_MASK (0xF << FSPI_STS1_IP_ERRID_SHIFT)
390 +#define FSPI_STS1_AHB_ERRCD_SHIFT 8
391 +#define FSPI_STS1_AHB_ERRCD_MASK (0xF << FSPI_STS1_AHB_ERRCD_SHIFT)
392 +#define FSPI_STS1_AHB_ERRID_SHIFT 0
393 +#define FSPI_STS1_AHB_ERRID_MASK (0xF << FSPI_STS1_AHB_ERRID_SHIFT)
394 +
395 +#define FSPI_AHBSPNST 0xEC
396 +#define FSPI_AHBSPNST_DATLFT_SHIFT 16
397 +#define FSPI_AHBSPNST_DATLFT_MASK \
398 + (0xFFFF << FSPI_AHBSPNST_DATLFT_SHIFT)
399 +#define FSPI_AHBSPNST_BUFID_SHIFT 1
400 +#define FSPI_AHBSPNST_BUFID_MASK (7 << FSPI_AHBSPNST_BUFID_SHIFT)
401 +#define FSPI_AHBSPNST_ACTIVE_SHIFT 0
402 +#define FSPI_AHBSPNST_ACTIVE_MASK (1 << FSPI_AHBSPNST_ACTIVE_SHIFT)
403 +
404 +#define FSPI_IPRXFSTS 0xF0
405 +#define FSPI_IPRXFSTS_RDCNTR_SHIFT 16
406 +#define FSPI_IPRXFSTS_RDCNTR_MASK \
407 + (0xFFFF << FSPI_IPRXFSTS_RDCNTR_SHIFT)
408 +#define FSPI_IPRXFSTS_FILL_SHIFT 0
409 +#define FSPI_IPRXFSTS_FILL_MASK (0xFF << FSPI_IPRXFSTS_FILL_SHIFT)
410 +
411 +#define FSPI_IPTXFSTS 0xF4
412 +#define FSPI_IPTXFSTS_WRCNTR_SHIFT 16
413 +#define FSPI_IPTXFSTS_WRCNTR_MASK \
414 + (0xFFFF << FSPI_IPTXFSTS_WRCNTR_SHIFT)
415 +#define FSPI_IPTXFSTS_FILL_SHIFT 0
416 +#define FSPI_IPTXFSTS_FILL_MASK (0xFF << FSPI_IPTXFSTS_FILL_SHIFT)
417 +
418 +#define FSPI_RFDR 0x100
419 +#define FSPI_TFDR 0x180
420 +
421 +#define FSPI_LUT_BASE 0x200
422 +
423 +/* register map end */
424 +
425 +/*
426 + * The definition of the LUT register shows below:
427 + *
428 + * ---------------------------------------------------
429 + * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
430 + * ---------------------------------------------------
431 + */
432 +#define OPRND0_SHIFT 0
433 +#define PAD0_SHIFT 8
434 +#define INSTR0_SHIFT 10
435 +#define OPRND1_SHIFT 16
436 +
437 +/* Instruction set for the LUT register. */
438 +
439 +#define LUT_STOP 0x00
440 +#define LUT_CMD 0x01
441 +#define LUT_ADDR 0x02
442 +#define LUT_CADDR_SDR 0x03
443 +#define LUT_MODE 0x04
444 +#define LUT_MODE2 0x05
445 +#define LUT_MODE4 0x06
446 +#define LUT_MODE8 0x07
447 +#define LUT_NXP_WRITE 0x08
448 +#define LUT_NXP_READ 0x09
449 +#define LUT_LEARN_SDR 0x0A
450 +#define LUT_DATSZ_SDR 0x0B
451 +#define LUT_DUMMY 0x0C
452 +#define LUT_DUMMY_RWDS_SDR 0x0D
453 +#define LUT_JMP_ON_CS 0x1F
454 +#define LUT_CMD_DDR 0x21
455 +#define LUT_ADDR_DDR 0x22
456 +#define LUT_CADDR_DDR 0x23
457 +#define LUT_MODE_DDR 0x24
458 +#define LUT_MODE2_DDR 0x25
459 +#define LUT_MODE4_DDR 0x26
460 +#define LUT_MODE8_DDR 0x27
461 +#define LUT_WRITE_DDR 0x28
462 +#define LUT_READ_DDR 0x29
463 +#define LUT_LEARN_DDR 0x2A
464 +#define LUT_DATSZ_DDR 0x2B
465 +#define LUT_DUMMY_DDR 0x2C
466 +#define LUT_DUMMY_RWDS_DDR 0x2D
467 +
468 +
469 +/*
470 + * The PAD definitions for LUT register.
471 + *
472 + * The pad stands for the lines number of IO[0:3].
473 + * For example, the Quad read need four IO lines, so you should
474 + * set LUT_PAD4 which means we use four IO lines.
475 + */
476 +#define LUT_PAD1 0
477 +#define LUT_PAD2 1
478 +#define LUT_PAD4 2
479 +#define LUT_PAD8 3
480 +
481 +/* Oprands for the LUT register. */
482 +#define ADDR24BIT 0x18
483 +#define ADDR32BIT 0x20
484 +
485 +/* Macros for constructing the LUT register. */
486 +#define LUT0(ins, pad, opr) \
487 + (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
488 + ((LUT_##ins) << INSTR0_SHIFT))
489 +
490 +#define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
491 +
492 +/* other macros for LUT register. */
493 +#define FSPI_LUT(x) (FSPI_LUT_BASE + (x) * 4)
494 +#define FSPI_LUT_NUM 128
495 +
496 +/* SEQID -- we can have 32 seqids at most. */
497 +#define SEQID_READ 0
498 +#define SEQID_WREN 1
499 +#define SEQID_WRDI 2
500 +#define SEQID_RDSR 3
501 +#define SEQID_SE 4
502 +#define SEQID_CHIP_ERASE 5
503 +#define SEQID_PP 6
504 +#define SEQID_RDID 7
505 +#define SEQID_WRSR 8
506 +#define SEQID_RDCR 9
507 +#define SEQID_EN4B 10
508 +#define SEQID_BRWR 11
509 +#define SEQID_RD_EVCR 12
510 +#define SEQID_WD_EVCR 13
511 +#define SEQID_RDFSR 14
512 +
513 +#define FSPI_MIN_IOMAP SZ_4M
514 +
515 +#define FSPI_RX_MAX_IPBUF_SIZE 0x200 /* 64 * 64bits */
516 +#define FSPI_TX_MAX_IPBUF_SIZE 0x400 /* 128 * 64bits */
517 +#define FSPI_RX_MAX_AHBBUF_SIZE 0x800 /* 256 * 64bits */
518 +#define FSPI_TX_MAX_AHBBUF_SIZE 0x40 /* 8 * 64bits */
519 +
520 +#define TX_IPBUF_SIZE FSPI_TX_MAX_IPBUF_SIZE
521 +#define RX_IPBUF_SIZE FSPI_RX_MAX_IPBUF_SIZE
522 +#define RX_AHBBUF_SIZE FSPI_RX_MAX_AHBBUF_SIZE
523 +#define TX_AHBBUF_SIZE FSPI_TX_MAX_AHBBUF_SIZE
524 +
525 +#define FSPI_SINGLE_MODE 1
526 +#define FSPI_OCTAL_MODE 8
527 +
528 +#define FSPINOR_OP_READ_1_1_8_4B 0x7c
529 +
530 +enum nxp_fspi_devtype {
531 + NXP_FSPI_LX2160A,
532 +};
533 +
534 +struct nxp_fspi_devtype_data {
535 + enum nxp_fspi_devtype devtype;
536 + int rxfifo;
537 + int txfifo;
538 + int ahb_buf_size;
539 + int driver_data;
540 +};
541 +
542 +static struct nxp_fspi_devtype_data lx2160a_data = {
543 + .devtype = NXP_FSPI_LX2160A,
544 + .rxfifo = RX_IPBUF_SIZE,
545 + .txfifo = TX_IPBUF_SIZE,
546 + .ahb_buf_size = RX_AHBBUF_SIZE,
547 + .driver_data = 0,
548 +};
549 +
550 +#define NXP_FSPI_MAX_CHIP 4
551 +struct nxp_fspi {
552 + struct mtd_info mtd[NXP_FSPI_MAX_CHIP];
553 + struct spi_nor nor[NXP_FSPI_MAX_CHIP];
554 + void __iomem *iobase;
555 + void __iomem *ahb_addr;
556 + u32 memmap_phy;
557 + u32 memmap_offs;
558 + u32 memmap_len;
559 + struct clk *clk, *clk_en;
560 + struct device *dev;
561 + struct completion c;
562 + struct nxp_fspi_devtype_data *devtype_data;
563 + u32 nor_size;
564 + u32 nor_num;
565 + u32 clk_rate;
566 + u32 spi_rx_bus_width;
567 + u32 spi_tx_bus_width;
568 + unsigned int chip_base_addr; /* We may support two chips. */
569 + bool has_second_chip;
570 + struct mutex lock;
571 + struct pm_qos_request pm_qos_req;
572 +};
573 +
574 +static inline void nxp_fspi_unlock_lut(struct nxp_fspi *fspi)
575 +{
576 + writel(FSPI_LUTKEY_VALUE, fspi->iobase + FSPI_LUTKEY);
577 + writel(FSPI_LCKER_UNLOCK, fspi->iobase + FSPI_LCKCR);
578 +}
579 +
580 +static inline void nxp_fspi_lock_lut(struct nxp_fspi *fspi)
581 +{
582 + writel(FSPI_LUTKEY_VALUE, fspi->iobase + FSPI_LUTKEY);
583 + writel(FSPI_LCKER_LOCK, fspi->iobase + FSPI_LCKCR);
584 +}
585 +
586 +static irqreturn_t nxp_fspi_irq_handler(int irq, void *dev_id)
587 +{
588 + struct nxp_fspi *fspi = dev_id;
589 + u32 reg;
590 +
591 + reg = readl(fspi->iobase + FSPI_INTR);
592 + writel(FSPI_INTR_IPCMDDONE_MASK, fspi->iobase + FSPI_INTR);
593 + if (reg & FSPI_INTR_IPCMDDONE_MASK)
594 + complete(&fspi->c);
595 +
596 + return IRQ_HANDLED;
597 +}
598 +
599 +static void nxp_fspi_init_lut(struct nxp_fspi *fspi)
600 +{
601 + void __iomem *base = fspi->iobase;
602 + struct spi_nor *nor = &fspi->nor[0];
603 + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
604 + u32 lut_base;
605 + u8 op, dm;
606 + int i;
607 +
608 + nxp_fspi_unlock_lut(fspi);
609 +
610 + /* Clear all the LUT table */
611 + for (i = 0; i < FSPI_LUT_NUM; i++)
612 + writel(0, base + FSPI_LUT_BASE + i * 4);
613 +
614 + /* Read */
615 + lut_base = SEQID_READ * 4;
616 + op = nor->read_opcode;
617 + dm = nor->read_dummy;
618 +
619 + if (fspi->spi_rx_bus_width == FSPI_OCTAL_MODE) {
620 + dm = 8;
621 + op = FSPINOR_OP_READ_1_1_8_4B;
622 + writel(LUT0(CMD, PAD1, op) | LUT1(ADDR, PAD1, addrlen),
623 + base + FSPI_LUT(lut_base));
624 + writel(LUT0(DUMMY, PAD8, dm) | LUT1(NXP_READ, PAD8, 0),
625 + base + FSPI_LUT(lut_base + 1));
626 + } else {
627 + if ((op == SPINOR_OP_READ_FAST_4B) ||
628 + (op == SPINOR_OP_READ_FAST) ||
629 + (op == SPINOR_OP_READ) ||
630 + (op == SPINOR_OP_READ_4B)) {
631 + dm = 8;
632 + writel(LUT0(CMD, PAD1, op) | LUT1(ADDR, PAD1, addrlen),
633 + base + FSPI_LUT(lut_base));
634 + writel(LUT0(DUMMY, PAD1, dm) | LUT1(NXP_READ, PAD1, 0),
635 + base + FSPI_LUT(lut_base + 1));
636 + } else if (nor->read_proto == SNOR_PROTO_1_4_4) {
637 + dev_dbg(nor->dev, "Unsupported opcode : 0x%.2x\n", op);
638 + /* TODO Add support for other Read ops. */
639 + } else {
640 + dev_dbg(nor->dev, "Unsupported opcode : 0x%.2x\n", op);
641 + }
642 + }
643 +
644 + /* Write enable */
645 + lut_base = SEQID_WREN * 4;
646 + writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + FSPI_LUT(lut_base));
647 +
648 + /* Page Program */
649 + lut_base = SEQID_PP * 4;
650 + writel(LUT0(CMD, PAD1, nor->program_opcode) | LUT1(ADDR, PAD1, addrlen),
651 + base + FSPI_LUT(lut_base));
652 + writel(LUT0(NXP_WRITE, PAD1, 0), base + FSPI_LUT(lut_base + 1));
653 +
654 + /* Read Status */
655 + lut_base = SEQID_RDSR * 4;
656 + writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(NXP_READ, PAD1, 0x1),
657 + base + FSPI_LUT(lut_base));
658 +
659 + /* Erase a sector */
660 + lut_base = SEQID_SE * 4;
661 + writel(LUT0(CMD, PAD1, nor->erase_opcode) | LUT1(ADDR, PAD1, addrlen),
662 + base + FSPI_LUT(lut_base));
663 +
664 + /* Erase the whole chip */
665 + lut_base = SEQID_CHIP_ERASE * 4;
666 + writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
667 + base + FSPI_LUT(lut_base));
668 +
669 + /* READ ID */
670 + lut_base = SEQID_RDID * 4;
671 + writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(NXP_READ, PAD1, 0x8),
672 + base + FSPI_LUT(lut_base));
673 +
674 + /* Write Register */
675 + lut_base = SEQID_WRSR * 4;
676 + writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(NXP_WRITE, PAD1, 0x2),
677 + base + FSPI_LUT(lut_base));
678 +
679 + /* Read Configuration Register */
680 + lut_base = SEQID_RDCR * 4;
681 + writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(NXP_READ, PAD1, 0x1),
682 + base + FSPI_LUT(lut_base));
683 +
684 + /* Write disable */
685 + lut_base = SEQID_WRDI * 4;
686 + writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + FSPI_LUT(lut_base));
687 +
688 + /* Enter 4 Byte Mode (Micron) */
689 + lut_base = SEQID_EN4B * 4;
690 + writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + FSPI_LUT(lut_base));
691 +
692 + /* Enter 4 Byte Mode (Spansion) */
693 + lut_base = SEQID_BRWR * 4;
694 + writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + FSPI_LUT(lut_base));
695 +
696 + /* Read EVCR register */
697 + lut_base = SEQID_RD_EVCR * 4;
698 + writel(LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
699 + base + FSPI_LUT(lut_base));
700 +
701 + /* Write EVCR register */
702 + lut_base = SEQID_WD_EVCR * 4;
703 + writel(LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
704 + base + FSPI_LUT(lut_base));
705 +
706 + /* Read Flag Status */
707 + lut_base = SEQID_RDFSR * 4;
708 + writel(LUT0(CMD, PAD1, SPINOR_OP_RDFSR) | LUT1(NXP_READ, PAD1, 0x1),
709 + base + FSPI_LUT(lut_base));
710 +
711 + nxp_fspi_lock_lut(fspi);
712 +}
713 +
714 +/* Get the SEQID for the command */
715 +static int nxp_fspi_get_seqid(struct nxp_fspi *fspi, u8 cmd)
716 +{
717 +
718 + switch (cmd) {
719 + case SPINOR_OP_READ_1_1_4_4B:
720 + case SPINOR_OP_READ_1_1_4:
721 + case SPINOR_OP_READ:
722 + case SPINOR_OP_READ_4B:
723 + case SPINOR_OP_READ_FAST:
724 + case SPINOR_OP_READ_FAST_4B:
725 + return SEQID_READ;
726 + case SPINOR_OP_WREN:
727 + return SEQID_WREN;
728 + case SPINOR_OP_WRDI:
729 + return SEQID_WRDI;
730 + case SPINOR_OP_RDSR:
731 + return SEQID_RDSR;
732 + case SPINOR_OP_RDFSR:
733 + return SEQID_RDFSR;
734 + case SPINOR_OP_BE_4K:
735 + case SPINOR_OP_SE:
736 + case SPINOR_OP_SE_4B:
737 + case SPINOR_OP_BE_4K_4B:
738 + return SEQID_SE;
739 + case SPINOR_OP_CHIP_ERASE:
740 + return SEQID_CHIP_ERASE;
741 + case SPINOR_OP_PP:
742 + case SPINOR_OP_PP_4B:
743 + return SEQID_PP;
744 + case SPINOR_OP_RDID:
745 + return SEQID_RDID;
746 + case SPINOR_OP_WRSR:
747 + return SEQID_WRSR;
748 + case SPINOR_OP_RDCR:
749 + return SEQID_RDCR;
750 + case SPINOR_OP_EN4B:
751 + return SEQID_EN4B;
752 + case SPINOR_OP_BRWR:
753 + return SEQID_BRWR;
754 + case SPINOR_OP_RD_EVCR:
755 + return SEQID_RD_EVCR;
756 + case SPINOR_OP_WD_EVCR:
757 + return SEQID_WD_EVCR;
758 + default:
759 + dev_err(fspi->dev, "Unsupported cmd 0x%.2x\n", cmd);
760 + break;
761 + }
762 + return -EINVAL;
763 +}
764 +
765 +static int
766 +nxp_fspi_runcmd(struct nxp_fspi *fspi, u8 cmd, unsigned int addr, int len)
767 +{
768 + void __iomem *base = fspi->iobase;
769 + int seqid;
770 + int seqnum = 0;
771 + u32 reg;
772 + int err;
773 + int iprxfcr = 0;
774 +
775 + iprxfcr = readl(fspi->iobase + FSPI_IPRXFCR);
776 + /* invalid RXFIFO first */
777 + iprxfcr &= ~FSPI_IPRXFCR_DMA_EN_MASK;
778 + iprxfcr = iprxfcr | FSPI_IPRXFCR_CLR_MASK;
779 + writel(iprxfcr, fspi->iobase + FSPI_IPRXFCR);
780 +
781 + init_completion(&fspi->c);
782 + dev_dbg(fspi->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
783 + fspi->chip_base_addr, addr, len, cmd);
784 +
785 + /* write address */
786 + writel(fspi->chip_base_addr + addr, base + FSPI_IPCR0);
787 +
788 + seqid = nxp_fspi_get_seqid(fspi, cmd);
789 +
790 + writel((seqnum << FSPI_IPCR1_SEQNUM_SHIFT) |
791 + (seqid << FSPI_IPCR1_SEQID_SHIFT) | len,
792 + base + FSPI_IPCR1);
793 +
794 + /* wait till controller is idle */
795 + do {
796 + reg = readl(base + FSPI_STS0);
797 + if ((reg & FSPI_STS0_ARB_IDLE_MASK) &&
798 + (reg & FSPI_STS0_SEQ_IDLE_MASK))
799 + break;
800 + udelay(1);
801 + dev_dbg(fspi->dev, "The controller is busy, 0x%x\n", reg);
802 + } while (1);
803 +
804 + /* trigger the LUT now */
805 + writel(1, base + FSPI_IPCMD);
806 +
807 + /* Wait for the interrupt. */
808 + if (!wait_for_completion_timeout(&fspi->c, msecs_to_jiffies(1000))) {
809 + dev_err(fspi->dev,
810 + "cmd 0x%.2x timeout, addr@%.8x, Status0:0x%.8x, Status1:0x%.8x\n",
811 + cmd, addr, readl(base + FSPI_STS0),
812 + readl(base + FSPI_STS1));
813 + err = -ETIMEDOUT;
814 + } else {
815 + err = 0;
816 + dev_dbg(fspi->dev, "FSPI Intr done,INTR:<0x%.8x>\n",
817 + readl(base + FSPI_INTR));
818 + }
819 +
820 + return err;
821 +}
822 +
823 +/* Read out the data from the FSPI_RBDR buffer registers. */
824 +static void nxp_fspi_read_data(struct nxp_fspi *fspi, int len, u8 *rxbuf)
825 +{
826 + int i = 0, j = 0, tmp_size = 0;
827 + int size;
828 + u32 tmp = 0;
829 +
830 + while (len > 0) {
831 +
832 + size = len / 8;
833 +
834 + for (i = 0; i < size; ++i) {
835 + /* Wait for RXFIFO available*/
836 + while (!(readl(fspi->iobase + FSPI_INTR)
837 + & FSPI_INTR_IPRXWA_MASK))
838 + ;
839 +
840 + j = 0;
841 + tmp_size = 8;
842 + while (tmp_size > 0) {
843 + tmp = 0;
844 + tmp = readl(fspi->iobase + FSPI_RFDR + j * 4);
845 + memcpy(rxbuf, &tmp, 4);
846 + tmp_size -= 4;
847 + j++;
848 + rxbuf += 4;
849 + }
850 +
851 + /* move the FIFO pointer */
852 + writel(FSPI_INTR_IPRXWA_MASK,
853 + fspi->iobase + FSPI_INTR);
854 + len -= 8;
855 + }
856 +
857 + size = len % 8;
858 +
859 + j = 0;
860 + if (size) {
861 + /* Wait for RXFIFO available*/
862 + while (!(readl(fspi->iobase + FSPI_INTR)
863 + & FSPI_INTR_IPRXWA_MASK))
864 + ;
865 +
866 + while (len > 0) {
867 + tmp = 0;
868 + size = (len < 4) ? len : 4;
869 + tmp = readl(fspi->iobase + FSPI_RFDR + j * 4);
870 + memcpy(rxbuf, &tmp, size);
871 + len -= size;
872 + j++;
873 + rxbuf += size;
874 + }
875 + }
876 +
877 + /* invalid the RXFIFO */
878 + writel(FSPI_IPRXFCR_CLR_MASK,
879 + fspi->iobase + FSPI_IPRXFCR);
880 +
881 + writel(FSPI_INTR_IPRXWA_MASK,
882 + fspi->iobase + FSPI_INTR);
883 + }
884 +}
885 +
886 +static inline void nxp_fspi_invalid(struct nxp_fspi *fspi)
887 +{
888 + u32 reg;
889 +
890 + reg = readl(fspi->iobase + FSPI_MCR0);
891 + writel(reg | FSPI_MCR0_SWRST_MASK, fspi->iobase + FSPI_MCR0);
892 +
893 + /*
894 + * The minimum delay : 1 AHB + 2 SFCK clocks.
895 + * Delay 1 us is enough.
896 + */
897 + while (readl(fspi->iobase + FSPI_MCR0) & FSPI_MCR0_SWRST_MASK)
898 + ;
899 +}
900 +
901 +static ssize_t nxp_fspi_nor_write(struct nxp_fspi *fspi,
902 + struct spi_nor *nor, u8 opcode,
903 + unsigned int to, u32 *txbuf,
904 + unsigned int count)
905 +{
906 + int ret, i, j;
907 + int size, tmp_size;
908 + u32 data = 0;
909 +
910 + dev_dbg(fspi->dev, "nor write to 0x%.8x:0x%.8x, len : %d\n",
911 + fspi->chip_base_addr, to, count);
912 +
913 + /* clear the TX FIFO. */
914 + writel(FSPI_IPTXFCR_CLR_MASK, fspi->iobase + FSPI_IPTXFCR);
915 +
916 + size = count / 8;
917 + for (i = 0; i < size; i++) {
918 + /* Wait for TXFIFO empty*/
919 + while (!(readl(fspi->iobase + FSPI_INTR)
920 + & FSPI_INTR_IPTXWE_MASK))
921 + ;
922 + j = 0;
923 + tmp_size = 8;
924 + while (tmp_size > 0) {
925 + data = 0;
926 + memcpy(&data, txbuf, 4);
927 + writel(data, fspi->iobase + FSPI_TFDR + j * 4);
928 + tmp_size -= 4;
929 + j++;
930 + txbuf += 1;
931 + }
932 +
933 + writel(FSPI_INTR_IPTXWE_MASK, fspi->iobase + FSPI_INTR);
934 + }
935 +
936 + size = count % 8;
937 + if (size) {
938 + /* Wait for TXFIFO empty*/
939 + while (!(readl(fspi->iobase + FSPI_INTR)
940 + & FSPI_INTR_IPTXWE_MASK))
941 + ;
942 +
943 + j = 0;
944 + tmp_size = 0;
945 + while (size > 0) {
946 + data = 0;
947 + tmp_size = (size < 4) ? size : 4;
948 + memcpy(&data, txbuf, tmp_size);
949 + writel(data, fspi->iobase + FSPI_TFDR + j * 4);
950 + size -= tmp_size;
951 + j++;
952 + txbuf += 1;
953 + }
954 +
955 + writel(FSPI_INTR_IPTXWE_MASK, fspi->iobase + FSPI_INTR);
956 + }
957 +
958 + /* Trigger it */
959 + ret = nxp_fspi_runcmd(fspi, opcode, to, count);
960 +
961 + if (ret == 0)
962 + return count;
963 +
964 + return ret;
965 +}
966 +
967 +static void nxp_fspi_set_map_addr(struct nxp_fspi *fspi)
968 +{
969 + int nor_size = fspi->nor_size >> 10;
970 + void __iomem *base = fspi->iobase;
971 +
972 + /*
973 + * Supporting same flash device as slaves on different chip-select.
974 + * As SAMEDEVICEEN bit set, by default, in mcr2 reg then need not to
975 + * configure FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register as setting for
976 + * these would be ignored.
977 + * Need to Reset SAMEDEVICEEN bit in mcr2 reg, when require to add
978 + * support for different flashes.
979 + */
980 + writel(nor_size, base + FSPI_FLSHA1CR0);
981 + writel(0, base + FSPI_FLSHA2CR0);
982 + writel(0, base + FSPI_FLSHB1CR0);
983 + writel(0, base + FSPI_FLSHB2CR0);
984 +}
985 +
986 +static void nxp_fspi_init_ahb_read(struct nxp_fspi *fspi)
987 +{
988 + void __iomem *base = fspi->iobase;
989 + struct spi_nor *nor = &fspi->nor[0];
990 + int i = 0;
991 + int seqid;
992 +
993 + /* AHB configuration for access buffer 0~7. */
994 + for (i = 0; i < 7; i++)
995 + writel(0, base + FSPI_AHBRX_BUF0CR0 + 4 * i);
996 +
997 + /*
998 + * Set ADATSZ with the maximum AHB buffer size to improve the read
999 + * performance.
1000 + */
1001 + writel((fspi->devtype_data->ahb_buf_size / 8 |
1002 + FSPI_AHBRXBUF0CR7_PREF_MASK), base + FSPI_AHBRX_BUF7CR0);
1003 +
1004 + /* prefetch and no start address alignment limitation */
1005 + writel(FSPI_AHBCR_PREF_EN_MASK | FSPI_AHBCR_RDADDROPT_MASK,
1006 + base + FSPI_AHBCR);
1007 +
1008 +
1009 + /* Set the default lut sequence for AHB Read. */
1010 + seqid = nxp_fspi_get_seqid(fspi, nor->read_opcode);
1011 + writel(seqid, base + FSPI_FLSHA1CR2);
1012 +}
1013 +
1014 +/* This function was used to prepare and enable FSPI clock */
1015 +static int nxp_fspi_clk_prep_enable(struct nxp_fspi *fspi)
1016 +{
1017 + int ret;
1018 +
1019 + ret = clk_prepare_enable(fspi->clk_en);
1020 + if (ret)
1021 + return ret;
1022 +
1023 + ret = clk_prepare_enable(fspi->clk);
1024 + if (ret) {
1025 + clk_disable_unprepare(fspi->clk_en);
1026 + return ret;
1027 + }
1028 +
1029 + return 0;
1030 +}
1031 +
1032 +/* This function was used to disable and unprepare FSPI clock */
1033 +static void nxp_fspi_clk_disable_unprep(struct nxp_fspi *fspi)
1034 +{
1035 + clk_disable_unprepare(fspi->clk);
1036 + clk_disable_unprepare(fspi->clk_en);
1037 +}
1038 +
1039 +/* We use this function to do some basic init for spi_nor_scan(). */
1040 +static int nxp_fspi_nor_setup(struct nxp_fspi *fspi)
1041 +{
1042 + void __iomem *base = fspi->iobase;
1043 + u32 reg;
1044 +
1045 + /* Reset the module */
1046 + writel(FSPI_MCR0_SWRST_MASK, base + FSPI_MCR0);
1047 + do {
1048 + udelay(1);
1049 + } while (0x1 & readl(base + FSPI_MCR0));
1050 +
1051 + /* Disable the module */
1052 + writel(FSPI_MCR0_MDIS_MASK, base + FSPI_MCR0);
1053 +
1054 + /* Reset the DLL register to default value */
1055 + writel(FSPI_DLLACR_OVRDEN_MASK, base + FSPI_DLLACR);
1056 + writel(FSPI_DLLBCR_OVRDEN_MASK, base + FSPI_DLLBCR);
1057 +
1058 + /* enable module */
1059 + writel(FSPI_MCR0_AHB_TIMEOUT_MASK | FSPI_MCR0_IP_TIMEOUT_MASK,
1060 + base + FSPI_MCR0);
1061 +
1062 + /* Read the register value */
1063 + reg = readl(base + FSPI_MCR0);
1064 +
1065 + /* Init the LUT table. */
1066 + nxp_fspi_init_lut(fspi);
1067 +
1068 + /* enable the interrupt */
1069 + writel(FSPI_INTEN_IPCMDDONE_MASK, fspi->iobase + FSPI_INTEN);
1070 + return 0;
1071 +}
1072 +
1073 +static int nxp_fspi_nor_setup_last(struct nxp_fspi *fspi)
1074 +{
1075 + unsigned long rate = fspi->clk_rate;
1076 + int ret;
1077 +
1078 + /* disable and unprepare clock to avoid glitch pass to controller */
1079 + nxp_fspi_clk_disable_unprep(fspi);
1080 +
1081 + ret = clk_set_rate(fspi->clk, rate);
1082 + if (ret)
1083 + return ret;
1084 +
1085 + ret = nxp_fspi_clk_prep_enable(fspi);
1086 + if (ret)
1087 + return ret;
1088 +
1089 + /* Init the LUT table again. */
1090 + nxp_fspi_init_lut(fspi);
1091 +
1092 + /* Init for AHB read */
1093 + nxp_fspi_init_ahb_read(fspi);
1094 +
1095 + return 0;
1096 +}
1097 +
1098 +static void nxp_fspi_set_base_addr(struct nxp_fspi *fspi,
1099 + struct spi_nor *nor)
1100 +{
1101 + fspi->chip_base_addr = fspi->nor_size * (nor - fspi->nor);
1102 +}
1103 +
1104 +static int nxp_fspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
1105 + int len)
1106 +{
1107 + int ret;
1108 + struct nxp_fspi *fspi = nor->priv;
1109 +
1110 + ret = nxp_fspi_runcmd(fspi, opcode, 0, len);
1111 + if (ret)
1112 + return ret;
1113 +
1114 + nxp_fspi_read_data(fspi, len, buf);
1115 + return 0;
1116 +}
1117 +
1118 +static int nxp_fspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
1119 + int len)
1120 +{
1121 + struct nxp_fspi *fspi = nor->priv;
1122 + int ret;
1123 +
1124 + if (!buf) {
1125 + ret = nxp_fspi_runcmd(fspi, opcode, 0, 1);
1126 + if (ret)
1127 + return ret;
1128 +
1129 + if (opcode == SPINOR_OP_CHIP_ERASE)
1130 + nxp_fspi_invalid(fspi);
1131 +
1132 + } else if (len > 0) {
1133 + ret = nxp_fspi_nor_write(fspi, nor, opcode, 0,
1134 + (u32 *)buf, len);
1135 + } else {
1136 + dev_err(fspi->dev, "invalid cmd %d\n", opcode);
1137 + ret = -EINVAL;
1138 + }
1139 +
1140 + return ret;
1141 +}
1142 +
1143 +static ssize_t nxp_fspi_write(struct spi_nor *nor, loff_t to,
1144 + size_t len, const u_char *buf)
1145 +{
1146 + struct nxp_fspi *fspi = nor->priv;
1147 + ssize_t tx_size = 0, act_wrt = 0, ret = 0;
1148 +
1149 + while (len > 0) {
1150 + tx_size = (len > TX_IPBUF_SIZE) ? TX_IPBUF_SIZE : len;
1151 +
1152 + act_wrt = nxp_fspi_nor_write(fspi, nor, nor->program_opcode, to,
1153 + (u32 *)buf, tx_size);
1154 + len -= tx_size;
1155 + to += tx_size;
1156 + ret += act_wrt;
1157 + }
1158 +
1159 + /* invalid the data in the AHB buffer. */
1160 + nxp_fspi_invalid(fspi);
1161 + return ret;
1162 +}
1163 +
1164 +static ssize_t nxp_fspi_read(struct spi_nor *nor, loff_t from,
1165 + size_t len, u_char *buf)
1166 +{
1167 + struct nxp_fspi *fspi = nor->priv;
1168 +
1169 + /* if necessary, ioremap buffer before AHB read, */
1170 + if (!fspi->ahb_addr) {
1171 + fspi->memmap_offs = fspi->chip_base_addr + from;
1172 + fspi->memmap_len = len > FSPI_MIN_IOMAP ?
1173 + len : FSPI_MIN_IOMAP;
1174 +
1175 + fspi->ahb_addr = ioremap_nocache(
1176 + fspi->memmap_phy + fspi->memmap_offs,
1177 + fspi->memmap_len);
1178 + if (!fspi->ahb_addr) {
1179 + dev_err(fspi->dev, "ioremap failed\n");
1180 + return -ENOMEM;
1181 + }
1182 + /* ioremap if the data requested is out of range */
1183 + } else if (fspi->chip_base_addr + from < fspi->memmap_offs
1184 + || fspi->chip_base_addr + from + len >
1185 + fspi->memmap_offs + fspi->memmap_len) {
1186 + iounmap(fspi->ahb_addr);
1187 +
1188 + fspi->memmap_offs = fspi->chip_base_addr + from;
1189 + fspi->memmap_len = len > FSPI_MIN_IOMAP ?
1190 + len : FSPI_MIN_IOMAP;
1191 + fspi->ahb_addr = ioremap_nocache(
1192 + fspi->memmap_phy + fspi->memmap_offs,
1193 + fspi->memmap_len);
1194 + if (!fspi->ahb_addr) {
1195 + dev_err(fspi->dev, "ioremap failed\n");
1196 + return -ENOMEM;
1197 + }
1198 + }
1199 +
1200 + dev_dbg(fspi->dev, "cmd [%x],read from %p, len:%zd\n",
1201 + nor->read_opcode, fspi->ahb_addr + fspi->chip_base_addr
1202 + + from - fspi->memmap_offs, len);
1203 +
1204 + /* Read out the data directly from the AHB buffer.*/
1205 + memcpy_toio(buf, fspi->ahb_addr + fspi->chip_base_addr
1206 + + from - fspi->memmap_offs, len);
1207 +
1208 + return len;
1209 +}
1210 +
1211 +static int nxp_fspi_erase(struct spi_nor *nor, loff_t offs)
1212 +{
1213 + struct nxp_fspi *fspi = nor->priv;
1214 + int ret;
1215 +
1216 + dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
1217 + nor->mtd.erasesize / 1024, fspi->chip_base_addr, (u32)offs);
1218 +
1219 + ret = nxp_fspi_runcmd(fspi, nor->erase_opcode, offs, 0);
1220 + if (ret)
1221 + return ret;
1222 +
1223 + nxp_fspi_invalid(fspi);
1224 + return 0;
1225 +}
1226 +
1227 +static int nxp_fspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
1228 +{
1229 + struct nxp_fspi *fspi = nor->priv;
1230 + int ret;
1231 +
1232 + mutex_lock(&fspi->lock);
1233 +
1234 + ret = nxp_fspi_clk_prep_enable(fspi);
1235 + if (ret)
1236 + goto err_mutex;
1237 +
1238 + nxp_fspi_set_base_addr(fspi, nor);
1239 + return 0;
1240 +
1241 +err_mutex:
1242 + mutex_unlock(&fspi->lock);
1243 + return ret;
1244 +}
1245 +
1246 +static void nxp_fspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
1247 +{
1248 + struct nxp_fspi *fspi = nor->priv;
1249 +
1250 + nxp_fspi_clk_disable_unprep(fspi);
1251 + mutex_unlock(&fspi->lock);
1252 +}
1253 +
1254 +static const struct of_device_id nxp_fspi_dt_ids[] = {
1255 + { .compatible = "nxp,lx2160a-fspi", .data = (void *)&lx2160a_data, },
1256 + { /* sentinel */ }
1257 +};
1258 +MODULE_DEVICE_TABLE(of, nxp_fspi_dt_ids);
1259 +
1260 +static int nxp_fspi_probe(struct platform_device *pdev)
1261 +{
1262 + struct spi_nor_hwcaps hwcaps = {
1263 + .mask = SPINOR_OP_READ_FAST_4B |
1264 + SPINOR_OP_READ_4B |
1265 + SNOR_HWCAPS_PP
1266 + };
1267 + struct device_node *np = pdev->dev.of_node;
1268 + struct device *dev = &pdev->dev;
1269 + struct nxp_fspi *fspi;
1270 + struct resource *res;
1271 + struct spi_nor *nor;
1272 + struct mtd_info *mtd;
1273 + int ret, i = 0;
1274 + int find_node = 0;
1275 +
1276 + const struct of_device_id *of_id =
1277 + of_match_device(nxp_fspi_dt_ids, &pdev->dev);
1278 +
1279 + fspi = devm_kzalloc(dev, sizeof(*fspi), GFP_KERNEL);
1280 + if (!fspi)
1281 + return -ENOMEM;
1282 +
1283 + fspi->nor_num = of_get_child_count(dev->of_node);
1284 + if (!fspi->nor_num || fspi->nor_num > 4)
1285 + return -ENODEV;
1286 +
1287 + fspi->dev = dev;
1288 + fspi->devtype_data = (struct nxp_fspi_devtype_data *)of_id->data;
1289 + platform_set_drvdata(pdev, fspi);
1290 +
1291 + /* find the resources */
1292 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "FSPI");
1293 + if (!res) {
1294 + dev_err(dev, "FSPI get resource IORESOURCE_MEM failed\n");
1295 + return -ENODEV;
1296 + }
1297 +
1298 + fspi->iobase = devm_ioremap_resource(dev, res);
1299 + if (IS_ERR(fspi->iobase))
1300 + return PTR_ERR(fspi->iobase);
1301 +
1302 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1303 + "FSPI-memory");
1304 + if (!res) {
1305 + dev_err(dev,
1306 + "FSPI-memory get resource IORESOURCE_MEM failed\n");
1307 + return -ENODEV;
1308 + }
1309 +
1310 + if (!devm_request_mem_region(dev, res->start, resource_size(res),
1311 + res->name)) {
1312 + dev_err(dev, "can't request region for resource %pR\n", res);
1313 + return -EBUSY;
1314 + }
1315 +
1316 + fspi->memmap_phy = res->start;
1317 +
1318 + /* find the clocks */
1319 + fspi->clk_en = devm_clk_get(dev, "fspi_en");
1320 + if (IS_ERR(fspi->clk_en))
1321 + return PTR_ERR(fspi->clk_en);
1322 +
1323 + fspi->clk = devm_clk_get(dev, "fspi");
1324 + if (IS_ERR(fspi->clk))
1325 + return PTR_ERR(fspi->clk);
1326 +
1327 + ret = nxp_fspi_clk_prep_enable(fspi);
1328 + if (ret) {
1329 + dev_err(dev, "can not enable the clock\n");
1330 + goto clk_failed;
1331 + }
1332 +
1333 + /* find the irq */
1334 + ret = platform_get_irq(pdev, 0);
1335 + if (ret < 0) {
1336 + dev_err(dev, "failed to get the irq: %d\n", ret);
1337 + goto irq_failed;
1338 + }
1339 +
1340 + ret = devm_request_irq(dev, ret,
1341 + nxp_fspi_irq_handler, 0, pdev->name, fspi);
1342 + if (ret) {
1343 + dev_err(dev, "failed to request irq: %d\n", ret);
1344 + goto irq_failed;
1345 + }
1346 +
1347 + ret = nxp_fspi_nor_setup(fspi);
1348 + if (ret)
1349 + goto irq_failed;
1350 +
1351 + if (of_get_property(np, "nxp,fspi-has-second-chip", NULL))
1352 + fspi->has_second_chip = true;
1353 +
1354 + mutex_init(&fspi->lock);
1355 +
1356 + find_node = 0;
1357 + /* iterate the subnodes. */
1358 + for_each_available_child_of_node(dev->of_node, np) {
1359 + /* skip the holes */
1360 + if (!fspi->has_second_chip)
1361 + i *= 2;
1362 +
1363 + nor = &fspi->nor[i];
1364 + mtd = &nor->mtd;
1365 +
1366 + nor->dev = dev;
1367 + spi_nor_set_flash_node(nor, np);
1368 + nor->priv = fspi;
1369 +
1370 + /* fill the hooks */
1371 + nor->read_reg = nxp_fspi_read_reg;
1372 + nor->write_reg = nxp_fspi_write_reg;
1373 + nor->read = nxp_fspi_read;
1374 + nor->write = nxp_fspi_write;
1375 + nor->erase = nxp_fspi_erase;
1376 +
1377 + nor->prepare = nxp_fspi_prep;
1378 + nor->unprepare = nxp_fspi_unprep;
1379 +
1380 + ret = of_property_read_u32(np, "spi-max-frequency",
1381 + &fspi->clk_rate);
1382 + if (ret < 0)
1383 + goto next_node;
1384 +
1385 + /* set the chip address for READID */
1386 + nxp_fspi_set_base_addr(fspi, nor);
1387 +
1388 + ret = of_property_read_u32(np, "spi-rx-bus-width",
1389 + &fspi->spi_rx_bus_width);
1390 + if (ret < 0)
1391 + fspi->spi_rx_bus_width = FSPI_SINGLE_MODE;
1392 +
1393 + ret = of_property_read_u32(np, "spi-tx-bus-width",
1394 + &fspi->spi_tx_bus_width);
1395 + if (ret < 0)
1396 + fspi->spi_tx_bus_width = FSPI_SINGLE_MODE;
1397 +
1398 + ret = spi_nor_scan(nor, NULL, &hwcaps);
1399 + if (ret)
1400 + goto next_node;
1401 +
1402 + ret = mtd_device_register(mtd, NULL, 0);
1403 + if (ret)
1404 + goto next_node;
1405 +
1406 + /* Set the correct NOR size now. */
1407 + if (fspi->nor_size == 0) {
1408 + fspi->nor_size = mtd->size;
1409 +
1410 + /* Map the SPI NOR to accessiable address */
1411 + nxp_fspi_set_map_addr(fspi);
1412 + }
1413 +
1414 + /*
1415 + * The write is working in the unit of the TX FIFO,
1416 + * not in the unit of the SPI NOR's page size.
1417 + *
1418 + * So shrink the spi_nor->page_size if it is larger then the
1419 + * TX FIFO.
1420 + */
1421 + if (nor->page_size > fspi->devtype_data->txfifo)
1422 + nor->page_size = fspi->devtype_data->txfifo;
1423 +
1424 + find_node++;
1425 +next_node:
1426 + i++;
1427 + }
1428 +
1429 + if (find_node == 0)
1430 + goto mutex_failed;
1431 +
1432 + /* finish the rest init. */
1433 + ret = nxp_fspi_nor_setup_last(fspi);
1434 + if (ret)
1435 + goto last_init_failed;
1436 +
1437 + nxp_fspi_clk_disable_unprep(fspi);
1438 + return 0;
1439 +
1440 +last_init_failed:
1441 + for (i = 0; i < fspi->nor_num; i++) {
1442 + /* skip the holes */
1443 + if (!fspi->has_second_chip)
1444 + i *= 2;
1445 + mtd_device_unregister(&fspi->mtd[i]);
1446 + }
1447 +mutex_failed:
1448 + mutex_destroy(&fspi->lock);
1449 +irq_failed:
1450 + nxp_fspi_clk_disable_unprep(fspi);
1451 +clk_failed:
1452 + dev_err(dev, "NXP FSPI probe failed\n");
1453 + return ret;
1454 +}
1455 +
1456 +static int nxp_fspi_remove(struct platform_device *pdev)
1457 +{
1458 + struct nxp_fspi *fspi = platform_get_drvdata(pdev);
1459 + int i;
1460 +
1461 + for (i = 0; i < fspi->nor_num; i++) {
1462 + /* skip the holes */
1463 + if (!fspi->has_second_chip)
1464 + i *= 2;
1465 + mtd_device_unregister(&fspi->nor[i].mtd);
1466 + }
1467 +
1468 + /* disable the hardware */
1469 + writel(FSPI_MCR0_MDIS_MASK, fspi->iobase + FSPI_MCR0);
1470 +
1471 + mutex_destroy(&fspi->lock);
1472 +
1473 + if (fspi->ahb_addr)
1474 + iounmap(fspi->ahb_addr);
1475 +
1476 + return 0;
1477 +}
1478 +
1479 +static int nxp_fspi_suspend(struct platform_device *pdev, pm_message_t state)
1480 +{
1481 + return 0;
1482 +}
1483 +
1484 +static int nxp_fspi_resume(struct platform_device *pdev)
1485 +{
1486 + return 0;
1487 +}
1488 +
1489 +static struct platform_driver nxp_fspi_driver = {
1490 + .driver = {
1491 + .name = "nxp-fspi",
1492 + .bus = &platform_bus_type,
1493 + .of_match_table = nxp_fspi_dt_ids,
1494 + },
1495 + .probe = nxp_fspi_probe,
1496 + .remove = nxp_fspi_remove,
1497 + .suspend = nxp_fspi_suspend,
1498 + .resume = nxp_fspi_resume,
1499 +};
1500 +module_platform_driver(nxp_fspi_driver);
1501 +
1502 +MODULE_DESCRIPTION("NXP FSPI Controller Driver");
1503 +MODULE_AUTHOR("NXP Semiconductor");
1504 +MODULE_LICENSE("GPL v2");
1505 --- a/drivers/mtd/spi-nor/spi-nor.c
1506 +++ b/drivers/mtd/spi-nor/spi-nor.c
1507 @@ -269,6 +269,7 @@ static inline int set_4byte(struct spi_n
1508 u8 cmd;
1509
1510 switch (JEDEC_MFR(info)) {
1511 + case SNOR_MFR_ST:
1512 case SNOR_MFR_MICRON:
1513 /* Some Micron need WREN command; all will accept it */
1514 need_wren = true;
1515 @@ -1039,7 +1040,7 @@ static const struct flash_info spi_nor_i
1516 { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1517 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
1518
1519 - /* Micron */
1520 + /* Micron <--> ST Micro */
1521 { "n25q016a", INFO(0x20bb15, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_QUAD_READ) },
1522 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1523 { "n25q032a", INFO(0x20bb16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
1524 @@ -1054,6 +1055,12 @@ static const struct flash_info spi_nor_i
1525 { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1526 { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
1527
1528 + /* Micron */
1529 + {
1530 + "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
1531 + SECT_4K | USE_FSR | SPI_NOR_4B_OPCODES)
1532 + },
1533 +
1534 /* PMC */
1535 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
1536 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
1537 @@ -2431,6 +2438,7 @@ static int spi_nor_init_params(struct sp
1538 params->quad_enable = macronix_quad_enable;
1539 break;
1540
1541 + case SNOR_MFR_ST:
1542 case SNOR_MFR_MICRON:
1543 break;
1544
1545 @@ -2749,7 +2757,8 @@ int spi_nor_scan(struct spi_nor *nor, co
1546 mtd->_read = spi_nor_read;
1547
1548 /* NOR protection support for STmicro/Micron chips and similar */
1549 - if (JEDEC_MFR(info) == SNOR_MFR_MICRON ||
1550 + if (JEDEC_MFR(info) == SNOR_MFR_ST ||
1551 + JEDEC_MFR(info) == SNOR_MFR_MICRON ||
1552 JEDEC_MFR(info) == SNOR_MFR_WINBOND ||
1553 info->flags & SPI_NOR_HAS_LOCK) {
1554 nor->flash_lock = stm_lock;
1555 --- a/include/linux/mtd/cfi.h
1556 +++ b/include/linux/mtd/cfi.h
1557 @@ -377,6 +377,7 @@ struct cfi_fixup {
1558 #define CFI_MFR_SHARP 0x00B0
1559 #define CFI_MFR_SST 0x00BF
1560 #define CFI_MFR_ST 0x0020 /* STMicroelectronics */
1561 +#define CFI_MFR_MICRON 0x002C /* Micron */
1562 #define CFI_MFR_TOSHIBA 0x0098
1563 #define CFI_MFR_WINBOND 0x00DA
1564
1565 --- a/include/linux/mtd/spi-nor.h
1566 +++ b/include/linux/mtd/spi-nor.h
1567 @@ -23,7 +23,8 @@
1568 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
1569 #define SNOR_MFR_GIGADEVICE 0xc8
1570 #define SNOR_MFR_INTEL CFI_MFR_INTEL
1571 -#define SNOR_MFR_MICRON CFI_MFR_ST /* ST Micro <--> Micron */
1572 +#define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */
1573 +#define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */
1574 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
1575 #define SNOR_MFR_SPANSION CFI_MFR_AMD
1576 #define SNOR_MFR_SST CFI_MFR_SST
OpenWrt Source Repository