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layerscape: update patches-4.14 to LSDK 19.03
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.14 / 816-pcie-support-layerscape.patch
1 From c54a010fe105281259b996d318ed85efc4103fee Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 6 May 2019 15:18:05 +0800
4 Subject: [PATCH] pcie: support layerscape
5
6 This is an integrated patch of pcie for layerscape
7
8 Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
9 Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
10 Signed-off-by: Biwen Li <biwen.li@nxp.com>
11 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
12 Signed-off-by: Christoph Hellwig <hch@lst.de>
13 Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
14 Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
15 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
16 Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
17 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
18 Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
19 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
20 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
22 Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
23 Signed-off-by: Po Liu <po.liu@nxp.com>
24 Signed-off-by: Rob Herring <robh@kernel.org>
25 Signed-off-by: Rolf Evers-Fischer <rolf.evers.fischer@aptiv.com>
26 Signed-off-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
27 Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
28 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
29 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
30 ---
31 arch/arm/kernel/bios32.c | 43 ++
32 arch/arm64/kernel/pci.c | 43 ++
33 drivers/misc/pci_endpoint_test.c | 332 ++++++++++---
34 drivers/pci/Kconfig | 1 +
35 drivers/pci/dwc/Kconfig | 39 +-
36 drivers/pci/dwc/Makefile | 2 +-
37 drivers/pci/dwc/pci-dra7xx.c | 9 -
38 drivers/pci/dwc/pci-layerscape-ep.c | 146 ++++++
39 drivers/pci/dwc/pci-layerscape.c | 12 +
40 drivers/pci/dwc/pcie-designware-ep.c | 338 ++++++++++++--
41 drivers/pci/dwc/pcie-designware-host.c | 5 +-
42 drivers/pci/dwc/pcie-designware-plat.c | 159 ++++++-
43 drivers/pci/dwc/pcie-designware.c | 5 +-
44 drivers/pci/dwc/pcie-designware.h | 57 ++-
45 drivers/pci/endpoint/Kconfig | 1 +
46 drivers/pci/endpoint/Makefile | 1 +
47 drivers/pci/endpoint/functions/Kconfig | 1 +
48 drivers/pci/endpoint/functions/Makefile | 1 +
49 drivers/pci/endpoint/functions/pci-epf-test.c | 191 +++++---
50 drivers/pci/endpoint/pci-ep-cfs.c | 95 +++-
51 drivers/pci/endpoint/pci-epc-core.c | 159 +++++--
52 drivers/pci/endpoint/pci-epc-mem.c | 13 +-
53 drivers/pci/endpoint/pci-epf-core.c | 116 +++--
54 drivers/pci/host/pci-host-common.c | 8 -
55 drivers/pci/host/pcie-xilinx-nwl.c | 9 -
56 drivers/pci/host/pcie-xilinx.c | 7 -
57 drivers/pci/mobiveil/Kconfig | 50 ++
58 drivers/pci/mobiveil/Makefile | 7 +
59 drivers/pci/mobiveil/pci-layerscape-gen4-ep.c | 178 +++++++
60 drivers/pci/mobiveil/pci-layerscape-gen4.c | 292 ++++++++++++
61 drivers/pci/mobiveil/pcie-mobiveil-ep.c | 512 +++++++++++++++++++++
62 drivers/pci/mobiveil/pcie-mobiveil-host.c | 640 ++++++++++++++++++++++++++
63 drivers/pci/mobiveil/pcie-mobiveil-plat.c | 54 +++
64 drivers/pci/mobiveil/pcie-mobiveil.c | 334 ++++++++++++++
65 drivers/pci/mobiveil/pcie-mobiveil.h | 296 ++++++++++++
66 drivers/pci/pcie/portdrv_core.c | 29 ++
67 drivers/pci/quirks.c | 15 +
68 include/linux/pci-ep-cfs.h | 5 +-
69 include/linux/pci-epc.h | 73 +--
70 include/linux/pci-epf.h | 12 +-
71 include/linux/pci.h | 1 +
72 include/uapi/linux/pcitest.h | 3 +
73 tools/pci/pcitest.c | 51 +-
74 tools/pci/pcitest.sh | 15 +
75 44 files changed, 3917 insertions(+), 443 deletions(-)
76 create mode 100644 drivers/pci/dwc/pci-layerscape-ep.c
77 create mode 100644 drivers/pci/mobiveil/Kconfig
78 create mode 100644 drivers/pci/mobiveil/Makefile
79 create mode 100644 drivers/pci/mobiveil/pci-layerscape-gen4-ep.c
80 create mode 100644 drivers/pci/mobiveil/pci-layerscape-gen4.c
81 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil-ep.c
82 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil-host.c
83 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil-plat.c
84 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil.c
85 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil.h
86
87 --- a/arch/arm/kernel/bios32.c
88 +++ b/arch/arm/kernel/bios32.c
89 @@ -12,6 +12,8 @@
90 #include <linux/slab.h>
91 #include <linux/init.h>
92 #include <linux/io.h>
93 +#include <linux/of_irq.h>
94 +#include <linux/pcieport_if.h>
95
96 #include <asm/mach-types.h>
97 #include <asm/mach/map.h>
98 @@ -65,6 +67,47 @@ void pcibios_report_status(u_int status_
99 }
100
101 /*
102 + * Check device tree if the service interrupts are there
103 + */
104 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
105 +{
106 + int ret, count = 0;
107 + struct device_node *np = NULL;
108 +
109 + if (dev->bus->dev.of_node)
110 + np = dev->bus->dev.of_node;
111 +
112 + if (np == NULL)
113 + return 0;
114 +
115 + if (!IS_ENABLED(CONFIG_OF_IRQ))
116 + return 0;
117 +
118 + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
119 + * request irq for aer
120 + */
121 + if (mask & PCIE_PORT_SERVICE_AER) {
122 + ret = of_irq_get_byname(np, "aer");
123 + if (ret > 0) {
124 + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
125 + count++;
126 + }
127 + }
128 +
129 + if (mask & PCIE_PORT_SERVICE_PME) {
130 + ret = of_irq_get_byname(np, "pme");
131 + if (ret > 0) {
132 + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
133 + count++;
134 + }
135 + }
136 +
137 + /* TODO: add more service interrupts if there it is in the device tree*/
138 +
139 + return count;
140 +}
141 +
142 +/*
143 * We don't use this to fix the device, but initialisation of it.
144 * It's not the correct use for this, but it works.
145 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
146 --- a/arch/arm64/kernel/pci.c
147 +++ b/arch/arm64/kernel/pci.c
148 @@ -17,6 +17,8 @@
149 #include <linux/mm.h>
150 #include <linux/of_pci.h>
151 #include <linux/of_platform.h>
152 +#include <linux/of_irq.h>
153 +#include <linux/pcieport_if.h>
154 #include <linux/pci.h>
155 #include <linux/pci-acpi.h>
156 #include <linux/pci-ecam.h>
157 @@ -36,6 +38,47 @@ int pcibios_alloc_irq(struct pci_dev *de
158 #endif
159
160 /*
161 + * Check device tree if the service interrupts are there
162 + */
163 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
164 +{
165 + int ret, count = 0;
166 + struct device_node *np = NULL;
167 +
168 + if (dev->bus->dev.of_node)
169 + np = dev->bus->dev.of_node;
170 +
171 + if (np == NULL)
172 + return 0;
173 +
174 + if (!IS_ENABLED(CONFIG_OF_IRQ))
175 + return 0;
176 +
177 + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
178 + * request irq for aer
179 + */
180 + if (mask & PCIE_PORT_SERVICE_AER) {
181 + ret = of_irq_get_byname(np, "aer");
182 + if (ret > 0) {
183 + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
184 + count++;
185 + }
186 + }
187 +
188 + if (mask & PCIE_PORT_SERVICE_PME) {
189 + ret = of_irq_get_byname(np, "pme");
190 + if (ret > 0) {
191 + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
192 + count++;
193 + }
194 + }
195 +
196 + /* TODO: add more service interrupts if there it is in the device tree*/
197 +
198 + return count;
199 +}
200 +
201 +/*
202 * raw_pci_read/write - Platform-specific PCI config space access.
203 */
204 int raw_pci_read(unsigned int domain, unsigned int bus,
205 --- a/drivers/misc/pci_endpoint_test.c
206 +++ b/drivers/misc/pci_endpoint_test.c
207 @@ -35,38 +35,45 @@
208
209 #include <uapi/linux/pcitest.h>
210
211 -#define DRV_MODULE_NAME "pci-endpoint-test"
212 +#define DRV_MODULE_NAME "pci-endpoint-test"
213
214 -#define PCI_ENDPOINT_TEST_MAGIC 0x0
215 +#define IRQ_TYPE_UNDEFINED -1
216 +#define IRQ_TYPE_LEGACY 0
217 +#define IRQ_TYPE_MSI 1
218 +#define IRQ_TYPE_MSIX 2
219 +
220 +#define PCI_ENDPOINT_TEST_MAGIC 0x0
221 +
222 +#define PCI_ENDPOINT_TEST_COMMAND 0x4
223 +#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
224 +#define COMMAND_RAISE_MSI_IRQ BIT(1)
225 +#define COMMAND_RAISE_MSIX_IRQ BIT(2)
226 +#define COMMAND_READ BIT(3)
227 +#define COMMAND_WRITE BIT(4)
228 +#define COMMAND_COPY BIT(5)
229 +
230 +#define PCI_ENDPOINT_TEST_STATUS 0x8
231 +#define STATUS_READ_SUCCESS BIT(0)
232 +#define STATUS_READ_FAIL BIT(1)
233 +#define STATUS_WRITE_SUCCESS BIT(2)
234 +#define STATUS_WRITE_FAIL BIT(3)
235 +#define STATUS_COPY_SUCCESS BIT(4)
236 +#define STATUS_COPY_FAIL BIT(5)
237 +#define STATUS_IRQ_RAISED BIT(6)
238 +#define STATUS_SRC_ADDR_INVALID BIT(7)
239 +#define STATUS_DST_ADDR_INVALID BIT(8)
240
241 -#define PCI_ENDPOINT_TEST_COMMAND 0x4
242 -#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
243 -#define COMMAND_RAISE_MSI_IRQ BIT(1)
244 -#define MSI_NUMBER_SHIFT 2
245 -/* 6 bits for MSI number */
246 -#define COMMAND_READ BIT(8)
247 -#define COMMAND_WRITE BIT(9)
248 -#define COMMAND_COPY BIT(10)
249 -
250 -#define PCI_ENDPOINT_TEST_STATUS 0x8
251 -#define STATUS_READ_SUCCESS BIT(0)
252 -#define STATUS_READ_FAIL BIT(1)
253 -#define STATUS_WRITE_SUCCESS BIT(2)
254 -#define STATUS_WRITE_FAIL BIT(3)
255 -#define STATUS_COPY_SUCCESS BIT(4)
256 -#define STATUS_COPY_FAIL BIT(5)
257 -#define STATUS_IRQ_RAISED BIT(6)
258 -#define STATUS_SRC_ADDR_INVALID BIT(7)
259 -#define STATUS_DST_ADDR_INVALID BIT(8)
260 -
261 -#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc
262 +#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
263 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
264
265 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
266 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
267
268 -#define PCI_ENDPOINT_TEST_SIZE 0x1c
269 -#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
270 +#define PCI_ENDPOINT_TEST_SIZE 0x1c
271 +#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
272 +
273 +#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
274 +#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
275
276 static DEFINE_IDA(pci_endpoint_test_ida);
277
278 @@ -77,6 +84,10 @@ static bool no_msi;
279 module_param(no_msi, bool, 0444);
280 MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
281
282 +static int irq_type = IRQ_TYPE_MSI;
283 +module_param(irq_type, int, 0444);
284 +MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
285 +
286 enum pci_barno {
287 BAR_0,
288 BAR_1,
289 @@ -92,6 +103,7 @@ struct pci_endpoint_test {
290 void __iomem *bar[6];
291 struct completion irq_raised;
292 int last_irq;
293 + int num_irqs;
294 /* mutex to protect the ioctls */
295 struct mutex mutex;
296 struct miscdevice miscdev;
297 @@ -102,7 +114,7 @@ struct pci_endpoint_test {
298 struct pci_endpoint_test_data {
299 enum pci_barno test_reg_bar;
300 size_t alignment;
301 - bool no_msi;
302 + int irq_type;
303 };
304
305 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
306 @@ -146,6 +158,100 @@ static irqreturn_t pci_endpoint_test_irq
307 return IRQ_HANDLED;
308 }
309
310 +static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
311 +{
312 + struct pci_dev *pdev = test->pdev;
313 +
314 + pci_free_irq_vectors(pdev);
315 +}
316 +
317 +static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
318 + int type)
319 +{
320 + int irq = -1;
321 + struct pci_dev *pdev = test->pdev;
322 + struct device *dev = &pdev->dev;
323 + bool res = true;
324 +
325 + switch (type) {
326 + case IRQ_TYPE_LEGACY:
327 + irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
328 + if (irq < 0)
329 + dev_err(dev, "Failed to get Legacy interrupt\n");
330 + break;
331 + case IRQ_TYPE_MSI:
332 + irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
333 + if (irq < 0)
334 + dev_err(dev, "Failed to get MSI interrupts\n");
335 + break;
336 + case IRQ_TYPE_MSIX:
337 + irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
338 + if (irq < 0)
339 + dev_err(dev, "Failed to get MSI-X interrupts\n");
340 + break;
341 + default:
342 + dev_err(dev, "Invalid IRQ type selected\n");
343 + }
344 +
345 + if (irq < 0) {
346 + irq = 0;
347 + res = false;
348 + }
349 + test->num_irqs = irq;
350 +
351 + return res;
352 +}
353 +
354 +static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
355 +{
356 + int i;
357 + struct pci_dev *pdev = test->pdev;
358 + struct device *dev = &pdev->dev;
359 +
360 + for (i = 0; i < test->num_irqs; i++)
361 + devm_free_irq(dev, pci_irq_vector(pdev, i), test);
362 +
363 + test->num_irqs = 0;
364 +}
365 +
366 +static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
367 +{
368 + int i;
369 + int err;
370 + struct pci_dev *pdev = test->pdev;
371 + struct device *dev = &pdev->dev;
372 +
373 + for (i = 0; i < test->num_irqs; i++) {
374 + err = devm_request_irq(dev, pci_irq_vector(pdev, i),
375 + pci_endpoint_test_irqhandler,
376 + IRQF_SHARED, DRV_MODULE_NAME, test);
377 + if (err)
378 + goto fail;
379 + }
380 +
381 + return true;
382 +
383 +fail:
384 + switch (irq_type) {
385 + case IRQ_TYPE_LEGACY:
386 + dev_err(dev, "Failed to request IRQ %d for Legacy\n",
387 + pci_irq_vector(pdev, i));
388 + break;
389 + case IRQ_TYPE_MSI:
390 + dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
391 + pci_irq_vector(pdev, i),
392 + i + 1);
393 + break;
394 + case IRQ_TYPE_MSIX:
395 + dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
396 + pci_irq_vector(pdev, i),
397 + i + 1);
398 + break;
399 + }
400 +
401 + return false;
402 +}
403 +
404 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
405 enum pci_barno barno)
406 {
407 @@ -178,6 +284,9 @@ static bool pci_endpoint_test_legacy_irq
408 {
409 u32 val;
410
411 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
412 + IRQ_TYPE_LEGACY);
413 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
414 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
415 COMMAND_RAISE_LEGACY_IRQ);
416 val = wait_for_completion_timeout(&test->irq_raised,
417 @@ -189,20 +298,24 @@ static bool pci_endpoint_test_legacy_irq
418 }
419
420 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
421 - u8 msi_num)
422 + u16 msi_num, bool msix)
423 {
424 u32 val;
425 struct pci_dev *pdev = test->pdev;
426
427 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
428 + msix == false ? IRQ_TYPE_MSI :
429 + IRQ_TYPE_MSIX);
430 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
431 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
432 - msi_num << MSI_NUMBER_SHIFT |
433 - COMMAND_RAISE_MSI_IRQ);
434 + msix == false ? COMMAND_RAISE_MSI_IRQ :
435 + COMMAND_RAISE_MSIX_IRQ);
436 val = wait_for_completion_timeout(&test->irq_raised,
437 msecs_to_jiffies(1000));
438 if (!val)
439 return false;
440
441 - if (test->last_irq - pdev->irq == msi_num - 1)
442 + if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
443 return true;
444
445 return false;
446 @@ -226,10 +339,18 @@ static bool pci_endpoint_test_copy(struc
447 u32 src_crc32;
448 u32 dst_crc32;
449
450 + if (size > SIZE_MAX - alignment)
451 + goto err;
452 +
453 + if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
454 + dev_err(dev, "Invalid IRQ type option\n");
455 + goto err;
456 + }
457 +
458 orig_src_addr = dma_alloc_coherent(dev, size + alignment,
459 &orig_src_phys_addr, GFP_KERNEL);
460 if (!orig_src_addr) {
461 - dev_err(dev, "failed to allocate source buffer\n");
462 + dev_err(dev, "Failed to allocate source buffer\n");
463 ret = false;
464 goto err;
465 }
466 @@ -255,7 +376,7 @@ static bool pci_endpoint_test_copy(struc
467 orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
468 &orig_dst_phys_addr, GFP_KERNEL);
469 if (!orig_dst_addr) {
470 - dev_err(dev, "failed to allocate destination address\n");
471 + dev_err(dev, "Failed to allocate destination address\n");
472 ret = false;
473 goto err_orig_src_addr;
474 }
475 @@ -277,8 +398,10 @@ static bool pci_endpoint_test_copy(struc
476 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
477 size);
478
479 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
480 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
481 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
482 - 1 << MSI_NUMBER_SHIFT | COMMAND_COPY);
483 + COMMAND_COPY);
484
485 wait_for_completion(&test->irq_raised);
486
487 @@ -311,10 +434,18 @@ static bool pci_endpoint_test_write(stru
488 size_t alignment = test->alignment;
489 u32 crc32;
490
491 + if (size > SIZE_MAX - alignment)
492 + goto err;
493 +
494 + if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
495 + dev_err(dev, "Invalid IRQ type option\n");
496 + goto err;
497 + }
498 +
499 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
500 GFP_KERNEL);
501 if (!orig_addr) {
502 - dev_err(dev, "failed to allocate address\n");
503 + dev_err(dev, "Failed to allocate address\n");
504 ret = false;
505 goto err;
506 }
507 @@ -341,8 +472,10 @@ static bool pci_endpoint_test_write(stru
508
509 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
510
511 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
512 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
513 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
514 - 1 << MSI_NUMBER_SHIFT | COMMAND_READ);
515 + COMMAND_READ);
516
517 wait_for_completion(&test->irq_raised);
518
519 @@ -369,10 +502,18 @@ static bool pci_endpoint_test_read(struc
520 size_t alignment = test->alignment;
521 u32 crc32;
522
523 + if (size > SIZE_MAX - alignment)
524 + goto err;
525 +
526 + if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
527 + dev_err(dev, "Invalid IRQ type option\n");
528 + goto err;
529 + }
530 +
531 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
532 GFP_KERNEL);
533 if (!orig_addr) {
534 - dev_err(dev, "failed to allocate destination address\n");
535 + dev_err(dev, "Failed to allocate destination address\n");
536 ret = false;
537 goto err;
538 }
539 @@ -393,8 +534,10 @@ static bool pci_endpoint_test_read(struc
540
541 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
542
543 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
544 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
545 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
546 - 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE);
547 + COMMAND_WRITE);
548
549 wait_for_completion(&test->irq_raised);
550
551 @@ -407,6 +550,38 @@ err:
552 return ret;
553 }
554
555 +static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
556 + int req_irq_type)
557 +{
558 + struct pci_dev *pdev = test->pdev;
559 + struct device *dev = &pdev->dev;
560 +
561 + if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
562 + dev_err(dev, "Invalid IRQ type option\n");
563 + return false;
564 + }
565 +
566 + if (irq_type == req_irq_type)
567 + return true;
568 +
569 + pci_endpoint_test_release_irq(test);
570 + pci_endpoint_test_free_irq_vectors(test);
571 +
572 + if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
573 + goto err;
574 +
575 + if (!pci_endpoint_test_request_irq(test))
576 + goto err;
577 +
578 + irq_type = req_irq_type;
579 + return true;
580 +
581 +err:
582 + pci_endpoint_test_free_irq_vectors(test);
583 + irq_type = IRQ_TYPE_UNDEFINED;
584 + return false;
585 +}
586 +
587 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
588 unsigned long arg)
589 {
590 @@ -426,7 +601,8 @@ static long pci_endpoint_test_ioctl(stru
591 ret = pci_endpoint_test_legacy_irq(test);
592 break;
593 case PCITEST_MSI:
594 - ret = pci_endpoint_test_msi_irq(test, arg);
595 + case PCITEST_MSIX:
596 + ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
597 break;
598 case PCITEST_WRITE:
599 ret = pci_endpoint_test_write(test, arg);
600 @@ -437,6 +613,12 @@ static long pci_endpoint_test_ioctl(stru
601 case PCITEST_COPY:
602 ret = pci_endpoint_test_copy(test, arg);
603 break;
604 + case PCITEST_SET_IRQTYPE:
605 + ret = pci_endpoint_test_set_irq(test, arg);
606 + break;
607 + case PCITEST_GET_IRQTYPE:
608 + ret = irq_type;
609 + break;
610 }
611
612 ret:
613 @@ -452,9 +634,7 @@ static const struct file_operations pci_
614 static int pci_endpoint_test_probe(struct pci_dev *pdev,
615 const struct pci_device_id *ent)
616 {
617 - int i;
618 int err;
619 - int irq = 0;
620 int id;
621 char name[20];
622 enum pci_barno bar;
623 @@ -476,11 +656,14 @@ static int pci_endpoint_test_probe(struc
624 test->alignment = 0;
625 test->pdev = pdev;
626
627 + if (no_msi)
628 + irq_type = IRQ_TYPE_LEGACY;
629 +
630 data = (struct pci_endpoint_test_data *)ent->driver_data;
631 if (data) {
632 test_reg_bar = data->test_reg_bar;
633 test->alignment = data->alignment;
634 - no_msi = data->no_msi;
635 + irq_type = data->irq_type;
636 }
637
638 init_completion(&test->irq_raised);
639 @@ -500,35 +683,21 @@ static int pci_endpoint_test_probe(struc
640
641 pci_set_master(pdev);
642
643 - if (!no_msi) {
644 - irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
645 - if (irq < 0)
646 - dev_err(dev, "failed to get MSI interrupts\n");
647 - }
648 + if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type))
649 + goto err_disable_irq;
650
651 - err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
652 - IRQF_SHARED, DRV_MODULE_NAME, test);
653 - if (err) {
654 - dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
655 - goto err_disable_msi;
656 - }
657 -
658 - for (i = 1; i < irq; i++) {
659 - err = devm_request_irq(dev, pdev->irq + i,
660 - pci_endpoint_test_irqhandler,
661 - IRQF_SHARED, DRV_MODULE_NAME, test);
662 - if (err)
663 - dev_err(dev, "failed to request IRQ %d for MSI %d\n",
664 - pdev->irq + i, i + 1);
665 - }
666 + if (!pci_endpoint_test_request_irq(test))
667 + goto err_disable_irq;
668
669 for (bar = BAR_0; bar <= BAR_5; bar++) {
670 - base = pci_ioremap_bar(pdev, bar);
671 - if (!base) {
672 - dev_err(dev, "failed to read BAR%d\n", bar);
673 - WARN_ON(bar == test_reg_bar);
674 + if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
675 + base = pci_ioremap_bar(pdev, bar);
676 + if (!base) {
677 + dev_err(dev, "Failed to read BAR%d\n", bar);
678 + WARN_ON(bar == test_reg_bar);
679 + }
680 + test->bar[bar] = base;
681 }
682 - test->bar[bar] = base;
683 }
684
685 test->base = test->bar[test_reg_bar];
686 @@ -544,24 +713,31 @@ static int pci_endpoint_test_probe(struc
687 id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
688 if (id < 0) {
689 err = id;
690 - dev_err(dev, "unable to get id\n");
691 + dev_err(dev, "Unable to get id\n");
692 goto err_iounmap;
693 }
694
695 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
696 misc_device = &test->miscdev;
697 misc_device->minor = MISC_DYNAMIC_MINOR;
698 - misc_device->name = name;
699 + misc_device->name = kstrdup(name, GFP_KERNEL);
700 + if (!misc_device->name) {
701 + err = -ENOMEM;
702 + goto err_ida_remove;
703 + }
704 misc_device->fops = &pci_endpoint_test_fops,
705
706 err = misc_register(misc_device);
707 if (err) {
708 - dev_err(dev, "failed to register device\n");
709 - goto err_ida_remove;
710 + dev_err(dev, "Failed to register device\n");
711 + goto err_kfree_name;
712 }
713
714 return 0;
715
716 +err_kfree_name:
717 + kfree(misc_device->name);
718 +
719 err_ida_remove:
720 ida_simple_remove(&pci_endpoint_test_ida, id);
721
722 @@ -570,9 +746,10 @@ err_iounmap:
723 if (test->bar[bar])
724 pci_iounmap(pdev, test->bar[bar]);
725 }
726 + pci_endpoint_test_release_irq(test);
727
728 -err_disable_msi:
729 - pci_disable_msi(pdev);
730 +err_disable_irq:
731 + pci_endpoint_test_free_irq_vectors(test);
732 pci_release_regions(pdev);
733
734 err_disable_pdev:
735 @@ -594,12 +771,16 @@ static void pci_endpoint_test_remove(str
736 return;
737
738 misc_deregister(&test->miscdev);
739 + kfree(misc_device->name);
740 ida_simple_remove(&pci_endpoint_test_ida, id);
741 for (bar = BAR_0; bar <= BAR_5; bar++) {
742 if (test->bar[bar])
743 pci_iounmap(pdev, test->bar[bar]);
744 }
745 - pci_disable_msi(pdev);
746 +
747 + pci_endpoint_test_release_irq(test);
748 + pci_endpoint_test_free_irq_vectors(test);
749 +
750 pci_release_regions(pdev);
751 pci_disable_device(pdev);
752 }
753 @@ -607,6 +788,7 @@ static void pci_endpoint_test_remove(str
754 static const struct pci_device_id pci_endpoint_test_tbl[] = {
755 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
756 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
757 + { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID) },
758 { }
759 };
760 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
761 --- a/drivers/pci/Kconfig
762 +++ b/drivers/pci/Kconfig
763 @@ -142,6 +142,7 @@ config PCI_HYPERV
764
765 source "drivers/pci/hotplug/Kconfig"
766 source "drivers/pci/dwc/Kconfig"
767 +source "drivers/pci/mobiveil/Kconfig"
768 source "drivers/pci/host/Kconfig"
769 source "drivers/pci/endpoint/Kconfig"
770 source "drivers/pci/switch/Kconfig"
771 --- a/drivers/pci/dwc/Kconfig
772 +++ b/drivers/pci/dwc/Kconfig
773 @@ -50,17 +50,36 @@ config PCI_DRA7XX_EP
774 endif
775
776 config PCIE_DW_PLAT
777 - bool "Platform bus based DesignWare PCIe Controller"
778 - depends on PCI
779 - depends on PCI_MSI_IRQ_DOMAIN
780 - select PCIE_DW_HOST
781 - ---help---
782 - This selects the DesignWare PCIe controller support. Select this if
783 - you have a PCIe controller on Platform bus.
784 + bool
785
786 - If you have a controller with this interface, say Y or M here.
787 +config PCIE_DW_PLAT_HOST
788 + bool "Platform bus based DesignWare PCIe Controller - Host mode"
789 + depends on PCI && PCI_MSI_IRQ_DOMAIN
790 + select PCIE_DW_HOST
791 + select PCIE_DW_PLAT
792 + help
793 + Enables support for the PCIe controller in the Designware IP to
794 + work in host mode. There are two instances of PCIe controller in
795 + Designware IP.
796 + This controller can work either as EP or RC. In order to enable
797 + host-specific features PCIE_DW_PLAT_HOST must be selected and in
798 + order to enable device-specific features PCI_DW_PLAT_EP must be
799 + selected.
800
801 - If unsure, say N.
802 +config PCIE_DW_PLAT_EP
803 + bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
804 + depends on PCI && PCI_MSI_IRQ_DOMAIN
805 + depends on PCI_ENDPOINT
806 + select PCIE_DW_EP
807 + select PCIE_DW_PLAT
808 + help
809 + Enables support for the PCIe controller in the Designware IP to
810 + work in endpoint mode. There are two instances of PCIe controller
811 + in Designware IP.
812 + This controller can work either as EP or RC. In order to enable
813 + host-specific features PCIE_DW_PLAT_HOST must be selected and in
814 + order to enable device-specific features PCI_DW_PLAT_EP must be
815 + selected.
816
817 config PCI_EXYNOS
818 bool "Samsung Exynos PCIe controller"
819 --- a/drivers/pci/dwc/Makefile
820 +++ b/drivers/pci/dwc/Makefile
821 @@ -10,7 +10,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
822 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
823 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
824 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
825 -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
826 +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
827 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
828 obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
829 obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
830 --- a/drivers/pci/dwc/pci-dra7xx.c
831 +++ b/drivers/pci/dwc/pci-dra7xx.c
832 @@ -337,15 +337,6 @@ static irqreturn_t dra7xx_pcie_irq_handl
833 return IRQ_HANDLED;
834 }
835
836 -static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
837 -{
838 - u32 reg;
839 -
840 - reg = PCI_BASE_ADDRESS_0 + (4 * bar);
841 - dw_pcie_writel_dbi2(pci, reg, 0x0);
842 - dw_pcie_writel_dbi(pci, reg, 0x0);
843 -}
844 -
845 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
846 {
847 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
848 --- /dev/null
849 +++ b/drivers/pci/dwc/pci-layerscape-ep.c
850 @@ -0,0 +1,146 @@
851 +// SPDX-License-Identifier: GPL-2.0
852 +/*
853 + * PCIe controller EP driver for Freescale Layerscape SoCs
854 + *
855 + * Copyright (C) 2018 NXP Semiconductor.
856 + *
857 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
858 + */
859 +
860 +#include <linux/kernel.h>
861 +#include <linux/init.h>
862 +#include <linux/of_pci.h>
863 +#include <linux/of_platform.h>
864 +#include <linux/of_address.h>
865 +#include <linux/pci.h>
866 +#include <linux/platform_device.h>
867 +#include <linux/resource.h>
868 +
869 +#include "pcie-designware.h"
870 +
871 +#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
872 +
873 +struct ls_pcie_ep {
874 + struct dw_pcie *pci;
875 +};
876 +
877 +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
878 +
879 +static int ls_pcie_establish_link(struct dw_pcie *pci)
880 +{
881 + return 0;
882 +}
883 +
884 +static const struct dw_pcie_ops ls_pcie_ep_ops = {
885 + .start_link = ls_pcie_establish_link,
886 +};
887 +
888 +static const struct of_device_id ls_pcie_ep_of_match[] = {
889 + { .compatible = "fsl,ls-pcie-ep",},
890 + { },
891 +};
892 +
893 +static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
894 +{
895 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
896 + struct pci_epc *epc = ep->epc;
897 + enum pci_barno bar;
898 +
899 + for (bar = BAR_0; bar <= BAR_5; bar++)
900 + dw_pcie_ep_reset_bar(pci, bar);
901 +
902 + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
903 +}
904 +
905 +static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
906 + enum pci_epc_irq_type type, u16 interrupt_num)
907 +{
908 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
909 +
910 + switch (type) {
911 + case PCI_EPC_IRQ_LEGACY:
912 + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
913 + case PCI_EPC_IRQ_MSI:
914 + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
915 + case PCI_EPC_IRQ_MSIX:
916 + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
917 + default:
918 + dev_err(pci->dev, "UNKNOWN IRQ type\n");
919 + return -EINVAL;
920 + }
921 +}
922 +
923 +static struct dw_pcie_ep_ops pcie_ep_ops = {
924 + .ep_init = ls_pcie_ep_init,
925 + .raise_irq = ls_pcie_ep_raise_irq,
926 +};
927 +
928 +static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
929 + struct platform_device *pdev)
930 +{
931 + struct dw_pcie *pci = pcie->pci;
932 + struct device *dev = pci->dev;
933 + struct dw_pcie_ep *ep;
934 + struct resource *res;
935 + int ret;
936 +
937 + ep = &pci->ep;
938 + ep->ops = &pcie_ep_ops;
939 +
940 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
941 + if (!res)
942 + return -EINVAL;
943 +
944 + ep->phys_base = res->start;
945 + ep->addr_size = resource_size(res);
946 +
947 + ret = dw_pcie_ep_init(ep);
948 + if (ret) {
949 + dev_err(dev, "failed to initialize endpoint\n");
950 + return ret;
951 + }
952 +
953 + return 0;
954 +}
955 +
956 +static int __init ls_pcie_ep_probe(struct platform_device *pdev)
957 +{
958 + struct device *dev = &pdev->dev;
959 + struct dw_pcie *pci;
960 + struct ls_pcie_ep *pcie;
961 + struct resource *dbi_base;
962 + int ret;
963 +
964 + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
965 + if (!pcie)
966 + return -ENOMEM;
967 +
968 + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
969 + if (!pci)
970 + return -ENOMEM;
971 +
972 + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
973 + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
974 + if (IS_ERR(pci->dbi_base))
975 + return PTR_ERR(pci->dbi_base);
976 +
977 + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
978 + pci->dev = dev;
979 + pci->ops = &ls_pcie_ep_ops;
980 + pcie->pci = pci;
981 +
982 + platform_set_drvdata(pdev, pcie);
983 +
984 + ret = ls_add_pcie_ep(pcie, pdev);
985 +
986 + return ret;
987 +}
988 +
989 +static struct platform_driver ls_pcie_ep_driver = {
990 + .driver = {
991 + .name = "layerscape-pcie-ep",
992 + .of_match_table = ls_pcie_ep_of_match,
993 + .suppress_bind_attrs = true,
994 + },
995 +};
996 +builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
997 --- a/drivers/pci/dwc/pci-layerscape.c
998 +++ b/drivers/pci/dwc/pci-layerscape.c
999 @@ -33,6 +33,8 @@
1000
1001 /* PEX Internal Configuration Registers */
1002 #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
1003 +#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
1004 +#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
1005
1006 #define PCIE_IATU_NUM 6
1007
1008 @@ -124,6 +126,14 @@ static int ls_pcie_link_up(struct dw_pci
1009 return 1;
1010 }
1011
1012 +/* Forward error response of outbound non-posted requests */
1013 +static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
1014 +{
1015 + struct dw_pcie *pci = pcie->pci;
1016 +
1017 + iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
1018 +}
1019 +
1020 static int ls_pcie_host_init(struct pcie_port *pp)
1021 {
1022 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1023 @@ -135,6 +145,7 @@ static int ls_pcie_host_init(struct pcie
1024 * dw_pcie_setup_rc() will reconfigure the outbound windows.
1025 */
1026 ls_pcie_disable_outbound_atus(pcie);
1027 + ls_pcie_fix_error_response(pcie);
1028
1029 dw_pcie_dbi_ro_wr_en(pci);
1030 ls_pcie_clear_multifunction(pcie);
1031 @@ -253,6 +264,7 @@ static struct ls_pcie_drvdata ls2088_drv
1032 };
1033
1034 static const struct of_device_id ls_pcie_of_match[] = {
1035 + { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
1036 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
1037 { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1038 { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1039 --- a/drivers/pci/dwc/pcie-designware-ep.c
1040 +++ b/drivers/pci/dwc/pcie-designware-ep.c
1041 @@ -1,20 +1,9 @@
1042 +// SPDX-License-Identifier: GPL-2.0
1043 /**
1044 * Synopsys DesignWare PCIe Endpoint controller driver
1045 *
1046 * Copyright (C) 2017 Texas Instruments
1047 * Author: Kishon Vijay Abraham I <kishon@ti.com>
1048 - *
1049 - * This program is free software: you can redistribute it and/or modify
1050 - * it under the terms of the GNU General Public License version 2 of
1051 - * the License as published by the Free Software Foundation.
1052 - *
1053 - * This program is distributed in the hope that it will be useful,
1054 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1055 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1056 - * GNU General Public License for more details.
1057 - *
1058 - * You should have received a copy of the GNU General Public License
1059 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1060 */
1061
1062 #include <linux/of.h>
1063 @@ -30,7 +19,8 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep
1064 pci_epc_linkup(epc);
1065 }
1066
1067 -static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
1068 +static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
1069 + int flags)
1070 {
1071 u32 reg;
1072
1073 @@ -38,10 +28,52 @@ static void dw_pcie_ep_reset_bar(struct
1074 dw_pcie_dbi_ro_wr_en(pci);
1075 dw_pcie_writel_dbi2(pci, reg, 0x0);
1076 dw_pcie_writel_dbi(pci, reg, 0x0);
1077 + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1078 + dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
1079 + dw_pcie_writel_dbi(pci, reg + 4, 0x0);
1080 + }
1081 dw_pcie_dbi_ro_wr_dis(pci);
1082 }
1083
1084 -static int dw_pcie_ep_write_header(struct pci_epc *epc,
1085 +void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
1086 +{
1087 + __dw_pcie_ep_reset_bar(pci, bar, 0);
1088 +}
1089 +
1090 +static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
1091 + u8 cap)
1092 +{
1093 + u8 cap_id, next_cap_ptr;
1094 + u16 reg;
1095 +
1096 + reg = dw_pcie_readw_dbi(pci, cap_ptr);
1097 + next_cap_ptr = (reg & 0xff00) >> 8;
1098 + cap_id = (reg & 0x00ff);
1099 +
1100 + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
1101 + return 0;
1102 +
1103 + if (cap_id == cap)
1104 + return cap_ptr;
1105 +
1106 + return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
1107 +}
1108 +
1109 +static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap)
1110 +{
1111 + u8 next_cap_ptr;
1112 + u16 reg;
1113 +
1114 + reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
1115 + next_cap_ptr = (reg & 0x00ff);
1116 +
1117 + if (!next_cap_ptr)
1118 + return 0;
1119 +
1120 + return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
1121 +}
1122 +
1123 +static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
1124 struct pci_epf_header *hdr)
1125 {
1126 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1127 @@ -74,8 +106,7 @@ static int dw_pcie_ep_inbound_atu(struct
1128 u32 free_win;
1129 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1130
1131 - free_win = find_first_zero_bit(&ep->ib_window_map,
1132 - sizeof(ep->ib_window_map));
1133 + free_win = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
1134 if (free_win >= ep->num_ib_windows) {
1135 dev_err(pci->dev, "no free inbound window\n");
1136 return -EINVAL;
1137 @@ -89,7 +120,7 @@ static int dw_pcie_ep_inbound_atu(struct
1138 }
1139
1140 ep->bar_to_atu[bar] = free_win;
1141 - set_bit(free_win, &ep->ib_window_map);
1142 + set_bit(free_win, ep->ib_window_map);
1143
1144 return 0;
1145 }
1146 @@ -100,8 +131,7 @@ static int dw_pcie_ep_outbound_atu(struc
1147 u32 free_win;
1148 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1149
1150 - free_win = find_first_zero_bit(&ep->ob_window_map,
1151 - sizeof(ep->ob_window_map));
1152 + free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
1153 if (free_win >= ep->num_ob_windows) {
1154 dev_err(pci->dev, "no free outbound window\n");
1155 return -EINVAL;
1156 @@ -110,30 +140,35 @@ static int dw_pcie_ep_outbound_atu(struc
1157 dw_pcie_prog_outbound_atu(pci, free_win, PCIE_ATU_TYPE_MEM,
1158 phys_addr, pci_addr, size);
1159
1160 - set_bit(free_win, &ep->ob_window_map);
1161 + set_bit(free_win, ep->ob_window_map);
1162 ep->outbound_addr[free_win] = phys_addr;
1163
1164 return 0;
1165 }
1166
1167 -static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
1168 +static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
1169 + struct pci_epf_bar *epf_bar)
1170 {
1171 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1172 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1173 + enum pci_barno bar = epf_bar->barno;
1174 u32 atu_index = ep->bar_to_atu[bar];
1175
1176 - dw_pcie_ep_reset_bar(pci, bar);
1177 + __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
1178
1179 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
1180 - clear_bit(atu_index, &ep->ib_window_map);
1181 + clear_bit(atu_index, ep->ib_window_map);
1182 }
1183
1184 -static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
1185 - dma_addr_t bar_phys, size_t size, int flags)
1186 +static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
1187 + struct pci_epf_bar *epf_bar)
1188 {
1189 int ret;
1190 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1191 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1192 + enum pci_barno bar = epf_bar->barno;
1193 + size_t size = epf_bar->size;
1194 + int flags = epf_bar->flags;
1195 enum dw_pcie_as_type as_type;
1196 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
1197
1198 @@ -142,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci
1199 else
1200 as_type = DW_PCIE_AS_IO;
1201
1202 - ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
1203 + ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type);
1204 if (ret)
1205 return ret;
1206
1207 dw_pcie_dbi_ro_wr_en(pci);
1208 - dw_pcie_writel_dbi2(pci, reg, size - 1);
1209 +
1210 + dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
1211 dw_pcie_writel_dbi(pci, reg, flags);
1212 +
1213 + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1214 + dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
1215 + dw_pcie_writel_dbi(pci, reg + 4, 0);
1216 + }
1217 +
1218 dw_pcie_dbi_ro_wr_dis(pci);
1219
1220 return 0;
1221 @@ -169,7 +211,8 @@ static int dw_pcie_find_index(struct dw_
1222 return -EINVAL;
1223 }
1224
1225 -static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
1226 +static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
1227 + phys_addr_t addr)
1228 {
1229 int ret;
1230 u32 atu_index;
1231 @@ -181,10 +224,11 @@ static void dw_pcie_ep_unmap_addr(struct
1232 return;
1233
1234 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_OUTBOUND);
1235 - clear_bit(atu_index, &ep->ob_window_map);
1236 + clear_bit(atu_index, ep->ob_window_map);
1237 }
1238
1239 -static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
1240 +static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
1241 + phys_addr_t addr,
1242 u64 pci_addr, size_t size)
1243 {
1244 int ret;
1245 @@ -200,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc
1246 return 0;
1247 }
1248
1249 -static int dw_pcie_ep_get_msi(struct pci_epc *epc)
1250 +static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
1251 {
1252 - int val;
1253 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1254 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1255 + u32 val, reg;
1256 +
1257 + if (!ep->msi_cap)
1258 + return -EINVAL;
1259
1260 - val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
1261 - if (!(val & MSI_CAP_MSI_EN_MASK))
1262 + reg = ep->msi_cap + PCI_MSI_FLAGS;
1263 + val = dw_pcie_readw_dbi(pci, reg);
1264 + if (!(val & PCI_MSI_FLAGS_ENABLE))
1265 return -EINVAL;
1266
1267 - val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
1268 + val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
1269 +
1270 return val;
1271 }
1272
1273 -static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
1274 +static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
1275 {
1276 - int val;
1277 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1278 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1279 + u32 val, reg;
1280 +
1281 + if (!ep->msi_cap)
1282 + return -EINVAL;
1283
1284 - val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
1285 - val &= ~MSI_CAP_MMC_MASK;
1286 - val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
1287 + reg = ep->msi_cap + PCI_MSI_FLAGS;
1288 + val = dw_pcie_readw_dbi(pci, reg);
1289 + val &= ~PCI_MSI_FLAGS_QMASK;
1290 + val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
1291 dw_pcie_dbi_ro_wr_en(pci);
1292 - dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
1293 + dw_pcie_writew_dbi(pci, reg, val);
1294 dw_pcie_dbi_ro_wr_dis(pci);
1295
1296 return 0;
1297 }
1298
1299 -static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
1300 - enum pci_epc_irq_type type, u8 interrupt_num)
1301 +static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
1302 +{
1303 + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1304 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1305 + u32 val, reg;
1306 +
1307 + if (!ep->msix_cap)
1308 + return -EINVAL;
1309 +
1310 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
1311 + val = dw_pcie_readw_dbi(pci, reg);
1312 + if (!(val & PCI_MSIX_FLAGS_ENABLE))
1313 + return -EINVAL;
1314 +
1315 + val &= PCI_MSIX_FLAGS_QSIZE;
1316 +
1317 + return val;
1318 +}
1319 +
1320 +static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
1321 +{
1322 + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1323 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1324 + u32 val, reg;
1325 +
1326 + if (!ep->msix_cap)
1327 + return -EINVAL;
1328 +
1329 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
1330 + val = dw_pcie_readw_dbi(pci, reg);
1331 + val &= ~PCI_MSIX_FLAGS_QSIZE;
1332 + val |= interrupts;
1333 + dw_pcie_dbi_ro_wr_en(pci);
1334 + dw_pcie_writew_dbi(pci, reg, val);
1335 + dw_pcie_dbi_ro_wr_dis(pci);
1336 +
1337 + return 0;
1338 +}
1339 +
1340 +static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
1341 + enum pci_epc_irq_type type, u16 interrupt_num)
1342 {
1343 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1344
1345 if (!ep->ops->raise_irq)
1346 return -EINVAL;
1347
1348 - return ep->ops->raise_irq(ep, type, interrupt_num);
1349 + return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
1350 }
1351
1352 static void dw_pcie_ep_stop(struct pci_epc *epc)
1353 @@ -271,15 +363,130 @@ static const struct pci_epc_ops epc_ops
1354 .unmap_addr = dw_pcie_ep_unmap_addr,
1355 .set_msi = dw_pcie_ep_set_msi,
1356 .get_msi = dw_pcie_ep_get_msi,
1357 + .set_msix = dw_pcie_ep_set_msix,
1358 + .get_msix = dw_pcie_ep_get_msix,
1359 .raise_irq = dw_pcie_ep_raise_irq,
1360 .start = dw_pcie_ep_start,
1361 .stop = dw_pcie_ep_stop,
1362 };
1363
1364 +int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
1365 +{
1366 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1367 + struct device *dev = pci->dev;
1368 +
1369 + dev_err(dev, "EP cannot trigger legacy IRQs\n");
1370 +
1371 + return -EINVAL;
1372 +}
1373 +
1374 +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
1375 + u8 interrupt_num)
1376 +{
1377 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1378 + struct pci_epc *epc = ep->epc;
1379 + u16 msg_ctrl, msg_data;
1380 + u32 msg_addr_lower, msg_addr_upper, reg;
1381 + u64 msg_addr;
1382 + bool has_upper;
1383 + int ret;
1384 +
1385 + if (!ep->msi_cap)
1386 + return -EINVAL;
1387 +
1388 + /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
1389 + reg = ep->msi_cap + PCI_MSI_FLAGS;
1390 + msg_ctrl = dw_pcie_readw_dbi(pci, reg);
1391 + has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
1392 + reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
1393 + msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
1394 + if (has_upper) {
1395 + reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
1396 + msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
1397 + reg = ep->msi_cap + PCI_MSI_DATA_64;
1398 + msg_data = dw_pcie_readw_dbi(pci, reg);
1399 + } else {
1400 + msg_addr_upper = 0;
1401 + reg = ep->msi_cap + PCI_MSI_DATA_32;
1402 + msg_data = dw_pcie_readw_dbi(pci, reg);
1403 + }
1404 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
1405 + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
1406 + epc->mem->page_size);
1407 + if (ret)
1408 + return ret;
1409 +
1410 + writel(msg_data | (interrupt_num - 1), ep->msi_mem);
1411 +
1412 + dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
1413 +
1414 + return 0;
1415 +}
1416 +
1417 +int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
1418 + u16 interrupt_num)
1419 +{
1420 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1421 + struct pci_epc *epc = ep->epc;
1422 + u16 tbl_offset, bir;
1423 + u32 bar_addr_upper, bar_addr_lower;
1424 + u32 msg_addr_upper, msg_addr_lower;
1425 + u32 reg, msg_data, vec_ctrl;
1426 + u64 tbl_addr, msg_addr, reg_u64;
1427 + void __iomem *msix_tbl;
1428 + int ret;
1429 +
1430 + reg = ep->msix_cap + PCI_MSIX_TABLE;
1431 + tbl_offset = dw_pcie_readl_dbi(pci, reg);
1432 + bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
1433 + tbl_offset &= PCI_MSIX_TABLE_OFFSET;
1434 +
1435 + reg = PCI_BASE_ADDRESS_0 + (4 * bir);
1436 + bar_addr_upper = 0;
1437 + bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
1438 + reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
1439 + if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1440 + bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
1441 +
1442 + tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower;
1443 + tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE));
1444 + tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK;
1445 +
1446 + msix_tbl = ioremap_nocache(ep->phys_base + tbl_addr,
1447 + PCI_MSIX_ENTRY_SIZE);
1448 + if (!msix_tbl)
1449 + return -EINVAL;
1450 +
1451 + msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR);
1452 + msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR);
1453 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
1454 + msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA);
1455 + vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL);
1456 +
1457 + iounmap(msix_tbl);
1458 +
1459 + if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)
1460 + return -EPERM;
1461 +
1462 + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
1463 + epc->mem->page_size);
1464 + if (ret)
1465 + return ret;
1466 +
1467 + writel(msg_data, ep->msi_mem);
1468 +
1469 + dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
1470 +
1471 + return 0;
1472 +}
1473 +
1474 void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
1475 {
1476 struct pci_epc *epc = ep->epc;
1477
1478 + pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
1479 + epc->mem->page_size);
1480 +
1481 pci_epc_mem_exit(epc);
1482 }
1483
1484 @@ -293,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
1485 struct device_node *np = dev->of_node;
1486
1487 if (!pci->dbi_base || !pci->dbi_base2) {
1488 - dev_err(dev, "dbi_base/deb_base2 is not populated\n");
1489 + dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
1490 return -EINVAL;
1491 }
1492
1493 @@ -302,12 +509,32 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
1494 dev_err(dev, "unable to read *num-ib-windows* property\n");
1495 return ret;
1496 }
1497 + if (ep->num_ib_windows > MAX_IATU_IN) {
1498 + dev_err(dev, "invalid *num-ib-windows*\n");
1499 + return -EINVAL;
1500 + }
1501
1502 ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
1503 if (ret < 0) {
1504 dev_err(dev, "unable to read *num-ob-windows* property\n");
1505 return ret;
1506 }
1507 + if (ep->num_ob_windows > MAX_IATU_OUT) {
1508 + dev_err(dev, "invalid *num-ob-windows*\n");
1509 + return -EINVAL;
1510 + }
1511 +
1512 + ep->ib_window_map = devm_kzalloc(dev, sizeof(long) *
1513 + BITS_TO_LONGS(ep->num_ib_windows),
1514 + GFP_KERNEL);
1515 + if (!ep->ib_window_map)
1516 + return -ENOMEM;
1517 +
1518 + ep->ob_window_map = devm_kzalloc(dev, sizeof(long) *
1519 + BITS_TO_LONGS(ep->num_ob_windows),
1520 + GFP_KERNEL);
1521 + if (!ep->ob_window_map)
1522 + return -ENOMEM;
1523
1524 addr = devm_kzalloc(dev, sizeof(phys_addr_t) * ep->num_ob_windows,
1525 GFP_KERNEL);
1526 @@ -315,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
1527 return -ENOMEM;
1528 ep->outbound_addr = addr;
1529
1530 - if (ep->ops->ep_init)
1531 - ep->ops->ep_init(ep);
1532 -
1533 epc = devm_pci_epc_create(dev, &epc_ops);
1534 if (IS_ERR(epc)) {
1535 dev_err(dev, "failed to create epc device\n");
1536 return PTR_ERR(epc);
1537 }
1538
1539 + ep->epc = epc;
1540 + epc_set_drvdata(epc, ep);
1541 +
1542 + if (ep->ops->ep_init)
1543 + ep->ops->ep_init(ep);
1544 +
1545 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
1546 if (ret < 0)
1547 epc->max_functions = 1;
1548 @@ -335,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
1549 return ret;
1550 }
1551
1552 - ep->epc = epc;
1553 - epc_set_drvdata(epc, ep);
1554 + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
1555 + epc->mem->page_size);
1556 + if (!ep->msi_mem) {
1557 + dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
1558 + return -ENOMEM;
1559 + }
1560 + ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
1561 +
1562 + ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);
1563 +
1564 dw_pcie_setup(pci);
1565
1566 return 0;
1567 --- a/drivers/pci/dwc/pcie-designware-host.c
1568 +++ b/drivers/pci/dwc/pcie-designware-host.c
1569 @@ -1,3 +1,4 @@
1570 +// SPDX-License-Identifier: GPL-2.0
1571 /*
1572 * Synopsys DesignWare PCIe host controller driver
1573 *
1574 @@ -5,10 +6,6 @@
1575 * http://www.samsung.com
1576 *
1577 * Author: Jingoo Han <jg1.han@samsung.com>
1578 - *
1579 - * This program is free software; you can redistribute it and/or modify
1580 - * it under the terms of the GNU General Public License version 2 as
1581 - * published by the Free Software Foundation.
1582 */
1583
1584 #include <linux/irqdomain.h>
1585 --- a/drivers/pci/dwc/pcie-designware-plat.c
1586 +++ b/drivers/pci/dwc/pcie-designware-plat.c
1587 @@ -1,13 +1,10 @@
1588 +// SPDX-License-Identifier: GPL-2.0
1589 /*
1590 * PCIe RC driver for Synopsys DesignWare Core
1591 *
1592 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
1593 *
1594 * Authors: Joao Pinto <Joao.Pinto@synopsys.com>
1595 - *
1596 - * This program is free software; you can redistribute it and/or modify
1597 - * it under the terms of the GNU General Public License version 2 as
1598 - * published by the Free Software Foundation.
1599 */
1600 #include <linux/clk.h>
1601 #include <linux/delay.h>
1602 @@ -15,19 +12,29 @@
1603 #include <linux/interrupt.h>
1604 #include <linux/kernel.h>
1605 #include <linux/init.h>
1606 +#include <linux/of_device.h>
1607 #include <linux/of_gpio.h>
1608 #include <linux/pci.h>
1609 #include <linux/platform_device.h>
1610 #include <linux/resource.h>
1611 #include <linux/signal.h>
1612 #include <linux/types.h>
1613 +#include <linux/regmap.h>
1614
1615 #include "pcie-designware.h"
1616
1617 struct dw_plat_pcie {
1618 - struct dw_pcie *pci;
1619 + struct dw_pcie *pci;
1620 + struct regmap *regmap;
1621 + enum dw_pcie_device_mode mode;
1622 +};
1623 +
1624 +struct dw_plat_pcie_of_data {
1625 + enum dw_pcie_device_mode mode;
1626 };
1627
1628 +static const struct of_device_id dw_plat_pcie_of_match[];
1629 +
1630 static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg)
1631 {
1632 struct pcie_port *pp = arg;
1633 @@ -52,9 +59,58 @@ static const struct dw_pcie_host_ops dw_
1634 .host_init = dw_plat_pcie_host_init,
1635 };
1636
1637 -static int dw_plat_add_pcie_port(struct pcie_port *pp,
1638 +static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
1639 +{
1640 + return 0;
1641 +}
1642 +
1643 +static const struct dw_pcie_ops dw_pcie_ops = {
1644 + .start_link = dw_plat_pcie_establish_link,
1645 +};
1646 +
1647 +static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
1648 +{
1649 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1650 + struct pci_epc *epc = ep->epc;
1651 + enum pci_barno bar;
1652 +
1653 + for (bar = BAR_0; bar <= BAR_5; bar++)
1654 + dw_pcie_ep_reset_bar(pci, bar);
1655 +
1656 + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
1657 + epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
1658 +}
1659 +
1660 +static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
1661 + enum pci_epc_irq_type type,
1662 + u16 interrupt_num)
1663 +{
1664 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1665 +
1666 + switch (type) {
1667 + case PCI_EPC_IRQ_LEGACY:
1668 + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
1669 + case PCI_EPC_IRQ_MSI:
1670 + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
1671 + case PCI_EPC_IRQ_MSIX:
1672 + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
1673 + default:
1674 + dev_err(pci->dev, "UNKNOWN IRQ type\n");
1675 + }
1676 +
1677 + return 0;
1678 +}
1679 +
1680 +static struct dw_pcie_ep_ops pcie_ep_ops = {
1681 + .ep_init = dw_plat_pcie_ep_init,
1682 + .raise_irq = dw_plat_pcie_ep_raise_irq,
1683 +};
1684 +
1685 +static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
1686 struct platform_device *pdev)
1687 {
1688 + struct dw_pcie *pci = dw_plat_pcie->pci;
1689 + struct pcie_port *pp = &pci->pp;
1690 struct device *dev = &pdev->dev;
1691 int ret;
1692
1693 @@ -82,15 +138,44 @@ static int dw_plat_add_pcie_port(struct
1694
1695 ret = dw_pcie_host_init(pp);
1696 if (ret) {
1697 - dev_err(dev, "failed to initialize host\n");
1698 + dev_err(dev, "Failed to initialize host\n");
1699 return ret;
1700 }
1701
1702 return 0;
1703 }
1704
1705 -static const struct dw_pcie_ops dw_pcie_ops = {
1706 -};
1707 +static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie,
1708 + struct platform_device *pdev)
1709 +{
1710 + int ret;
1711 + struct dw_pcie_ep *ep;
1712 + struct resource *res;
1713 + struct device *dev = &pdev->dev;
1714 + struct dw_pcie *pci = dw_plat_pcie->pci;
1715 +
1716 + ep = &pci->ep;
1717 + ep->ops = &pcie_ep_ops;
1718 +
1719 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
1720 + pci->dbi_base2 = devm_ioremap_resource(dev, res);
1721 + if (IS_ERR(pci->dbi_base2))
1722 + return PTR_ERR(pci->dbi_base2);
1723 +
1724 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
1725 + if (!res)
1726 + return -EINVAL;
1727 +
1728 + ep->phys_base = res->start;
1729 + ep->addr_size = resource_size(res);
1730 +
1731 + ret = dw_pcie_ep_init(ep);
1732 + if (ret) {
1733 + dev_err(dev, "Failed to initialize endpoint\n");
1734 + return ret;
1735 + }
1736 + return 0;
1737 +}
1738
1739 static int dw_plat_pcie_probe(struct platform_device *pdev)
1740 {
1741 @@ -99,6 +184,16 @@ static int dw_plat_pcie_probe(struct pla
1742 struct dw_pcie *pci;
1743 struct resource *res; /* Resource from DT */
1744 int ret;
1745 + const struct of_device_id *match;
1746 + const struct dw_plat_pcie_of_data *data;
1747 + enum dw_pcie_device_mode mode;
1748 +
1749 + match = of_match_device(dw_plat_pcie_of_match, dev);
1750 + if (!match)
1751 + return -EINVAL;
1752 +
1753 + data = (struct dw_plat_pcie_of_data *)match->data;
1754 + mode = (enum dw_pcie_device_mode)data->mode;
1755
1756 dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL);
1757 if (!dw_plat_pcie)
1758 @@ -112,23 +207,59 @@ static int dw_plat_pcie_probe(struct pla
1759 pci->ops = &dw_pcie_ops;
1760
1761 dw_plat_pcie->pci = pci;
1762 + dw_plat_pcie->mode = mode;
1763 +
1764 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1765 + if (!res)
1766 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1767
1768 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1769 pci->dbi_base = devm_ioremap_resource(dev, res);
1770 if (IS_ERR(pci->dbi_base))
1771 return PTR_ERR(pci->dbi_base);
1772
1773 platform_set_drvdata(pdev, dw_plat_pcie);
1774
1775 - ret = dw_plat_add_pcie_port(&pci->pp, pdev);
1776 - if (ret < 0)
1777 - return ret;
1778 + switch (dw_plat_pcie->mode) {
1779 + case DW_PCIE_RC_TYPE:
1780 + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST))
1781 + return -ENODEV;
1782 +
1783 + ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev);
1784 + if (ret < 0)
1785 + return ret;
1786 + break;
1787 + case DW_PCIE_EP_TYPE:
1788 + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP))
1789 + return -ENODEV;
1790 +
1791 + ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev);
1792 + if (ret < 0)
1793 + return ret;
1794 + break;
1795 + default:
1796 + dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
1797 + }
1798
1799 return 0;
1800 }
1801
1802 +static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = {
1803 + .mode = DW_PCIE_RC_TYPE,
1804 +};
1805 +
1806 +static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = {
1807 + .mode = DW_PCIE_EP_TYPE,
1808 +};
1809 +
1810 static const struct of_device_id dw_plat_pcie_of_match[] = {
1811 - { .compatible = "snps,dw-pcie", },
1812 + {
1813 + .compatible = "snps,dw-pcie",
1814 + .data = &dw_plat_pcie_rc_of_data,
1815 + },
1816 + {
1817 + .compatible = "snps,dw-pcie-ep",
1818 + .data = &dw_plat_pcie_ep_of_data,
1819 + },
1820 {},
1821 };
1822
1823 --- a/drivers/pci/dwc/pcie-designware.c
1824 +++ b/drivers/pci/dwc/pcie-designware.c
1825 @@ -1,3 +1,4 @@
1826 +// SPDX-License-Identifier: GPL-2.0
1827 /*
1828 * Synopsys DesignWare PCIe host controller driver
1829 *
1830 @@ -5,10 +6,6 @@
1831 * http://www.samsung.com
1832 *
1833 * Author: Jingoo Han <jg1.han@samsung.com>
1834 - *
1835 - * This program is free software; you can redistribute it and/or modify
1836 - * it under the terms of the GNU General Public License version 2 as
1837 - * published by the Free Software Foundation.
1838 */
1839
1840 #include <linux/delay.h>
1841 --- a/drivers/pci/dwc/pcie-designware.h
1842 +++ b/drivers/pci/dwc/pcie-designware.h
1843 @@ -1,3 +1,4 @@
1844 +// SPDX-License-Identifier: GPL-2.0
1845 /*
1846 * Synopsys DesignWare PCIe host controller driver
1847 *
1848 @@ -5,10 +6,6 @@
1849 * http://www.samsung.com
1850 *
1851 * Author: Jingoo Han <jg1.han@samsung.com>
1852 - *
1853 - * This program is free software; you can redistribute it and/or modify
1854 - * it under the terms of the GNU General Public License version 2 as
1855 - * published by the Free Software Foundation.
1856 */
1857
1858 #ifndef _PCIE_DESIGNWARE_H
1859 @@ -97,15 +94,6 @@
1860 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
1861 ((0x3 << 20) | ((region) << 9) | (0x1 << 8))
1862
1863 -#define MSI_MESSAGE_CONTROL 0x52
1864 -#define MSI_CAP_MMC_SHIFT 1
1865 -#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT)
1866 -#define MSI_CAP_MME_SHIFT 4
1867 -#define MSI_CAP_MSI_EN_MASK 0x1
1868 -#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
1869 -#define MSI_MESSAGE_ADDR_L32 0x54
1870 -#define MSI_MESSAGE_ADDR_U32 0x58
1871 -
1872 /*
1873 * Maximum number of MSI IRQs can be 256 per controller. But keep
1874 * it 32 as of now. Probably we will never need more than 32. If needed,
1875 @@ -114,6 +102,10 @@
1876 #define MAX_MSI_IRQS 32
1877 #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
1878
1879 +/* Maximum number of inbound/outbound iATUs */
1880 +#define MAX_IATU_IN 256
1881 +#define MAX_IATU_OUT 256
1882 +
1883 struct pcie_port;
1884 struct dw_pcie;
1885 struct dw_pcie_ep;
1886 @@ -181,8 +173,8 @@ enum dw_pcie_as_type {
1887
1888 struct dw_pcie_ep_ops {
1889 void (*ep_init)(struct dw_pcie_ep *ep);
1890 - int (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
1891 - u8 interrupt_num);
1892 + int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
1893 + enum pci_epc_irq_type type, u16 interrupt_num);
1894 };
1895
1896 struct dw_pcie_ep {
1897 @@ -193,10 +185,14 @@ struct dw_pcie_ep {
1898 size_t page_size;
1899 u8 bar_to_atu[6];
1900 phys_addr_t *outbound_addr;
1901 - unsigned long ib_window_map;
1902 - unsigned long ob_window_map;
1903 + unsigned long *ib_window_map;
1904 + unsigned long *ob_window_map;
1905 u32 num_ib_windows;
1906 u32 num_ob_windows;
1907 + void __iomem *msi_mem;
1908 + phys_addr_t msi_mem_phys;
1909 + u8 msi_cap; /* MSI capability offset */
1910 + u8 msix_cap; /* MSI-X capability offset */
1911 };
1912
1913 struct dw_pcie_ops {
1914 @@ -335,6 +331,12 @@ static inline int dw_pcie_host_init(stru
1915 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
1916 int dw_pcie_ep_init(struct dw_pcie_ep *ep);
1917 void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
1918 +int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
1919 +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
1920 + u8 interrupt_num);
1921 +int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
1922 + u16 interrupt_num);
1923 +void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
1924 #else
1925 static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
1926 {
1927 @@ -348,5 +350,26 @@ static inline int dw_pcie_ep_init(struct
1928 static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
1929 {
1930 }
1931 +
1932 +static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
1933 +{
1934 + return 0;
1935 +}
1936 +
1937 +static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
1938 + u8 interrupt_num)
1939 +{
1940 + return 0;
1941 +}
1942 +
1943 +static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
1944 + u16 interrupt_num)
1945 +{
1946 + return 0;
1947 +}
1948 +
1949 +static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
1950 +{
1951 +}
1952 #endif
1953 #endif /* _PCIE_DESIGNWARE_H */
1954 --- a/drivers/pci/endpoint/Kconfig
1955 +++ b/drivers/pci/endpoint/Kconfig
1956 @@ -1,3 +1,4 @@
1957 +# SPDX-License-Identifier: GPL-2.0
1958 #
1959 # PCI Endpoint Support
1960 #
1961 --- a/drivers/pci/endpoint/Makefile
1962 +++ b/drivers/pci/endpoint/Makefile
1963 @@ -1,3 +1,4 @@
1964 +# SPDX-License-Identifier: GPL-2.0
1965 #
1966 # Makefile for PCI Endpoint Support
1967 #
1968 --- a/drivers/pci/endpoint/functions/Kconfig
1969 +++ b/drivers/pci/endpoint/functions/Kconfig
1970 @@ -1,3 +1,4 @@
1971 +# SPDX-License-Identifier: GPL-2.0
1972 #
1973 # PCI Endpoint Functions
1974 #
1975 --- a/drivers/pci/endpoint/functions/Makefile
1976 +++ b/drivers/pci/endpoint/functions/Makefile
1977 @@ -1,3 +1,4 @@
1978 +# SPDX-License-Identifier: GPL-2.0
1979 #
1980 # Makefile for PCI Endpoint Functions
1981 #
1982 --- a/drivers/pci/endpoint/functions/pci-epf-test.c
1983 +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
1984 @@ -1,20 +1,9 @@
1985 +// SPDX-License-Identifier: GPL-2.0
1986 /**
1987 * Test driver to test endpoint functionality
1988 *
1989 * Copyright (C) 2017 Texas Instruments
1990 * Author: Kishon Vijay Abraham I <kishon@ti.com>
1991 - *
1992 - * This program is free software: you can redistribute it and/or modify
1993 - * it under the terms of the GNU General Public License version 2 of
1994 - * the License as published by the Free Software Foundation.
1995 - *
1996 - * This program is distributed in the hope that it will be useful,
1997 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1998 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1999 - * GNU General Public License for more details.
2000 - *
2001 - * You should have received a copy of the GNU General Public License
2002 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2003 */
2004
2005 #include <linux/crc32.h>
2006 @@ -29,13 +18,16 @@
2007 #include <linux/pci-epf.h>
2008 #include <linux/pci_regs.h>
2009
2010 +#define IRQ_TYPE_LEGACY 0
2011 +#define IRQ_TYPE_MSI 1
2012 +#define IRQ_TYPE_MSIX 2
2013 +
2014 #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
2015 #define COMMAND_RAISE_MSI_IRQ BIT(1)
2016 -#define MSI_NUMBER_SHIFT 2
2017 -#define MSI_NUMBER_MASK (0x3f << MSI_NUMBER_SHIFT)
2018 -#define COMMAND_READ BIT(8)
2019 -#define COMMAND_WRITE BIT(9)
2020 -#define COMMAND_COPY BIT(10)
2021 +#define COMMAND_RAISE_MSIX_IRQ BIT(2)
2022 +#define COMMAND_READ BIT(3)
2023 +#define COMMAND_WRITE BIT(4)
2024 +#define COMMAND_COPY BIT(5)
2025
2026 #define STATUS_READ_SUCCESS BIT(0)
2027 #define STATUS_READ_FAIL BIT(1)
2028 @@ -56,6 +48,7 @@ struct pci_epf_test {
2029 struct pci_epf *epf;
2030 enum pci_barno test_reg_bar;
2031 bool linkup_notifier;
2032 + bool msix_available;
2033 struct delayed_work cmd_handler;
2034 };
2035
2036 @@ -67,6 +60,8 @@ struct pci_epf_test_reg {
2037 u64 dst_addr;
2038 u32 size;
2039 u32 checksum;
2040 + u32 irq_type;
2041 + u32 irq_number;
2042 } __packed;
2043
2044 static struct pci_epf_header test_header = {
2045 @@ -81,7 +76,7 @@ struct pci_epf_test_data {
2046 bool linkup_notifier;
2047 };
2048
2049 -static int bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
2050 +static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
2051
2052 static int pci_epf_test_copy(struct pci_epf_test *epf_test)
2053 {
2054 @@ -98,43 +93,45 @@ static int pci_epf_test_copy(struct pci_
2055
2056 src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size);
2057 if (!src_addr) {
2058 - dev_err(dev, "failed to allocate source address\n");
2059 + dev_err(dev, "Failed to allocate source address\n");
2060 reg->status = STATUS_SRC_ADDR_INVALID;
2061 ret = -ENOMEM;
2062 goto err;
2063 }
2064
2065 - ret = pci_epc_map_addr(epc, src_phys_addr, reg->src_addr, reg->size);
2066 + ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr,
2067 + reg->size);
2068 if (ret) {
2069 - dev_err(dev, "failed to map source address\n");
2070 + dev_err(dev, "Failed to map source address\n");
2071 reg->status = STATUS_SRC_ADDR_INVALID;
2072 goto err_src_addr;
2073 }
2074
2075 dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size);
2076 if (!dst_addr) {
2077 - dev_err(dev, "failed to allocate destination address\n");
2078 + dev_err(dev, "Failed to allocate destination address\n");
2079 reg->status = STATUS_DST_ADDR_INVALID;
2080 ret = -ENOMEM;
2081 goto err_src_map_addr;
2082 }
2083
2084 - ret = pci_epc_map_addr(epc, dst_phys_addr, reg->dst_addr, reg->size);
2085 + ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr,
2086 + reg->size);
2087 if (ret) {
2088 - dev_err(dev, "failed to map destination address\n");
2089 + dev_err(dev, "Failed to map destination address\n");
2090 reg->status = STATUS_DST_ADDR_INVALID;
2091 goto err_dst_addr;
2092 }
2093
2094 memcpy(dst_addr, src_addr, reg->size);
2095
2096 - pci_epc_unmap_addr(epc, dst_phys_addr);
2097 + pci_epc_unmap_addr(epc, epf->func_no, dst_phys_addr);
2098
2099 err_dst_addr:
2100 pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size);
2101
2102 err_src_map_addr:
2103 - pci_epc_unmap_addr(epc, src_phys_addr);
2104 + pci_epc_unmap_addr(epc, epf->func_no, src_phys_addr);
2105
2106 err_src_addr:
2107 pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size);
2108 @@ -158,15 +155,16 @@ static int pci_epf_test_read(struct pci_
2109
2110 src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
2111 if (!src_addr) {
2112 - dev_err(dev, "failed to allocate address\n");
2113 + dev_err(dev, "Failed to allocate address\n");
2114 reg->status = STATUS_SRC_ADDR_INVALID;
2115 ret = -ENOMEM;
2116 goto err;
2117 }
2118
2119 - ret = pci_epc_map_addr(epc, phys_addr, reg->src_addr, reg->size);
2120 + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr,
2121 + reg->size);
2122 if (ret) {
2123 - dev_err(dev, "failed to map address\n");
2124 + dev_err(dev, "Failed to map address\n");
2125 reg->status = STATUS_SRC_ADDR_INVALID;
2126 goto err_addr;
2127 }
2128 @@ -186,7 +184,7 @@ static int pci_epf_test_read(struct pci_
2129 kfree(buf);
2130
2131 err_map_addr:
2132 - pci_epc_unmap_addr(epc, phys_addr);
2133 + pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
2134
2135 err_addr:
2136 pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size);
2137 @@ -209,15 +207,16 @@ static int pci_epf_test_write(struct pci
2138
2139 dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
2140 if (!dst_addr) {
2141 - dev_err(dev, "failed to allocate address\n");
2142 + dev_err(dev, "Failed to allocate address\n");
2143 reg->status = STATUS_DST_ADDR_INVALID;
2144 ret = -ENOMEM;
2145 goto err;
2146 }
2147
2148 - ret = pci_epc_map_addr(epc, phys_addr, reg->dst_addr, reg->size);
2149 + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr,
2150 + reg->size);
2151 if (ret) {
2152 - dev_err(dev, "failed to map address\n");
2153 + dev_err(dev, "Failed to map address\n");
2154 reg->status = STATUS_DST_ADDR_INVALID;
2155 goto err_addr;
2156 }
2157 @@ -237,12 +236,12 @@ static int pci_epf_test_write(struct pci
2158 * wait 1ms inorder for the write to complete. Without this delay L3
2159 * error in observed in the host system.
2160 */
2161 - mdelay(1);
2162 + usleep_range(1000, 2000);
2163
2164 kfree(buf);
2165
2166 err_map_addr:
2167 - pci_epc_unmap_addr(epc, phys_addr);
2168 + pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
2169
2170 err_addr:
2171 pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size);
2172 @@ -251,31 +250,42 @@ err:
2173 return ret;
2174 }
2175
2176 -static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq)
2177 +static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq_type,
2178 + u16 irq)
2179 {
2180 - u8 msi_count;
2181 struct pci_epf *epf = epf_test->epf;
2182 + struct device *dev = &epf->dev;
2183 struct pci_epc *epc = epf->epc;
2184 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
2185 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
2186
2187 reg->status |= STATUS_IRQ_RAISED;
2188 - msi_count = pci_epc_get_msi(epc);
2189 - if (irq > msi_count || msi_count <= 0)
2190 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
2191 - else
2192 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
2193 +
2194 + switch (irq_type) {
2195 + case IRQ_TYPE_LEGACY:
2196 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
2197 + break;
2198 + case IRQ_TYPE_MSI:
2199 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
2200 + break;
2201 + case IRQ_TYPE_MSIX:
2202 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSIX, irq);
2203 + break;
2204 + default:
2205 + dev_err(dev, "Failed to raise IRQ, unknown type\n");
2206 + break;
2207 + }
2208 }
2209
2210 static void pci_epf_test_cmd_handler(struct work_struct *work)
2211 {
2212 int ret;
2213 - u8 irq;
2214 - u8 msi_count;
2215 + int count;
2216 u32 command;
2217 struct pci_epf_test *epf_test = container_of(work, struct pci_epf_test,
2218 cmd_handler.work);
2219 struct pci_epf *epf = epf_test->epf;
2220 + struct device *dev = &epf->dev;
2221 struct pci_epc *epc = epf->epc;
2222 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
2223 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
2224 @@ -287,11 +297,14 @@ static void pci_epf_test_cmd_handler(str
2225 reg->command = 0;
2226 reg->status = 0;
2227
2228 - irq = (command & MSI_NUMBER_MASK) >> MSI_NUMBER_SHIFT;
2229 + if (reg->irq_type > IRQ_TYPE_MSIX) {
2230 + dev_err(dev, "Failed to detect IRQ type\n");
2231 + goto reset_handler;
2232 + }
2233
2234 if (command & COMMAND_RAISE_LEGACY_IRQ) {
2235 reg->status = STATUS_IRQ_RAISED;
2236 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
2237 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
2238 goto reset_handler;
2239 }
2240
2241 @@ -301,7 +314,8 @@ static void pci_epf_test_cmd_handler(str
2242 reg->status |= STATUS_WRITE_FAIL;
2243 else
2244 reg->status |= STATUS_WRITE_SUCCESS;
2245 - pci_epf_test_raise_irq(epf_test, irq);
2246 + pci_epf_test_raise_irq(epf_test, reg->irq_type,
2247 + reg->irq_number);
2248 goto reset_handler;
2249 }
2250
2251 @@ -311,7 +325,8 @@ static void pci_epf_test_cmd_handler(str
2252 reg->status |= STATUS_READ_SUCCESS;
2253 else
2254 reg->status |= STATUS_READ_FAIL;
2255 - pci_epf_test_raise_irq(epf_test, irq);
2256 + pci_epf_test_raise_irq(epf_test, reg->irq_type,
2257 + reg->irq_number);
2258 goto reset_handler;
2259 }
2260
2261 @@ -321,16 +336,28 @@ static void pci_epf_test_cmd_handler(str
2262 reg->status |= STATUS_COPY_SUCCESS;
2263 else
2264 reg->status |= STATUS_COPY_FAIL;
2265 - pci_epf_test_raise_irq(epf_test, irq);
2266 + pci_epf_test_raise_irq(epf_test, reg->irq_type,
2267 + reg->irq_number);
2268 goto reset_handler;
2269 }
2270
2271 if (command & COMMAND_RAISE_MSI_IRQ) {
2272 - msi_count = pci_epc_get_msi(epc);
2273 - if (irq > msi_count || msi_count <= 0)
2274 + count = pci_epc_get_msi(epc, epf->func_no);
2275 + if (reg->irq_number > count || count <= 0)
2276 + goto reset_handler;
2277 + reg->status = STATUS_IRQ_RAISED;
2278 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI,
2279 + reg->irq_number);
2280 + goto reset_handler;
2281 + }
2282 +
2283 + if (command & COMMAND_RAISE_MSIX_IRQ) {
2284 + count = pci_epc_get_msix(epc, epf->func_no);
2285 + if (reg->irq_number > count || count <= 0)
2286 goto reset_handler;
2287 reg->status = STATUS_IRQ_RAISED;
2288 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
2289 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSIX,
2290 + reg->irq_number);
2291 goto reset_handler;
2292 }
2293
2294 @@ -351,21 +378,23 @@ static void pci_epf_test_unbind(struct p
2295 {
2296 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
2297 struct pci_epc *epc = epf->epc;
2298 + struct pci_epf_bar *epf_bar;
2299 int bar;
2300
2301 cancel_delayed_work(&epf_test->cmd_handler);
2302 pci_epc_stop(epc);
2303 for (bar = BAR_0; bar <= BAR_5; bar++) {
2304 + epf_bar = &epf->bar[bar];
2305 +
2306 if (epf_test->reg[bar]) {
2307 pci_epf_free_space(epf, epf_test->reg[bar], bar);
2308 - pci_epc_clear_bar(epc, bar);
2309 + pci_epc_clear_bar(epc, epf->func_no, epf_bar);
2310 }
2311 }
2312 }
2313
2314 static int pci_epf_test_set_bar(struct pci_epf *epf)
2315 {
2316 - int flags;
2317 int bar;
2318 int ret;
2319 struct pci_epf_bar *epf_bar;
2320 @@ -374,20 +403,27 @@ static int pci_epf_test_set_bar(struct p
2321 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
2322 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
2323
2324 - flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32;
2325 - if (sizeof(dma_addr_t) == 0x8)
2326 - flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
2327 -
2328 for (bar = BAR_0; bar <= BAR_5; bar++) {
2329 epf_bar = &epf->bar[bar];
2330 - ret = pci_epc_set_bar(epc, bar, epf_bar->phys_addr,
2331 - epf_bar->size, flags);
2332 +
2333 + epf_bar->flags |= upper_32_bits(epf_bar->size) ?
2334 + PCI_BASE_ADDRESS_MEM_TYPE_64 :
2335 + PCI_BASE_ADDRESS_MEM_TYPE_32;
2336 +
2337 + ret = pci_epc_set_bar(epc, epf->func_no, epf_bar);
2338 if (ret) {
2339 pci_epf_free_space(epf, epf_test->reg[bar], bar);
2340 - dev_err(dev, "failed to set BAR%d\n", bar);
2341 + dev_err(dev, "Failed to set BAR%d\n", bar);
2342 if (bar == test_reg_bar)
2343 return ret;
2344 }
2345 + /*
2346 + * pci_epc_set_bar() sets PCI_BASE_ADDRESS_MEM_TYPE_64
2347 + * if the specific implementation required a 64-bit BAR,
2348 + * even if we only requested a 32-bit BAR.
2349 + */
2350 + if (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
2351 + bar++;
2352 }
2353
2354 return 0;
2355 @@ -404,7 +440,7 @@ static int pci_epf_test_alloc_space(stru
2356 base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg),
2357 test_reg_bar);
2358 if (!base) {
2359 - dev_err(dev, "failed to allocated register space\n");
2360 + dev_err(dev, "Failed to allocated register space\n");
2361 return -ENOMEM;
2362 }
2363 epf_test->reg[test_reg_bar] = base;
2364 @@ -414,7 +450,7 @@ static int pci_epf_test_alloc_space(stru
2365 continue;
2366 base = pci_epf_alloc_space(epf, bar_size[bar], bar);
2367 if (!base)
2368 - dev_err(dev, "failed to allocate space for BAR%d\n",
2369 + dev_err(dev, "Failed to allocate space for BAR%d\n",
2370 bar);
2371 epf_test->reg[bar] = base;
2372 }
2373 @@ -433,9 +469,18 @@ static int pci_epf_test_bind(struct pci_
2374 if (WARN_ON_ONCE(!epc))
2375 return -EINVAL;
2376
2377 - ret = pci_epc_write_header(epc, header);
2378 + if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER)
2379 + epf_test->linkup_notifier = false;
2380 + else
2381 + epf_test->linkup_notifier = true;
2382 +
2383 + epf_test->msix_available = epc->features & EPC_FEATURE_MSIX_AVAILABLE;
2384 +
2385 + epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features);
2386 +
2387 + ret = pci_epc_write_header(epc, epf->func_no, header);
2388 if (ret) {
2389 - dev_err(dev, "configuration header write failed\n");
2390 + dev_err(dev, "Configuration header write failed\n");
2391 return ret;
2392 }
2393
2394 @@ -447,9 +492,19 @@ static int pci_epf_test_bind(struct pci_
2395 if (ret)
2396 return ret;
2397
2398 - ret = pci_epc_set_msi(epc, epf->msi_interrupts);
2399 - if (ret)
2400 + ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
2401 + if (ret) {
2402 + dev_err(dev, "MSI configuration failed\n");
2403 return ret;
2404 + }
2405 +
2406 + if (epf_test->msix_available) {
2407 + ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
2408 + if (ret) {
2409 + dev_err(dev, "MSI-X configuration failed\n");
2410 + return ret;
2411 + }
2412 + }
2413
2414 if (!epf_test->linkup_notifier)
2415 queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work);
2416 @@ -517,7 +572,7 @@ static int __init pci_epf_test_init(void
2417 WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
2418 ret = pci_epf_register_driver(&test_driver);
2419 if (ret) {
2420 - pr_err("failed to register pci epf test driver --> %d\n", ret);
2421 + pr_err("Failed to register pci epf test driver --> %d\n", ret);
2422 return ret;
2423 }
2424
2425 --- a/drivers/pci/endpoint/pci-ep-cfs.c
2426 +++ b/drivers/pci/endpoint/pci-ep-cfs.c
2427 @@ -1,35 +1,28 @@
2428 +// SPDX-License-Identifier: GPL-2.0
2429 /**
2430 * configfs to configure the PCI endpoint
2431 *
2432 * Copyright (C) 2017 Texas Instruments
2433 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2434 - *
2435 - * This program is free software: you can redistribute it and/or modify
2436 - * it under the terms of the GNU General Public License version 2 of
2437 - * the License as published by the Free Software Foundation.
2438 - *
2439 - * This program is distributed in the hope that it will be useful,
2440 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2441 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2442 - * GNU General Public License for more details.
2443 - *
2444 - * You should have received a copy of the GNU General Public License
2445 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2446 */
2447
2448 #include <linux/module.h>
2449 +#include <linux/idr.h>
2450 #include <linux/slab.h>
2451
2452 #include <linux/pci-epc.h>
2453 #include <linux/pci-epf.h>
2454 #include <linux/pci-ep-cfs.h>
2455
2456 +static DEFINE_IDR(functions_idr);
2457 +static DEFINE_MUTEX(functions_mutex);
2458 static struct config_group *functions_group;
2459 static struct config_group *controllers_group;
2460
2461 struct pci_epf_group {
2462 struct config_group group;
2463 struct pci_epf *epf;
2464 + int index;
2465 };
2466
2467 struct pci_epc_group {
2468 @@ -151,7 +144,7 @@ static struct configfs_item_operations p
2469 .drop_link = pci_epc_epf_unlink,
2470 };
2471
2472 -static struct config_item_type pci_epc_type = {
2473 +static const struct config_item_type pci_epc_type = {
2474 .ct_item_ops = &pci_epc_item_ops,
2475 .ct_attrs = pci_epc_attrs,
2476 .ct_owner = THIS_MODULE,
2477 @@ -293,6 +286,28 @@ static ssize_t pci_epf_msi_interrupts_sh
2478 to_pci_epf_group(item)->epf->msi_interrupts);
2479 }
2480
2481 +static ssize_t pci_epf_msix_interrupts_store(struct config_item *item,
2482 + const char *page, size_t len)
2483 +{
2484 + u16 val;
2485 + int ret;
2486 +
2487 + ret = kstrtou16(page, 0, &val);
2488 + if (ret)
2489 + return ret;
2490 +
2491 + to_pci_epf_group(item)->epf->msix_interrupts = val;
2492 +
2493 + return len;
2494 +}
2495 +
2496 +static ssize_t pci_epf_msix_interrupts_show(struct config_item *item,
2497 + char *page)
2498 +{
2499 + return sprintf(page, "%d\n",
2500 + to_pci_epf_group(item)->epf->msix_interrupts);
2501 +}
2502 +
2503 PCI_EPF_HEADER_R(vendorid)
2504 PCI_EPF_HEADER_W_u16(vendorid)
2505
2506 @@ -334,6 +349,7 @@ CONFIGFS_ATTR(pci_epf_, subsys_vendor_id
2507 CONFIGFS_ATTR(pci_epf_, subsys_id);
2508 CONFIGFS_ATTR(pci_epf_, interrupt_pin);
2509 CONFIGFS_ATTR(pci_epf_, msi_interrupts);
2510 +CONFIGFS_ATTR(pci_epf_, msix_interrupts);
2511
2512 static struct configfs_attribute *pci_epf_attrs[] = {
2513 &pci_epf_attr_vendorid,
2514 @@ -347,6 +363,7 @@ static struct configfs_attribute *pci_ep
2515 &pci_epf_attr_subsys_id,
2516 &pci_epf_attr_interrupt_pin,
2517 &pci_epf_attr_msi_interrupts,
2518 + &pci_epf_attr_msix_interrupts,
2519 NULL,
2520 };
2521
2522 @@ -354,6 +371,9 @@ static void pci_epf_release(struct confi
2523 {
2524 struct pci_epf_group *epf_group = to_pci_epf_group(item);
2525
2526 + mutex_lock(&functions_mutex);
2527 + idr_remove(&functions_idr, epf_group->index);
2528 + mutex_unlock(&functions_mutex);
2529 pci_epf_destroy(epf_group->epf);
2530 kfree(epf_group);
2531 }
2532 @@ -362,7 +382,7 @@ static struct configfs_item_operations p
2533 .release = pci_epf_release,
2534 };
2535
2536 -static struct config_item_type pci_epf_type = {
2537 +static const struct config_item_type pci_epf_type = {
2538 .ct_item_ops = &pci_epf_ops,
2539 .ct_attrs = pci_epf_attrs,
2540 .ct_owner = THIS_MODULE,
2541 @@ -373,22 +393,57 @@ static struct config_group *pci_epf_make
2542 {
2543 struct pci_epf_group *epf_group;
2544 struct pci_epf *epf;
2545 + char *epf_name;
2546 + int index, err;
2547
2548 epf_group = kzalloc(sizeof(*epf_group), GFP_KERNEL);
2549 if (!epf_group)
2550 return ERR_PTR(-ENOMEM);
2551
2552 + mutex_lock(&functions_mutex);
2553 + index = idr_alloc(&functions_idr, epf_group, 0, 0, GFP_KERNEL);
2554 + mutex_unlock(&functions_mutex);
2555 + if (index < 0) {
2556 + err = index;
2557 + goto free_group;
2558 + }
2559 +
2560 + epf_group->index = index;
2561 +
2562 config_group_init_type_name(&epf_group->group, name, &pci_epf_type);
2563
2564 - epf = pci_epf_create(group->cg_item.ci_name);
2565 + epf_name = kasprintf(GFP_KERNEL, "%s.%d",
2566 + group->cg_item.ci_name, epf_group->index);
2567 + if (!epf_name) {
2568 + err = -ENOMEM;
2569 + goto remove_idr;
2570 + }
2571 +
2572 + epf = pci_epf_create(epf_name);
2573 if (IS_ERR(epf)) {
2574 pr_err("failed to create endpoint function device\n");
2575 - return ERR_PTR(-EINVAL);
2576 + err = -EINVAL;
2577 + goto free_name;
2578 }
2579
2580 epf_group->epf = epf;
2581
2582 + kfree(epf_name);
2583 +
2584 return &epf_group->group;
2585 +
2586 +free_name:
2587 + kfree(epf_name);
2588 +
2589 +remove_idr:
2590 + mutex_lock(&functions_mutex);
2591 + idr_remove(&functions_idr, epf_group->index);
2592 + mutex_unlock(&functions_mutex);
2593 +
2594 +free_group:
2595 + kfree(epf_group);
2596 +
2597 + return ERR_PTR(err);
2598 }
2599
2600 static void pci_epf_drop(struct config_group *group, struct config_item *item)
2601 @@ -401,7 +456,7 @@ static struct configfs_group_operations
2602 .drop_item = &pci_epf_drop,
2603 };
2604
2605 -static struct config_item_type pci_epf_group_type = {
2606 +static const struct config_item_type pci_epf_group_type = {
2607 .ct_group_ops = &pci_epf_group_ops,
2608 .ct_owner = THIS_MODULE,
2609 };
2610 @@ -429,15 +484,15 @@ void pci_ep_cfs_remove_epf_group(struct
2611 }
2612 EXPORT_SYMBOL(pci_ep_cfs_remove_epf_group);
2613
2614 -static struct config_item_type pci_functions_type = {
2615 +static const struct config_item_type pci_functions_type = {
2616 .ct_owner = THIS_MODULE,
2617 };
2618
2619 -static struct config_item_type pci_controllers_type = {
2620 +static const struct config_item_type pci_controllers_type = {
2621 .ct_owner = THIS_MODULE,
2622 };
2623
2624 -static struct config_item_type pci_ep_type = {
2625 +static const struct config_item_type pci_ep_type = {
2626 .ct_owner = THIS_MODULE,
2627 };
2628
2629 --- a/drivers/pci/endpoint/pci-epc-core.c
2630 +++ b/drivers/pci/endpoint/pci-epc-core.c
2631 @@ -1,20 +1,9 @@
2632 +// SPDX-License-Identifier: GPL-2.0
2633 /**
2634 * PCI Endpoint *Controller* (EPC) library
2635 *
2636 * Copyright (C) 2017 Texas Instruments
2637 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2638 - *
2639 - * This program is free software: you can redistribute it and/or modify
2640 - * it under the terms of the GNU General Public License version 2 of
2641 - * the License as published by the Free Software Foundation.
2642 - *
2643 - * This program is distributed in the hope that it will be useful,
2644 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2645 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2646 - * GNU General Public License for more details.
2647 - *
2648 - * You should have received a copy of the GNU General Public License
2649 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2650 */
2651
2652 #include <linux/device.h>
2653 @@ -141,25 +130,26 @@ EXPORT_SYMBOL_GPL(pci_epc_start);
2654 /**
2655 * pci_epc_raise_irq() - interrupt the host system
2656 * @epc: the EPC device which has to interrupt the host
2657 - * @type: specify the type of interrupt; legacy or MSI
2658 - * @interrupt_num: the MSI interrupt number
2659 + * @func_no: the endpoint function number in the EPC device
2660 + * @type: specify the type of interrupt; legacy, MSI or MSI-X
2661 + * @interrupt_num: the MSI or MSI-X interrupt number
2662 *
2663 - * Invoke to raise an MSI or legacy interrupt
2664 + * Invoke to raise an legacy, MSI or MSI-X interrupt
2665 */
2666 -int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
2667 - u8 interrupt_num)
2668 +int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
2669 + enum pci_epc_irq_type type, u16 interrupt_num)
2670 {
2671 int ret;
2672 unsigned long flags;
2673
2674 - if (IS_ERR(epc))
2675 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2676 return -EINVAL;
2677
2678 if (!epc->ops->raise_irq)
2679 return 0;
2680
2681 spin_lock_irqsave(&epc->lock, flags);
2682 - ret = epc->ops->raise_irq(epc, type, interrupt_num);
2683 + ret = epc->ops->raise_irq(epc, func_no, type, interrupt_num);
2684 spin_unlock_irqrestore(&epc->lock, flags);
2685
2686 return ret;
2687 @@ -169,22 +159,23 @@ EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
2688 /**
2689 * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated
2690 * @epc: the EPC device to which MSI interrupts was requested
2691 + * @func_no: the endpoint function number in the EPC device
2692 *
2693 * Invoke to get the number of MSI interrupts allocated by the RC
2694 */
2695 -int pci_epc_get_msi(struct pci_epc *epc)
2696 +int pci_epc_get_msi(struct pci_epc *epc, u8 func_no)
2697 {
2698 int interrupt;
2699 unsigned long flags;
2700
2701 - if (IS_ERR(epc))
2702 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2703 return 0;
2704
2705 if (!epc->ops->get_msi)
2706 return 0;
2707
2708 spin_lock_irqsave(&epc->lock, flags);
2709 - interrupt = epc->ops->get_msi(epc);
2710 + interrupt = epc->ops->get_msi(epc, func_no);
2711 spin_unlock_irqrestore(&epc->lock, flags);
2712
2713 if (interrupt < 0)
2714 @@ -199,17 +190,19 @@ EXPORT_SYMBOL_GPL(pci_epc_get_msi);
2715 /**
2716 * pci_epc_set_msi() - set the number of MSI interrupt numbers required
2717 * @epc: the EPC device on which MSI has to be configured
2718 + * @func_no: the endpoint function number in the EPC device
2719 * @interrupts: number of MSI interrupts required by the EPF
2720 *
2721 * Invoke to set the required number of MSI interrupts.
2722 */
2723 -int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts)
2724 +int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
2725 {
2726 int ret;
2727 u8 encode_int;
2728 unsigned long flags;
2729
2730 - if (IS_ERR(epc))
2731 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2732 + interrupts > 32)
2733 return -EINVAL;
2734
2735 if (!epc->ops->set_msi)
2736 @@ -218,7 +211,7 @@ int pci_epc_set_msi(struct pci_epc *epc,
2737 encode_int = order_base_2(interrupts);
2738
2739 spin_lock_irqsave(&epc->lock, flags);
2740 - ret = epc->ops->set_msi(epc, encode_int);
2741 + ret = epc->ops->set_msi(epc, func_no, encode_int);
2742 spin_unlock_irqrestore(&epc->lock, flags);
2743
2744 return ret;
2745 @@ -226,24 +219,83 @@ int pci_epc_set_msi(struct pci_epc *epc,
2746 EXPORT_SYMBOL_GPL(pci_epc_set_msi);
2747
2748 /**
2749 + * pci_epc_get_msix() - get the number of MSI-X interrupt numbers allocated
2750 + * @epc: the EPC device to which MSI-X interrupts was requested
2751 + * @func_no: the endpoint function number in the EPC device
2752 + *
2753 + * Invoke to get the number of MSI-X interrupts allocated by the RC
2754 + */
2755 +int pci_epc_get_msix(struct pci_epc *epc, u8 func_no)
2756 +{
2757 + int interrupt;
2758 + unsigned long flags;
2759 +
2760 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2761 + return 0;
2762 +
2763 + if (!epc->ops->get_msix)
2764 + return 0;
2765 +
2766 + spin_lock_irqsave(&epc->lock, flags);
2767 + interrupt = epc->ops->get_msix(epc, func_no);
2768 + spin_unlock_irqrestore(&epc->lock, flags);
2769 +
2770 + if (interrupt < 0)
2771 + return 0;
2772 +
2773 + return interrupt + 1;
2774 +}
2775 +EXPORT_SYMBOL_GPL(pci_epc_get_msix);
2776 +
2777 +/**
2778 + * pci_epc_set_msix() - set the number of MSI-X interrupt numbers required
2779 + * @epc: the EPC device on which MSI-X has to be configured
2780 + * @func_no: the endpoint function number in the EPC device
2781 + * @interrupts: number of MSI-X interrupts required by the EPF
2782 + *
2783 + * Invoke to set the required number of MSI-X interrupts.
2784 + */
2785 +int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
2786 +{
2787 + int ret;
2788 + unsigned long flags;
2789 +
2790 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2791 + interrupts < 1 || interrupts > 2048)
2792 + return -EINVAL;
2793 +
2794 + if (!epc->ops->set_msix)
2795 + return 0;
2796 +
2797 + spin_lock_irqsave(&epc->lock, flags);
2798 + ret = epc->ops->set_msix(epc, func_no, interrupts - 1);
2799 + spin_unlock_irqrestore(&epc->lock, flags);
2800 +
2801 + return ret;
2802 +}
2803 +EXPORT_SYMBOL_GPL(pci_epc_set_msix);
2804 +
2805 +/**
2806 * pci_epc_unmap_addr() - unmap CPU address from PCI address
2807 * @epc: the EPC device on which address is allocated
2808 + * @func_no: the endpoint function number in the EPC device
2809 * @phys_addr: physical address of the local system
2810 *
2811 * Invoke to unmap the CPU address from PCI address.
2812 */
2813 -void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr)
2814 +void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
2815 + phys_addr_t phys_addr)
2816 {
2817 unsigned long flags;
2818
2819 - if (IS_ERR(epc))
2820 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2821 return;
2822
2823 if (!epc->ops->unmap_addr)
2824 return;
2825
2826 spin_lock_irqsave(&epc->lock, flags);
2827 - epc->ops->unmap_addr(epc, phys_addr);
2828 + epc->ops->unmap_addr(epc, func_no, phys_addr);
2829 spin_unlock_irqrestore(&epc->lock, flags);
2830 }
2831 EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
2832 @@ -251,26 +303,27 @@ EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
2833 /**
2834 * pci_epc_map_addr() - map CPU address to PCI address
2835 * @epc: the EPC device on which address is allocated
2836 + * @func_no: the endpoint function number in the EPC device
2837 * @phys_addr: physical address of the local system
2838 * @pci_addr: PCI address to which the physical address should be mapped
2839 * @size: the size of the allocation
2840 *
2841 * Invoke to map CPU address with PCI address.
2842 */
2843 -int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
2844 - u64 pci_addr, size_t size)
2845 +int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
2846 + phys_addr_t phys_addr, u64 pci_addr, size_t size)
2847 {
2848 int ret;
2849 unsigned long flags;
2850
2851 - if (IS_ERR(epc))
2852 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2853 return -EINVAL;
2854
2855 if (!epc->ops->map_addr)
2856 return 0;
2857
2858 spin_lock_irqsave(&epc->lock, flags);
2859 - ret = epc->ops->map_addr(epc, phys_addr, pci_addr, size);
2860 + ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size);
2861 spin_unlock_irqrestore(&epc->lock, flags);
2862
2863 return ret;
2864 @@ -280,22 +333,26 @@ EXPORT_SYMBOL_GPL(pci_epc_map_addr);
2865 /**
2866 * pci_epc_clear_bar() - reset the BAR
2867 * @epc: the EPC device for which the BAR has to be cleared
2868 - * @bar: the BAR number that has to be reset
2869 + * @func_no: the endpoint function number in the EPC device
2870 + * @epf_bar: the struct epf_bar that contains the BAR information
2871 *
2872 * Invoke to reset the BAR of the endpoint device.
2873 */
2874 -void pci_epc_clear_bar(struct pci_epc *epc, int bar)
2875 +void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
2876 + struct pci_epf_bar *epf_bar)
2877 {
2878 unsigned long flags;
2879
2880 - if (IS_ERR(epc))
2881 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2882 + (epf_bar->barno == BAR_5 &&
2883 + epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
2884 return;
2885
2886 if (!epc->ops->clear_bar)
2887 return;
2888
2889 spin_lock_irqsave(&epc->lock, flags);
2890 - epc->ops->clear_bar(epc, bar);
2891 + epc->ops->clear_bar(epc, func_no, epf_bar);
2892 spin_unlock_irqrestore(&epc->lock, flags);
2893 }
2894 EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
2895 @@ -303,26 +360,32 @@ EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
2896 /**
2897 * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space
2898 * @epc: the EPC device on which BAR has to be configured
2899 - * @bar: the BAR number that has to be configured
2900 - * @size: the size of the addr space
2901 - * @flags: specify memory allocation/io allocation/32bit address/64 bit address
2902 + * @func_no: the endpoint function number in the EPC device
2903 + * @epf_bar: the struct epf_bar that contains the BAR information
2904 *
2905 * Invoke to configure the BAR of the endpoint device.
2906 */
2907 -int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
2908 - dma_addr_t bar_phys, size_t size, int flags)
2909 +int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
2910 + struct pci_epf_bar *epf_bar)
2911 {
2912 int ret;
2913 unsigned long irq_flags;
2914 + int flags = epf_bar->flags;
2915
2916 - if (IS_ERR(epc))
2917 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2918 + (epf_bar->barno == BAR_5 &&
2919 + flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ||
2920 + (flags & PCI_BASE_ADDRESS_SPACE_IO &&
2921 + flags & PCI_BASE_ADDRESS_IO_MASK) ||
2922 + (upper_32_bits(epf_bar->size) &&
2923 + !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
2924 return -EINVAL;
2925
2926 if (!epc->ops->set_bar)
2927 return 0;
2928
2929 spin_lock_irqsave(&epc->lock, irq_flags);
2930 - ret = epc->ops->set_bar(epc, bar, bar_phys, size, flags);
2931 + ret = epc->ops->set_bar(epc, func_no, epf_bar);
2932 spin_unlock_irqrestore(&epc->lock, irq_flags);
2933
2934 return ret;
2935 @@ -332,6 +395,7 @@ EXPORT_SYMBOL_GPL(pci_epc_set_bar);
2936 /**
2937 * pci_epc_write_header() - write standard configuration header
2938 * @epc: the EPC device to which the configuration header should be written
2939 + * @func_no: the endpoint function number in the EPC device
2940 * @header: standard configuration header fields
2941 *
2942 * Invoke to write the configuration header to the endpoint controller. Every
2943 @@ -339,19 +403,20 @@ EXPORT_SYMBOL_GPL(pci_epc_set_bar);
2944 * configuration header would be written. The callback function should write
2945 * the header fields to this dedicated location.
2946 */
2947 -int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *header)
2948 +int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
2949 + struct pci_epf_header *header)
2950 {
2951 int ret;
2952 unsigned long flags;
2953
2954 - if (IS_ERR(epc))
2955 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2956 return -EINVAL;
2957
2958 if (!epc->ops->write_header)
2959 return 0;
2960
2961 spin_lock_irqsave(&epc->lock, flags);
2962 - ret = epc->ops->write_header(epc, header);
2963 + ret = epc->ops->write_header(epc, func_no, header);
2964 spin_unlock_irqrestore(&epc->lock, flags);
2965
2966 return ret;
2967 --- a/drivers/pci/endpoint/pci-epc-mem.c
2968 +++ b/drivers/pci/endpoint/pci-epc-mem.c
2969 @@ -1,20 +1,9 @@
2970 +// SPDX-License-Identifier: GPL-2.0
2971 /**
2972 * PCI Endpoint *Controller* Address Space Management
2973 *
2974 * Copyright (C) 2017 Texas Instruments
2975 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2976 - *
2977 - * This program is free software: you can redistribute it and/or modify
2978 - * it under the terms of the GNU General Public License version 2 of
2979 - * the License as published by the Free Software Foundation.
2980 - *
2981 - * This program is distributed in the hope that it will be useful,
2982 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2983 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2984 - * GNU General Public License for more details.
2985 - *
2986 - * You should have received a copy of the GNU General Public License
2987 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2988 */
2989
2990 #include <linux/io.h>
2991 --- a/drivers/pci/endpoint/pci-epf-core.c
2992 +++ b/drivers/pci/endpoint/pci-epf-core.c
2993 @@ -1,20 +1,9 @@
2994 +// SPDX-License-Identifier: GPL-2.0
2995 /**
2996 * PCI Endpoint *Function* (EPF) library
2997 *
2998 * Copyright (C) 2017 Texas Instruments
2999 * Author: Kishon Vijay Abraham I <kishon@ti.com>
3000 - *
3001 - * This program is free software: you can redistribute it and/or modify
3002 - * it under the terms of the GNU General Public License version 2 of
3003 - * the License as published by the Free Software Foundation.
3004 - *
3005 - * This program is distributed in the hope that it will be useful,
3006 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
3007 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3008 - * GNU General Public License for more details.
3009 - *
3010 - * You should have received a copy of the GNU General Public License
3011 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
3012 */
3013
3014 #include <linux/device.h>
3015 @@ -26,6 +15,8 @@
3016 #include <linux/pci-epf.h>
3017 #include <linux/pci-ep-cfs.h>
3018
3019 +static DEFINE_MUTEX(pci_epf_mutex);
3020 +
3021 static struct bus_type pci_epf_bus_type;
3022 static const struct device_type pci_epf_type;
3023
3024 @@ -109,6 +100,8 @@ void pci_epf_free_space(struct pci_epf *
3025
3026 epf->bar[bar].phys_addr = 0;
3027 epf->bar[bar].size = 0;
3028 + epf->bar[bar].barno = 0;
3029 + epf->bar[bar].flags = 0;
3030 }
3031 EXPORT_SYMBOL_GPL(pci_epf_free_space);
3032
3033 @@ -137,11 +130,27 @@ void *pci_epf_alloc_space(struct pci_epf
3034
3035 epf->bar[bar].phys_addr = phys_addr;
3036 epf->bar[bar].size = size;
3037 + epf->bar[bar].barno = bar;
3038 + epf->bar[bar].flags = PCI_BASE_ADDRESS_SPACE_MEMORY;
3039
3040 return space;
3041 }
3042 EXPORT_SYMBOL_GPL(pci_epf_alloc_space);
3043
3044 +static void pci_epf_remove_cfs(struct pci_epf_driver *driver)
3045 +{
3046 + struct config_group *group, *tmp;
3047 +
3048 + if (!IS_ENABLED(CONFIG_PCI_ENDPOINT_CONFIGFS))
3049 + return;
3050 +
3051 + mutex_lock(&pci_epf_mutex);
3052 + list_for_each_entry_safe(group, tmp, &driver->epf_group, group_entry)
3053 + pci_ep_cfs_remove_epf_group(group);
3054 + list_del(&driver->epf_group);
3055 + mutex_unlock(&pci_epf_mutex);
3056 +}
3057 +
3058 /**
3059 * pci_epf_unregister_driver() - unregister the PCI EPF driver
3060 * @driver: the PCI EPF driver that has to be unregistered
3061 @@ -150,11 +159,38 @@ EXPORT_SYMBOL_GPL(pci_epf_alloc_space);
3062 */
3063 void pci_epf_unregister_driver(struct pci_epf_driver *driver)
3064 {
3065 - pci_ep_cfs_remove_epf_group(driver->group);
3066 + pci_epf_remove_cfs(driver);
3067 driver_unregister(&driver->driver);
3068 }
3069 EXPORT_SYMBOL_GPL(pci_epf_unregister_driver);
3070
3071 +static int pci_epf_add_cfs(struct pci_epf_driver *driver)
3072 +{
3073 + struct config_group *group;
3074 + const struct pci_epf_device_id *id;
3075 +
3076 + if (!IS_ENABLED(CONFIG_PCI_ENDPOINT_CONFIGFS))
3077 + return 0;
3078 +
3079 + INIT_LIST_HEAD(&driver->epf_group);
3080 +
3081 + id = driver->id_table;
3082 + while (id->name[0]) {
3083 + group = pci_ep_cfs_add_epf_group(id->name);
3084 + if (IS_ERR(group)) {
3085 + pci_epf_remove_cfs(driver);
3086 + return PTR_ERR(group);
3087 + }
3088 +
3089 + mutex_lock(&pci_epf_mutex);
3090 + list_add_tail(&group->group_entry, &driver->epf_group);
3091 + mutex_unlock(&pci_epf_mutex);
3092 + id++;
3093 + }
3094 +
3095 + return 0;
3096 +}
3097 +
3098 /**
3099 * __pci_epf_register_driver() - register a new PCI EPF driver
3100 * @driver: structure representing PCI EPF driver
3101 @@ -180,7 +216,7 @@ int __pci_epf_register_driver(struct pci
3102 if (ret)
3103 return ret;
3104
3105 - driver->group = pci_ep_cfs_add_epf_group(driver->driver.name);
3106 + pci_epf_add_cfs(driver);
3107
3108 return 0;
3109 }
3110 @@ -211,29 +247,17 @@ struct pci_epf *pci_epf_create(const cha
3111 int ret;
3112 struct pci_epf *epf;
3113 struct device *dev;
3114 - char *func_name;
3115 - char *buf;
3116 + int len;
3117
3118 epf = kzalloc(sizeof(*epf), GFP_KERNEL);
3119 - if (!epf) {
3120 - ret = -ENOMEM;
3121 - goto err_ret;
3122 - }
3123 + if (!epf)
3124 + return ERR_PTR(-ENOMEM);
3125
3126 - buf = kstrdup(name, GFP_KERNEL);
3127 - if (!buf) {
3128 - ret = -ENOMEM;
3129 - goto free_epf;
3130 - }
3131 -
3132 - func_name = buf;
3133 - buf = strchrnul(buf, '.');
3134 - *buf = '\0';
3135 -
3136 - epf->name = kstrdup(func_name, GFP_KERNEL);
3137 + len = strchrnul(name, '.') - name;
3138 + epf->name = kstrndup(name, len, GFP_KERNEL);
3139 if (!epf->name) {
3140 - ret = -ENOMEM;
3141 - goto free_func_name;
3142 + kfree(epf);
3143 + return ERR_PTR(-ENOMEM);
3144 }
3145
3146 dev = &epf->dev;
3147 @@ -242,28 +266,18 @@ struct pci_epf *pci_epf_create(const cha
3148 dev->type = &pci_epf_type;
3149
3150 ret = dev_set_name(dev, "%s", name);
3151 - if (ret)
3152 - goto put_dev;
3153 + if (ret) {
3154 + put_device(dev);
3155 + return ERR_PTR(ret);
3156 + }
3157
3158 ret = device_add(dev);
3159 - if (ret)
3160 - goto put_dev;
3161 + if (ret) {
3162 + put_device(dev);
3163 + return ERR_PTR(ret);
3164 + }
3165
3166 - kfree(func_name);
3167 return epf;
3168 -
3169 -put_dev:
3170 - put_device(dev);
3171 - kfree(epf->name);
3172 -
3173 -free_func_name:
3174 - kfree(func_name);
3175 -
3176 -free_epf:
3177 - kfree(epf);
3178 -
3179 -err_ret:
3180 - return ERR_PTR(ret);
3181 }
3182 EXPORT_SYMBOL_GPL(pci_epf_create);
3183
3184 --- a/drivers/pci/host/pci-host-common.c
3185 +++ b/drivers/pci/host/pci-host-common.c
3186 @@ -113,9 +113,7 @@ err_out:
3187 int pci_host_common_probe(struct platform_device *pdev,
3188 struct pci_ecam_ops *ops)
3189 {
3190 - const char *type;
3191 struct device *dev = &pdev->dev;
3192 - struct device_node *np = dev->of_node;
3193 struct pci_bus *bus, *child;
3194 struct pci_host_bridge *bridge;
3195 struct pci_config_window *cfg;
3196 @@ -126,12 +124,6 @@ int pci_host_common_probe(struct platfor
3197 if (!bridge)
3198 return -ENOMEM;
3199
3200 - type = of_get_property(np, "device_type", NULL);
3201 - if (!type || strcmp(type, "pci")) {
3202 - dev_err(dev, "invalid \"device_type\" %s\n", type);
3203 - return -EINVAL;
3204 - }
3205 -
3206 of_pci_check_probe_only();
3207
3208 /* Parse and map our Configuration Space windows */
3209 --- a/drivers/pci/host/pcie-xilinx-nwl.c
3210 +++ b/drivers/pci/host/pcie-xilinx-nwl.c
3211 @@ -779,16 +779,7 @@ static int nwl_pcie_parse_dt(struct nwl_
3212 struct platform_device *pdev)
3213 {
3214 struct device *dev = pcie->dev;
3215 - struct device_node *node = dev->of_node;
3216 struct resource *res;
3217 - const char *type;
3218 -
3219 - /* Check for device type */
3220 - type = of_get_property(node, "device_type", NULL);
3221 - if (!type || strcmp(type, "pci")) {
3222 - dev_err(dev, "invalid \"device_type\" %s\n", type);
3223 - return -EINVAL;
3224 - }
3225
3226 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
3227 pcie->breg_base = devm_ioremap_resource(dev, res);
3228 --- a/drivers/pci/host/pcie-xilinx.c
3229 +++ b/drivers/pci/host/pcie-xilinx.c
3230 @@ -576,15 +576,8 @@ static int xilinx_pcie_parse_dt(struct x
3231 struct device *dev = port->dev;
3232 struct device_node *node = dev->of_node;
3233 struct resource regs;
3234 - const char *type;
3235 int err;
3236
3237 - type = of_get_property(node, "device_type", NULL);
3238 - if (!type || strcmp(type, "pci")) {
3239 - dev_err(dev, "invalid \"device_type\" %s\n", type);
3240 - return -EINVAL;
3241 - }
3242 -
3243 err = of_address_to_resource(node, 0, &regs);
3244 if (err) {
3245 dev_err(dev, "missing \"reg\" property\n");
3246 --- /dev/null
3247 +++ b/drivers/pci/mobiveil/Kconfig
3248 @@ -0,0 +1,50 @@
3249 +# SPDX-License-Identifier: GPL-2.0
3250 +
3251 +menu "Mobiveil PCIe Core Support"
3252 + depends on PCI
3253 +
3254 +config PCIE_MOBIVEIL
3255 + bool
3256 +
3257 +config PCIE_MOBIVEIL_HOST
3258 + bool
3259 + depends on PCI_MSI_IRQ_DOMAIN
3260 + select PCIE_MOBIVEIL
3261 +
3262 +config PCIE_MOBIVEIL_EP
3263 + bool
3264 + depends on PCI_ENDPOINT
3265 + select PCIE_MOBIVEIL
3266 +
3267 +config PCIE_MOBIVEIL_PLAT
3268 + bool "Mobiveil AXI PCIe controller"
3269 + depends on ARCH_ZYNQMP || COMPILE_TEST
3270 + depends on OF
3271 + select PCIE_MOBIVEIL_HOST
3272 + help
3273 + Say Y here if you want to enable support for the Mobiveil AXI PCIe
3274 + Soft IP. It has up to 8 outbound and inbound windows
3275 + for address translation and it is a PCIe Gen4 IP.
3276 +
3277 +config PCI_LAYERSCAPE_GEN4
3278 + bool "Freescale Layerscpe PCIe Gen4 controller in RC mode"
3279 + depends on PCI
3280 + depends on OF && (ARM64 || ARCH_LAYERSCAPE)
3281 + depends on PCI_MSI_IRQ_DOMAIN
3282 + select PCIE_MOBIVEIL_HOST
3283 + help
3284 + Say Y here if you want PCIe Gen4 controller support on
3285 + Layerscape SoCs. And the PCIe controller work in RC mode
3286 + by setting the RCW[HOST_AGT_PEX] to 0.
3287 +
3288 +config PCI_LAYERSCAPE_GEN4_EP
3289 + bool "Freescale Layerscpe PCIe Gen4 controller in EP mode"
3290 + depends on PCI
3291 + depends on OF && (ARM64 || ARCH_LAYERSCAPE)
3292 + depends on PCI_ENDPOINT
3293 + select PCIE_MOBIVEIL_EP
3294 + help
3295 + Say Y here if you want PCIe Gen4 controller support on
3296 + Layerscape SoCs. And the PCIe controller work in EP mode
3297 + by setting the RCW[HOST_AGT_PEX] to 1.
3298 +endmenu
3299 --- /dev/null
3300 +++ b/drivers/pci/mobiveil/Makefile
3301 @@ -0,0 +1,7 @@
3302 +# SPDX-License-Identifier: GPL-2.0
3303 +obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
3304 +obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
3305 +obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
3306 +obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
3307 +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
3308 +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4_EP) += pci-layerscape-gen4-ep.o
3309 --- /dev/null
3310 +++ b/drivers/pci/mobiveil/pci-layerscape-gen4-ep.c
3311 @@ -0,0 +1,178 @@
3312 +// SPDX-License-Identifier: GPL-2.0
3313 +/*
3314 + * PCIe controller EP driver for Freescale Layerscape SoCs
3315 + *
3316 + * Copyright (C) 2018 NXP Semiconductor.
3317 + *
3318 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
3319 + */
3320 +
3321 +#include <linux/kernel.h>
3322 +#include <linux/init.h>
3323 +#include <linux/of_pci.h>
3324 +#include <linux/of_platform.h>
3325 +#include <linux/of_address.h>
3326 +#include <linux/pci.h>
3327 +#include <linux/platform_device.h>
3328 +#include <linux/resource.h>
3329 +
3330 +#include "pcie-mobiveil.h"
3331 +
3332 +struct ls_pcie_g4_ep {
3333 + struct mobiveil_pcie *mv_pci;
3334 +};
3335 +
3336 +#define to_ls_pcie_g4_ep(x) dev_get_drvdata((x)->dev)
3337 +
3338 +static const struct of_device_id ls_pcie_g4_ep_of_match[] = {
3339 + { .compatible = "fsl,lx2160a-pcie-ep",},
3340 + { },
3341 +};
3342 +
3343 +static void ls_pcie_g4_get_bar_num(struct mobiveil_pcie_ep *ep)
3344 +{
3345 + struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
3346 + u32 type, reg;
3347 + u8 bar;
3348 +
3349 + ep->bar_num = BAR_5 + 1;
3350 +
3351 + for (bar = BAR_0; bar <= BAR_5; bar++) {
3352 + reg = PCI_BASE_ADDRESS_0 + (4 * bar);
3353 + type = csr_readl(mv_pci, reg) &
3354 + PCI_BASE_ADDRESS_MEM_TYPE_MASK;
3355 + if (type & PCI_BASE_ADDRESS_MEM_TYPE_64)
3356 + ep->bar_num--;
3357 + }
3358 +}
3359 +
3360 +static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
3361 +{
3362 + struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
3363 + struct pci_epc *epc = ep->epc;
3364 + enum pci_barno bar;
3365 + int win_idx, val;
3366 +
3367 + /*
3368 + * Errata: unsupported request error on inbound posted write
3369 + * transaction, PCIe controller reports advisory error instead
3370 + * of uncorrectable error message to RC.
3371 + * workaround: set the bit20(unsupported_request_Error_severity) with
3372 + * value 1 in uncorrectable_Error_Severity_Register, make the
3373 + * unsupported request error generate the fatal error.
3374 + */
3375 + val = csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY);
3376 + val |= 1 << UNSUPPORTED_REQUEST_ERROR_SHIFT;
3377 + csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY);
3378 +
3379 + ls_pcie_g4_get_bar_num(ep);
3380 +
3381 + for (bar = BAR_0; bar < (ep->bar_num * ep->pf_num); bar++)
3382 + mobiveil_pcie_ep_reset_bar(mv_pci, bar);
3383 +
3384 + for (win_idx = 0; win_idx < MAX_IATU_OUT; win_idx++)
3385 + mobiveil_pcie_disable_ob_win(mv_pci, win_idx);
3386 +
3387 + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
3388 + epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
3389 +}
3390 +
3391 +static int ls_pcie_g4_ep_raise_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
3392 + enum pci_epc_irq_type type,
3393 + u16 interrupt_num)
3394 +{
3395 + struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
3396 +
3397 + switch (type) {
3398 + case PCI_EPC_IRQ_LEGACY:
3399 + return mobiveil_pcie_ep_raise_legacy_irq(ep, func_no);
3400 + case PCI_EPC_IRQ_MSI:
3401 + return mobiveil_pcie_ep_raise_msi_irq(ep, func_no,
3402 + interrupt_num);
3403 + case PCI_EPC_IRQ_MSIX:
3404 + return mobiveil_pcie_ep_raise_msix_irq(ep, func_no,
3405 + interrupt_num);
3406 + default:
3407 + dev_err(&mv_pci->pdev->dev, "UNKNOWN IRQ type\n");
3408 + }
3409 +
3410 + return 0;
3411 +}
3412 +
3413 +static struct mobiveil_pcie_ep_ops pcie_ep_ops = {
3414 + .ep_init = ls_pcie_g4_ep_init,
3415 + .raise_irq = ls_pcie_g4_ep_raise_irq,
3416 +};
3417 +
3418 +static int __init ls_pcie_gen4_add_pcie_ep(struct ls_pcie_g4_ep *ls_pcie_g4_ep,
3419 + struct platform_device *pdev)
3420 +{
3421 + struct mobiveil_pcie *mv_pci = ls_pcie_g4_ep->mv_pci;
3422 + struct device *dev = &pdev->dev;
3423 + struct mobiveil_pcie_ep *ep;
3424 + struct resource *res;
3425 + int ret;
3426 + struct device_node *np = dev->of_node;
3427 +
3428 + ep = &mv_pci->ep;
3429 + ep->ops = &pcie_ep_ops;
3430 +
3431 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
3432 + if (!res)
3433 + return -EINVAL;
3434 +
3435 + ep->phys_base = res->start;
3436 + ep->addr_size = resource_size(res);
3437 +
3438 + ret = of_property_read_u32(np, "max-functions", &ep->pf_num);
3439 + if (ret < 0)
3440 + ep->pf_num = 1;
3441 +
3442 + ret = mobiveil_pcie_ep_init(ep);
3443 + if (ret) {
3444 + dev_err(dev, "failed to initialize endpoint\n");
3445 + return ret;
3446 + }
3447 +
3448 + return 0;
3449 +}
3450 +
3451 +static int __init ls_pcie_g4_ep_probe(struct platform_device *pdev)
3452 +{
3453 + struct device *dev = &pdev->dev;
3454 + struct mobiveil_pcie *mv_pci;
3455 + struct ls_pcie_g4_ep *ls_pcie_g4_ep;
3456 + struct resource *res;
3457 + int ret;
3458 +
3459 + ls_pcie_g4_ep = devm_kzalloc(dev, sizeof(*ls_pcie_g4_ep), GFP_KERNEL);
3460 + if (!ls_pcie_g4_ep)
3461 + return -ENOMEM;
3462 +
3463 + mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
3464 + if (!mv_pci)
3465 + return -ENOMEM;
3466 +
3467 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3468 + mv_pci->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
3469 + if (IS_ERR(mv_pci->csr_axi_slave_base))
3470 + return PTR_ERR(mv_pci->csr_axi_slave_base);
3471 +
3472 + mv_pci->pdev = pdev;
3473 + ls_pcie_g4_ep->mv_pci = mv_pci;
3474 +
3475 + platform_set_drvdata(pdev, ls_pcie_g4_ep);
3476 +
3477 + ret = ls_pcie_gen4_add_pcie_ep(ls_pcie_g4_ep, pdev);
3478 +
3479 + return ret;
3480 +}
3481 +
3482 +static struct platform_driver ls_pcie_g4_ep_driver = {
3483 + .driver = {
3484 + .name = "layerscape-pcie-gen4-ep",
3485 + .of_match_table = ls_pcie_g4_ep_of_match,
3486 + .suppress_bind_attrs = true,
3487 + },
3488 +};
3489 +builtin_platform_driver_probe(ls_pcie_g4_ep_driver, ls_pcie_g4_ep_probe);
3490 --- /dev/null
3491 +++ b/drivers/pci/mobiveil/pci-layerscape-gen4.c
3492 @@ -0,0 +1,292 @@
3493 +// SPDX-License-Identifier: GPL-2.0
3494 +/*
3495 + * PCIe host controller driver for NXP Layerscape SoCs
3496 + *
3497 + * Copyright 2018 NXP
3498 + *
3499 + * Author: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
3500 + */
3501 +
3502 +#include <linux/kernel.h>
3503 +#include <linux/interrupt.h>
3504 +#include <linux/init.h>
3505 +#include <linux/of_pci.h>
3506 +#include <linux/of_platform.h>
3507 +#include <linux/of_irq.h>
3508 +#include <linux/of_address.h>
3509 +#include <linux/pci.h>
3510 +#include <linux/platform_device.h>
3511 +#include <linux/resource.h>
3512 +#include <linux/mfd/syscon.h>
3513 +#include <linux/regmap.h>
3514 +
3515 +#include "pcie-mobiveil.h"
3516 +
3517 +/* LUT and PF control registers */
3518 +#define PCIE_LUT_OFF (0x80000)
3519 +#define PCIE_LUT_GCR (0x28)
3520 +#define PCIE_LUT_GCR_RRE (0)
3521 +
3522 +#define PCIE_PF_OFF (0xc0000)
3523 +#define PCIE_PF_INT_STAT (0x18)
3524 +#define PF_INT_STAT_PABRST (31)
3525 +
3526 +#define PCIE_PF_DBG (0x7fc)
3527 +#define PF_DBG_LTSSM_MASK (0x3f)
3528 +#define PF_DBG_WE (31)
3529 +#define PF_DBG_PABR (27)
3530 +
3531 +#define LS_PCIE_G4_LTSSM_L0 0x2d /* L0 state */
3532 +
3533 +#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev)
3534 +
3535 +struct ls_pcie_g4 {
3536 + struct mobiveil_pcie *pci;
3537 + struct delayed_work dwork;
3538 + int irq;
3539 +};
3540 +
3541 +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)
3542 +{
3543 + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
3544 +}
3545 +
3546 +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie,
3547 + u32 off, u32 val)
3548 +{
3549 + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
3550 +}
3551 +
3552 +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off)
3553 +{
3554 + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
3555 +}
3556 +
3557 +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie,
3558 + u32 off, u32 val)
3559 +{
3560 + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
3561 +}
3562 +
3563 +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
3564 +{
3565 + struct mobiveil_pcie *mv_pci = pcie->pci;
3566 + u32 header_type;
3567 +
3568 + header_type = csr_readb(mv_pci, PCI_HEADER_TYPE);
3569 + header_type &= 0x7f;
3570 +
3571 + return header_type == PCI_HEADER_TYPE_BRIDGE;
3572 +}
3573 +
3574 +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci)
3575 +{
3576 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
3577 + u32 state;
3578 +
3579 + state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3580 + state = state & PF_DBG_LTSSM_MASK;
3581 +
3582 + if (state == LS_PCIE_G4_LTSSM_L0)
3583 + return 1;
3584 +
3585 + return 0;
3586 +}
3587 +
3588 +static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie)
3589 +{
3590 + struct mobiveil_pcie *mv_pci = pcie->pci;
3591 + u32 val, act_stat;
3592 + int to = 100;
3593 +
3594 + /* Poll for pab_csb_reset to set and PAB activity to clear */
3595 + do {
3596 + usleep_range(10, 15);
3597 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT);
3598 + act_stat = csr_readl(mv_pci, PAB_ACTIVITY_STAT);
3599 + } while (((val & 1 << PF_INT_STAT_PABRST) == 0 || act_stat) && to--);
3600 + if (to < 0) {
3601 + dev_err(&mv_pci->pdev->dev, "poll PABRST&PABACT timeout\n");
3602 + return;
3603 + }
3604 +
3605 + /* clear PEX_RESET bit in PEX_PF0_DBG register */
3606 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3607 + val |= 1 << PF_DBG_WE;
3608 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
3609 +
3610 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3611 + val |= 1 << PF_DBG_PABR;
3612 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
3613 +
3614 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3615 + val &= ~(1 << PF_DBG_WE);
3616 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
3617 +
3618 + mobiveil_host_init(mv_pci, true);
3619 +
3620 + to = 100;
3621 + while (!ls_pcie_g4_link_up(mv_pci) && to--)
3622 + usleep_range(200, 250);
3623 + if (to < 0)
3624 + dev_err(&mv_pci->pdev->dev, "PCIe link trainning timeout\n");
3625 +}
3626 +
3627 +static irqreturn_t ls_pcie_g4_handler(int irq, void *dev_id)
3628 +{
3629 + struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id;
3630 + struct mobiveil_pcie *mv_pci = pcie->pci;
3631 + u32 val;
3632 +
3633 + val = csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT);
3634 + if (!val)
3635 + return IRQ_NONE;
3636 +
3637 + if (val & PAB_INTP_RESET)
3638 + schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1));
3639 +
3640 + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT);
3641 +
3642 + return IRQ_HANDLED;
3643 +}
3644 +
3645 +static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci)
3646 +{
3647 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci);
3648 + u32 val;
3649 + int ret;
3650 +
3651 + pcie->irq = platform_get_irq_byname(mv_pci->pdev, "intr");
3652 + if (pcie->irq < 0) {
3653 + dev_err(&mv_pci->pdev->dev, "Can't get 'intr' irq.\n");
3654 + return pcie->irq;
3655 + }
3656 + ret = devm_request_irq(&mv_pci->pdev->dev, pcie->irq,
3657 + ls_pcie_g4_handler, IRQF_SHARED,
3658 + mv_pci->pdev->name, pcie);
3659 + if (ret) {
3660 + dev_err(&mv_pci->pdev->dev, "Can't register PCIe IRQ.\n");
3661 + return ret;
3662 + }
3663 +
3664 + /* Enable interrupts */
3665 + val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET |
3666 + PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC;
3667 + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB);
3668 +
3669 + return 0;
3670 +}
3671 +
3672 +static void ls_pcie_g4_reset(struct work_struct *work)
3673 +{
3674 + struct delayed_work *dwork = container_of(work, struct delayed_work,
3675 + work);
3676 + struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork);
3677 + struct mobiveil_pcie *mv_pci = pcie->pci;
3678 + u16 ctrl;
3679 +
3680 + ctrl = csr_readw(mv_pci, PCI_BRIDGE_CONTROL);
3681 + ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3682 + csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL);
3683 + ls_pcie_g4_reinit_hw(pcie);
3684 +}
3685 +
3686 +static int ls_pcie_g4_read_other_conf(struct pci_bus *bus, unsigned int devfn,
3687 + int where, int size, u32 *val)
3688 +{
3689 + struct mobiveil_pcie *pci = bus->sysdata;
3690 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
3691 + int ret;
3692 +
3693 + if (where == PCI_VENDOR_ID)
3694 + ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR,
3695 + 0 << PCIE_LUT_GCR_RRE);
3696 +
3697 + ret = pci_generic_config_read(bus, devfn, where, size, val);
3698 +
3699 + if (where == PCI_VENDOR_ID)
3700 + ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR,
3701 + 1 << PCIE_LUT_GCR_RRE);
3702 +
3703 + return ret;
3704 +}
3705 +
3706 +static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = {
3707 + .interrupt_init = ls_pcie_g4_interrupt_init,
3708 + .read_other_conf = ls_pcie_g4_read_other_conf,
3709 +};
3710 +
3711 +static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = {
3712 + .link_up = ls_pcie_g4_link_up,
3713 +};
3714 +
3715 +static void workaround_tkt381274(struct ls_pcie_g4 *pcie)
3716 +{
3717 + struct mobiveil_pcie *mv_pci = pcie->pci;
3718 + u32 val;
3719 +
3720 + /* Set ACK latency timeout */
3721 + val = csr_readl(mv_pci, GPEX_ACK_REPLAY_TO);
3722 + val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
3723 + val |= (4 << ACK_LAT_TO_VAL_SHIFT);
3724 + csr_writel(mv_pci, val, GPEX_ACK_REPLAY_TO);
3725 +}
3726 +
3727 +static int __init ls_pcie_g4_probe(struct platform_device *pdev)
3728 +{
3729 + struct device *dev = &pdev->dev;
3730 + struct mobiveil_pcie *mv_pci;
3731 + struct ls_pcie_g4 *pcie;
3732 + struct device_node *np = dev->of_node;
3733 + int ret;
3734 +
3735 + if (!of_parse_phandle(np, "msi-parent", 0)) {
3736 + dev_err(dev, "failed to find msi-parent\n");
3737 + return -EINVAL;
3738 + }
3739 +
3740 + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
3741 + if (!pcie)
3742 + return -ENOMEM;
3743 +
3744 + mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
3745 + if (!mv_pci)
3746 + return -ENOMEM;
3747 +
3748 + mv_pci->pdev = pdev;
3749 + mv_pci->ops = &ls_pcie_g4_pab_ops;
3750 + mv_pci->rp.ops = &ls_pcie_g4_rp_ops;
3751 + pcie->pci = mv_pci;
3752 +
3753 + platform_set_drvdata(pdev, pcie);
3754 +
3755 + INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset);
3756 +
3757 + ret = mobiveil_pcie_host_probe(mv_pci);
3758 + if (ret) {
3759 + dev_err(dev, "fail to probe!\n");
3760 + return ret;
3761 + }
3762 +
3763 + if (!ls_pcie_g4_is_bridge(pcie))
3764 + return -ENODEV;
3765 +
3766 + workaround_tkt381274(pcie);
3767 +
3768 + return 0;
3769 +}
3770 +
3771 +static const struct of_device_id ls_pcie_g4_of_match[] = {
3772 + { .compatible = "fsl,lx2160a-pcie", },
3773 + { },
3774 +};
3775 +
3776 +static struct platform_driver ls_pcie_g4_driver = {
3777 + .driver = {
3778 + .name = "layerscape-pcie-gen4",
3779 + .of_match_table = ls_pcie_g4_of_match,
3780 + .suppress_bind_attrs = true,
3781 + },
3782 +};
3783 +
3784 +builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe);
3785 --- /dev/null
3786 +++ b/drivers/pci/mobiveil/pcie-mobiveil-ep.c
3787 @@ -0,0 +1,512 @@
3788 +// SPDX-License-Identifier: GPL-2.0
3789 +/**
3790 + * Mobiveil PCIe Endpoint controller driver
3791 + *
3792 + * Copyright (C) 2018 NXP Semiconductor.
3793 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
3794 + */
3795 +
3796 +#include <linux/of.h>
3797 +#include <linux/pci-epc.h>
3798 +#include <linux/pci-epf.h>
3799 +#include <linux/platform_device.h>
3800 +#include "pcie-mobiveil.h"
3801 +
3802 +void mobiveil_pcie_ep_linkup(struct mobiveil_pcie_ep *ep)
3803 +{
3804 + struct pci_epc *epc = ep->epc;
3805 +
3806 + pci_epc_linkup(epc);
3807 +}
3808 +
3809 +static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
3810 + enum pci_barno bar)
3811 +{
3812 + csr_writel(pcie, bar, GPEX_BAR_SELECT);
3813 + csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
3814 + csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW);
3815 +}
3816 +
3817 +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
3818 + enum pci_barno bar)
3819 +{
3820 + __mobiveil_pcie_ep_reset_bar(pcie, bar);
3821 +}
3822 +
3823 +static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
3824 + u8 cap_ptr, u8 cap)
3825 +{
3826 + u8 cap_id, next_cap_ptr;
3827 + u16 reg;
3828 +
3829 + reg = csr_readw(pcie, cap_ptr);
3830 + next_cap_ptr = (reg & 0xff00) >> 8;
3831 + cap_id = (reg & 0x00ff);
3832 +
3833 + if (cap_id == cap)
3834 + return cap_ptr;
3835 +
3836 + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
3837 + return 0;
3838 +
3839 + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
3840 +}
3841 +
3842 +static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie *pcie,
3843 + u8 cap)
3844 +{
3845 + u8 next_cap_ptr;
3846 + u16 reg;
3847 +
3848 + reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
3849 + next_cap_ptr = (reg & 0x00ff);
3850 +
3851 + if (!next_cap_ptr)
3852 + return 0;
3853 +
3854 + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
3855 +}
3856 +
3857 +static int mobiveil_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
3858 + struct pci_epf_header *hdr)
3859 +{
3860 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3861 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3862 +
3863 + csr_writew(pcie, hdr->vendorid, PCI_VENDOR_ID);
3864 + csr_writew(pcie, hdr->deviceid, PCI_DEVICE_ID);
3865 + csr_writeb(pcie, hdr->revid, PCI_REVISION_ID);
3866 + csr_writeb(pcie, hdr->progif_code, PCI_CLASS_PROG);
3867 + csr_writew(pcie, hdr->subclass_code | hdr->baseclass_code << 8,
3868 + PCI_CLASS_DEVICE);
3869 + csr_writeb(pcie, hdr->cache_line_size, PCI_CACHE_LINE_SIZE);
3870 + csr_writew(pcie, hdr->subsys_vendor_id, PCI_SUBSYSTEM_VENDOR_ID);
3871 + csr_writew(pcie, hdr->subsys_id, PCI_SUBSYSTEM_ID);
3872 + csr_writeb(pcie, hdr->interrupt_pin, PCI_INTERRUPT_PIN);
3873 +
3874 + return 0;
3875 +}
3876 +
3877 +static int mobiveil_pcie_ep_inbound_atu(struct mobiveil_pcie_ep *ep,
3878 + u8 func_no, enum pci_barno bar,
3879 + dma_addr_t cpu_addr)
3880 +{
3881 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3882 +
3883 + program_ib_windows_ep(pcie, func_no, bar, cpu_addr);
3884 +
3885 + return 0;
3886 +}
3887 +
3888 +static int mobiveil_pcie_ep_outbound_atu(struct mobiveil_pcie_ep *ep,
3889 + phys_addr_t phys_addr,
3890 + u64 pci_addr, u8 func_no,
3891 + size_t size)
3892 +{
3893 + int ret;
3894 + u32 free_win;
3895 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3896 +
3897 + free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
3898 + if (free_win >= ep->num_ob_windows) {
3899 + dev_err(&pcie->pdev->dev, "No free outbound window\n");
3900 + return -EINVAL;
3901 + }
3902 +
3903 + ret = program_ob_windows_ep(pcie, free_win, MEM_WINDOW_TYPE,
3904 + phys_addr, pci_addr, func_no, size);
3905 + if (ret < 0) {
3906 + dev_err(&pcie->pdev->dev, "Failed to program IB window\n");
3907 + return ret;
3908 + }
3909 +
3910 + set_bit(free_win, ep->ob_window_map);
3911 + ep->outbound_addr[free_win] = phys_addr;
3912 +
3913 + return 0;
3914 +}
3915 +
3916 +static void mobiveil_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
3917 + struct pci_epf_bar *epf_bar)
3918 +{
3919 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3920 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3921 + enum pci_barno bar = epf_bar->barno;
3922 +
3923 + if (bar < ep->bar_num) {
3924 + __mobiveil_pcie_ep_reset_bar(pcie,
3925 + func_no * ep->bar_num + bar);
3926 +
3927 + mobiveil_pcie_disable_ib_win_ep(pcie, func_no, bar);
3928 + }
3929 +}
3930 +
3931 +static int mobiveil_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
3932 + struct pci_epf_bar *epf_bar)
3933 +{
3934 + int ret;
3935 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3936 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3937 + enum pci_barno bar = epf_bar->barno;
3938 + size_t size = epf_bar->size;
3939 +
3940 + if (bar < ep->bar_num) {
3941 + ret = mobiveil_pcie_ep_inbound_atu(ep, func_no, bar,
3942 + epf_bar->phys_addr);
3943 + if (ret)
3944 + return ret;
3945 +
3946 + csr_writel(pcie, func_no * ep->bar_num + bar,
3947 + GPEX_BAR_SELECT);
3948 + csr_writel(pcie, lower_32_bits(~(size - 1)),
3949 + GPEX_BAR_SIZE_LDW);
3950 + csr_writel(pcie, upper_32_bits(~(size - 1)),
3951 + GPEX_BAR_SIZE_UDW);
3952 + }
3953 +
3954 + return 0;
3955 +}
3956 +
3957 +static int mobiveil_pcie_find_index(struct mobiveil_pcie_ep *ep,
3958 + phys_addr_t addr,
3959 + u32 *atu_index)
3960 +{
3961 + u32 index;
3962 +
3963 + for (index = 0; index < ep->num_ob_windows; index++) {
3964 + if (ep->outbound_addr[index] != addr)
3965 + continue;
3966 + *atu_index = index;
3967 + return 0;
3968 + }
3969 +
3970 + return -EINVAL;
3971 +}
3972 +
3973 +static void mobiveil_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
3974 + phys_addr_t addr)
3975 +{
3976 + int ret;
3977 + u32 atu_index;
3978 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3979 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3980 +
3981 + ret = mobiveil_pcie_find_index(ep, addr, &atu_index);
3982 + if (ret < 0)
3983 + return;
3984 +
3985 + mobiveil_pcie_disable_ob_win(pcie, atu_index);
3986 + clear_bit(atu_index, ep->ob_window_map);
3987 +}
3988 +
3989 +static int mobiveil_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
3990 + phys_addr_t addr,
3991 + u64 pci_addr, size_t size)
3992 +{
3993 + int ret;
3994 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3995 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3996 +
3997 + ret = mobiveil_pcie_ep_outbound_atu(ep, addr, pci_addr, func_no, size);
3998 + if (ret) {
3999 + dev_err(&pcie->pdev->dev, "Failed to enable address\n");
4000 + return ret;
4001 + }
4002 +
4003 + return 0;
4004 +}
4005 +
4006 +static int mobiveil_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
4007 +{
4008 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
4009 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4010 + u32 val, reg;
4011 +
4012 + if (!ep->msi_cap)
4013 + return -EINVAL;
4014 +
4015 + reg = ep->msi_cap + PCI_MSI_FLAGS;
4016 + val = csr_readw(pcie, reg);
4017 + if (!(val & PCI_MSI_FLAGS_ENABLE))
4018 + return -EINVAL;
4019 +
4020 + val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
4021 +
4022 + return val;
4023 +}
4024 +
4025 +static int mobiveil_pcie_ep_set_msi(struct pci_epc *epc,
4026 + u8 func_no, u8 interrupts)
4027 +{
4028 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
4029 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4030 + u32 val, reg;
4031 +
4032 + if (!ep->msi_cap)
4033 + return -EINVAL;
4034 +
4035 + reg = ep->msi_cap + PCI_MSI_FLAGS;
4036 + val = csr_readw(pcie, reg);
4037 + val &= ~PCI_MSI_FLAGS_QMASK;
4038 + val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
4039 + csr_writew(pcie, val, reg);
4040 +
4041 + return 0;
4042 +}
4043 +
4044 +static int mobiveil_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
4045 +{
4046 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
4047 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4048 + u32 val, reg;
4049 +
4050 + if (!ep->msix_cap)
4051 + return -EINVAL;
4052 +
4053 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
4054 + val = csr_readw(pcie, reg);
4055 + if (!(val & PCI_MSIX_FLAGS_ENABLE))
4056 + return -EINVAL;
4057 +
4058 + val &= PCI_MSIX_FLAGS_QSIZE;
4059 +
4060 + return val;
4061 +}
4062 +
4063 +static int mobiveil_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no,
4064 + u16 interrupts)
4065 +{
4066 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
4067 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4068 + u32 val, reg;
4069 +
4070 + if (!ep->msix_cap)
4071 + return -EINVAL;
4072 +
4073 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
4074 + val = csr_readw(pcie, reg);
4075 + val &= ~PCI_MSIX_FLAGS_QSIZE;
4076 + val |= interrupts;
4077 + csr_writew(pcie, val, reg);
4078 +
4079 + return 0;
4080 +}
4081 +
4082 +static int mobiveil_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
4083 + enum pci_epc_irq_type type,
4084 + u16 interrupt_num)
4085 +{
4086 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
4087 +
4088 + if (!ep->ops->raise_irq)
4089 + return -EINVAL;
4090 +
4091 + return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
4092 +}
4093 +
4094 +static const struct pci_epc_ops epc_ops = {
4095 + .write_header = mobiveil_pcie_ep_write_header,
4096 + .set_bar = mobiveil_pcie_ep_set_bar,
4097 + .clear_bar = mobiveil_pcie_ep_clear_bar,
4098 + .map_addr = mobiveil_pcie_ep_map_addr,
4099 + .unmap_addr = mobiveil_pcie_ep_unmap_addr,
4100 + .set_msi = mobiveil_pcie_ep_set_msi,
4101 + .get_msi = mobiveil_pcie_ep_get_msi,
4102 + .set_msix = mobiveil_pcie_ep_set_msix,
4103 + .get_msix = mobiveil_pcie_ep_get_msix,
4104 + .raise_irq = mobiveil_pcie_ep_raise_irq,
4105 +};
4106 +
4107 +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no)
4108 +{
4109 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4110 +
4111 + dev_err(&pcie->pdev->dev, "EP cannot trigger legacy IRQs\n");
4112 +
4113 + return -EINVAL;
4114 +}
4115 +
4116 +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
4117 + u8 interrupt_num)
4118 +{
4119 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4120 + struct pci_epc *epc = ep->epc;
4121 + u16 msg_ctrl, msg_data;
4122 + u32 msg_addr_lower, msg_addr_upper, reg;
4123 + u64 msg_addr;
4124 + u32 func_num;
4125 + bool has_upper;
4126 + int ret;
4127 +
4128 + if (!ep->msi_cap)
4129 + return -EINVAL;
4130 +
4131 + func_num = csr_readl(pcie, PAB_CTRL);
4132 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4133 + func_num |= (func_no & FUNC_SEL_MASK) << FUNC_SEL_SHIFT;
4134 + csr_writel(pcie, func_num, PAB_CTRL);
4135 +
4136 + /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
4137 + reg = ep->msi_cap + PCI_MSI_FLAGS;
4138 + msg_ctrl = csr_readw(pcie, reg);
4139 + has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
4140 + reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
4141 + msg_addr_lower = csr_readl(pcie, reg);
4142 + if (has_upper) {
4143 + reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
4144 + msg_addr_upper = csr_readl(pcie, reg);
4145 + reg = ep->msi_cap + PCI_MSI_DATA_64;
4146 + msg_data = csr_readw(pcie, reg);
4147 + } else {
4148 + msg_addr_upper = 0;
4149 + reg = ep->msi_cap + PCI_MSI_DATA_32;
4150 + msg_data = csr_readw(pcie, reg);
4151 + }
4152 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
4153 +
4154 + func_num = csr_readl(pcie, PAB_CTRL);
4155 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4156 + csr_writel(pcie, func_num, PAB_CTRL);
4157 +
4158 + ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
4159 + msg_addr, epc->mem->page_size);
4160 + if (ret)
4161 + return ret;
4162 +
4163 + writel(msg_data | (interrupt_num - 1), ep->msi_mem);
4164 +
4165 + mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
4166 +
4167 + return 0;
4168 +}
4169 +
4170 +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
4171 + u16 interrupt_num)
4172 +{
4173 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4174 + struct pci_epc *epc = ep->epc;
4175 + u32 msg_addr_upper, msg_addr_lower;
4176 + u32 msg_data;
4177 + u64 msg_addr;
4178 + u32 func_num;
4179 + int ret;
4180 +
4181 + func_num = csr_readl(pcie, PAB_CTRL);
4182 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4183 + func_num |= (func_no & FUNC_SEL_MASK) << FUNC_SEL_SHIFT;
4184 + csr_writel(pcie, func_num, PAB_CTRL);
4185 +
4186 + msg_addr_lower = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
4187 + PCI_MSIX_ENTRY_LOWER_ADDR +
4188 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
4189 + msg_addr_upper = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
4190 + PCI_MSIX_ENTRY_UPPER_ADDR +
4191 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
4192 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
4193 + msg_data = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
4194 + PCI_MSIX_ENTRY_DATA +
4195 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
4196 +
4197 + func_num = csr_readl(pcie, PAB_CTRL);
4198 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4199 + csr_writel(pcie, func_num, PAB_CTRL);
4200 +
4201 + ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
4202 + msg_addr, epc->mem->page_size);
4203 + if (ret)
4204 + return ret;
4205 +
4206 + writel(msg_data, ep->msi_mem);
4207 +
4208 + mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
4209 +
4210 + return 0;
4211 +}
4212 +
4213 +void mobiveil_pcie_ep_exit(struct mobiveil_pcie_ep *ep)
4214 +{
4215 + struct pci_epc *epc = ep->epc;
4216 +
4217 + pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
4218 + epc->mem->page_size);
4219 +
4220 + pci_epc_mem_exit(epc);
4221 +}
4222 +
4223 +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep)
4224 +{
4225 + int ret;
4226 + void *addr;
4227 + struct pci_epc *epc;
4228 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4229 + struct device *dev = &pcie->pdev->dev;
4230 + struct device_node *np = dev->of_node;
4231 +
4232 + if (!pcie->csr_axi_slave_base) {
4233 + dev_err(dev, "csr_base is not populated\n");
4234 + return -EINVAL;
4235 + }
4236 +
4237 + ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
4238 + if (ret < 0) {
4239 + dev_err(dev, "Unable to read *num-ob-windows* property\n");
4240 + return ret;
4241 + }
4242 +
4243 + if (ep->num_ob_windows > MAX_IATU_OUT) {
4244 + dev_err(dev, "Invalid *num-ob-windows*\n");
4245 + return -EINVAL;
4246 + }
4247 + ep->ob_window_map = devm_kcalloc(dev,
4248 + BITS_TO_LONGS(ep->num_ob_windows),
4249 + sizeof(long),
4250 + GFP_KERNEL);
4251 + if (!ep->ob_window_map)
4252 + return -ENOMEM;
4253 +
4254 + addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t),
4255 + GFP_KERNEL);
4256 + if (!addr)
4257 + return -ENOMEM;
4258 + ep->outbound_addr = addr;
4259 +
4260 + mobiveil_pcie_enable_bridge_pio(pcie);
4261 + mobiveil_pcie_enable_engine_apio(pcie);
4262 + mobiveil_pcie_enable_engine_ppio(pcie);
4263 + mobiveil_pcie_enable_msi_ep(pcie);
4264 +
4265 + epc = devm_pci_epc_create(dev, &epc_ops);
4266 + if (IS_ERR(epc)) {
4267 + dev_err(dev, "Failed to create epc device\n");
4268 + return PTR_ERR(epc);
4269 + }
4270 +
4271 + ep->epc = epc;
4272 + epc_set_drvdata(epc, ep);
4273 +
4274 + ep->msi_cap = mobiveil_pcie_ep_find_capability(pcie, PCI_CAP_ID_MSI);
4275 +
4276 + ep->msix_cap = mobiveil_pcie_ep_find_capability(pcie,
4277 + PCI_CAP_ID_MSIX);
4278 +
4279 + if (ep->ops->ep_init)
4280 + ep->ops->ep_init(ep);
4281 +
4282 + epc->max_functions = ep->pf_num;
4283 +
4284 + ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
4285 + ep->page_size);
4286 + if (ret < 0) {
4287 + dev_err(dev, "Failed to initialize address space\n");
4288 + return ret;
4289 + }
4290 +
4291 + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
4292 + epc->mem->page_size);
4293 + if (!ep->msi_mem) {
4294 + dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
4295 + return -ENOMEM;
4296 + }
4297 +
4298 + return 0;
4299 +}
4300 --- /dev/null
4301 +++ b/drivers/pci/mobiveil/pcie-mobiveil-host.c
4302 @@ -0,0 +1,640 @@
4303 +// SPDX-License-Identifier: GPL-2.0
4304 +/*
4305 + * PCIe host controller driver for Mobiveil PCIe Host controller
4306 + *
4307 + * Copyright (c) 2018 Mobiveil Inc.
4308 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
4309 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
4310 + */
4311 +
4312 +#include <linux/init.h>
4313 +#include <linux/interrupt.h>
4314 +#include <linux/irq.h>
4315 +#include <linux/irqchip/chained_irq.h>
4316 +#include <linux/irqdomain.h>
4317 +#include <linux/kernel.h>
4318 +#include <linux/module.h>
4319 +#include <linux/msi.h>
4320 +#include <linux/of_address.h>
4321 +#include <linux/of_irq.h>
4322 +#include <linux/of_platform.h>
4323 +#include <linux/of_pci.h>
4324 +#include <linux/pci.h>
4325 +#include <linux/platform_device.h>
4326 +#include <linux/slab.h>
4327 +
4328 +#include "pcie-mobiveil.h"
4329 +
4330 +static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
4331 +{
4332 + struct mobiveil_pcie *pcie = bus->sysdata;
4333 +
4334 + /* If there is no link, then there is no device */
4335 + if (bus->number > pcie->rp.root_bus_nr && !mobiveil_pcie_link_up(pcie))
4336 + return false;
4337 +
4338 + /* Only one device down on each root port */
4339 + if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
4340 + return false;
4341 +
4342 + /*
4343 + * Do not read more than one device on the bus directly
4344 + * attached to RC
4345 + */
4346 + if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0))
4347 + return false;
4348 +
4349 + return true;
4350 +}
4351 +
4352 +/*
4353 + * mobiveil_pcie_map_bus - routine to get the configuration base of either
4354 + * root port or endpoint
4355 + */
4356 +static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
4357 + unsigned int devfn, int where)
4358 +{
4359 + struct mobiveil_pcie *pcie = bus->sysdata;
4360 + u32 value;
4361 +
4362 + if (!mobiveil_pcie_valid_device(bus, devfn))
4363 + return NULL;
4364 +
4365 + /* RC config access */
4366 + if (bus->number == pcie->rp.root_bus_nr)
4367 + return pcie->csr_axi_slave_base + where;
4368 +
4369 + /*
4370 + * EP config access (in Config/APIO space)
4371 + * Program PEX Address base (31..16 bits) with appropriate value
4372 + * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
4373 + * Relies on pci_lock serialization
4374 + */
4375 + value = bus->number << PAB_BUS_SHIFT |
4376 + PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
4377 + PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
4378 +
4379 + csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
4380 +
4381 + return pcie->rp.config_axi_slave_base + where;
4382 +}
4383 +
4384 +static int mobiveil_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
4385 + int where, int size, u32 *val)
4386 +{
4387 + struct mobiveil_pcie *pcie = bus->sysdata;
4388 + struct root_port *rp = &pcie->rp;
4389 +
4390 + if (bus->number > rp->root_bus_nr && rp->ops->read_other_conf)
4391 + return rp->ops->read_other_conf(bus, devfn, where, size, val);
4392 +
4393 + return pci_generic_config_read(bus, devfn, where, size, val);
4394 +}
4395 +static struct pci_ops mobiveil_pcie_ops = {
4396 + .map_bus = mobiveil_pcie_map_bus,
4397 + .read = mobiveil_pcie_config_read,
4398 + .write = pci_generic_config_write,
4399 +};
4400 +
4401 +static void mobiveil_pcie_isr(struct irq_desc *desc)
4402 +{
4403 + struct irq_chip *chip = irq_desc_get_chip(desc);
4404 + struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
4405 + struct device *dev = &pcie->pdev->dev;
4406 + struct mobiveil_msi *msi = &pcie->rp.msi;
4407 + u32 msi_data, msi_addr_lo, msi_addr_hi;
4408 + u32 intr_status, msi_status;
4409 + unsigned long shifted_status;
4410 + u32 bit, virq, val, mask;
4411 +
4412 + /*
4413 + * The core provides a single interrupt for both INTx/MSI messages.
4414 + * So we'll read both INTx and MSI status
4415 + */
4416 +
4417 + chained_irq_enter(chip, desc);
4418 +
4419 + /* read INTx status */
4420 + val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
4421 + mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
4422 + intr_status = val & mask;
4423 +
4424 + /* Handle INTx */
4425 + if (intr_status & PAB_INTP_INTX_MASK) {
4426 + shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
4427 + shifted_status &= PAB_INTP_INTX_MASK;
4428 + shifted_status >>= PAB_INTX_START;
4429 + do {
4430 + for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
4431 + virq = irq_find_mapping(pcie->rp.intx_domain,
4432 + bit + 1);
4433 + if (virq)
4434 + generic_handle_irq(virq);
4435 + else
4436 + dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
4437 + bit);
4438 +
4439 + /* clear interrupt handled */
4440 + csr_writel(pcie, 1 << (PAB_INTX_START + bit),
4441 + PAB_INTP_AMBA_MISC_STAT);
4442 + }
4443 +
4444 + shifted_status = csr_readl(pcie,
4445 + PAB_INTP_AMBA_MISC_STAT);
4446 + shifted_status &= PAB_INTP_INTX_MASK;
4447 + shifted_status >>= PAB_INTX_START;
4448 + } while (shifted_status != 0);
4449 + }
4450 +
4451 + /* read extra MSI status register */
4452 + msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
4453 +
4454 + /* handle MSI interrupts */
4455 + while (msi_status & 1) {
4456 + msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
4457 +
4458 + /*
4459 + * MSI_STATUS_OFFSET register gets updated to zero
4460 + * once we pop not only the MSI data but also address
4461 + * from MSI hardware FIFO. So keeping these following
4462 + * two dummy reads.
4463 + */
4464 + msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
4465 + MSI_ADDR_L_OFFSET);
4466 + msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
4467 + MSI_ADDR_H_OFFSET);
4468 + dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
4469 + msi_data, msi_addr_hi, msi_addr_lo);
4470 +
4471 + virq = irq_find_mapping(msi->dev_domain, msi_data);
4472 + if (virq)
4473 + generic_handle_irq(virq);
4474 +
4475 + msi_status = readl_relaxed(pcie->apb_csr_base +
4476 + MSI_STATUS_OFFSET);
4477 + }
4478 +
4479 + /* Clear the interrupt status */
4480 + csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
4481 + chained_irq_exit(chip, desc);
4482 +}
4483 +
4484 +static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
4485 +{
4486 + struct device *dev = &pcie->pdev->dev;
4487 + struct platform_device *pdev = pcie->pdev;
4488 + struct device_node *node = dev->of_node;
4489 + struct resource *res;
4490 +
4491 + /* map config resource */
4492 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4493 + "config_axi_slave");
4494 + pcie->rp.config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
4495 + if (IS_ERR(pcie->rp.config_axi_slave_base))
4496 + return PTR_ERR(pcie->rp.config_axi_slave_base);
4497 + pcie->rp.ob_io_res = res;
4498 +
4499 + /* map csr resource */
4500 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4501 + "csr_axi_slave");
4502 + pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
4503 + if (IS_ERR(pcie->csr_axi_slave_base))
4504 + return PTR_ERR(pcie->csr_axi_slave_base);
4505 + pcie->pcie_reg_base = res->start;
4506 +
4507 + /* read the number of windows requested */
4508 + if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
4509 + pcie->apio_wins = MAX_PIO_WINDOWS;
4510 +
4511 + if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
4512 + pcie->ppio_wins = MAX_PIO_WINDOWS;
4513 +
4514 + return 0;
4515 +}
4516 +
4517 +static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
4518 +{
4519 + phys_addr_t msg_addr = pcie->pcie_reg_base;
4520 + struct mobiveil_msi *msi = &pcie->rp.msi;
4521 +
4522 + msi->num_of_vectors = PCI_NUM_MSI;
4523 + msi->msi_pages_phys = (phys_addr_t)msg_addr;
4524 +
4525 + writel_relaxed(lower_32_bits(msg_addr),
4526 + pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
4527 + writel_relaxed(upper_32_bits(msg_addr),
4528 + pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
4529 + writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
4530 + writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
4531 +}
4532 +
4533 +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
4534 +{
4535 + u32 value, pab_ctrl, type;
4536 + struct resource_entry *win;
4537 + int i;
4538 +
4539 + /* Disable all inbound/outbound windows */
4540 + for (i = 0; i < pcie->apio_wins; i++)
4541 + mobiveil_pcie_disable_ob_win(pcie, i);
4542 + for (i = 0; i < pcie->ppio_wins; i++)
4543 + mobiveil_pcie_disable_ib_win(pcie, i);
4544 +
4545 + pcie->ib_wins_configured = 0;
4546 + pcie->ob_wins_configured = 0;
4547 +
4548 + if (!reinit) {
4549 + /* setup bus numbers */
4550 + value = csr_readl(pcie, PCI_PRIMARY_BUS);
4551 + value &= 0xff000000;
4552 + value |= 0x00ff0100;
4553 + csr_writel(pcie, value, PCI_PRIMARY_BUS);
4554 + }
4555 +
4556 + /*
4557 + * program Bus Master Enable Bit in Command Register in PAB Config
4558 + * Space
4559 + */
4560 + value = csr_readl(pcie, PCI_COMMAND);
4561 + value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
4562 + csr_writel(pcie, value, PCI_COMMAND);
4563 +
4564 + /*
4565 + * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
4566 + * register
4567 + */
4568 + pab_ctrl = csr_readl(pcie, PAB_CTRL);
4569 + pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
4570 + csr_writel(pcie, pab_ctrl, PAB_CTRL);
4571 +
4572 + /*
4573 + * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
4574 + * PAB_AXI_PIO_CTRL Register
4575 + */
4576 + value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
4577 + value |= APIO_EN_MASK;
4578 + csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
4579 +
4580 + /* Enable PCIe PIO master */
4581 + value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
4582 + value |= 1 << PIO_ENABLE_SHIFT;
4583 + csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
4584 +
4585 + /*
4586 + * we'll program one outbound window for config reads and
4587 + * another default inbound window for all the upstream traffic
4588 + * rest of the outbound windows will be configured according to
4589 + * the "ranges" field defined in device tree
4590 + */
4591 +
4592 + /* config outbound translation window */
4593 + program_ob_windows(pcie, WIN_NUM_0, pcie->rp.ob_io_res->start, 0,
4594 + CFG_WINDOW_TYPE, resource_size(pcie->rp.ob_io_res));
4595 +
4596 + /* memory inbound translation window */
4597 + program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
4598 +
4599 + /* Get the I/O and memory ranges from DT */
4600 + resource_list_for_each_entry(win, pcie->resources) {
4601 + if (resource_type(win->res) == IORESOURCE_MEM) {
4602 + type = MEM_WINDOW_TYPE;
4603 + } else if (resource_type(win->res) == IORESOURCE_IO) {
4604 + type = IO_WINDOW_TYPE;
4605 + } else if (resource_type(win->res) == IORESOURCE_BUS) {
4606 + pcie->rp.root_bus_nr = win->res->start;
4607 + continue;
4608 + } else {
4609 + continue;
4610 + }
4611 +
4612 + /* configure outbound translation window */
4613 + program_ob_windows(pcie, pcie->ob_wins_configured,
4614 + win->res->start,
4615 + win->res->start - win->offset,
4616 + type, resource_size(win->res));
4617 + }
4618 +
4619 + /* fixup for PCIe class register */
4620 + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
4621 + value &= 0xff;
4622 + value |= (PCI_CLASS_BRIDGE_PCI << 16);
4623 + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
4624 +
4625 + return 0;
4626 +}
4627 +
4628 +static void mobiveil_mask_intx_irq(struct irq_data *data)
4629 +{
4630 + struct irq_desc *desc = irq_to_desc(data->irq);
4631 + struct mobiveil_pcie *pcie;
4632 + unsigned long flags;
4633 + u32 mask, shifted_val;
4634 +
4635 + pcie = irq_desc_get_chip_data(desc);
4636 + mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
4637 + raw_spin_lock_irqsave(&pcie->rp.intx_mask_lock, flags);
4638 + shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
4639 + shifted_val &= ~mask;
4640 + csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
4641 + raw_spin_unlock_irqrestore(&pcie->rp.intx_mask_lock, flags);
4642 +}
4643 +
4644 +static void mobiveil_unmask_intx_irq(struct irq_data *data)
4645 +{
4646 + struct irq_desc *desc = irq_to_desc(data->irq);
4647 + struct mobiveil_pcie *pcie;
4648 + unsigned long flags;
4649 + u32 shifted_val, mask;
4650 +
4651 + pcie = irq_desc_get_chip_data(desc);
4652 + mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
4653 + raw_spin_lock_irqsave(&pcie->rp.intx_mask_lock, flags);
4654 + shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
4655 + shifted_val |= mask;
4656 + csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
4657 + raw_spin_unlock_irqrestore(&pcie->rp.intx_mask_lock, flags);
4658 +}
4659 +
4660 +static struct irq_chip intx_irq_chip = {
4661 + .name = "mobiveil_pcie:intx",
4662 + .irq_enable = mobiveil_unmask_intx_irq,
4663 + .irq_disable = mobiveil_mask_intx_irq,
4664 + .irq_mask = mobiveil_mask_intx_irq,
4665 + .irq_unmask = mobiveil_unmask_intx_irq,
4666 +};
4667 +
4668 +/* routine to setup the INTx related data */
4669 +static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
4670 + irq_hw_number_t hwirq)
4671 +{
4672 + irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
4673 + irq_set_chip_data(irq, domain->host_data);
4674 +
4675 + return 0;
4676 +}
4677 +
4678 +/* INTx domain operations structure */
4679 +static const struct irq_domain_ops intx_domain_ops = {
4680 + .map = mobiveil_pcie_intx_map,
4681 +};
4682 +
4683 +static struct irq_chip mobiveil_msi_irq_chip = {
4684 + .name = "Mobiveil PCIe MSI",
4685 + .irq_mask = pci_msi_mask_irq,
4686 + .irq_unmask = pci_msi_unmask_irq,
4687 +};
4688 +
4689 +static struct msi_domain_info mobiveil_msi_domain_info = {
4690 + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
4691 + MSI_FLAG_PCI_MSIX),
4692 + .chip = &mobiveil_msi_irq_chip,
4693 +};
4694 +
4695 +static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
4696 +{
4697 + struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
4698 + phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
4699 +
4700 + msg->address_lo = lower_32_bits(addr);
4701 + msg->address_hi = upper_32_bits(addr);
4702 + msg->data = data->hwirq;
4703 +
4704 + dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
4705 + (int)data->hwirq, msg->address_hi, msg->address_lo);
4706 +}
4707 +
4708 +static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
4709 + const struct cpumask *mask, bool force)
4710 +{
4711 + return -EINVAL;
4712 +}
4713 +
4714 +static struct irq_chip mobiveil_msi_bottom_irq_chip = {
4715 + .name = "Mobiveil MSI",
4716 + .irq_compose_msi_msg = mobiveil_compose_msi_msg,
4717 + .irq_set_affinity = mobiveil_msi_set_affinity,
4718 +};
4719 +
4720 +static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
4721 + unsigned int virq,
4722 + unsigned int nr_irqs, void *args)
4723 +{
4724 + struct mobiveil_pcie *pcie = domain->host_data;
4725 + struct mobiveil_msi *msi = &pcie->rp.msi;
4726 + unsigned long bit;
4727 +
4728 + WARN_ON(nr_irqs != 1);
4729 + mutex_lock(&msi->lock);
4730 +
4731 + bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
4732 + if (bit >= msi->num_of_vectors) {
4733 + mutex_unlock(&msi->lock);
4734 + return -ENOSPC;
4735 + }
4736 +
4737 + set_bit(bit, msi->msi_irq_in_use);
4738 +
4739 + mutex_unlock(&msi->lock);
4740 +
4741 + irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
4742 + domain->host_data, handle_level_irq, NULL, NULL);
4743 + return 0;
4744 +}
4745 +
4746 +static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
4747 + unsigned int virq,
4748 + unsigned int nr_irqs)
4749 +{
4750 + struct irq_data *d = irq_domain_get_irq_data(domain, virq);
4751 + struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
4752 + struct mobiveil_msi *msi = &pcie->rp.msi;
4753 +
4754 + mutex_lock(&msi->lock);
4755 +
4756 + if (!test_bit(d->hwirq, msi->msi_irq_in_use))
4757 + dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
4758 + d->hwirq);
4759 + else
4760 + __clear_bit(d->hwirq, msi->msi_irq_in_use);
4761 +
4762 + mutex_unlock(&msi->lock);
4763 +}
4764 +static const struct irq_domain_ops msi_domain_ops = {
4765 + .alloc = mobiveil_irq_msi_domain_alloc,
4766 + .free = mobiveil_irq_msi_domain_free,
4767 +};
4768 +
4769 +static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
4770 +{
4771 + struct device *dev = &pcie->pdev->dev;
4772 + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
4773 + struct mobiveil_msi *msi = &pcie->rp.msi;
4774 +
4775 + mutex_init(&msi->lock);
4776 + msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
4777 + &msi_domain_ops, pcie);
4778 + if (!msi->dev_domain) {
4779 + dev_err(dev, "failed to create IRQ domain\n");
4780 + return -ENOMEM;
4781 + }
4782 +
4783 + msi->msi_domain = pci_msi_create_irq_domain(fwnode,
4784 + &mobiveil_msi_domain_info,
4785 + msi->dev_domain);
4786 + if (!msi->msi_domain) {
4787 + dev_err(dev, "failed to create MSI domain\n");
4788 + irq_domain_remove(msi->dev_domain);
4789 + return -ENOMEM;
4790 + }
4791 +
4792 + return 0;
4793 +}
4794 +
4795 +static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
4796 +{
4797 + struct device *dev = &pcie->pdev->dev;
4798 + struct device_node *node = dev->of_node;
4799 + int ret;
4800 +
4801 + /* setup INTx */
4802 + pcie->rp.intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
4803 + &intx_domain_ops, pcie);
4804 +
4805 + if (!pcie->rp.intx_domain) {
4806 + dev_err(dev, "Failed to get a INTx IRQ domain\n");
4807 + return -ENOMEM;
4808 + }
4809 +
4810 + raw_spin_lock_init(&pcie->rp.intx_mask_lock);
4811 +
4812 + /* setup MSI */
4813 + ret = mobiveil_allocate_msi_domains(pcie);
4814 + if (ret)
4815 + return ret;
4816 +
4817 + return 0;
4818 +}
4819 +
4820 +static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie)
4821 +{
4822 + struct device *dev = &pcie->pdev->dev;
4823 + struct resource *res;
4824 + int ret;
4825 +
4826 + if (pcie->rp.ops->interrupt_init)
4827 + return pcie->rp.ops->interrupt_init(pcie);
4828 +
4829 + /* map MSI config resource */
4830 + res = platform_get_resource_byname(pcie->pdev, IORESOURCE_MEM,
4831 + "apb_csr");
4832 + pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
4833 + if (IS_ERR(pcie->apb_csr_base))
4834 + return PTR_ERR(pcie->apb_csr_base);
4835 +
4836 + /* setup MSI hardware registers */
4837 + mobiveil_pcie_enable_msi(pcie);
4838 +
4839 + pcie->rp.irq = platform_get_irq(pcie->pdev, 0);
4840 + if (pcie->rp.irq <= 0) {
4841 + dev_err(dev, "failed to map IRQ: %d\n", pcie->rp.irq);
4842 + return -ENODEV;
4843 + }
4844 +
4845 + /* initialize the IRQ domains */
4846 + ret = mobiveil_pcie_init_irq_domain(pcie);
4847 + if (ret) {
4848 + dev_err(dev, "Failed creating IRQ Domain\n");
4849 + return ret;
4850 + }
4851 +
4852 + irq_set_chained_handler_and_data(pcie->rp.irq,
4853 + mobiveil_pcie_isr, pcie);
4854 +
4855 + /* Enable interrupts */
4856 + csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
4857 + PAB_INTP_AMBA_MISC_ENB);
4858 +
4859 + return 0;
4860 +}
4861 +
4862 +int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
4863 +{
4864 + struct pci_bus *bus;
4865 + struct pci_bus *child;
4866 + struct pci_host_bridge *bridge;
4867 + struct device *dev = &pcie->pdev->dev;
4868 + struct device_node *np = dev->of_node;
4869 + resource_size_t iobase;
4870 + int ret;
4871 +
4872 + ret = mobiveil_pcie_parse_dt(pcie);
4873 + if (ret) {
4874 + dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
4875 + return ret;
4876 + }
4877 +
4878 + /* allocate the PCIe port */
4879 + bridge = devm_pci_alloc_host_bridge(dev, 0);
4880 + if (!bridge)
4881 + return -ENOMEM;
4882 +
4883 + /* parse the host bridge base addresses from the device tree file */
4884 + ret = of_pci_get_host_bridge_resources(np, 0, 0xff,
4885 + &bridge->windows, &iobase);
4886 + if (ret) {
4887 + dev_err(dev, "Getting bridge resources failed\n");
4888 + return ret;
4889 + }
4890 +
4891 + pcie->resources = &bridge->windows;
4892 +
4893 + /*
4894 + * configure all inbound and outbound windows and prepare the RC for
4895 + * config access
4896 + */
4897 + ret = mobiveil_host_init(pcie, false);
4898 + if (ret) {
4899 + dev_err(dev, "Failed to initialize host\n");
4900 + goto error;
4901 + }
4902 +
4903 + ret = mobiveil_pcie_interrupt_init(pcie);
4904 + if (ret) {
4905 + dev_err(dev, "Interrupt init failed\n");
4906 + goto error;
4907 + }
4908 +
4909 + ret = devm_request_pci_bus_resources(dev, pcie->resources);
4910 + if (ret)
4911 + goto error;
4912 +
4913 + /* Initialize bridge */
4914 + bridge->dev.parent = dev;
4915 + bridge->sysdata = pcie;
4916 + bridge->busnr = pcie->rp.root_bus_nr;
4917 + bridge->ops = &mobiveil_pcie_ops;
4918 + bridge->map_irq = of_irq_parse_and_map_pci;
4919 + bridge->swizzle_irq = pci_common_swizzle;
4920 +
4921 + ret = mobiveil_bringup_link(pcie);
4922 + if (ret) {
4923 + dev_info(dev, "link bring-up failed\n");
4924 + }
4925 +
4926 + /* setup the kernel resources for the newly added PCIe root bus */
4927 + ret = pci_scan_root_bus_bridge(bridge);
4928 + if (ret)
4929 + goto error;
4930 +
4931 + bus = bridge->bus;
4932 +
4933 + pci_assign_unassigned_bus_resources(bus);
4934 + list_for_each_entry(child, &bus->children, node)
4935 + pcie_bus_configure_settings(child);
4936 + pci_bus_add_devices(bus);
4937 +
4938 + return 0;
4939 +error:
4940 + pci_free_resource_list(pcie->resources);
4941 + return ret;
4942 +}
4943 --- /dev/null
4944 +++ b/drivers/pci/mobiveil/pcie-mobiveil-plat.c
4945 @@ -0,0 +1,54 @@
4946 +// SPDX-License-Identifier: GPL-2.0
4947 +/*
4948 + * PCIe host controller driver for Mobiveil PCIe Host controller
4949 + *
4950 + * Copyright (c) 2018 Mobiveil Inc.
4951 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
4952 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
4953 + */
4954 +
4955 +#include <linux/init.h>
4956 +#include <linux/kernel.h>
4957 +#include <linux/module.h>
4958 +#include <linux/of_pci.h>
4959 +#include <linux/pci.h>
4960 +#include <linux/platform_device.h>
4961 +#include <linux/slab.h>
4962 +
4963 +#include "pcie-mobiveil.h"
4964 +
4965 +static int mobiveil_pcie_probe(struct platform_device *pdev)
4966 +{
4967 + struct mobiveil_pcie *pcie;
4968 + struct device *dev = &pdev->dev;
4969 +
4970 + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
4971 + if (!pcie)
4972 + return -ENOMEM;
4973 +
4974 + pcie->pdev = pdev;
4975 +
4976 + return mobiveil_pcie_host_probe(pcie);
4977 +}
4978 +
4979 +static const struct of_device_id mobiveil_pcie_of_match[] = {
4980 + {.compatible = "mbvl,gpex40-pcie",},
4981 + {},
4982 +};
4983 +
4984 +MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
4985 +
4986 +static struct platform_driver mobiveil_pcie_driver = {
4987 + .probe = mobiveil_pcie_probe,
4988 + .driver = {
4989 + .name = "mobiveil-pcie",
4990 + .of_match_table = mobiveil_pcie_of_match,
4991 + .suppress_bind_attrs = true,
4992 + },
4993 +};
4994 +
4995 +builtin_platform_driver(mobiveil_pcie_driver);
4996 +
4997 +MODULE_LICENSE("GPL v2");
4998 +MODULE_DESCRIPTION("Mobiveil PCIe host controller driver");
4999 +MODULE_AUTHOR("Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>");
5000 --- /dev/null
5001 +++ b/drivers/pci/mobiveil/pcie-mobiveil.c
5002 @@ -0,0 +1,334 @@
5003 +// SPDX-License-Identifier: GPL-2.0
5004 +/*
5005 + * PCIe host controller driver for Mobiveil PCIe Host controller
5006 + *
5007 + * Copyright (c) 2018 Mobiveil Inc.
5008 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
5009 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
5010 + */
5011 +
5012 +#include <linux/delay.h>
5013 +#include <linux/init.h>
5014 +#include <linux/kernel.h>
5015 +#include <linux/pci.h>
5016 +#include <linux/platform_device.h>
5017 +
5018 +#include "pcie-mobiveil.h"
5019 +
5020 +/*
5021 + * mobiveil_pcie_sel_page - routine to access paged register
5022 + *
5023 + * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
5024 + * for this scheme to work extracted higher 6 bits of the offset will be
5025 + * written to pg_sel field of PAB_CTRL register and rest of the lower 10
5026 + * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
5027 + */
5028 +static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
5029 +{
5030 + u32 val;
5031 +
5032 + val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
5033 + val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
5034 + val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
5035 +
5036 + writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
5037 +}
5038 +
5039 +static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
5040 +{
5041 + if (off < PAGED_ADDR_BNDRY) {
5042 + /* For directly accessed registers, clear the pg_sel field */
5043 + mobiveil_pcie_sel_page(pcie, 0);
5044 + return pcie->csr_axi_slave_base + off;
5045 + }
5046 +
5047 + mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
5048 + return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
5049 +}
5050 +
5051 +static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
5052 +{
5053 + if ((uintptr_t)addr & (size - 1)) {
5054 + *val = 0;
5055 + return PCIBIOS_BAD_REGISTER_NUMBER;
5056 + }
5057 +
5058 + switch (size) {
5059 + case 4:
5060 + *val = readl(addr);
5061 + break;
5062 + case 2:
5063 + *val = readw(addr);
5064 + break;
5065 + case 1:
5066 + *val = readb(addr);
5067 + break;
5068 + default:
5069 + *val = 0;
5070 + return PCIBIOS_BAD_REGISTER_NUMBER;
5071 + }
5072 +
5073 + return PCIBIOS_SUCCESSFUL;
5074 +}
5075 +
5076 +static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
5077 +{
5078 + if ((uintptr_t)addr & (size - 1))
5079 + return PCIBIOS_BAD_REGISTER_NUMBER;
5080 +
5081 + switch (size) {
5082 + case 4:
5083 + writel(val, addr);
5084 + break;
5085 + case 2:
5086 + writew(val, addr);
5087 + break;
5088 + case 1:
5089 + writeb(val, addr);
5090 + break;
5091 + default:
5092 + return PCIBIOS_BAD_REGISTER_NUMBER;
5093 + }
5094 +
5095 + return PCIBIOS_SUCCESSFUL;
5096 +}
5097 +
5098 +u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
5099 +{
5100 + void *addr;
5101 + u32 val;
5102 + int ret;
5103 +
5104 + addr = mobiveil_pcie_comp_addr(pcie, off);
5105 +
5106 + ret = mobiveil_pcie_read(addr, size, &val);
5107 + if (ret)
5108 + dev_err(&pcie->pdev->dev, "read CSR address failed\n");
5109 +
5110 + return val;
5111 +}
5112 +
5113 +void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
5114 +{
5115 + void *addr;
5116 + int ret;
5117 +
5118 + addr = mobiveil_pcie_comp_addr(pcie, off);
5119 +
5120 + ret = mobiveil_pcie_write(addr, size, val);
5121 + if (ret)
5122 + dev_err(&pcie->pdev->dev, "write CSR address failed\n");
5123 +}
5124 +
5125 +bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
5126 +{
5127 + if (pcie->ops->link_up)
5128 + return pcie->ops->link_up(pcie);
5129 +
5130 + return (csr_readl(pcie, LTSSM_STATUS) &
5131 + LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
5132 +}
5133 +
5134 +void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5135 + u64 pci_addr, u32 type, u64 size)
5136 +{
5137 + u32 value;
5138 + u64 size64 = ~(size - 1);
5139 +
5140 + if (win_num >= pcie->ppio_wins) {
5141 + dev_err(&pcie->pdev->dev,
5142 + "ERROR: max inbound windows reached !\n");
5143 + return;
5144 + }
5145 +
5146 + value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
5147 + value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT |
5148 + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5149 + value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) |
5150 + (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5151 + csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
5152 +
5153 + csr_writel(pcie, upper_32_bits(size64),
5154 + PAB_EXT_PEX_AMAP_SIZEN(win_num));
5155 +
5156 + csr_writel(pcie, lower_32_bits(cpu_addr),
5157 + PAB_PEX_AMAP_AXI_WIN(win_num));
5158 + csr_writel(pcie, upper_32_bits(cpu_addr),
5159 + PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
5160 +
5161 + csr_writel(pcie, lower_32_bits(pci_addr),
5162 + PAB_PEX_AMAP_PEX_WIN_L(win_num));
5163 + csr_writel(pcie, upper_32_bits(pci_addr),
5164 + PAB_PEX_AMAP_PEX_WIN_H(win_num));
5165 +
5166 + pcie->ib_wins_configured++;
5167 +}
5168 +
5169 +/*
5170 + * routine to program the outbound windows
5171 + */
5172 +void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5173 + u64 pci_addr, u32 type, u64 size)
5174 +{
5175 +
5176 + u32 value;
5177 + u64 size64 = ~(size - 1);
5178 +
5179 + if (win_num >= pcie->apio_wins) {
5180 + dev_err(&pcie->pdev->dev,
5181 + "ERROR: max outbound windows reached !\n");
5182 + return;
5183 + }
5184 +
5185 + /*
5186 + * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
5187 + * to 4 KB in PAB_AXI_AMAP_CTRL register
5188 + */
5189 + value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
5190 + value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
5191 + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5192 + value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
5193 + (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5194 + csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
5195 +
5196 + csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
5197 +
5198 + /*
5199 + * program AXI window base with appropriate value in
5200 + * PAB_AXI_AMAP_AXI_WIN0 register
5201 + */
5202 + csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
5203 + PAB_AXI_AMAP_AXI_WIN(win_num));
5204 + csr_writel(pcie, upper_32_bits(cpu_addr),
5205 + PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
5206 +
5207 + csr_writel(pcie, lower_32_bits(pci_addr),
5208 + PAB_AXI_AMAP_PEX_WIN_L(win_num));
5209 + csr_writel(pcie, upper_32_bits(pci_addr),
5210 + PAB_AXI_AMAP_PEX_WIN_H(win_num));
5211 +
5212 + pcie->ob_wins_configured++;
5213 +}
5214 +
5215 +int program_ob_windows_ep(struct mobiveil_pcie *pcie, int win_num, int type,
5216 + u64 phys, u64 bus_addr, u8 func, u64 size)
5217 +{
5218 + u32 val;
5219 + u32 size_h, size_l;
5220 +
5221 + if (size & (size - 1))
5222 + size = 1 << (1 + ilog2(size));
5223 +
5224 + size_h = upper_32_bits(~(size - 1));
5225 + size_l = lower_32_bits(~(size - 1));
5226 +
5227 + val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
5228 + val &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
5229 + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5230 + val |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
5231 + (size_l & (WIN_SIZE_MASK << WIN_SIZE_SHIFT));
5232 + csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(win_num));
5233 +
5234 + csr_writel(pcie, func, PAB_AXI_AMAP_PCI_HDR_PARAM(win_num));
5235 + csr_writel(pcie, lower_32_bits(phys), PAB_AXI_AMAP_AXI_WIN(win_num));
5236 + csr_writel(pcie, upper_32_bits(phys),
5237 + PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
5238 + csr_writel(pcie, lower_32_bits(bus_addr),
5239 + PAB_AXI_AMAP_PEX_WIN_L(win_num));
5240 + csr_writel(pcie, upper_32_bits(bus_addr),
5241 + PAB_AXI_AMAP_PEX_WIN_H(win_num));
5242 + csr_writel(pcie, size_h, PAB_EXT_AXI_AMAP_SIZE(win_num));
5243 +
5244 + return 0;
5245 +}
5246 +
5247 +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
5248 + int bar, u64 phys)
5249 +{
5250 + csr_writel(pcie, upper_32_bits(phys),
5251 + PAB_EXT_PEX_BAR_AMAP(func_no, bar));
5252 + csr_writel(pcie, lower_32_bits(phys) | PEX_BAR_AMAP_EN,
5253 + PAB_PEX_BAR_AMAP(func_no, bar));
5254 +}
5255 +
5256 +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pcie,
5257 + u8 func_no, u8 bar)
5258 +{
5259 + u32 val;
5260 +
5261 + val = csr_readl(pcie, PAB_PEX_BAR_AMAP(func_no, bar));
5262 + val &= ~(1 << 0);
5263 + csr_writel(pcie, val, PAB_PEX_BAR_AMAP(func_no, bar));
5264 +}
5265 +
5266 +int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
5267 +{
5268 + int retries;
5269 +
5270 + /* check if the link is up or not */
5271 + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
5272 + if (mobiveil_pcie_link_up(pcie))
5273 + return 0;
5274 +
5275 + usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
5276 + }
5277 +
5278 + dev_info(&pcie->pdev->dev, "link never came up\n");
5279 +
5280 + return -ETIMEDOUT;
5281 +}
5282 +
5283 +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pcie, int win_num)
5284 +{
5285 + u32 val;
5286 +
5287 + val = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
5288 + val &= ~(1 << AMAP_CTRL_EN_SHIFT);
5289 + csr_writel(pcie, val, PAB_PEX_AMAP_CTRL(win_num));
5290 +}
5291 +
5292 +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int win_num)
5293 +{
5294 + u32 val;
5295 +
5296 + val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
5297 + val &= ~(1 << WIN_ENABLE_SHIFT);
5298 + csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(win_num));
5299 +}
5300 +
5301 +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pcie)
5302 +{
5303 + u32 val;
5304 +
5305 + val = csr_readl(pcie, PAB_CTRL);
5306 + val |= 1 << AMBA_PIO_ENABLE_SHIFT;
5307 + val |= 1 << PEX_PIO_ENABLE_SHIFT;
5308 + csr_writel(pcie, val, PAB_CTRL);
5309 +}
5310 +
5311 +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pcie)
5312 +{
5313 + u32 val;
5314 +
5315 + val = csr_readl(pcie, PAB_AXI_PIO_CTRL);
5316 + val |= APIO_EN_MASK;
5317 + csr_writel(pcie, val, PAB_AXI_PIO_CTRL);
5318 +}
5319 +
5320 +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pcie)
5321 +{
5322 + u32 val;
5323 +
5324 + val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
5325 + val |= 1 << PIO_ENABLE_SHIFT;
5326 + csr_writel(pcie, val, PAB_PEX_PIO_CTRL);
5327 +}
5328 +
5329 +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pcie)
5330 +{
5331 + u32 val;
5332 +
5333 + val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
5334 + val |= 1 << 0;
5335 + csr_writel(pcie, val, PAB_INTP_AMBA_MISC_ENB);
5336 +}
5337 --- /dev/null
5338 +++ b/drivers/pci/mobiveil/pcie-mobiveil.h
5339 @@ -0,0 +1,296 @@
5340 +/* SPDX-License-Identifier: GPL-2.0 */
5341 +/*
5342 + * PCIe host controller driver for Mobiveil PCIe Host controller
5343 + *
5344 + * Copyright (c) 2018 Mobiveil Inc.
5345 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
5346 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
5347 + */
5348 +
5349 +#ifndef _PCIE_MOBIVEIL_H
5350 +#define _PCIE_MOBIVEIL_H
5351 +
5352 +#include <linux/pci.h>
5353 +#include <linux/irq.h>
5354 +#include <linux/msi.h>
5355 +#include "../pci.h"
5356 +
5357 +#include <linux/pci-epc.h>
5358 +#include <linux/pci-epf.h>
5359 +
5360 +#define MAX_IATU_OUT 256
5361 +/* register offsets and bit positions */
5362 +
5363 +/*
5364 + * translation tables are grouped into windows, each window registers are
5365 + * grouped into blocks of 4 or 16 registers each
5366 + */
5367 +#define PAB_REG_BLOCK_SIZE 16
5368 +#define PAB_EXT_REG_BLOCK_SIZE 4
5369 +
5370 +#define PAB_REG_ADDR(offset, win) \
5371 + (offset + (win * PAB_REG_BLOCK_SIZE))
5372 +#define PAB_EXT_REG_ADDR(offset, win) \
5373 + (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
5374 +
5375 +#define LTSSM_STATUS 0x0404
5376 +#define LTSSM_STATUS_L0_MASK 0x3f
5377 +#define LTSSM_STATUS_L0 0x2d
5378 +
5379 +#define PAB_CTRL 0x0808
5380 +#define AMBA_PIO_ENABLE_SHIFT 0
5381 +#define PEX_PIO_ENABLE_SHIFT 1
5382 +#define PAGE_SEL_SHIFT 13
5383 +#define PAGE_SEL_MASK 0x3f
5384 +#define PAGE_LO_MASK 0x3ff
5385 +#define PAGE_SEL_OFFSET_SHIFT 10
5386 +#define FUNC_SEL_SHIFT 19
5387 +#define FUNC_SEL_MASK 0x1ff
5388 +#define MSI_SW_CTRL_EN (1 << 29)
5389 +
5390 +#define PAB_ACTIVITY_STAT 0x81c
5391 +
5392 +#define PAB_AXI_PIO_CTRL 0x0840
5393 +#define APIO_EN_MASK 0xf
5394 +
5395 +#define PAB_PEX_PIO_CTRL 0x08c0
5396 +#define PIO_ENABLE_SHIFT 0
5397 +
5398 +#define PAB_INTP_AMBA_MISC_ENB 0x0b0c
5399 +#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
5400 +#define PAB_INTP_RESET (0x1 << 1)
5401 +#define PAB_INTP_MSI (0x1 << 3)
5402 +#define PAB_INTP_INTA (0x1 << 5)
5403 +#define PAB_INTP_INTB (0x1 << 6)
5404 +#define PAB_INTP_INTC (0x1 << 7)
5405 +#define PAB_INTP_INTD (0x1 << 8)
5406 +#define PAB_INTP_PCIE_UE (0x1 << 9)
5407 +#define PAB_INTP_IE_PMREDI (0x1 << 29)
5408 +#define PAB_INTP_IE_EC (0x1 << 30)
5409 +#define PAB_INTP_MSI_MASK PAB_INTP_MSI
5410 +#define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\
5411 + PAB_INTP_INTC | PAB_INTP_INTD)
5412 +
5413 +#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
5414 +#define WIN_ENABLE_SHIFT 0
5415 +#define WIN_TYPE_SHIFT 1
5416 +#define WIN_TYPE_MASK 0x3
5417 +#define WIN_SIZE_SHIFT 10
5418 +#define WIN_SIZE_MASK 0x3fffff
5419 +
5420 +#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
5421 +
5422 +#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
5423 +#define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
5424 +#define AXI_WINDOW_ALIGN_MASK 3
5425 +
5426 +#define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
5427 +#define PAB_BUS_SHIFT 24
5428 +#define PAB_DEVICE_SHIFT 19
5429 +#define PAB_FUNCTION_SHIFT 16
5430 +
5431 +#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
5432 +#define PAB_INTP_AXI_PIO_CLASS 0x474
5433 +
5434 +#define GPEX_ACK_REPLAY_TO 0x438
5435 +#define ACK_LAT_TO_VAL_MASK 0x1fff
5436 +#define ACK_LAT_TO_VAL_SHIFT 0
5437 +
5438 +#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
5439 +#define AMAP_CTRL_EN_SHIFT 0
5440 +#define AMAP_CTRL_TYPE_SHIFT 1
5441 +#define AMAP_CTRL_TYPE_MASK 3
5442 +
5443 +#define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
5444 +#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win)
5445 +#define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
5446 +#define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
5447 +#define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
5448 +
5449 +/* PPIO WINs EP mode */
5450 +#define PAB_PEX_BAR_AMAP(func, bar) (0x1ba0 + 0x20 * func + 4 * bar)
5451 +#define PAB_EXT_PEX_BAR_AMAP(func, bar) (0x84a0 + 0x20 * func + 4 * bar)
5452 +#define PEX_BAR_AMAP_EN (1 << 0)
5453 +
5454 +#define PAB_AXI_AMAP_PCI_HDR_PARAM(idx) (0x5ba0 + 0x04 * idx)
5455 +#define PAB_MSIX_TABLE_PBA_ACCESS 0xD000
5456 +
5457 +#define GPEX_BAR_ENABLE 0x4D4
5458 +#define GPEX_BAR_SIZE_LDW 0x4D8
5459 +#define GPEX_BAR_SIZE_UDW 0x4DC
5460 +#define GPEX_BAR_SELECT 0x4E0
5461 +
5462 +#define CFG_UNCORRECTABLE_ERROR_SEVERITY 0x10c
5463 +#define UNSUPPORTED_REQUEST_ERROR_SHIFT 20
5464 +#define CFG_UNCORRECTABLE_ERROR_MASK 0x108
5465 +
5466 +/* starting offset of INTX bits in status register */
5467 +#define PAB_INTX_START 5
5468 +
5469 +/* supported number of MSI interrupts */
5470 +#define PCI_NUM_MSI 16
5471 +
5472 +/* MSI registers */
5473 +#define MSI_BASE_LO_OFFSET 0x04
5474 +#define MSI_BASE_HI_OFFSET 0x08
5475 +#define MSI_SIZE_OFFSET 0x0c
5476 +#define MSI_ENABLE_OFFSET 0x14
5477 +#define MSI_STATUS_OFFSET 0x18
5478 +#define MSI_DATA_OFFSET 0x20
5479 +#define MSI_ADDR_L_OFFSET 0x24
5480 +#define MSI_ADDR_H_OFFSET 0x28
5481 +
5482 +/* outbound and inbound window definitions */
5483 +#define WIN_NUM_0 0
5484 +#define WIN_NUM_1 1
5485 +#define CFG_WINDOW_TYPE 0
5486 +#define IO_WINDOW_TYPE 1
5487 +#define MEM_WINDOW_TYPE 2
5488 +#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
5489 +#define MAX_PIO_WINDOWS 8
5490 +
5491 +/* Parameters for the waiting for link up routine */
5492 +#define LINK_WAIT_MAX_RETRIES 10
5493 +#define LINK_WAIT_MIN 90000
5494 +#define LINK_WAIT_MAX 100000
5495 +
5496 +#define PAGED_ADDR_BNDRY 0xc00
5497 +#define OFFSET_TO_PAGE_ADDR(off) \
5498 + ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
5499 +#define OFFSET_TO_PAGE_IDX(off) \
5500 + ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
5501 +
5502 +struct mobiveil_pcie;
5503 +struct mobiveil_pcie_ep;
5504 +
5505 +struct mobiveil_msi { /* MSI information */
5506 + struct mutex lock; /* protect bitmap variable */
5507 + struct irq_domain *msi_domain;
5508 + struct irq_domain *dev_domain;
5509 + phys_addr_t msi_pages_phys;
5510 + int num_of_vectors;
5511 + DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
5512 +};
5513 +
5514 +struct mobiveil_rp_ops {
5515 + int (*interrupt_init)(struct mobiveil_pcie *pcie);
5516 + int (*read_other_conf)(struct pci_bus *bus, unsigned int devfn,
5517 + int where, int size, u32 *val);
5518 +};
5519 +
5520 +struct root_port {
5521 + u8 root_bus_nr;
5522 + void __iomem *config_axi_slave_base; /* endpoint config base */
5523 + struct resource *ob_io_res;
5524 + struct mobiveil_rp_ops *ops;
5525 + int irq;
5526 + raw_spinlock_t intx_mask_lock;
5527 + struct irq_domain *intx_domain;
5528 + struct mobiveil_msi msi;
5529 +};
5530 +
5531 +struct mobiveil_pab_ops {
5532 + int (*link_up)(struct mobiveil_pcie *pcie);
5533 +};
5534 +
5535 +struct mobiveil_pcie_ep_ops {
5536 + void (*ep_init)(struct mobiveil_pcie_ep *ep);
5537 + int (*raise_irq)(struct mobiveil_pcie_ep *ep, u8 func_no,
5538 + enum pci_epc_irq_type type, u16 interrupt_num);
5539 +};
5540 +
5541 +struct mobiveil_pcie_ep {
5542 + struct pci_epc *epc;
5543 + struct mobiveil_pcie_ep_ops *ops;
5544 + phys_addr_t phys_base;
5545 + size_t addr_size;
5546 + size_t page_size;
5547 + phys_addr_t *outbound_addr;
5548 + unsigned long *ob_window_map;
5549 + u32 num_ob_windows;
5550 + void __iomem *msi_mem;
5551 + phys_addr_t msi_mem_phys;
5552 + u8 msi_cap; /* MSI capability offset */
5553 + u8 msix_cap; /* MSI-X capability offset */
5554 + u8 bar_num;
5555 + u32 pf_num;
5556 +};
5557 +
5558 +struct mobiveil_pcie {
5559 + struct platform_device *pdev;
5560 + struct list_head *resources;
5561 + void __iomem *csr_axi_slave_base; /* PAB registers base */
5562 + phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
5563 + void __iomem *apb_csr_base; /* MSI register base */
5564 + u32 apio_wins;
5565 + u32 ppio_wins;
5566 + u32 ob_wins_configured; /* configured outbound windows */
5567 + u32 ib_wins_configured; /* configured inbound windows */
5568 + const struct mobiveil_pab_ops *ops;
5569 + struct root_port rp;
5570 + struct mobiveil_pcie_ep ep;
5571 +};
5572 +#define to_mobiveil_pcie_from_ep(endpoint) \
5573 + container_of((endpoint), struct mobiveil_pcie, ep)
5574 +
5575 +int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
5576 +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
5577 +bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
5578 +int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
5579 +void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5580 + u64 pci_addr, u32 type, u64 size);
5581 +void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5582 + u64 pci_addr, u32 type, u64 size);
5583 +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
5584 +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
5585 +u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
5586 +void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
5587 +
5588 +static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
5589 +{
5590 + return csr_read(pcie, off, 0x4);
5591 +}
5592 +
5593 +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off)
5594 +{
5595 + return csr_read(pcie, off, 0x2);
5596 +}
5597 +
5598 +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off)
5599 +{
5600 + return csr_read(pcie, off, 0x1);
5601 +}
5602 +
5603 +static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
5604 +{
5605 + csr_write(pcie, val, off, 0x4);
5606 +}
5607 +
5608 +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
5609 +{
5610 + csr_write(pcie, val, off, 0x2);
5611 +}
5612 +
5613 +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
5614 +{
5615 + csr_write(pcie, val, off, 0x1);
5616 +}
5617 +
5618 +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
5619 + int bar, u64 phys);
5620 +int program_ob_windows_ep(struct mobiveil_pcie *pcie, int win_num, int type,
5621 + u64 phys, u64 bus_addr, u8 func, u64 size);
5622 +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pci,
5623 + u8 func_no, u8 bar);
5624 +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep);
5625 +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no);
5626 +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
5627 + u8 interrupt_num);
5628 +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
5629 + u16 interrupt_num);
5630 +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pci, enum pci_barno bar);
5631 +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pci);
5632 +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pci);
5633 +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pci);
5634 +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pci);
5635 +#endif /* _PCIE_MOBIVEIL_H */
5636 --- a/drivers/pci/pcie/portdrv_core.c
5637 +++ b/drivers/pci/pcie/portdrv_core.c
5638 @@ -45,6 +45,20 @@ static void release_pcie_device(struct d
5639 }
5640
5641 /**
5642 + * pcibios_check_service_irqs - check irqs in the device tree
5643 + * @dev: PCI Express port to handle
5644 + * @irqs: Array of irqs to populate
5645 + * @mask: Bitmask of port capabilities returned by get_port_device_capability()
5646 + *
5647 + * Return value: 0 means no service irqs in the device tree
5648 + *
5649 + */
5650 +int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
5651 +{
5652 + return 0;
5653 +}
5654 +
5655 +/**
5656 * pcie_port_enable_irq_vec - try to set up MSI-X or MSI as interrupt mode
5657 * for given port
5658 * @dev: PCI Express port to handle
5659 @@ -185,10 +199,25 @@ out_free_irqs:
5660 static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
5661 {
5662 int ret, i;
5663 + int irq = -1;
5664
5665 for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
5666 irqs[i] = -1;
5667
5668 + /* Check if some platforms owns independent irq pins for AER/PME etc.
5669 + * Some platforms may own independent AER/PME interrupts and set
5670 + * them in the device tree file.
5671 + */
5672 + ret = pcibios_check_service_irqs(dev, irqs, mask);
5673 + if (ret) {
5674 + if (dev->irq)
5675 + irq = dev->irq;
5676 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
5677 + if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
5678 + irqs[i] = irq;
5679 + return 0;
5680 + }
5681 +
5682 /*
5683 * If we support PME or hotplug, but we can't use MSI/MSI-X for
5684 * them, we have to fall back to INTx or other interrupts, e.g., a
5685 --- a/drivers/pci/quirks.c
5686 +++ b/drivers/pci/quirks.c
5687 @@ -3394,6 +3394,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_A
5688 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
5689 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
5690
5691 +/*
5692 + * NXP (Freescale Vendor ID) LS1088 chips do not behave correctly after
5693 + * bus reset. Link state of device does not comes UP and so config space
5694 + * never accessible again.
5695 + */
5696 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x80c0, quirk_no_bus_reset);
5697 +
5698 static void quirk_no_pm_reset(struct pci_dev *dev)
5699 {
5700 /*
5701 @@ -4878,3 +4885,11 @@ static void quirk_no_ats(struct pci_dev
5702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
5703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats);
5704 #endif /* CONFIG_PCI_ATS */
5705 +
5706 +/* Freescale PCIe doesn't support MSI in RC mode */
5707 +static void quirk_fsl_no_msi(struct pci_dev *pdev)
5708 +{
5709 + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5710 + pdev->no_msi = 1;
5711 +}
5712 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5713 --- a/include/linux/pci-ep-cfs.h
5714 +++ b/include/linux/pci-ep-cfs.h
5715 @@ -1,12 +1,9 @@
5716 +/* SPDX-License-Identifier: GPL-2.0+ */
5717 /**
5718 * PCI Endpoint ConfigFS header file
5719 *
5720 * Copyright (C) 2017 Texas Instruments
5721 * Author: Kishon Vijay Abraham I <kishon@ti.com>
5722 - *
5723 - * This program is free software: you can redistribute it and/or modify
5724 - * it under the terms of the GNU General Public License version 2 of
5725 - * the License as published by the Free Software Foundation.
5726 */
5727
5728 #ifndef __LINUX_PCI_EP_CFS_H
5729 --- a/include/linux/pci-epc.h
5730 +++ b/include/linux/pci-epc.h
5731 @@ -1,12 +1,9 @@
5732 +/* SPDX-License-Identifier: GPL-2.0+ */
5733 /**
5734 * PCI Endpoint *Controller* (EPC) header file
5735 *
5736 * Copyright (C) 2017 Texas Instruments
5737 * Author: Kishon Vijay Abraham I <kishon@ti.com>
5738 - *
5739 - * This program is free software: you can redistribute it and/or modify
5740 - * it under the terms of the GNU General Public License version 2 of
5741 - * the License as published by the Free Software Foundation.
5742 */
5743
5744 #ifndef __LINUX_PCI_EPC_H
5745 @@ -20,6 +17,7 @@ enum pci_epc_irq_type {
5746 PCI_EPC_IRQ_UNKNOWN,
5747 PCI_EPC_IRQ_LEGACY,
5748 PCI_EPC_IRQ_MSI,
5749 + PCI_EPC_IRQ_MSIX,
5750 };
5751
5752 /**
5753 @@ -33,24 +31,32 @@ enum pci_epc_irq_type {
5754 * capability register
5755 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
5756 * the MSI capability register
5757 - * @raise_irq: ops to raise a legacy or MSI interrupt
5758 + * @set_msix: ops to set the requested number of MSI-X interrupts in the
5759 + * MSI-X capability register
5760 + * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
5761 + * from the MSI-X capability register
5762 + * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
5763 * @start: ops to start the PCI link
5764 * @stop: ops to stop the PCI link
5765 * @owner: the module owner containing the ops
5766 */
5767 struct pci_epc_ops {
5768 - int (*write_header)(struct pci_epc *pci_epc,
5769 + int (*write_header)(struct pci_epc *epc, u8 func_no,
5770 struct pci_epf_header *hdr);
5771 - int (*set_bar)(struct pci_epc *epc, enum pci_barno bar,
5772 - dma_addr_t bar_phys, size_t size, int flags);
5773 - void (*clear_bar)(struct pci_epc *epc, enum pci_barno bar);
5774 - int (*map_addr)(struct pci_epc *epc, phys_addr_t addr,
5775 - u64 pci_addr, size_t size);
5776 - void (*unmap_addr)(struct pci_epc *epc, phys_addr_t addr);
5777 - int (*set_msi)(struct pci_epc *epc, u8 interrupts);
5778 - int (*get_msi)(struct pci_epc *epc);
5779 - int (*raise_irq)(struct pci_epc *pci_epc,
5780 - enum pci_epc_irq_type type, u8 interrupt_num);
5781 + int (*set_bar)(struct pci_epc *epc, u8 func_no,
5782 + struct pci_epf_bar *epf_bar);
5783 + void (*clear_bar)(struct pci_epc *epc, u8 func_no,
5784 + struct pci_epf_bar *epf_bar);
5785 + int (*map_addr)(struct pci_epc *epc, u8 func_no,
5786 + phys_addr_t addr, u64 pci_addr, size_t size);
5787 + void (*unmap_addr)(struct pci_epc *epc, u8 func_no,
5788 + phys_addr_t addr);
5789 + int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
5790 + int (*get_msi)(struct pci_epc *epc, u8 func_no);
5791 + int (*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts);
5792 + int (*get_msix)(struct pci_epc *epc, u8 func_no);
5793 + int (*raise_irq)(struct pci_epc *epc, u8 func_no,
5794 + enum pci_epc_irq_type type, u16 interrupt_num);
5795 int (*start)(struct pci_epc *epc);
5796 void (*stop)(struct pci_epc *epc);
5797 struct module *owner;
5798 @@ -91,8 +97,17 @@ struct pci_epc {
5799 struct config_group *group;
5800 /* spinlock to protect against concurrent access of EP controller */
5801 spinlock_t lock;
5802 + unsigned int features;
5803 };
5804
5805 +#define EPC_FEATURE_NO_LINKUP_NOTIFIER BIT(0)
5806 +#define EPC_FEATURE_BAR_MASK (BIT(1) | BIT(2) | BIT(3))
5807 +#define EPC_FEATURE_MSIX_AVAILABLE BIT(4)
5808 +#define EPC_FEATURE_SET_BAR(features, bar) \
5809 + (features |= (EPC_FEATURE_BAR_MASK & (bar << 1)))
5810 +#define EPC_FEATURE_GET_BAR(features) \
5811 + ((features & EPC_FEATURE_BAR_MASK) >> 1)
5812 +
5813 #define to_pci_epc(device) container_of((device), struct pci_epc, dev)
5814
5815 #define pci_epc_create(dev, ops) \
5816 @@ -124,17 +139,23 @@ void pci_epc_destroy(struct pci_epc *epc
5817 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
5818 void pci_epc_linkup(struct pci_epc *epc);
5819 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
5820 -int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *hdr);
5821 -int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
5822 - dma_addr_t bar_phys, size_t size, int flags);
5823 -void pci_epc_clear_bar(struct pci_epc *epc, int bar);
5824 -int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
5825 +int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
5826 + struct pci_epf_header *hdr);
5827 +int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
5828 + struct pci_epf_bar *epf_bar);
5829 +void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
5830 + struct pci_epf_bar *epf_bar);
5831 +int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
5832 + phys_addr_t phys_addr,
5833 u64 pci_addr, size_t size);
5834 -void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr);
5835 -int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts);
5836 -int pci_epc_get_msi(struct pci_epc *epc);
5837 -int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
5838 - u8 interrupt_num);
5839 +void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
5840 + phys_addr_t phys_addr);
5841 +int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
5842 +int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
5843 +int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts);
5844 +int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
5845 +int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
5846 + enum pci_epc_irq_type type, u16 interrupt_num);
5847 int pci_epc_start(struct pci_epc *epc);
5848 void pci_epc_stop(struct pci_epc *epc);
5849 struct pci_epc *pci_epc_get(const char *epc_name);
5850 --- a/include/linux/pci-epf.h
5851 +++ b/include/linux/pci-epf.h
5852 @@ -1,12 +1,9 @@
5853 +/* SPDX-License-Identifier: GPL-2.0+ */
5854 /**
5855 * PCI Endpoint *Function* (EPF) header file
5856 *
5857 * Copyright (C) 2017 Texas Instruments
5858 * Author: Kishon Vijay Abraham I <kishon@ti.com>
5859 - *
5860 - * This program is free software: you can redistribute it and/or modify
5861 - * it under the terms of the GNU General Public License version 2 of
5862 - * the License as published by the Free Software Foundation.
5863 */
5864
5865 #ifndef __LINUX_PCI_EPF_H
5866 @@ -75,7 +72,7 @@ struct pci_epf_ops {
5867 * @driver: PCI EPF driver
5868 * @ops: set of function pointers for performing EPF operations
5869 * @owner: the owner of the module that registers the PCI EPF driver
5870 - * @group: configfs group corresponding to the PCI EPF driver
5871 + * @epf_group: list of configfs group corresponding to the PCI EPF driver
5872 * @id_table: identifies EPF devices for probing
5873 */
5874 struct pci_epf_driver {
5875 @@ -85,7 +82,7 @@ struct pci_epf_driver {
5876 struct device_driver driver;
5877 struct pci_epf_ops *ops;
5878 struct module *owner;
5879 - struct config_group *group;
5880 + struct list_head epf_group;
5881 const struct pci_epf_device_id *id_table;
5882 };
5883
5884 @@ -100,6 +97,8 @@ struct pci_epf_driver {
5885 struct pci_epf_bar {
5886 dma_addr_t phys_addr;
5887 size_t size;
5888 + enum pci_barno barno;
5889 + int flags;
5890 };
5891
5892 /**
5893 @@ -120,6 +119,7 @@ struct pci_epf {
5894 struct pci_epf_header *header;
5895 struct pci_epf_bar bar[6];
5896 u8 msi_interrupts;
5897 + u16 msix_interrupts;
5898 u8 func_no;
5899
5900 struct pci_epc *epc;
5901 --- a/include/linux/pci.h
5902 +++ b/include/linux/pci.h
5903 @@ -1946,6 +1946,7 @@ void pcibios_release_device(struct pci_d
5904 void pcibios_penalize_isa_irq(int irq, int active);
5905 int pcibios_alloc_irq(struct pci_dev *dev);
5906 void pcibios_free_irq(struct pci_dev *dev);
5907 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
5908
5909 #ifdef CONFIG_HIBERNATE_CALLBACKS
5910 extern struct dev_pm_ops pcibios_pm_ops;
5911 --- a/include/uapi/linux/pcitest.h
5912 +++ b/include/uapi/linux/pcitest.h
5913 @@ -16,5 +16,8 @@
5914 #define PCITEST_WRITE _IOW('P', 0x4, unsigned long)
5915 #define PCITEST_READ _IOW('P', 0x5, unsigned long)
5916 #define PCITEST_COPY _IOW('P', 0x6, unsigned long)
5917 +#define PCITEST_MSIX _IOW('P', 0x7, int)
5918 +#define PCITEST_SET_IRQTYPE _IOW('P', 0x8, int)
5919 +#define PCITEST_GET_IRQTYPE _IO('P', 0x9)
5920
5921 #endif /* __UAPI_LINUX_PCITEST_H */
5922 --- a/tools/pci/pcitest.c
5923 +++ b/tools/pci/pcitest.c
5924 @@ -31,12 +31,17 @@
5925 #define BILLION 1E9
5926
5927 static char *result[] = { "NOT OKAY", "OKAY" };
5928 +static char *irq[] = { "LEGACY", "MSI", "MSI-X" };
5929
5930 struct pci_test {
5931 char *device;
5932 char barnum;
5933 bool legacyirq;
5934 unsigned int msinum;
5935 + unsigned int msixnum;
5936 + int irqtype;
5937 + bool set_irqtype;
5938 + bool get_irqtype;
5939 bool read;
5940 bool write;
5941 bool copy;
5942 @@ -65,6 +70,24 @@ static int run_test(struct pci_test *tes
5943 fprintf(stdout, "%s\n", result[ret]);
5944 }
5945
5946 + if (test->set_irqtype) {
5947 + ret = ioctl(fd, PCITEST_SET_IRQTYPE, test->irqtype);
5948 + fprintf(stdout, "SET IRQ TYPE TO %s:\t\t", irq[test->irqtype]);
5949 + if (ret < 0)
5950 + fprintf(stdout, "FAILED\n");
5951 + else
5952 + fprintf(stdout, "%s\n", result[ret]);
5953 + }
5954 +
5955 + if (test->get_irqtype) {
5956 + ret = ioctl(fd, PCITEST_GET_IRQTYPE);
5957 + fprintf(stdout, "GET IRQ TYPE:\t\t");
5958 + if (ret < 0)
5959 + fprintf(stdout, "FAILED\n");
5960 + else
5961 + fprintf(stdout, "%s\n", irq[ret]);
5962 + }
5963 +
5964 if (test->legacyirq) {
5965 ret = ioctl(fd, PCITEST_LEGACY_IRQ, 0);
5966 fprintf(stdout, "LEGACY IRQ:\t");
5967 @@ -83,6 +106,15 @@ static int run_test(struct pci_test *tes
5968 fprintf(stdout, "%s\n", result[ret]);
5969 }
5970
5971 + if (test->msixnum > 0 && test->msixnum <= 2048) {
5972 + ret = ioctl(fd, PCITEST_MSIX, test->msixnum);
5973 + fprintf(stdout, "MSI-X%d:\t\t", test->msixnum);
5974 + if (ret < 0)
5975 + fprintf(stdout, "TEST FAILED\n");
5976 + else
5977 + fprintf(stdout, "%s\n", result[ret]);
5978 + }
5979 +
5980 if (test->write) {
5981 ret = ioctl(fd, PCITEST_WRITE, test->size);
5982 fprintf(stdout, "WRITE (%7ld bytes):\t\t", test->size);
5983 @@ -133,7 +165,7 @@ int main(int argc, char **argv)
5984 /* set default endpoint device */
5985 test->device = "/dev/pci-endpoint-test.0";
5986
5987 - while ((c = getopt(argc, argv, "D:b:m:lrwcs:")) != EOF)
5988 + while ((c = getopt(argc, argv, "D:b:m:x:i:Ilrwcs:")) != EOF)
5989 switch (c) {
5990 case 'D':
5991 test->device = optarg;
5992 @@ -151,6 +183,20 @@ int main(int argc, char **argv)
5993 if (test->msinum < 1 || test->msinum > 32)
5994 goto usage;
5995 continue;
5996 + case 'x':
5997 + test->msixnum = atoi(optarg);
5998 + if (test->msixnum < 1 || test->msixnum > 2048)
5999 + goto usage;
6000 + continue;
6001 + case 'i':
6002 + test->irqtype = atoi(optarg);
6003 + if (test->irqtype < 0 || test->irqtype > 2)
6004 + goto usage;
6005 + test->set_irqtype = true;
6006 + continue;
6007 + case 'I':
6008 + test->get_irqtype = true;
6009 + continue;
6010 case 'r':
6011 test->read = true;
6012 continue;
6013 @@ -173,6 +219,9 @@ usage:
6014 "\t-D <dev> PCI endpoint test device {default: /dev/pci-endpoint-test.0}\n"
6015 "\t-b <bar num> BAR test (bar number between 0..5)\n"
6016 "\t-m <msi num> MSI test (msi number between 1..32)\n"
6017 + "\t-x <msix num> \tMSI-X test (msix number between 1..2048)\n"
6018 + "\t-i <irq type> \tSet IRQ type (0 - Legacy, 1 - MSI, 2 - MSI-X)\n"
6019 + "\t-I Get current IRQ type configured\n"
6020 "\t-l Legacy IRQ test\n"
6021 "\t-r Read buffer test\n"
6022 "\t-w Write buffer test\n"
6023 --- a/tools/pci/pcitest.sh
6024 +++ b/tools/pci/pcitest.sh
6025 @@ -16,7 +16,10 @@ echo
6026 echo "Interrupt tests"
6027 echo
6028
6029 +pcitest -i 0
6030 pcitest -l
6031 +
6032 +pcitest -i 1
6033 msi=1
6034
6035 while [ $msi -lt 33 ]
6036 @@ -26,9 +29,21 @@ do
6037 done
6038 echo
6039
6040 +pcitest -i 2
6041 +msix=1
6042 +
6043 +while [ $msix -lt 2049 ]
6044 +do
6045 + pcitest -x $msix
6046 + msix=`expr $msix + 1`
6047 +done
6048 +echo
6049 +
6050 echo "Read Tests"
6051 echo
6052
6053 +pcitest -i 1
6054 +
6055 pcitest -r -s 1
6056 pcitest -r -s 1024
6057 pcitest -r -s 1025
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