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kernel: bump 4.14 to 4.14.144
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.14 / 816-pcie-support-layerscape.patch
1 From c54a010fe105281259b996d318ed85efc4103fee Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 6 May 2019 15:18:05 +0800
4 Subject: [PATCH] pcie: support layerscape
5
6 This is an integrated patch of pcie for layerscape
7
8 Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
9 Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
10 Signed-off-by: Biwen Li <biwen.li@nxp.com>
11 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
12 Signed-off-by: Christoph Hellwig <hch@lst.de>
13 Signed-off-by: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
14 Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
15 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
16 Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
17 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
18 Signed-off-by: Jia-Ju Bai <baijiaju1990@gmail.com>
19 Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
20 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
22 Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
23 Signed-off-by: Po Liu <po.liu@nxp.com>
24 Signed-off-by: Rob Herring <robh@kernel.org>
25 Signed-off-by: Rolf Evers-Fischer <rolf.evers.fischer@aptiv.com>
26 Signed-off-by: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
27 Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
28 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
29 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
30 ---
31 arch/arm/kernel/bios32.c | 43 ++
32 arch/arm64/kernel/pci.c | 43 ++
33 drivers/misc/pci_endpoint_test.c | 332 ++++++++++---
34 drivers/pci/Kconfig | 1 +
35 drivers/pci/dwc/Kconfig | 39 +-
36 drivers/pci/dwc/Makefile | 2 +-
37 drivers/pci/dwc/pci-dra7xx.c | 9 -
38 drivers/pci/dwc/pci-layerscape-ep.c | 146 ++++++
39 drivers/pci/dwc/pci-layerscape.c | 12 +
40 drivers/pci/dwc/pcie-designware-ep.c | 338 ++++++++++++--
41 drivers/pci/dwc/pcie-designware-host.c | 5 +-
42 drivers/pci/dwc/pcie-designware-plat.c | 159 ++++++-
43 drivers/pci/dwc/pcie-designware.c | 5 +-
44 drivers/pci/dwc/pcie-designware.h | 57 ++-
45 drivers/pci/endpoint/Kconfig | 1 +
46 drivers/pci/endpoint/Makefile | 1 +
47 drivers/pci/endpoint/functions/Kconfig | 1 +
48 drivers/pci/endpoint/functions/Makefile | 1 +
49 drivers/pci/endpoint/functions/pci-epf-test.c | 191 +++++---
50 drivers/pci/endpoint/pci-ep-cfs.c | 95 +++-
51 drivers/pci/endpoint/pci-epc-core.c | 159 +++++--
52 drivers/pci/endpoint/pci-epc-mem.c | 13 +-
53 drivers/pci/endpoint/pci-epf-core.c | 116 +++--
54 drivers/pci/host/pci-host-common.c | 8 -
55 drivers/pci/host/pcie-xilinx-nwl.c | 9 -
56 drivers/pci/host/pcie-xilinx.c | 7 -
57 drivers/pci/mobiveil/Kconfig | 50 ++
58 drivers/pci/mobiveil/Makefile | 7 +
59 drivers/pci/mobiveil/pci-layerscape-gen4-ep.c | 178 +++++++
60 drivers/pci/mobiveil/pci-layerscape-gen4.c | 292 ++++++++++++
61 drivers/pci/mobiveil/pcie-mobiveil-ep.c | 512 +++++++++++++++++++++
62 drivers/pci/mobiveil/pcie-mobiveil-host.c | 640 ++++++++++++++++++++++++++
63 drivers/pci/mobiveil/pcie-mobiveil-plat.c | 54 +++
64 drivers/pci/mobiveil/pcie-mobiveil.c | 334 ++++++++++++++
65 drivers/pci/mobiveil/pcie-mobiveil.h | 296 ++++++++++++
66 drivers/pci/pcie/portdrv_core.c | 29 ++
67 drivers/pci/quirks.c | 15 +
68 include/linux/pci-ep-cfs.h | 5 +-
69 include/linux/pci-epc.h | 73 +--
70 include/linux/pci-epf.h | 12 +-
71 include/linux/pci.h | 1 +
72 include/uapi/linux/pcitest.h | 3 +
73 tools/pci/pcitest.c | 51 +-
74 tools/pci/pcitest.sh | 15 +
75 44 files changed, 3917 insertions(+), 443 deletions(-)
76 create mode 100644 drivers/pci/dwc/pci-layerscape-ep.c
77 create mode 100644 drivers/pci/mobiveil/Kconfig
78 create mode 100644 drivers/pci/mobiveil/Makefile
79 create mode 100644 drivers/pci/mobiveil/pci-layerscape-gen4-ep.c
80 create mode 100644 drivers/pci/mobiveil/pci-layerscape-gen4.c
81 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil-ep.c
82 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil-host.c
83 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil-plat.c
84 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil.c
85 create mode 100644 drivers/pci/mobiveil/pcie-mobiveil.h
86
87 --- a/arch/arm/kernel/bios32.c
88 +++ b/arch/arm/kernel/bios32.c
89 @@ -12,6 +12,8 @@
90 #include <linux/slab.h>
91 #include <linux/init.h>
92 #include <linux/io.h>
93 +#include <linux/of_irq.h>
94 +#include <linux/pcieport_if.h>
95
96 #include <asm/mach-types.h>
97 #include <asm/mach/map.h>
98 @@ -65,6 +67,47 @@ void pcibios_report_status(u_int status_
99 }
100
101 /*
102 + * Check device tree if the service interrupts are there
103 + */
104 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
105 +{
106 + int ret, count = 0;
107 + struct device_node *np = NULL;
108 +
109 + if (dev->bus->dev.of_node)
110 + np = dev->bus->dev.of_node;
111 +
112 + if (np == NULL)
113 + return 0;
114 +
115 + if (!IS_ENABLED(CONFIG_OF_IRQ))
116 + return 0;
117 +
118 + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
119 + * request irq for aer
120 + */
121 + if (mask & PCIE_PORT_SERVICE_AER) {
122 + ret = of_irq_get_byname(np, "aer");
123 + if (ret > 0) {
124 + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
125 + count++;
126 + }
127 + }
128 +
129 + if (mask & PCIE_PORT_SERVICE_PME) {
130 + ret = of_irq_get_byname(np, "pme");
131 + if (ret > 0) {
132 + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
133 + count++;
134 + }
135 + }
136 +
137 + /* TODO: add more service interrupts if there it is in the device tree*/
138 +
139 + return count;
140 +}
141 +
142 +/*
143 * We don't use this to fix the device, but initialisation of it.
144 * It's not the correct use for this, but it works.
145 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
146 --- a/arch/arm64/kernel/pci.c
147 +++ b/arch/arm64/kernel/pci.c
148 @@ -17,6 +17,8 @@
149 #include <linux/mm.h>
150 #include <linux/of_pci.h>
151 #include <linux/of_platform.h>
152 +#include <linux/of_irq.h>
153 +#include <linux/pcieport_if.h>
154 #include <linux/pci.h>
155 #include <linux/pci-acpi.h>
156 #include <linux/pci-ecam.h>
157 @@ -36,6 +38,47 @@ int pcibios_alloc_irq(struct pci_dev *de
158 #endif
159
160 /*
161 + * Check device tree if the service interrupts are there
162 + */
163 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
164 +{
165 + int ret, count = 0;
166 + struct device_node *np = NULL;
167 +
168 + if (dev->bus->dev.of_node)
169 + np = dev->bus->dev.of_node;
170 +
171 + if (np == NULL)
172 + return 0;
173 +
174 + if (!IS_ENABLED(CONFIG_OF_IRQ))
175 + return 0;
176 +
177 + /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
178 + * request irq for aer
179 + */
180 + if (mask & PCIE_PORT_SERVICE_AER) {
181 + ret = of_irq_get_byname(np, "aer");
182 + if (ret > 0) {
183 + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
184 + count++;
185 + }
186 + }
187 +
188 + if (mask & PCIE_PORT_SERVICE_PME) {
189 + ret = of_irq_get_byname(np, "pme");
190 + if (ret > 0) {
191 + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
192 + count++;
193 + }
194 + }
195 +
196 + /* TODO: add more service interrupts if there it is in the device tree*/
197 +
198 + return count;
199 +}
200 +
201 +/*
202 * raw_pci_read/write - Platform-specific PCI config space access.
203 */
204 int raw_pci_read(unsigned int domain, unsigned int bus,
205 --- a/drivers/misc/pci_endpoint_test.c
206 +++ b/drivers/misc/pci_endpoint_test.c
207 @@ -35,38 +35,45 @@
208
209 #include <uapi/linux/pcitest.h>
210
211 -#define DRV_MODULE_NAME "pci-endpoint-test"
212 +#define DRV_MODULE_NAME "pci-endpoint-test"
213
214 -#define PCI_ENDPOINT_TEST_MAGIC 0x0
215 +#define IRQ_TYPE_UNDEFINED -1
216 +#define IRQ_TYPE_LEGACY 0
217 +#define IRQ_TYPE_MSI 1
218 +#define IRQ_TYPE_MSIX 2
219 +
220 +#define PCI_ENDPOINT_TEST_MAGIC 0x0
221 +
222 +#define PCI_ENDPOINT_TEST_COMMAND 0x4
223 +#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
224 +#define COMMAND_RAISE_MSI_IRQ BIT(1)
225 +#define COMMAND_RAISE_MSIX_IRQ BIT(2)
226 +#define COMMAND_READ BIT(3)
227 +#define COMMAND_WRITE BIT(4)
228 +#define COMMAND_COPY BIT(5)
229 +
230 +#define PCI_ENDPOINT_TEST_STATUS 0x8
231 +#define STATUS_READ_SUCCESS BIT(0)
232 +#define STATUS_READ_FAIL BIT(1)
233 +#define STATUS_WRITE_SUCCESS BIT(2)
234 +#define STATUS_WRITE_FAIL BIT(3)
235 +#define STATUS_COPY_SUCCESS BIT(4)
236 +#define STATUS_COPY_FAIL BIT(5)
237 +#define STATUS_IRQ_RAISED BIT(6)
238 +#define STATUS_SRC_ADDR_INVALID BIT(7)
239 +#define STATUS_DST_ADDR_INVALID BIT(8)
240
241 -#define PCI_ENDPOINT_TEST_COMMAND 0x4
242 -#define COMMAND_RAISE_LEGACY_IRQ BIT(0)
243 -#define COMMAND_RAISE_MSI_IRQ BIT(1)
244 -#define MSI_NUMBER_SHIFT 2
245 -/* 6 bits for MSI number */
246 -#define COMMAND_READ BIT(8)
247 -#define COMMAND_WRITE BIT(9)
248 -#define COMMAND_COPY BIT(10)
249 -
250 -#define PCI_ENDPOINT_TEST_STATUS 0x8
251 -#define STATUS_READ_SUCCESS BIT(0)
252 -#define STATUS_READ_FAIL BIT(1)
253 -#define STATUS_WRITE_SUCCESS BIT(2)
254 -#define STATUS_WRITE_FAIL BIT(3)
255 -#define STATUS_COPY_SUCCESS BIT(4)
256 -#define STATUS_COPY_FAIL BIT(5)
257 -#define STATUS_IRQ_RAISED BIT(6)
258 -#define STATUS_SRC_ADDR_INVALID BIT(7)
259 -#define STATUS_DST_ADDR_INVALID BIT(8)
260 -
261 -#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0xc
262 +#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
263 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
264
265 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
266 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
267
268 -#define PCI_ENDPOINT_TEST_SIZE 0x1c
269 -#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
270 +#define PCI_ENDPOINT_TEST_SIZE 0x1c
271 +#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
272 +
273 +#define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
274 +#define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
275
276 static DEFINE_IDA(pci_endpoint_test_ida);
277
278 @@ -77,6 +84,10 @@ static bool no_msi;
279 module_param(no_msi, bool, 0444);
280 MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
281
282 +static int irq_type = IRQ_TYPE_MSI;
283 +module_param(irq_type, int, 0444);
284 +MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
285 +
286 enum pci_barno {
287 BAR_0,
288 BAR_1,
289 @@ -92,6 +103,7 @@ struct pci_endpoint_test {
290 void __iomem *bar[6];
291 struct completion irq_raised;
292 int last_irq;
293 + int num_irqs;
294 /* mutex to protect the ioctls */
295 struct mutex mutex;
296 struct miscdevice miscdev;
297 @@ -102,7 +114,7 @@ struct pci_endpoint_test {
298 struct pci_endpoint_test_data {
299 enum pci_barno test_reg_bar;
300 size_t alignment;
301 - bool no_msi;
302 + int irq_type;
303 };
304
305 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
306 @@ -146,6 +158,100 @@ static irqreturn_t pci_endpoint_test_irq
307 return IRQ_HANDLED;
308 }
309
310 +static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
311 +{
312 + struct pci_dev *pdev = test->pdev;
313 +
314 + pci_free_irq_vectors(pdev);
315 +}
316 +
317 +static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
318 + int type)
319 +{
320 + int irq = -1;
321 + struct pci_dev *pdev = test->pdev;
322 + struct device *dev = &pdev->dev;
323 + bool res = true;
324 +
325 + switch (type) {
326 + case IRQ_TYPE_LEGACY:
327 + irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
328 + if (irq < 0)
329 + dev_err(dev, "Failed to get Legacy interrupt\n");
330 + break;
331 + case IRQ_TYPE_MSI:
332 + irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
333 + if (irq < 0)
334 + dev_err(dev, "Failed to get MSI interrupts\n");
335 + break;
336 + case IRQ_TYPE_MSIX:
337 + irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
338 + if (irq < 0)
339 + dev_err(dev, "Failed to get MSI-X interrupts\n");
340 + break;
341 + default:
342 + dev_err(dev, "Invalid IRQ type selected\n");
343 + }
344 +
345 + if (irq < 0) {
346 + irq = 0;
347 + res = false;
348 + }
349 + test->num_irqs = irq;
350 +
351 + return res;
352 +}
353 +
354 +static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
355 +{
356 + int i;
357 + struct pci_dev *pdev = test->pdev;
358 + struct device *dev = &pdev->dev;
359 +
360 + for (i = 0; i < test->num_irqs; i++)
361 + devm_free_irq(dev, pci_irq_vector(pdev, i), test);
362 +
363 + test->num_irqs = 0;
364 +}
365 +
366 +static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
367 +{
368 + int i;
369 + int err;
370 + struct pci_dev *pdev = test->pdev;
371 + struct device *dev = &pdev->dev;
372 +
373 + for (i = 0; i < test->num_irqs; i++) {
374 + err = devm_request_irq(dev, pci_irq_vector(pdev, i),
375 + pci_endpoint_test_irqhandler,
376 + IRQF_SHARED, DRV_MODULE_NAME, test);
377 + if (err)
378 + goto fail;
379 + }
380 +
381 + return true;
382 +
383 +fail:
384 + switch (irq_type) {
385 + case IRQ_TYPE_LEGACY:
386 + dev_err(dev, "Failed to request IRQ %d for Legacy\n",
387 + pci_irq_vector(pdev, i));
388 + break;
389 + case IRQ_TYPE_MSI:
390 + dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
391 + pci_irq_vector(pdev, i),
392 + i + 1);
393 + break;
394 + case IRQ_TYPE_MSIX:
395 + dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
396 + pci_irq_vector(pdev, i),
397 + i + 1);
398 + break;
399 + }
400 +
401 + return false;
402 +}
403 +
404 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
405 enum pci_barno barno)
406 {
407 @@ -178,6 +284,9 @@ static bool pci_endpoint_test_legacy_irq
408 {
409 u32 val;
410
411 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
412 + IRQ_TYPE_LEGACY);
413 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
414 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
415 COMMAND_RAISE_LEGACY_IRQ);
416 val = wait_for_completion_timeout(&test->irq_raised,
417 @@ -189,20 +298,24 @@ static bool pci_endpoint_test_legacy_irq
418 }
419
420 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
421 - u8 msi_num)
422 + u16 msi_num, bool msix)
423 {
424 u32 val;
425 struct pci_dev *pdev = test->pdev;
426
427 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
428 + msix == false ? IRQ_TYPE_MSI :
429 + IRQ_TYPE_MSIX);
430 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
431 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
432 - msi_num << MSI_NUMBER_SHIFT |
433 - COMMAND_RAISE_MSI_IRQ);
434 + msix == false ? COMMAND_RAISE_MSI_IRQ :
435 + COMMAND_RAISE_MSIX_IRQ);
436 val = wait_for_completion_timeout(&test->irq_raised,
437 msecs_to_jiffies(1000));
438 if (!val)
439 return false;
440
441 - if (test->last_irq - pdev->irq == msi_num - 1)
442 + if (pci_irq_vector(pdev, msi_num - 1) == test->last_irq)
443 return true;
444
445 return false;
446 @@ -226,10 +339,18 @@ static bool pci_endpoint_test_copy(struc
447 u32 src_crc32;
448 u32 dst_crc32;
449
450 + if (size > SIZE_MAX - alignment)
451 + goto err;
452 +
453 + if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
454 + dev_err(dev, "Invalid IRQ type option\n");
455 + goto err;
456 + }
457 +
458 orig_src_addr = dma_alloc_coherent(dev, size + alignment,
459 &orig_src_phys_addr, GFP_KERNEL);
460 if (!orig_src_addr) {
461 - dev_err(dev, "failed to allocate source buffer\n");
462 + dev_err(dev, "Failed to allocate source buffer\n");
463 ret = false;
464 goto err;
465 }
466 @@ -255,7 +376,7 @@ static bool pci_endpoint_test_copy(struc
467 orig_dst_addr = dma_alloc_coherent(dev, size + alignment,
468 &orig_dst_phys_addr, GFP_KERNEL);
469 if (!orig_dst_addr) {
470 - dev_err(dev, "failed to allocate destination address\n");
471 + dev_err(dev, "Failed to allocate destination address\n");
472 ret = false;
473 goto err_orig_src_addr;
474 }
475 @@ -277,8 +398,10 @@ static bool pci_endpoint_test_copy(struc
476 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
477 size);
478
479 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
480 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
481 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
482 - 1 << MSI_NUMBER_SHIFT | COMMAND_COPY);
483 + COMMAND_COPY);
484
485 wait_for_completion(&test->irq_raised);
486
487 @@ -311,10 +434,18 @@ static bool pci_endpoint_test_write(stru
488 size_t alignment = test->alignment;
489 u32 crc32;
490
491 + if (size > SIZE_MAX - alignment)
492 + goto err;
493 +
494 + if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
495 + dev_err(dev, "Invalid IRQ type option\n");
496 + goto err;
497 + }
498 +
499 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
500 GFP_KERNEL);
501 if (!orig_addr) {
502 - dev_err(dev, "failed to allocate address\n");
503 + dev_err(dev, "Failed to allocate address\n");
504 ret = false;
505 goto err;
506 }
507 @@ -341,8 +472,10 @@ static bool pci_endpoint_test_write(stru
508
509 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
510
511 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
512 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
513 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
514 - 1 << MSI_NUMBER_SHIFT | COMMAND_READ);
515 + COMMAND_READ);
516
517 wait_for_completion(&test->irq_raised);
518
519 @@ -369,10 +502,18 @@ static bool pci_endpoint_test_read(struc
520 size_t alignment = test->alignment;
521 u32 crc32;
522
523 + if (size > SIZE_MAX - alignment)
524 + goto err;
525 +
526 + if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
527 + dev_err(dev, "Invalid IRQ type option\n");
528 + goto err;
529 + }
530 +
531 orig_addr = dma_alloc_coherent(dev, size + alignment, &orig_phys_addr,
532 GFP_KERNEL);
533 if (!orig_addr) {
534 - dev_err(dev, "failed to allocate destination address\n");
535 + dev_err(dev, "Failed to allocate destination address\n");
536 ret = false;
537 goto err;
538 }
539 @@ -393,8 +534,10 @@ static bool pci_endpoint_test_read(struc
540
541 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
542
543 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
544 + pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
545 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
546 - 1 << MSI_NUMBER_SHIFT | COMMAND_WRITE);
547 + COMMAND_WRITE);
548
549 wait_for_completion(&test->irq_raised);
550
551 @@ -407,6 +550,38 @@ err:
552 return ret;
553 }
554
555 +static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
556 + int req_irq_type)
557 +{
558 + struct pci_dev *pdev = test->pdev;
559 + struct device *dev = &pdev->dev;
560 +
561 + if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
562 + dev_err(dev, "Invalid IRQ type option\n");
563 + return false;
564 + }
565 +
566 + if (irq_type == req_irq_type)
567 + return true;
568 +
569 + pci_endpoint_test_release_irq(test);
570 + pci_endpoint_test_free_irq_vectors(test);
571 +
572 + if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
573 + goto err;
574 +
575 + if (!pci_endpoint_test_request_irq(test))
576 + goto err;
577 +
578 + irq_type = req_irq_type;
579 + return true;
580 +
581 +err:
582 + pci_endpoint_test_free_irq_vectors(test);
583 + irq_type = IRQ_TYPE_UNDEFINED;
584 + return false;
585 +}
586 +
587 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
588 unsigned long arg)
589 {
590 @@ -426,7 +601,8 @@ static long pci_endpoint_test_ioctl(stru
591 ret = pci_endpoint_test_legacy_irq(test);
592 break;
593 case PCITEST_MSI:
594 - ret = pci_endpoint_test_msi_irq(test, arg);
595 + case PCITEST_MSIX:
596 + ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
597 break;
598 case PCITEST_WRITE:
599 ret = pci_endpoint_test_write(test, arg);
600 @@ -437,6 +613,12 @@ static long pci_endpoint_test_ioctl(stru
601 case PCITEST_COPY:
602 ret = pci_endpoint_test_copy(test, arg);
603 break;
604 + case PCITEST_SET_IRQTYPE:
605 + ret = pci_endpoint_test_set_irq(test, arg);
606 + break;
607 + case PCITEST_GET_IRQTYPE:
608 + ret = irq_type;
609 + break;
610 }
611
612 ret:
613 @@ -452,9 +634,7 @@ static const struct file_operations pci_
614 static int pci_endpoint_test_probe(struct pci_dev *pdev,
615 const struct pci_device_id *ent)
616 {
617 - int i;
618 int err;
619 - int irq = 0;
620 int id;
621 char name[20];
622 enum pci_barno bar;
623 @@ -476,12 +656,15 @@ static int pci_endpoint_test_probe(struc
624 test->alignment = 0;
625 test->pdev = pdev;
626
627 + if (no_msi)
628 + irq_type = IRQ_TYPE_LEGACY;
629 +
630 data = (struct pci_endpoint_test_data *)ent->driver_data;
631 if (data) {
632 test_reg_bar = data->test_reg_bar;
633 test->test_reg_bar = test_reg_bar;
634 test->alignment = data->alignment;
635 - no_msi = data->no_msi;
636 + irq_type = data->irq_type;
637 }
638
639 init_completion(&test->irq_raised);
640 @@ -501,35 +684,21 @@ static int pci_endpoint_test_probe(struc
641
642 pci_set_master(pdev);
643
644 - if (!no_msi) {
645 - irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
646 - if (irq < 0)
647 - dev_err(dev, "failed to get MSI interrupts\n");
648 - }
649 + if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type))
650 + goto err_disable_irq;
651
652 - err = devm_request_irq(dev, pdev->irq, pci_endpoint_test_irqhandler,
653 - IRQF_SHARED, DRV_MODULE_NAME, test);
654 - if (err) {
655 - dev_err(dev, "failed to request IRQ %d\n", pdev->irq);
656 - goto err_disable_msi;
657 - }
658 -
659 - for (i = 1; i < irq; i++) {
660 - err = devm_request_irq(dev, pdev->irq + i,
661 - pci_endpoint_test_irqhandler,
662 - IRQF_SHARED, DRV_MODULE_NAME, test);
663 - if (err)
664 - dev_err(dev, "failed to request IRQ %d for MSI %d\n",
665 - pdev->irq + i, i + 1);
666 - }
667 + if (!pci_endpoint_test_request_irq(test))
668 + goto err_disable_irq;
669
670 for (bar = BAR_0; bar <= BAR_5; bar++) {
671 - base = pci_ioremap_bar(pdev, bar);
672 - if (!base) {
673 - dev_err(dev, "failed to read BAR%d\n", bar);
674 - WARN_ON(bar == test_reg_bar);
675 + if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
676 + base = pci_ioremap_bar(pdev, bar);
677 + if (!base) {
678 + dev_err(dev, "Failed to read BAR%d\n", bar);
679 + WARN_ON(bar == test_reg_bar);
680 + }
681 + test->bar[bar] = base;
682 }
683 - test->bar[bar] = base;
684 }
685
686 test->base = test->bar[test_reg_bar];
687 @@ -545,24 +714,31 @@ static int pci_endpoint_test_probe(struc
688 id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
689 if (id < 0) {
690 err = id;
691 - dev_err(dev, "unable to get id\n");
692 + dev_err(dev, "Unable to get id\n");
693 goto err_iounmap;
694 }
695
696 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
697 misc_device = &test->miscdev;
698 misc_device->minor = MISC_DYNAMIC_MINOR;
699 - misc_device->name = name;
700 + misc_device->name = kstrdup(name, GFP_KERNEL);
701 + if (!misc_device->name) {
702 + err = -ENOMEM;
703 + goto err_ida_remove;
704 + }
705 misc_device->fops = &pci_endpoint_test_fops,
706
707 err = misc_register(misc_device);
708 if (err) {
709 - dev_err(dev, "failed to register device\n");
710 - goto err_ida_remove;
711 + dev_err(dev, "Failed to register device\n");
712 + goto err_kfree_name;
713 }
714
715 return 0;
716
717 +err_kfree_name:
718 + kfree(misc_device->name);
719 +
720 err_ida_remove:
721 ida_simple_remove(&pci_endpoint_test_ida, id);
722
723 @@ -571,9 +747,10 @@ err_iounmap:
724 if (test->bar[bar])
725 pci_iounmap(pdev, test->bar[bar]);
726 }
727 + pci_endpoint_test_release_irq(test);
728
729 -err_disable_msi:
730 - pci_disable_msi(pdev);
731 +err_disable_irq:
732 + pci_endpoint_test_free_irq_vectors(test);
733 pci_release_regions(pdev);
734
735 err_disable_pdev:
736 @@ -595,12 +772,16 @@ static void pci_endpoint_test_remove(str
737 return;
738
739 misc_deregister(&test->miscdev);
740 + kfree(misc_device->name);
741 ida_simple_remove(&pci_endpoint_test_ida, id);
742 for (bar = BAR_0; bar <= BAR_5; bar++) {
743 if (test->bar[bar])
744 pci_iounmap(pdev, test->bar[bar]);
745 }
746 - pci_disable_msi(pdev);
747 +
748 + pci_endpoint_test_release_irq(test);
749 + pci_endpoint_test_free_irq_vectors(test);
750 +
751 pci_release_regions(pdev);
752 pci_disable_device(pdev);
753 }
754 @@ -608,6 +789,7 @@ static void pci_endpoint_test_remove(str
755 static const struct pci_device_id pci_endpoint_test_tbl[] = {
756 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
757 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
758 + { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID) },
759 { }
760 };
761 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
762 --- a/drivers/pci/Kconfig
763 +++ b/drivers/pci/Kconfig
764 @@ -142,6 +142,7 @@ config PCI_HYPERV
765
766 source "drivers/pci/hotplug/Kconfig"
767 source "drivers/pci/dwc/Kconfig"
768 +source "drivers/pci/mobiveil/Kconfig"
769 source "drivers/pci/host/Kconfig"
770 source "drivers/pci/endpoint/Kconfig"
771 source "drivers/pci/switch/Kconfig"
772 --- a/drivers/pci/dwc/Kconfig
773 +++ b/drivers/pci/dwc/Kconfig
774 @@ -50,17 +50,36 @@ config PCI_DRA7XX_EP
775 endif
776
777 config PCIE_DW_PLAT
778 - bool "Platform bus based DesignWare PCIe Controller"
779 - depends on PCI
780 - depends on PCI_MSI_IRQ_DOMAIN
781 - select PCIE_DW_HOST
782 - ---help---
783 - This selects the DesignWare PCIe controller support. Select this if
784 - you have a PCIe controller on Platform bus.
785 + bool
786
787 - If you have a controller with this interface, say Y or M here.
788 +config PCIE_DW_PLAT_HOST
789 + bool "Platform bus based DesignWare PCIe Controller - Host mode"
790 + depends on PCI && PCI_MSI_IRQ_DOMAIN
791 + select PCIE_DW_HOST
792 + select PCIE_DW_PLAT
793 + help
794 + Enables support for the PCIe controller in the Designware IP to
795 + work in host mode. There are two instances of PCIe controller in
796 + Designware IP.
797 + This controller can work either as EP or RC. In order to enable
798 + host-specific features PCIE_DW_PLAT_HOST must be selected and in
799 + order to enable device-specific features PCI_DW_PLAT_EP must be
800 + selected.
801
802 - If unsure, say N.
803 +config PCIE_DW_PLAT_EP
804 + bool "Platform bus based DesignWare PCIe Controller - Endpoint mode"
805 + depends on PCI && PCI_MSI_IRQ_DOMAIN
806 + depends on PCI_ENDPOINT
807 + select PCIE_DW_EP
808 + select PCIE_DW_PLAT
809 + help
810 + Enables support for the PCIe controller in the Designware IP to
811 + work in endpoint mode. There are two instances of PCIe controller
812 + in Designware IP.
813 + This controller can work either as EP or RC. In order to enable
814 + host-specific features PCIE_DW_PLAT_HOST must be selected and in
815 + order to enable device-specific features PCI_DW_PLAT_EP must be
816 + selected.
817
818 config PCI_EXYNOS
819 bool "Samsung Exynos PCIe controller"
820 --- a/drivers/pci/dwc/Makefile
821 +++ b/drivers/pci/dwc/Makefile
822 @@ -10,7 +10,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
823 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
824 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
825 obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone-dw.o pci-keystone.o
826 -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
827 +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
828 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
829 obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
830 obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
831 --- a/drivers/pci/dwc/pci-dra7xx.c
832 +++ b/drivers/pci/dwc/pci-dra7xx.c
833 @@ -339,15 +339,6 @@ static irqreturn_t dra7xx_pcie_irq_handl
834 return IRQ_HANDLED;
835 }
836
837 -static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
838 -{
839 - u32 reg;
840 -
841 - reg = PCI_BASE_ADDRESS_0 + (4 * bar);
842 - dw_pcie_writel_dbi2(pci, reg, 0x0);
843 - dw_pcie_writel_dbi(pci, reg, 0x0);
844 -}
845 -
846 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
847 {
848 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
849 --- /dev/null
850 +++ b/drivers/pci/dwc/pci-layerscape-ep.c
851 @@ -0,0 +1,146 @@
852 +// SPDX-License-Identifier: GPL-2.0
853 +/*
854 + * PCIe controller EP driver for Freescale Layerscape SoCs
855 + *
856 + * Copyright (C) 2018 NXP Semiconductor.
857 + *
858 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
859 + */
860 +
861 +#include <linux/kernel.h>
862 +#include <linux/init.h>
863 +#include <linux/of_pci.h>
864 +#include <linux/of_platform.h>
865 +#include <linux/of_address.h>
866 +#include <linux/pci.h>
867 +#include <linux/platform_device.h>
868 +#include <linux/resource.h>
869 +
870 +#include "pcie-designware.h"
871 +
872 +#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
873 +
874 +struct ls_pcie_ep {
875 + struct dw_pcie *pci;
876 +};
877 +
878 +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
879 +
880 +static int ls_pcie_establish_link(struct dw_pcie *pci)
881 +{
882 + return 0;
883 +}
884 +
885 +static const struct dw_pcie_ops ls_pcie_ep_ops = {
886 + .start_link = ls_pcie_establish_link,
887 +};
888 +
889 +static const struct of_device_id ls_pcie_ep_of_match[] = {
890 + { .compatible = "fsl,ls-pcie-ep",},
891 + { },
892 +};
893 +
894 +static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
895 +{
896 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
897 + struct pci_epc *epc = ep->epc;
898 + enum pci_barno bar;
899 +
900 + for (bar = BAR_0; bar <= BAR_5; bar++)
901 + dw_pcie_ep_reset_bar(pci, bar);
902 +
903 + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
904 +}
905 +
906 +static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
907 + enum pci_epc_irq_type type, u16 interrupt_num)
908 +{
909 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
910 +
911 + switch (type) {
912 + case PCI_EPC_IRQ_LEGACY:
913 + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
914 + case PCI_EPC_IRQ_MSI:
915 + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
916 + case PCI_EPC_IRQ_MSIX:
917 + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
918 + default:
919 + dev_err(pci->dev, "UNKNOWN IRQ type\n");
920 + return -EINVAL;
921 + }
922 +}
923 +
924 +static struct dw_pcie_ep_ops pcie_ep_ops = {
925 + .ep_init = ls_pcie_ep_init,
926 + .raise_irq = ls_pcie_ep_raise_irq,
927 +};
928 +
929 +static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
930 + struct platform_device *pdev)
931 +{
932 + struct dw_pcie *pci = pcie->pci;
933 + struct device *dev = pci->dev;
934 + struct dw_pcie_ep *ep;
935 + struct resource *res;
936 + int ret;
937 +
938 + ep = &pci->ep;
939 + ep->ops = &pcie_ep_ops;
940 +
941 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
942 + if (!res)
943 + return -EINVAL;
944 +
945 + ep->phys_base = res->start;
946 + ep->addr_size = resource_size(res);
947 +
948 + ret = dw_pcie_ep_init(ep);
949 + if (ret) {
950 + dev_err(dev, "failed to initialize endpoint\n");
951 + return ret;
952 + }
953 +
954 + return 0;
955 +}
956 +
957 +static int __init ls_pcie_ep_probe(struct platform_device *pdev)
958 +{
959 + struct device *dev = &pdev->dev;
960 + struct dw_pcie *pci;
961 + struct ls_pcie_ep *pcie;
962 + struct resource *dbi_base;
963 + int ret;
964 +
965 + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
966 + if (!pcie)
967 + return -ENOMEM;
968 +
969 + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
970 + if (!pci)
971 + return -ENOMEM;
972 +
973 + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
974 + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
975 + if (IS_ERR(pci->dbi_base))
976 + return PTR_ERR(pci->dbi_base);
977 +
978 + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
979 + pci->dev = dev;
980 + pci->ops = &ls_pcie_ep_ops;
981 + pcie->pci = pci;
982 +
983 + platform_set_drvdata(pdev, pcie);
984 +
985 + ret = ls_add_pcie_ep(pcie, pdev);
986 +
987 + return ret;
988 +}
989 +
990 +static struct platform_driver ls_pcie_ep_driver = {
991 + .driver = {
992 + .name = "layerscape-pcie-ep",
993 + .of_match_table = ls_pcie_ep_of_match,
994 + .suppress_bind_attrs = true,
995 + },
996 +};
997 +builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
998 --- a/drivers/pci/dwc/pci-layerscape.c
999 +++ b/drivers/pci/dwc/pci-layerscape.c
1000 @@ -33,6 +33,8 @@
1001
1002 /* PEX Internal Configuration Registers */
1003 #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
1004 +#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
1005 +#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
1006
1007 #define PCIE_IATU_NUM 6
1008
1009 @@ -124,6 +126,14 @@ static int ls_pcie_link_up(struct dw_pci
1010 return 1;
1011 }
1012
1013 +/* Forward error response of outbound non-posted requests */
1014 +static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
1015 +{
1016 + struct dw_pcie *pci = pcie->pci;
1017 +
1018 + iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
1019 +}
1020 +
1021 static int ls_pcie_host_init(struct pcie_port *pp)
1022 {
1023 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1024 @@ -135,6 +145,7 @@ static int ls_pcie_host_init(struct pcie
1025 * dw_pcie_setup_rc() will reconfigure the outbound windows.
1026 */
1027 ls_pcie_disable_outbound_atus(pcie);
1028 + ls_pcie_fix_error_response(pcie);
1029
1030 dw_pcie_dbi_ro_wr_en(pci);
1031 ls_pcie_clear_multifunction(pcie);
1032 @@ -253,6 +264,7 @@ static struct ls_pcie_drvdata ls2088_drv
1033 };
1034
1035 static const struct of_device_id ls_pcie_of_match[] = {
1036 + { .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
1037 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
1038 { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1039 { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1040 --- a/drivers/pci/dwc/pcie-designware-ep.c
1041 +++ b/drivers/pci/dwc/pcie-designware-ep.c
1042 @@ -1,20 +1,9 @@
1043 +// SPDX-License-Identifier: GPL-2.0
1044 /**
1045 * Synopsys DesignWare PCIe Endpoint controller driver
1046 *
1047 * Copyright (C) 2017 Texas Instruments
1048 * Author: Kishon Vijay Abraham I <kishon@ti.com>
1049 - *
1050 - * This program is free software: you can redistribute it and/or modify
1051 - * it under the terms of the GNU General Public License version 2 of
1052 - * the License as published by the Free Software Foundation.
1053 - *
1054 - * This program is distributed in the hope that it will be useful,
1055 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1056 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1057 - * GNU General Public License for more details.
1058 - *
1059 - * You should have received a copy of the GNU General Public License
1060 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1061 */
1062
1063 #include <linux/of.h>
1064 @@ -30,7 +19,8 @@ void dw_pcie_ep_linkup(struct dw_pcie_ep
1065 pci_epc_linkup(epc);
1066 }
1067
1068 -static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
1069 +static void __dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar,
1070 + int flags)
1071 {
1072 u32 reg;
1073
1074 @@ -38,10 +28,52 @@ static void dw_pcie_ep_reset_bar(struct
1075 dw_pcie_dbi_ro_wr_en(pci);
1076 dw_pcie_writel_dbi2(pci, reg, 0x0);
1077 dw_pcie_writel_dbi(pci, reg, 0x0);
1078 + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1079 + dw_pcie_writel_dbi2(pci, reg + 4, 0x0);
1080 + dw_pcie_writel_dbi(pci, reg + 4, 0x0);
1081 + }
1082 dw_pcie_dbi_ro_wr_dis(pci);
1083 }
1084
1085 -static int dw_pcie_ep_write_header(struct pci_epc *epc,
1086 +void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
1087 +{
1088 + __dw_pcie_ep_reset_bar(pci, bar, 0);
1089 +}
1090 +
1091 +static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
1092 + u8 cap)
1093 +{
1094 + u8 cap_id, next_cap_ptr;
1095 + u16 reg;
1096 +
1097 + reg = dw_pcie_readw_dbi(pci, cap_ptr);
1098 + next_cap_ptr = (reg & 0xff00) >> 8;
1099 + cap_id = (reg & 0x00ff);
1100 +
1101 + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
1102 + return 0;
1103 +
1104 + if (cap_id == cap)
1105 + return cap_ptr;
1106 +
1107 + return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
1108 +}
1109 +
1110 +static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap)
1111 +{
1112 + u8 next_cap_ptr;
1113 + u16 reg;
1114 +
1115 + reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
1116 + next_cap_ptr = (reg & 0x00ff);
1117 +
1118 + if (!next_cap_ptr)
1119 + return 0;
1120 +
1121 + return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
1122 +}
1123 +
1124 +static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
1125 struct pci_epf_header *hdr)
1126 {
1127 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1128 @@ -114,24 +146,29 @@ static int dw_pcie_ep_outbound_atu(struc
1129 return 0;
1130 }
1131
1132 -static void dw_pcie_ep_clear_bar(struct pci_epc *epc, enum pci_barno bar)
1133 +static void dw_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
1134 + struct pci_epf_bar *epf_bar)
1135 {
1136 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1137 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1138 + enum pci_barno bar = epf_bar->barno;
1139 u32 atu_index = ep->bar_to_atu[bar];
1140
1141 - dw_pcie_ep_reset_bar(pci, bar);
1142 + __dw_pcie_ep_reset_bar(pci, bar, epf_bar->flags);
1143
1144 dw_pcie_disable_atu(pci, atu_index, DW_PCIE_REGION_INBOUND);
1145 clear_bit(atu_index, ep->ib_window_map);
1146 }
1147
1148 -static int dw_pcie_ep_set_bar(struct pci_epc *epc, enum pci_barno bar,
1149 - dma_addr_t bar_phys, size_t size, int flags)
1150 +static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
1151 + struct pci_epf_bar *epf_bar)
1152 {
1153 int ret;
1154 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1155 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1156 + enum pci_barno bar = epf_bar->barno;
1157 + size_t size = epf_bar->size;
1158 + int flags = epf_bar->flags;
1159 enum dw_pcie_as_type as_type;
1160 u32 reg = PCI_BASE_ADDRESS_0 + (4 * bar);
1161
1162 @@ -140,13 +177,20 @@ static int dw_pcie_ep_set_bar(struct pci
1163 else
1164 as_type = DW_PCIE_AS_IO;
1165
1166 - ret = dw_pcie_ep_inbound_atu(ep, bar, bar_phys, as_type);
1167 + ret = dw_pcie_ep_inbound_atu(ep, bar, epf_bar->phys_addr, as_type);
1168 if (ret)
1169 return ret;
1170
1171 dw_pcie_dbi_ro_wr_en(pci);
1172 - dw_pcie_writel_dbi2(pci, reg, size - 1);
1173 +
1174 + dw_pcie_writel_dbi2(pci, reg, lower_32_bits(size - 1));
1175 dw_pcie_writel_dbi(pci, reg, flags);
1176 +
1177 + if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) {
1178 + dw_pcie_writel_dbi2(pci, reg + 4, upper_32_bits(size - 1));
1179 + dw_pcie_writel_dbi(pci, reg + 4, 0);
1180 + }
1181 +
1182 dw_pcie_dbi_ro_wr_dis(pci);
1183
1184 return 0;
1185 @@ -167,7 +211,8 @@ static int dw_pcie_find_index(struct dw_
1186 return -EINVAL;
1187 }
1188
1189 -static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, phys_addr_t addr)
1190 +static void dw_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
1191 + phys_addr_t addr)
1192 {
1193 int ret;
1194 u32 atu_index;
1195 @@ -182,8 +227,9 @@ static void dw_pcie_ep_unmap_addr(struct
1196 clear_bit(atu_index, ep->ob_window_map);
1197 }
1198
1199 -static int dw_pcie_ep_map_addr(struct pci_epc *epc, phys_addr_t addr,
1200 - u64 pci_addr, size_t size)
1201 +static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
1202 + phys_addr_t addr,
1203 + u64 pci_addr, size_t size)
1204 {
1205 int ret;
1206 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1207 @@ -198,45 +244,93 @@ static int dw_pcie_ep_map_addr(struct pc
1208 return 0;
1209 }
1210
1211 -static int dw_pcie_ep_get_msi(struct pci_epc *epc)
1212 +static int dw_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
1213 +{
1214 + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1215 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1216 + u32 val, reg;
1217 +
1218 + if (!ep->msi_cap)
1219 + return -EINVAL;
1220 +
1221 + reg = ep->msi_cap + PCI_MSI_FLAGS;
1222 + val = dw_pcie_readw_dbi(pci, reg);
1223 + if (!(val & PCI_MSI_FLAGS_ENABLE))
1224 + return -EINVAL;
1225 +
1226 + val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
1227 +
1228 + return val;
1229 +}
1230 +
1231 +static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
1232 +{
1233 + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1234 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1235 + u32 val, reg;
1236 +
1237 + if (!ep->msi_cap)
1238 + return -EINVAL;
1239 +
1240 + reg = ep->msi_cap + PCI_MSI_FLAGS;
1241 + val = dw_pcie_readw_dbi(pci, reg);
1242 + val &= ~PCI_MSI_FLAGS_QMASK;
1243 + val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
1244 + dw_pcie_dbi_ro_wr_en(pci);
1245 + dw_pcie_writew_dbi(pci, reg, val);
1246 + dw_pcie_dbi_ro_wr_dis(pci);
1247 +
1248 + return 0;
1249 +}
1250 +
1251 +static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
1252 {
1253 - int val;
1254 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1255 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1256 + u32 val, reg;
1257 +
1258 + if (!ep->msix_cap)
1259 + return -EINVAL;
1260
1261 - val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
1262 - if (!(val & MSI_CAP_MSI_EN_MASK))
1263 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
1264 + val = dw_pcie_readw_dbi(pci, reg);
1265 + if (!(val & PCI_MSIX_FLAGS_ENABLE))
1266 return -EINVAL;
1267
1268 - val = (val & MSI_CAP_MME_MASK) >> MSI_CAP_MME_SHIFT;
1269 + val &= PCI_MSIX_FLAGS_QSIZE;
1270 +
1271 return val;
1272 }
1273
1274 -static int dw_pcie_ep_set_msi(struct pci_epc *epc, u8 encode_int)
1275 +static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
1276 {
1277 - int val;
1278 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1279 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1280 + u32 val, reg;
1281
1282 - val = dw_pcie_readw_dbi(pci, MSI_MESSAGE_CONTROL);
1283 - val &= ~MSI_CAP_MMC_MASK;
1284 - val |= (encode_int << MSI_CAP_MMC_SHIFT) & MSI_CAP_MMC_MASK;
1285 + if (!ep->msix_cap)
1286 + return -EINVAL;
1287 +
1288 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
1289 + val = dw_pcie_readw_dbi(pci, reg);
1290 + val &= ~PCI_MSIX_FLAGS_QSIZE;
1291 + val |= interrupts;
1292 dw_pcie_dbi_ro_wr_en(pci);
1293 - dw_pcie_writew_dbi(pci, MSI_MESSAGE_CONTROL, val);
1294 + dw_pcie_writew_dbi(pci, reg, val);
1295 dw_pcie_dbi_ro_wr_dis(pci);
1296
1297 return 0;
1298 }
1299
1300 -static int dw_pcie_ep_raise_irq(struct pci_epc *epc,
1301 - enum pci_epc_irq_type type, u8 interrupt_num)
1302 +static int dw_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
1303 + enum pci_epc_irq_type type, u16 interrupt_num)
1304 {
1305 struct dw_pcie_ep *ep = epc_get_drvdata(epc);
1306
1307 if (!ep->ops->raise_irq)
1308 return -EINVAL;
1309
1310 - return ep->ops->raise_irq(ep, type, interrupt_num);
1311 + return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
1312 }
1313
1314 static void dw_pcie_ep_stop(struct pci_epc *epc)
1315 @@ -269,15 +363,130 @@ static const struct pci_epc_ops epc_ops
1316 .unmap_addr = dw_pcie_ep_unmap_addr,
1317 .set_msi = dw_pcie_ep_set_msi,
1318 .get_msi = dw_pcie_ep_get_msi,
1319 + .set_msix = dw_pcie_ep_set_msix,
1320 + .get_msix = dw_pcie_ep_get_msix,
1321 .raise_irq = dw_pcie_ep_raise_irq,
1322 .start = dw_pcie_ep_start,
1323 .stop = dw_pcie_ep_stop,
1324 };
1325
1326 +int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
1327 +{
1328 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1329 + struct device *dev = pci->dev;
1330 +
1331 + dev_err(dev, "EP cannot trigger legacy IRQs\n");
1332 +
1333 + return -EINVAL;
1334 +}
1335 +
1336 +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
1337 + u8 interrupt_num)
1338 +{
1339 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1340 + struct pci_epc *epc = ep->epc;
1341 + u16 msg_ctrl, msg_data;
1342 + u32 msg_addr_lower, msg_addr_upper, reg;
1343 + u64 msg_addr;
1344 + bool has_upper;
1345 + int ret;
1346 +
1347 + if (!ep->msi_cap)
1348 + return -EINVAL;
1349 +
1350 + /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
1351 + reg = ep->msi_cap + PCI_MSI_FLAGS;
1352 + msg_ctrl = dw_pcie_readw_dbi(pci, reg);
1353 + has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
1354 + reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
1355 + msg_addr_lower = dw_pcie_readl_dbi(pci, reg);
1356 + if (has_upper) {
1357 + reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
1358 + msg_addr_upper = dw_pcie_readl_dbi(pci, reg);
1359 + reg = ep->msi_cap + PCI_MSI_DATA_64;
1360 + msg_data = dw_pcie_readw_dbi(pci, reg);
1361 + } else {
1362 + msg_addr_upper = 0;
1363 + reg = ep->msi_cap + PCI_MSI_DATA_32;
1364 + msg_data = dw_pcie_readw_dbi(pci, reg);
1365 + }
1366 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
1367 + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
1368 + epc->mem->page_size);
1369 + if (ret)
1370 + return ret;
1371 +
1372 + writel(msg_data | (interrupt_num - 1), ep->msi_mem);
1373 +
1374 + dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
1375 +
1376 + return 0;
1377 +}
1378 +
1379 +int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
1380 + u16 interrupt_num)
1381 +{
1382 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1383 + struct pci_epc *epc = ep->epc;
1384 + u16 tbl_offset, bir;
1385 + u32 bar_addr_upper, bar_addr_lower;
1386 + u32 msg_addr_upper, msg_addr_lower;
1387 + u32 reg, msg_data, vec_ctrl;
1388 + u64 tbl_addr, msg_addr, reg_u64;
1389 + void __iomem *msix_tbl;
1390 + int ret;
1391 +
1392 + reg = ep->msix_cap + PCI_MSIX_TABLE;
1393 + tbl_offset = dw_pcie_readl_dbi(pci, reg);
1394 + bir = (tbl_offset & PCI_MSIX_TABLE_BIR);
1395 + tbl_offset &= PCI_MSIX_TABLE_OFFSET;
1396 +
1397 + reg = PCI_BASE_ADDRESS_0 + (4 * bir);
1398 + bar_addr_upper = 0;
1399 + bar_addr_lower = dw_pcie_readl_dbi(pci, reg);
1400 + reg_u64 = (bar_addr_lower & PCI_BASE_ADDRESS_MEM_TYPE_MASK);
1401 + if (reg_u64 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1402 + bar_addr_upper = dw_pcie_readl_dbi(pci, reg + 4);
1403 +
1404 + tbl_addr = ((u64) bar_addr_upper) << 32 | bar_addr_lower;
1405 + tbl_addr += (tbl_offset + ((interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE));
1406 + tbl_addr &= PCI_BASE_ADDRESS_MEM_MASK;
1407 +
1408 + msix_tbl = ioremap_nocache(ep->phys_base + tbl_addr,
1409 + PCI_MSIX_ENTRY_SIZE);
1410 + if (!msix_tbl)
1411 + return -EINVAL;
1412 +
1413 + msg_addr_lower = readl(msix_tbl + PCI_MSIX_ENTRY_LOWER_ADDR);
1414 + msg_addr_upper = readl(msix_tbl + PCI_MSIX_ENTRY_UPPER_ADDR);
1415 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
1416 + msg_data = readl(msix_tbl + PCI_MSIX_ENTRY_DATA);
1417 + vec_ctrl = readl(msix_tbl + PCI_MSIX_ENTRY_VECTOR_CTRL);
1418 +
1419 + iounmap(msix_tbl);
1420 +
1421 + if (vec_ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT)
1422 + return -EPERM;
1423 +
1424 + ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
1425 + epc->mem->page_size);
1426 + if (ret)
1427 + return ret;
1428 +
1429 + writel(msg_data, ep->msi_mem);
1430 +
1431 + dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
1432 +
1433 + return 0;
1434 +}
1435 +
1436 void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
1437 {
1438 struct pci_epc *epc = ep->epc;
1439
1440 + pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
1441 + epc->mem->page_size);
1442 +
1443 pci_epc_mem_exit(epc);
1444 }
1445
1446 @@ -291,7 +500,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
1447 struct device_node *np = dev->of_node;
1448
1449 if (!pci->dbi_base || !pci->dbi_base2) {
1450 - dev_err(dev, "dbi_base/deb_base2 is not populated\n");
1451 + dev_err(dev, "dbi_base/dbi_base2 is not populated\n");
1452 return -EINVAL;
1453 }
1454
1455 @@ -333,15 +542,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
1456 return -ENOMEM;
1457 ep->outbound_addr = addr;
1458
1459 - if (ep->ops->ep_init)
1460 - ep->ops->ep_init(ep);
1461 -
1462 epc = devm_pci_epc_create(dev, &epc_ops);
1463 if (IS_ERR(epc)) {
1464 dev_err(dev, "failed to create epc device\n");
1465 return PTR_ERR(epc);
1466 }
1467
1468 + ep->epc = epc;
1469 + epc_set_drvdata(epc, ep);
1470 +
1471 + if (ep->ops->ep_init)
1472 + ep->ops->ep_init(ep);
1473 +
1474 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
1475 if (ret < 0)
1476 epc->max_functions = 1;
1477 @@ -353,8 +565,16 @@ int dw_pcie_ep_init(struct dw_pcie_ep *e
1478 return ret;
1479 }
1480
1481 - ep->epc = epc;
1482 - epc_set_drvdata(epc, ep);
1483 + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
1484 + epc->mem->page_size);
1485 + if (!ep->msi_mem) {
1486 + dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
1487 + return -ENOMEM;
1488 + }
1489 + ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
1490 +
1491 + ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);
1492 +
1493 dw_pcie_setup(pci);
1494
1495 return 0;
1496 --- a/drivers/pci/dwc/pcie-designware-host.c
1497 +++ b/drivers/pci/dwc/pcie-designware-host.c
1498 @@ -1,3 +1,4 @@
1499 +// SPDX-License-Identifier: GPL-2.0
1500 /*
1501 * Synopsys DesignWare PCIe host controller driver
1502 *
1503 @@ -5,10 +6,6 @@
1504 * http://www.samsung.com
1505 *
1506 * Author: Jingoo Han <jg1.han@samsung.com>
1507 - *
1508 - * This program is free software; you can redistribute it and/or modify
1509 - * it under the terms of the GNU General Public License version 2 as
1510 - * published by the Free Software Foundation.
1511 */
1512
1513 #include <linux/irqdomain.h>
1514 --- a/drivers/pci/dwc/pcie-designware-plat.c
1515 +++ b/drivers/pci/dwc/pcie-designware-plat.c
1516 @@ -1,13 +1,10 @@
1517 +// SPDX-License-Identifier: GPL-2.0
1518 /*
1519 * PCIe RC driver for Synopsys DesignWare Core
1520 *
1521 * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
1522 *
1523 * Authors: Joao Pinto <Joao.Pinto@synopsys.com>
1524 - *
1525 - * This program is free software; you can redistribute it and/or modify
1526 - * it under the terms of the GNU General Public License version 2 as
1527 - * published by the Free Software Foundation.
1528 */
1529 #include <linux/clk.h>
1530 #include <linux/delay.h>
1531 @@ -15,19 +12,29 @@
1532 #include <linux/interrupt.h>
1533 #include <linux/kernel.h>
1534 #include <linux/init.h>
1535 +#include <linux/of_device.h>
1536 #include <linux/of_gpio.h>
1537 #include <linux/pci.h>
1538 #include <linux/platform_device.h>
1539 #include <linux/resource.h>
1540 #include <linux/signal.h>
1541 #include <linux/types.h>
1542 +#include <linux/regmap.h>
1543
1544 #include "pcie-designware.h"
1545
1546 struct dw_plat_pcie {
1547 - struct dw_pcie *pci;
1548 + struct dw_pcie *pci;
1549 + struct regmap *regmap;
1550 + enum dw_pcie_device_mode mode;
1551 +};
1552 +
1553 +struct dw_plat_pcie_of_data {
1554 + enum dw_pcie_device_mode mode;
1555 };
1556
1557 +static const struct of_device_id dw_plat_pcie_of_match[];
1558 +
1559 static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg)
1560 {
1561 struct pcie_port *pp = arg;
1562 @@ -52,9 +59,58 @@ static const struct dw_pcie_host_ops dw_
1563 .host_init = dw_plat_pcie_host_init,
1564 };
1565
1566 -static int dw_plat_add_pcie_port(struct pcie_port *pp,
1567 +static int dw_plat_pcie_establish_link(struct dw_pcie *pci)
1568 +{
1569 + return 0;
1570 +}
1571 +
1572 +static const struct dw_pcie_ops dw_pcie_ops = {
1573 + .start_link = dw_plat_pcie_establish_link,
1574 +};
1575 +
1576 +static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
1577 +{
1578 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1579 + struct pci_epc *epc = ep->epc;
1580 + enum pci_barno bar;
1581 +
1582 + for (bar = BAR_0; bar <= BAR_5; bar++)
1583 + dw_pcie_ep_reset_bar(pci, bar);
1584 +
1585 + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
1586 + epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
1587 +}
1588 +
1589 +static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
1590 + enum pci_epc_irq_type type,
1591 + u16 interrupt_num)
1592 +{
1593 + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
1594 +
1595 + switch (type) {
1596 + case PCI_EPC_IRQ_LEGACY:
1597 + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
1598 + case PCI_EPC_IRQ_MSI:
1599 + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
1600 + case PCI_EPC_IRQ_MSIX:
1601 + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
1602 + default:
1603 + dev_err(pci->dev, "UNKNOWN IRQ type\n");
1604 + }
1605 +
1606 + return 0;
1607 +}
1608 +
1609 +static struct dw_pcie_ep_ops pcie_ep_ops = {
1610 + .ep_init = dw_plat_pcie_ep_init,
1611 + .raise_irq = dw_plat_pcie_ep_raise_irq,
1612 +};
1613 +
1614 +static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
1615 struct platform_device *pdev)
1616 {
1617 + struct dw_pcie *pci = dw_plat_pcie->pci;
1618 + struct pcie_port *pp = &pci->pp;
1619 struct device *dev = &pdev->dev;
1620 int ret;
1621
1622 @@ -82,15 +138,44 @@ static int dw_plat_add_pcie_port(struct
1623
1624 ret = dw_pcie_host_init(pp);
1625 if (ret) {
1626 - dev_err(dev, "failed to initialize host\n");
1627 + dev_err(dev, "Failed to initialize host\n");
1628 return ret;
1629 }
1630
1631 return 0;
1632 }
1633
1634 -static const struct dw_pcie_ops dw_pcie_ops = {
1635 -};
1636 +static int dw_plat_add_pcie_ep(struct dw_plat_pcie *dw_plat_pcie,
1637 + struct platform_device *pdev)
1638 +{
1639 + int ret;
1640 + struct dw_pcie_ep *ep;
1641 + struct resource *res;
1642 + struct device *dev = &pdev->dev;
1643 + struct dw_pcie *pci = dw_plat_pcie->pci;
1644 +
1645 + ep = &pci->ep;
1646 + ep->ops = &pcie_ep_ops;
1647 +
1648 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
1649 + pci->dbi_base2 = devm_ioremap_resource(dev, res);
1650 + if (IS_ERR(pci->dbi_base2))
1651 + return PTR_ERR(pci->dbi_base2);
1652 +
1653 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
1654 + if (!res)
1655 + return -EINVAL;
1656 +
1657 + ep->phys_base = res->start;
1658 + ep->addr_size = resource_size(res);
1659 +
1660 + ret = dw_pcie_ep_init(ep);
1661 + if (ret) {
1662 + dev_err(dev, "Failed to initialize endpoint\n");
1663 + return ret;
1664 + }
1665 + return 0;
1666 +}
1667
1668 static int dw_plat_pcie_probe(struct platform_device *pdev)
1669 {
1670 @@ -99,6 +184,16 @@ static int dw_plat_pcie_probe(struct pla
1671 struct dw_pcie *pci;
1672 struct resource *res; /* Resource from DT */
1673 int ret;
1674 + const struct of_device_id *match;
1675 + const struct dw_plat_pcie_of_data *data;
1676 + enum dw_pcie_device_mode mode;
1677 +
1678 + match = of_match_device(dw_plat_pcie_of_match, dev);
1679 + if (!match)
1680 + return -EINVAL;
1681 +
1682 + data = (struct dw_plat_pcie_of_data *)match->data;
1683 + mode = (enum dw_pcie_device_mode)data->mode;
1684
1685 dw_plat_pcie = devm_kzalloc(dev, sizeof(*dw_plat_pcie), GFP_KERNEL);
1686 if (!dw_plat_pcie)
1687 @@ -112,23 +207,59 @@ static int dw_plat_pcie_probe(struct pla
1688 pci->ops = &dw_pcie_ops;
1689
1690 dw_plat_pcie->pci = pci;
1691 + dw_plat_pcie->mode = mode;
1692 +
1693 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1694 + if (!res)
1695 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1696
1697 - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1698 pci->dbi_base = devm_ioremap_resource(dev, res);
1699 if (IS_ERR(pci->dbi_base))
1700 return PTR_ERR(pci->dbi_base);
1701
1702 platform_set_drvdata(pdev, dw_plat_pcie);
1703
1704 - ret = dw_plat_add_pcie_port(&pci->pp, pdev);
1705 - if (ret < 0)
1706 - return ret;
1707 + switch (dw_plat_pcie->mode) {
1708 + case DW_PCIE_RC_TYPE:
1709 + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_HOST))
1710 + return -ENODEV;
1711 +
1712 + ret = dw_plat_add_pcie_port(dw_plat_pcie, pdev);
1713 + if (ret < 0)
1714 + return ret;
1715 + break;
1716 + case DW_PCIE_EP_TYPE:
1717 + if (!IS_ENABLED(CONFIG_PCIE_DW_PLAT_EP))
1718 + return -ENODEV;
1719 +
1720 + ret = dw_plat_add_pcie_ep(dw_plat_pcie, pdev);
1721 + if (ret < 0)
1722 + return ret;
1723 + break;
1724 + default:
1725 + dev_err(dev, "INVALID device type %d\n", dw_plat_pcie->mode);
1726 + }
1727
1728 return 0;
1729 }
1730
1731 +static const struct dw_plat_pcie_of_data dw_plat_pcie_rc_of_data = {
1732 + .mode = DW_PCIE_RC_TYPE,
1733 +};
1734 +
1735 +static const struct dw_plat_pcie_of_data dw_plat_pcie_ep_of_data = {
1736 + .mode = DW_PCIE_EP_TYPE,
1737 +};
1738 +
1739 static const struct of_device_id dw_plat_pcie_of_match[] = {
1740 - { .compatible = "snps,dw-pcie", },
1741 + {
1742 + .compatible = "snps,dw-pcie",
1743 + .data = &dw_plat_pcie_rc_of_data,
1744 + },
1745 + {
1746 + .compatible = "snps,dw-pcie-ep",
1747 + .data = &dw_plat_pcie_ep_of_data,
1748 + },
1749 {},
1750 };
1751
1752 --- a/drivers/pci/dwc/pcie-designware.c
1753 +++ b/drivers/pci/dwc/pcie-designware.c
1754 @@ -1,3 +1,4 @@
1755 +// SPDX-License-Identifier: GPL-2.0
1756 /*
1757 * Synopsys DesignWare PCIe host controller driver
1758 *
1759 @@ -5,10 +6,6 @@
1760 * http://www.samsung.com
1761 *
1762 * Author: Jingoo Han <jg1.han@samsung.com>
1763 - *
1764 - * This program is free software; you can redistribute it and/or modify
1765 - * it under the terms of the GNU General Public License version 2 as
1766 - * published by the Free Software Foundation.
1767 */
1768
1769 #include <linux/delay.h>
1770 --- a/drivers/pci/dwc/pcie-designware.h
1771 +++ b/drivers/pci/dwc/pcie-designware.h
1772 @@ -1,3 +1,4 @@
1773 +// SPDX-License-Identifier: GPL-2.0
1774 /*
1775 * Synopsys DesignWare PCIe host controller driver
1776 *
1777 @@ -5,10 +6,6 @@
1778 * http://www.samsung.com
1779 *
1780 * Author: Jingoo Han <jg1.han@samsung.com>
1781 - *
1782 - * This program is free software; you can redistribute it and/or modify
1783 - * it under the terms of the GNU General Public License version 2 as
1784 - * published by the Free Software Foundation.
1785 */
1786
1787 #ifndef _PCIE_DESIGNWARE_H
1788 @@ -97,15 +94,6 @@
1789 #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
1790 ((0x3 << 20) | ((region) << 9) | (0x1 << 8))
1791
1792 -#define MSI_MESSAGE_CONTROL 0x52
1793 -#define MSI_CAP_MMC_SHIFT 1
1794 -#define MSI_CAP_MMC_MASK (7 << MSI_CAP_MMC_SHIFT)
1795 -#define MSI_CAP_MME_SHIFT 4
1796 -#define MSI_CAP_MSI_EN_MASK 0x1
1797 -#define MSI_CAP_MME_MASK (7 << MSI_CAP_MME_SHIFT)
1798 -#define MSI_MESSAGE_ADDR_L32 0x54
1799 -#define MSI_MESSAGE_ADDR_U32 0x58
1800 -
1801 /*
1802 * Maximum number of MSI IRQs can be 256 per controller. But keep
1803 * it 32 as of now. Probably we will never need more than 32. If needed,
1804 @@ -118,6 +106,10 @@
1805 #define MAX_IATU_IN 256
1806 #define MAX_IATU_OUT 256
1807
1808 +/* Maximum number of inbound/outbound iATUs */
1809 +#define MAX_IATU_IN 256
1810 +#define MAX_IATU_OUT 256
1811 +
1812 struct pcie_port;
1813 struct dw_pcie;
1814 struct dw_pcie_ep;
1815 @@ -185,8 +177,8 @@ enum dw_pcie_as_type {
1816
1817 struct dw_pcie_ep_ops {
1818 void (*ep_init)(struct dw_pcie_ep *ep);
1819 - int (*raise_irq)(struct dw_pcie_ep *ep, enum pci_epc_irq_type type,
1820 - u8 interrupt_num);
1821 + int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
1822 + enum pci_epc_irq_type type, u16 interrupt_num);
1823 };
1824
1825 struct dw_pcie_ep {
1826 @@ -201,6 +193,10 @@ struct dw_pcie_ep {
1827 unsigned long *ob_window_map;
1828 u32 num_ib_windows;
1829 u32 num_ob_windows;
1830 + void __iomem *msi_mem;
1831 + phys_addr_t msi_mem_phys;
1832 + u8 msi_cap; /* MSI capability offset */
1833 + u8 msix_cap; /* MSI-X capability offset */
1834 };
1835
1836 struct dw_pcie_ops {
1837 @@ -339,6 +335,12 @@ static inline int dw_pcie_host_init(stru
1838 void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);
1839 int dw_pcie_ep_init(struct dw_pcie_ep *ep);
1840 void dw_pcie_ep_exit(struct dw_pcie_ep *ep);
1841 +int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no);
1842 +int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
1843 + u8 interrupt_num);
1844 +int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
1845 + u16 interrupt_num);
1846 +void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
1847 #else
1848 static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
1849 {
1850 @@ -352,5 +354,26 @@ static inline int dw_pcie_ep_init(struct
1851 static inline void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
1852 {
1853 }
1854 +
1855 +static inline int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
1856 +{
1857 + return 0;
1858 +}
1859 +
1860 +static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
1861 + u8 interrupt_num)
1862 +{
1863 + return 0;
1864 +}
1865 +
1866 +static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
1867 + u16 interrupt_num)
1868 +{
1869 + return 0;
1870 +}
1871 +
1872 +static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
1873 +{
1874 +}
1875 #endif
1876 #endif /* _PCIE_DESIGNWARE_H */
1877 --- a/drivers/pci/endpoint/Kconfig
1878 +++ b/drivers/pci/endpoint/Kconfig
1879 @@ -1,3 +1,4 @@
1880 +# SPDX-License-Identifier: GPL-2.0
1881 #
1882 # PCI Endpoint Support
1883 #
1884 --- a/drivers/pci/endpoint/Makefile
1885 +++ b/drivers/pci/endpoint/Makefile
1886 @@ -1,3 +1,4 @@
1887 +# SPDX-License-Identifier: GPL-2.0
1888 #
1889 # Makefile for PCI Endpoint Support
1890 #
1891 --- a/drivers/pci/endpoint/functions/Kconfig
1892 +++ b/drivers/pci/endpoint/functions/Kconfig
1893 @@ -1,3 +1,4 @@
1894 +# SPDX-License-Identifier: GPL-2.0
1895 #
1896 # PCI Endpoint Functions
1897 #
1898 --- a/drivers/pci/endpoint/functions/Makefile
1899 +++ b/drivers/pci/endpoint/functions/Makefile
1900 @@ -1,3 +1,4 @@
1901 +# SPDX-License-Identifier: GPL-2.0
1902 #
1903 # Makefile for PCI Endpoint Functions
1904 #
1905 --- a/drivers/pci/endpoint/functions/pci-epf-test.c
1906 +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
1907 @@ -1,20 +1,9 @@
1908 +// SPDX-License-Identifier: GPL-2.0
1909 /**
1910 * Test driver to test endpoint functionality
1911 *
1912 * Copyright (C) 2017 Texas Instruments
1913 * Author: Kishon Vijay Abraham I <kishon@ti.com>
1914 - *
1915 - * This program is free software: you can redistribute it and/or modify
1916 - * it under the terms of the GNU General Public License version 2 of
1917 - * the License as published by the Free Software Foundation.
1918 - *
1919 - * This program is distributed in the hope that it will be useful,
1920 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
1921 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1922 - * GNU General Public License for more details.
1923 - *
1924 - * You should have received a copy of the GNU General Public License
1925 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
1926 */
1927
1928 #include <linux/crc32.h>
1929 @@ -29,13 +18,16 @@
1930 #include <linux/pci-epf.h>
1931 #include <linux/pci_regs.h>
1932
1933 +#define IRQ_TYPE_LEGACY 0
1934 +#define IRQ_TYPE_MSI 1
1935 +#define IRQ_TYPE_MSIX 2
1936 +
1937 #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
1938 #define COMMAND_RAISE_MSI_IRQ BIT(1)
1939 -#define MSI_NUMBER_SHIFT 2
1940 -#define MSI_NUMBER_MASK (0x3f << MSI_NUMBER_SHIFT)
1941 -#define COMMAND_READ BIT(8)
1942 -#define COMMAND_WRITE BIT(9)
1943 -#define COMMAND_COPY BIT(10)
1944 +#define COMMAND_RAISE_MSIX_IRQ BIT(2)
1945 +#define COMMAND_READ BIT(3)
1946 +#define COMMAND_WRITE BIT(4)
1947 +#define COMMAND_COPY BIT(5)
1948
1949 #define STATUS_READ_SUCCESS BIT(0)
1950 #define STATUS_READ_FAIL BIT(1)
1951 @@ -56,6 +48,7 @@ struct pci_epf_test {
1952 struct pci_epf *epf;
1953 enum pci_barno test_reg_bar;
1954 bool linkup_notifier;
1955 + bool msix_available;
1956 struct delayed_work cmd_handler;
1957 };
1958
1959 @@ -67,6 +60,8 @@ struct pci_epf_test_reg {
1960 u64 dst_addr;
1961 u32 size;
1962 u32 checksum;
1963 + u32 irq_type;
1964 + u32 irq_number;
1965 } __packed;
1966
1967 static struct pci_epf_header test_header = {
1968 @@ -81,7 +76,7 @@ struct pci_epf_test_data {
1969 bool linkup_notifier;
1970 };
1971
1972 -static int bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
1973 +static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
1974
1975 static int pci_epf_test_copy(struct pci_epf_test *epf_test)
1976 {
1977 @@ -98,43 +93,45 @@ static int pci_epf_test_copy(struct pci_
1978
1979 src_addr = pci_epc_mem_alloc_addr(epc, &src_phys_addr, reg->size);
1980 if (!src_addr) {
1981 - dev_err(dev, "failed to allocate source address\n");
1982 + dev_err(dev, "Failed to allocate source address\n");
1983 reg->status = STATUS_SRC_ADDR_INVALID;
1984 ret = -ENOMEM;
1985 goto err;
1986 }
1987
1988 - ret = pci_epc_map_addr(epc, src_phys_addr, reg->src_addr, reg->size);
1989 + ret = pci_epc_map_addr(epc, epf->func_no, src_phys_addr, reg->src_addr,
1990 + reg->size);
1991 if (ret) {
1992 - dev_err(dev, "failed to map source address\n");
1993 + dev_err(dev, "Failed to map source address\n");
1994 reg->status = STATUS_SRC_ADDR_INVALID;
1995 goto err_src_addr;
1996 }
1997
1998 dst_addr = pci_epc_mem_alloc_addr(epc, &dst_phys_addr, reg->size);
1999 if (!dst_addr) {
2000 - dev_err(dev, "failed to allocate destination address\n");
2001 + dev_err(dev, "Failed to allocate destination address\n");
2002 reg->status = STATUS_DST_ADDR_INVALID;
2003 ret = -ENOMEM;
2004 goto err_src_map_addr;
2005 }
2006
2007 - ret = pci_epc_map_addr(epc, dst_phys_addr, reg->dst_addr, reg->size);
2008 + ret = pci_epc_map_addr(epc, epf->func_no, dst_phys_addr, reg->dst_addr,
2009 + reg->size);
2010 if (ret) {
2011 - dev_err(dev, "failed to map destination address\n");
2012 + dev_err(dev, "Failed to map destination address\n");
2013 reg->status = STATUS_DST_ADDR_INVALID;
2014 goto err_dst_addr;
2015 }
2016
2017 memcpy(dst_addr, src_addr, reg->size);
2018
2019 - pci_epc_unmap_addr(epc, dst_phys_addr);
2020 + pci_epc_unmap_addr(epc, epf->func_no, dst_phys_addr);
2021
2022 err_dst_addr:
2023 pci_epc_mem_free_addr(epc, dst_phys_addr, dst_addr, reg->size);
2024
2025 err_src_map_addr:
2026 - pci_epc_unmap_addr(epc, src_phys_addr);
2027 + pci_epc_unmap_addr(epc, epf->func_no, src_phys_addr);
2028
2029 err_src_addr:
2030 pci_epc_mem_free_addr(epc, src_phys_addr, src_addr, reg->size);
2031 @@ -158,15 +155,16 @@ static int pci_epf_test_read(struct pci_
2032
2033 src_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
2034 if (!src_addr) {
2035 - dev_err(dev, "failed to allocate address\n");
2036 + dev_err(dev, "Failed to allocate address\n");
2037 reg->status = STATUS_SRC_ADDR_INVALID;
2038 ret = -ENOMEM;
2039 goto err;
2040 }
2041
2042 - ret = pci_epc_map_addr(epc, phys_addr, reg->src_addr, reg->size);
2043 + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->src_addr,
2044 + reg->size);
2045 if (ret) {
2046 - dev_err(dev, "failed to map address\n");
2047 + dev_err(dev, "Failed to map address\n");
2048 reg->status = STATUS_SRC_ADDR_INVALID;
2049 goto err_addr;
2050 }
2051 @@ -186,7 +184,7 @@ static int pci_epf_test_read(struct pci_
2052 kfree(buf);
2053
2054 err_map_addr:
2055 - pci_epc_unmap_addr(epc, phys_addr);
2056 + pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
2057
2058 err_addr:
2059 pci_epc_mem_free_addr(epc, phys_addr, src_addr, reg->size);
2060 @@ -209,15 +207,16 @@ static int pci_epf_test_write(struct pci
2061
2062 dst_addr = pci_epc_mem_alloc_addr(epc, &phys_addr, reg->size);
2063 if (!dst_addr) {
2064 - dev_err(dev, "failed to allocate address\n");
2065 + dev_err(dev, "Failed to allocate address\n");
2066 reg->status = STATUS_DST_ADDR_INVALID;
2067 ret = -ENOMEM;
2068 goto err;
2069 }
2070
2071 - ret = pci_epc_map_addr(epc, phys_addr, reg->dst_addr, reg->size);
2072 + ret = pci_epc_map_addr(epc, epf->func_no, phys_addr, reg->dst_addr,
2073 + reg->size);
2074 if (ret) {
2075 - dev_err(dev, "failed to map address\n");
2076 + dev_err(dev, "Failed to map address\n");
2077 reg->status = STATUS_DST_ADDR_INVALID;
2078 goto err_addr;
2079 }
2080 @@ -237,12 +236,12 @@ static int pci_epf_test_write(struct pci
2081 * wait 1ms inorder for the write to complete. Without this delay L3
2082 * error in observed in the host system.
2083 */
2084 - mdelay(1);
2085 + usleep_range(1000, 2000);
2086
2087 kfree(buf);
2088
2089 err_map_addr:
2090 - pci_epc_unmap_addr(epc, phys_addr);
2091 + pci_epc_unmap_addr(epc, epf->func_no, phys_addr);
2092
2093 err_addr:
2094 pci_epc_mem_free_addr(epc, phys_addr, dst_addr, reg->size);
2095 @@ -251,31 +250,42 @@ err:
2096 return ret;
2097 }
2098
2099 -static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq)
2100 +static void pci_epf_test_raise_irq(struct pci_epf_test *epf_test, u8 irq_type,
2101 + u16 irq)
2102 {
2103 - u8 msi_count;
2104 struct pci_epf *epf = epf_test->epf;
2105 + struct device *dev = &epf->dev;
2106 struct pci_epc *epc = epf->epc;
2107 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
2108 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
2109
2110 reg->status |= STATUS_IRQ_RAISED;
2111 - msi_count = pci_epc_get_msi(epc);
2112 - if (irq > msi_count || msi_count <= 0)
2113 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
2114 - else
2115 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
2116 +
2117 + switch (irq_type) {
2118 + case IRQ_TYPE_LEGACY:
2119 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
2120 + break;
2121 + case IRQ_TYPE_MSI:
2122 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI, irq);
2123 + break;
2124 + case IRQ_TYPE_MSIX:
2125 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSIX, irq);
2126 + break;
2127 + default:
2128 + dev_err(dev, "Failed to raise IRQ, unknown type\n");
2129 + break;
2130 + }
2131 }
2132
2133 static void pci_epf_test_cmd_handler(struct work_struct *work)
2134 {
2135 int ret;
2136 - u8 irq;
2137 - u8 msi_count;
2138 + int count;
2139 u32 command;
2140 struct pci_epf_test *epf_test = container_of(work, struct pci_epf_test,
2141 cmd_handler.work);
2142 struct pci_epf *epf = epf_test->epf;
2143 + struct device *dev = &epf->dev;
2144 struct pci_epc *epc = epf->epc;
2145 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
2146 struct pci_epf_test_reg *reg = epf_test->reg[test_reg_bar];
2147 @@ -287,11 +297,14 @@ static void pci_epf_test_cmd_handler(str
2148 reg->command = 0;
2149 reg->status = 0;
2150
2151 - irq = (command & MSI_NUMBER_MASK) >> MSI_NUMBER_SHIFT;
2152 + if (reg->irq_type > IRQ_TYPE_MSIX) {
2153 + dev_err(dev, "Failed to detect IRQ type\n");
2154 + goto reset_handler;
2155 + }
2156
2157 if (command & COMMAND_RAISE_LEGACY_IRQ) {
2158 reg->status = STATUS_IRQ_RAISED;
2159 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_LEGACY, 0);
2160 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_LEGACY, 0);
2161 goto reset_handler;
2162 }
2163
2164 @@ -301,7 +314,8 @@ static void pci_epf_test_cmd_handler(str
2165 reg->status |= STATUS_WRITE_FAIL;
2166 else
2167 reg->status |= STATUS_WRITE_SUCCESS;
2168 - pci_epf_test_raise_irq(epf_test, irq);
2169 + pci_epf_test_raise_irq(epf_test, reg->irq_type,
2170 + reg->irq_number);
2171 goto reset_handler;
2172 }
2173
2174 @@ -311,7 +325,8 @@ static void pci_epf_test_cmd_handler(str
2175 reg->status |= STATUS_READ_SUCCESS;
2176 else
2177 reg->status |= STATUS_READ_FAIL;
2178 - pci_epf_test_raise_irq(epf_test, irq);
2179 + pci_epf_test_raise_irq(epf_test, reg->irq_type,
2180 + reg->irq_number);
2181 goto reset_handler;
2182 }
2183
2184 @@ -321,16 +336,28 @@ static void pci_epf_test_cmd_handler(str
2185 reg->status |= STATUS_COPY_SUCCESS;
2186 else
2187 reg->status |= STATUS_COPY_FAIL;
2188 - pci_epf_test_raise_irq(epf_test, irq);
2189 + pci_epf_test_raise_irq(epf_test, reg->irq_type,
2190 + reg->irq_number);
2191 goto reset_handler;
2192 }
2193
2194 if (command & COMMAND_RAISE_MSI_IRQ) {
2195 - msi_count = pci_epc_get_msi(epc);
2196 - if (irq > msi_count || msi_count <= 0)
2197 + count = pci_epc_get_msi(epc, epf->func_no);
2198 + if (reg->irq_number > count || count <= 0)
2199 + goto reset_handler;
2200 + reg->status = STATUS_IRQ_RAISED;
2201 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSI,
2202 + reg->irq_number);
2203 + goto reset_handler;
2204 + }
2205 +
2206 + if (command & COMMAND_RAISE_MSIX_IRQ) {
2207 + count = pci_epc_get_msix(epc, epf->func_no);
2208 + if (reg->irq_number > count || count <= 0)
2209 goto reset_handler;
2210 reg->status = STATUS_IRQ_RAISED;
2211 - pci_epc_raise_irq(epc, PCI_EPC_IRQ_MSI, irq);
2212 + pci_epc_raise_irq(epc, epf->func_no, PCI_EPC_IRQ_MSIX,
2213 + reg->irq_number);
2214 goto reset_handler;
2215 }
2216
2217 @@ -351,21 +378,23 @@ static void pci_epf_test_unbind(struct p
2218 {
2219 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
2220 struct pci_epc *epc = epf->epc;
2221 + struct pci_epf_bar *epf_bar;
2222 int bar;
2223
2224 cancel_delayed_work(&epf_test->cmd_handler);
2225 pci_epc_stop(epc);
2226 for (bar = BAR_0; bar <= BAR_5; bar++) {
2227 + epf_bar = &epf->bar[bar];
2228 +
2229 if (epf_test->reg[bar]) {
2230 pci_epf_free_space(epf, epf_test->reg[bar], bar);
2231 - pci_epc_clear_bar(epc, bar);
2232 + pci_epc_clear_bar(epc, epf->func_no, epf_bar);
2233 }
2234 }
2235 }
2236
2237 static int pci_epf_test_set_bar(struct pci_epf *epf)
2238 {
2239 - int flags;
2240 int bar;
2241 int ret;
2242 struct pci_epf_bar *epf_bar;
2243 @@ -374,20 +403,27 @@ static int pci_epf_test_set_bar(struct p
2244 struct pci_epf_test *epf_test = epf_get_drvdata(epf);
2245 enum pci_barno test_reg_bar = epf_test->test_reg_bar;
2246
2247 - flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32;
2248 - if (sizeof(dma_addr_t) == 0x8)
2249 - flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
2250 -
2251 for (bar = BAR_0; bar <= BAR_5; bar++) {
2252 epf_bar = &epf->bar[bar];
2253 - ret = pci_epc_set_bar(epc, bar, epf_bar->phys_addr,
2254 - epf_bar->size, flags);
2255 +
2256 + epf_bar->flags |= upper_32_bits(epf_bar->size) ?
2257 + PCI_BASE_ADDRESS_MEM_TYPE_64 :
2258 + PCI_BASE_ADDRESS_MEM_TYPE_32;
2259 +
2260 + ret = pci_epc_set_bar(epc, epf->func_no, epf_bar);
2261 if (ret) {
2262 pci_epf_free_space(epf, epf_test->reg[bar], bar);
2263 - dev_err(dev, "failed to set BAR%d\n", bar);
2264 + dev_err(dev, "Failed to set BAR%d\n", bar);
2265 if (bar == test_reg_bar)
2266 return ret;
2267 }
2268 + /*
2269 + * pci_epc_set_bar() sets PCI_BASE_ADDRESS_MEM_TYPE_64
2270 + * if the specific implementation required a 64-bit BAR,
2271 + * even if we only requested a 32-bit BAR.
2272 + */
2273 + if (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
2274 + bar++;
2275 }
2276
2277 return 0;
2278 @@ -404,7 +440,7 @@ static int pci_epf_test_alloc_space(stru
2279 base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg),
2280 test_reg_bar);
2281 if (!base) {
2282 - dev_err(dev, "failed to allocated register space\n");
2283 + dev_err(dev, "Failed to allocated register space\n");
2284 return -ENOMEM;
2285 }
2286 epf_test->reg[test_reg_bar] = base;
2287 @@ -414,7 +450,7 @@ static int pci_epf_test_alloc_space(stru
2288 continue;
2289 base = pci_epf_alloc_space(epf, bar_size[bar], bar);
2290 if (!base)
2291 - dev_err(dev, "failed to allocate space for BAR%d\n",
2292 + dev_err(dev, "Failed to allocate space for BAR%d\n",
2293 bar);
2294 epf_test->reg[bar] = base;
2295 }
2296 @@ -433,9 +469,18 @@ static int pci_epf_test_bind(struct pci_
2297 if (WARN_ON_ONCE(!epc))
2298 return -EINVAL;
2299
2300 - ret = pci_epc_write_header(epc, header);
2301 + if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER)
2302 + epf_test->linkup_notifier = false;
2303 + else
2304 + epf_test->linkup_notifier = true;
2305 +
2306 + epf_test->msix_available = epc->features & EPC_FEATURE_MSIX_AVAILABLE;
2307 +
2308 + epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features);
2309 +
2310 + ret = pci_epc_write_header(epc, epf->func_no, header);
2311 if (ret) {
2312 - dev_err(dev, "configuration header write failed\n");
2313 + dev_err(dev, "Configuration header write failed\n");
2314 return ret;
2315 }
2316
2317 @@ -447,9 +492,19 @@ static int pci_epf_test_bind(struct pci_
2318 if (ret)
2319 return ret;
2320
2321 - ret = pci_epc_set_msi(epc, epf->msi_interrupts);
2322 - if (ret)
2323 + ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
2324 + if (ret) {
2325 + dev_err(dev, "MSI configuration failed\n");
2326 return ret;
2327 + }
2328 +
2329 + if (epf_test->msix_available) {
2330 + ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
2331 + if (ret) {
2332 + dev_err(dev, "MSI-X configuration failed\n");
2333 + return ret;
2334 + }
2335 + }
2336
2337 if (!epf_test->linkup_notifier)
2338 queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work);
2339 @@ -517,7 +572,7 @@ static int __init pci_epf_test_init(void
2340 WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
2341 ret = pci_epf_register_driver(&test_driver);
2342 if (ret) {
2343 - pr_err("failed to register pci epf test driver --> %d\n", ret);
2344 + pr_err("Failed to register pci epf test driver --> %d\n", ret);
2345 return ret;
2346 }
2347
2348 --- a/drivers/pci/endpoint/pci-ep-cfs.c
2349 +++ b/drivers/pci/endpoint/pci-ep-cfs.c
2350 @@ -1,35 +1,28 @@
2351 +// SPDX-License-Identifier: GPL-2.0
2352 /**
2353 * configfs to configure the PCI endpoint
2354 *
2355 * Copyright (C) 2017 Texas Instruments
2356 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2357 - *
2358 - * This program is free software: you can redistribute it and/or modify
2359 - * it under the terms of the GNU General Public License version 2 of
2360 - * the License as published by the Free Software Foundation.
2361 - *
2362 - * This program is distributed in the hope that it will be useful,
2363 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2364 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2365 - * GNU General Public License for more details.
2366 - *
2367 - * You should have received a copy of the GNU General Public License
2368 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2369 */
2370
2371 #include <linux/module.h>
2372 +#include <linux/idr.h>
2373 #include <linux/slab.h>
2374
2375 #include <linux/pci-epc.h>
2376 #include <linux/pci-epf.h>
2377 #include <linux/pci-ep-cfs.h>
2378
2379 +static DEFINE_IDR(functions_idr);
2380 +static DEFINE_MUTEX(functions_mutex);
2381 static struct config_group *functions_group;
2382 static struct config_group *controllers_group;
2383
2384 struct pci_epf_group {
2385 struct config_group group;
2386 struct pci_epf *epf;
2387 + int index;
2388 };
2389
2390 struct pci_epc_group {
2391 @@ -151,7 +144,7 @@ static struct configfs_item_operations p
2392 .drop_link = pci_epc_epf_unlink,
2393 };
2394
2395 -static struct config_item_type pci_epc_type = {
2396 +static const struct config_item_type pci_epc_type = {
2397 .ct_item_ops = &pci_epc_item_ops,
2398 .ct_attrs = pci_epc_attrs,
2399 .ct_owner = THIS_MODULE,
2400 @@ -293,6 +286,28 @@ static ssize_t pci_epf_msi_interrupts_sh
2401 to_pci_epf_group(item)->epf->msi_interrupts);
2402 }
2403
2404 +static ssize_t pci_epf_msix_interrupts_store(struct config_item *item,
2405 + const char *page, size_t len)
2406 +{
2407 + u16 val;
2408 + int ret;
2409 +
2410 + ret = kstrtou16(page, 0, &val);
2411 + if (ret)
2412 + return ret;
2413 +
2414 + to_pci_epf_group(item)->epf->msix_interrupts = val;
2415 +
2416 + return len;
2417 +}
2418 +
2419 +static ssize_t pci_epf_msix_interrupts_show(struct config_item *item,
2420 + char *page)
2421 +{
2422 + return sprintf(page, "%d\n",
2423 + to_pci_epf_group(item)->epf->msix_interrupts);
2424 +}
2425 +
2426 PCI_EPF_HEADER_R(vendorid)
2427 PCI_EPF_HEADER_W_u16(vendorid)
2428
2429 @@ -334,6 +349,7 @@ CONFIGFS_ATTR(pci_epf_, subsys_vendor_id
2430 CONFIGFS_ATTR(pci_epf_, subsys_id);
2431 CONFIGFS_ATTR(pci_epf_, interrupt_pin);
2432 CONFIGFS_ATTR(pci_epf_, msi_interrupts);
2433 +CONFIGFS_ATTR(pci_epf_, msix_interrupts);
2434
2435 static struct configfs_attribute *pci_epf_attrs[] = {
2436 &pci_epf_attr_vendorid,
2437 @@ -347,6 +363,7 @@ static struct configfs_attribute *pci_ep
2438 &pci_epf_attr_subsys_id,
2439 &pci_epf_attr_interrupt_pin,
2440 &pci_epf_attr_msi_interrupts,
2441 + &pci_epf_attr_msix_interrupts,
2442 NULL,
2443 };
2444
2445 @@ -354,6 +371,9 @@ static void pci_epf_release(struct confi
2446 {
2447 struct pci_epf_group *epf_group = to_pci_epf_group(item);
2448
2449 + mutex_lock(&functions_mutex);
2450 + idr_remove(&functions_idr, epf_group->index);
2451 + mutex_unlock(&functions_mutex);
2452 pci_epf_destroy(epf_group->epf);
2453 kfree(epf_group);
2454 }
2455 @@ -362,7 +382,7 @@ static struct configfs_item_operations p
2456 .release = pci_epf_release,
2457 };
2458
2459 -static struct config_item_type pci_epf_type = {
2460 +static const struct config_item_type pci_epf_type = {
2461 .ct_item_ops = &pci_epf_ops,
2462 .ct_attrs = pci_epf_attrs,
2463 .ct_owner = THIS_MODULE,
2464 @@ -373,22 +393,57 @@ static struct config_group *pci_epf_make
2465 {
2466 struct pci_epf_group *epf_group;
2467 struct pci_epf *epf;
2468 + char *epf_name;
2469 + int index, err;
2470
2471 epf_group = kzalloc(sizeof(*epf_group), GFP_KERNEL);
2472 if (!epf_group)
2473 return ERR_PTR(-ENOMEM);
2474
2475 + mutex_lock(&functions_mutex);
2476 + index = idr_alloc(&functions_idr, epf_group, 0, 0, GFP_KERNEL);
2477 + mutex_unlock(&functions_mutex);
2478 + if (index < 0) {
2479 + err = index;
2480 + goto free_group;
2481 + }
2482 +
2483 + epf_group->index = index;
2484 +
2485 config_group_init_type_name(&epf_group->group, name, &pci_epf_type);
2486
2487 - epf = pci_epf_create(group->cg_item.ci_name);
2488 + epf_name = kasprintf(GFP_KERNEL, "%s.%d",
2489 + group->cg_item.ci_name, epf_group->index);
2490 + if (!epf_name) {
2491 + err = -ENOMEM;
2492 + goto remove_idr;
2493 + }
2494 +
2495 + epf = pci_epf_create(epf_name);
2496 if (IS_ERR(epf)) {
2497 pr_err("failed to create endpoint function device\n");
2498 - return ERR_PTR(-EINVAL);
2499 + err = -EINVAL;
2500 + goto free_name;
2501 }
2502
2503 epf_group->epf = epf;
2504
2505 + kfree(epf_name);
2506 +
2507 return &epf_group->group;
2508 +
2509 +free_name:
2510 + kfree(epf_name);
2511 +
2512 +remove_idr:
2513 + mutex_lock(&functions_mutex);
2514 + idr_remove(&functions_idr, epf_group->index);
2515 + mutex_unlock(&functions_mutex);
2516 +
2517 +free_group:
2518 + kfree(epf_group);
2519 +
2520 + return ERR_PTR(err);
2521 }
2522
2523 static void pci_epf_drop(struct config_group *group, struct config_item *item)
2524 @@ -401,7 +456,7 @@ static struct configfs_group_operations
2525 .drop_item = &pci_epf_drop,
2526 };
2527
2528 -static struct config_item_type pci_epf_group_type = {
2529 +static const struct config_item_type pci_epf_group_type = {
2530 .ct_group_ops = &pci_epf_group_ops,
2531 .ct_owner = THIS_MODULE,
2532 };
2533 @@ -429,15 +484,15 @@ void pci_ep_cfs_remove_epf_group(struct
2534 }
2535 EXPORT_SYMBOL(pci_ep_cfs_remove_epf_group);
2536
2537 -static struct config_item_type pci_functions_type = {
2538 +static const struct config_item_type pci_functions_type = {
2539 .ct_owner = THIS_MODULE,
2540 };
2541
2542 -static struct config_item_type pci_controllers_type = {
2543 +static const struct config_item_type pci_controllers_type = {
2544 .ct_owner = THIS_MODULE,
2545 };
2546
2547 -static struct config_item_type pci_ep_type = {
2548 +static const struct config_item_type pci_ep_type = {
2549 .ct_owner = THIS_MODULE,
2550 };
2551
2552 --- a/drivers/pci/endpoint/pci-epc-core.c
2553 +++ b/drivers/pci/endpoint/pci-epc-core.c
2554 @@ -1,20 +1,9 @@
2555 +// SPDX-License-Identifier: GPL-2.0
2556 /**
2557 * PCI Endpoint *Controller* (EPC) library
2558 *
2559 * Copyright (C) 2017 Texas Instruments
2560 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2561 - *
2562 - * This program is free software: you can redistribute it and/or modify
2563 - * it under the terms of the GNU General Public License version 2 of
2564 - * the License as published by the Free Software Foundation.
2565 - *
2566 - * This program is distributed in the hope that it will be useful,
2567 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2568 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2569 - * GNU General Public License for more details.
2570 - *
2571 - * You should have received a copy of the GNU General Public License
2572 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2573 */
2574
2575 #include <linux/device.h>
2576 @@ -141,25 +130,26 @@ EXPORT_SYMBOL_GPL(pci_epc_start);
2577 /**
2578 * pci_epc_raise_irq() - interrupt the host system
2579 * @epc: the EPC device which has to interrupt the host
2580 - * @type: specify the type of interrupt; legacy or MSI
2581 - * @interrupt_num: the MSI interrupt number
2582 + * @func_no: the endpoint function number in the EPC device
2583 + * @type: specify the type of interrupt; legacy, MSI or MSI-X
2584 + * @interrupt_num: the MSI or MSI-X interrupt number
2585 *
2586 - * Invoke to raise an MSI or legacy interrupt
2587 + * Invoke to raise an legacy, MSI or MSI-X interrupt
2588 */
2589 -int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
2590 - u8 interrupt_num)
2591 +int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
2592 + enum pci_epc_irq_type type, u16 interrupt_num)
2593 {
2594 int ret;
2595 unsigned long flags;
2596
2597 - if (IS_ERR(epc))
2598 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2599 return -EINVAL;
2600
2601 if (!epc->ops->raise_irq)
2602 return 0;
2603
2604 spin_lock_irqsave(&epc->lock, flags);
2605 - ret = epc->ops->raise_irq(epc, type, interrupt_num);
2606 + ret = epc->ops->raise_irq(epc, func_no, type, interrupt_num);
2607 spin_unlock_irqrestore(&epc->lock, flags);
2608
2609 return ret;
2610 @@ -169,22 +159,23 @@ EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
2611 /**
2612 * pci_epc_get_msi() - get the number of MSI interrupt numbers allocated
2613 * @epc: the EPC device to which MSI interrupts was requested
2614 + * @func_no: the endpoint function number in the EPC device
2615 *
2616 * Invoke to get the number of MSI interrupts allocated by the RC
2617 */
2618 -int pci_epc_get_msi(struct pci_epc *epc)
2619 +int pci_epc_get_msi(struct pci_epc *epc, u8 func_no)
2620 {
2621 int interrupt;
2622 unsigned long flags;
2623
2624 - if (IS_ERR(epc))
2625 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2626 return 0;
2627
2628 if (!epc->ops->get_msi)
2629 return 0;
2630
2631 spin_lock_irqsave(&epc->lock, flags);
2632 - interrupt = epc->ops->get_msi(epc);
2633 + interrupt = epc->ops->get_msi(epc, func_no);
2634 spin_unlock_irqrestore(&epc->lock, flags);
2635
2636 if (interrupt < 0)
2637 @@ -199,17 +190,19 @@ EXPORT_SYMBOL_GPL(pci_epc_get_msi);
2638 /**
2639 * pci_epc_set_msi() - set the number of MSI interrupt numbers required
2640 * @epc: the EPC device on which MSI has to be configured
2641 + * @func_no: the endpoint function number in the EPC device
2642 * @interrupts: number of MSI interrupts required by the EPF
2643 *
2644 * Invoke to set the required number of MSI interrupts.
2645 */
2646 -int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts)
2647 +int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
2648 {
2649 int ret;
2650 u8 encode_int;
2651 unsigned long flags;
2652
2653 - if (IS_ERR(epc))
2654 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2655 + interrupts > 32)
2656 return -EINVAL;
2657
2658 if (!epc->ops->set_msi)
2659 @@ -218,7 +211,7 @@ int pci_epc_set_msi(struct pci_epc *epc,
2660 encode_int = order_base_2(interrupts);
2661
2662 spin_lock_irqsave(&epc->lock, flags);
2663 - ret = epc->ops->set_msi(epc, encode_int);
2664 + ret = epc->ops->set_msi(epc, func_no, encode_int);
2665 spin_unlock_irqrestore(&epc->lock, flags);
2666
2667 return ret;
2668 @@ -226,24 +219,83 @@ int pci_epc_set_msi(struct pci_epc *epc,
2669 EXPORT_SYMBOL_GPL(pci_epc_set_msi);
2670
2671 /**
2672 + * pci_epc_get_msix() - get the number of MSI-X interrupt numbers allocated
2673 + * @epc: the EPC device to which MSI-X interrupts was requested
2674 + * @func_no: the endpoint function number in the EPC device
2675 + *
2676 + * Invoke to get the number of MSI-X interrupts allocated by the RC
2677 + */
2678 +int pci_epc_get_msix(struct pci_epc *epc, u8 func_no)
2679 +{
2680 + int interrupt;
2681 + unsigned long flags;
2682 +
2683 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2684 + return 0;
2685 +
2686 + if (!epc->ops->get_msix)
2687 + return 0;
2688 +
2689 + spin_lock_irqsave(&epc->lock, flags);
2690 + interrupt = epc->ops->get_msix(epc, func_no);
2691 + spin_unlock_irqrestore(&epc->lock, flags);
2692 +
2693 + if (interrupt < 0)
2694 + return 0;
2695 +
2696 + return interrupt + 1;
2697 +}
2698 +EXPORT_SYMBOL_GPL(pci_epc_get_msix);
2699 +
2700 +/**
2701 + * pci_epc_set_msix() - set the number of MSI-X interrupt numbers required
2702 + * @epc: the EPC device on which MSI-X has to be configured
2703 + * @func_no: the endpoint function number in the EPC device
2704 + * @interrupts: number of MSI-X interrupts required by the EPF
2705 + *
2706 + * Invoke to set the required number of MSI-X interrupts.
2707 + */
2708 +int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
2709 +{
2710 + int ret;
2711 + unsigned long flags;
2712 +
2713 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2714 + interrupts < 1 || interrupts > 2048)
2715 + return -EINVAL;
2716 +
2717 + if (!epc->ops->set_msix)
2718 + return 0;
2719 +
2720 + spin_lock_irqsave(&epc->lock, flags);
2721 + ret = epc->ops->set_msix(epc, func_no, interrupts - 1);
2722 + spin_unlock_irqrestore(&epc->lock, flags);
2723 +
2724 + return ret;
2725 +}
2726 +EXPORT_SYMBOL_GPL(pci_epc_set_msix);
2727 +
2728 +/**
2729 * pci_epc_unmap_addr() - unmap CPU address from PCI address
2730 * @epc: the EPC device on which address is allocated
2731 + * @func_no: the endpoint function number in the EPC device
2732 * @phys_addr: physical address of the local system
2733 *
2734 * Invoke to unmap the CPU address from PCI address.
2735 */
2736 -void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr)
2737 +void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
2738 + phys_addr_t phys_addr)
2739 {
2740 unsigned long flags;
2741
2742 - if (IS_ERR(epc))
2743 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2744 return;
2745
2746 if (!epc->ops->unmap_addr)
2747 return;
2748
2749 spin_lock_irqsave(&epc->lock, flags);
2750 - epc->ops->unmap_addr(epc, phys_addr);
2751 + epc->ops->unmap_addr(epc, func_no, phys_addr);
2752 spin_unlock_irqrestore(&epc->lock, flags);
2753 }
2754 EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
2755 @@ -251,26 +303,27 @@ EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
2756 /**
2757 * pci_epc_map_addr() - map CPU address to PCI address
2758 * @epc: the EPC device on which address is allocated
2759 + * @func_no: the endpoint function number in the EPC device
2760 * @phys_addr: physical address of the local system
2761 * @pci_addr: PCI address to which the physical address should be mapped
2762 * @size: the size of the allocation
2763 *
2764 * Invoke to map CPU address with PCI address.
2765 */
2766 -int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
2767 - u64 pci_addr, size_t size)
2768 +int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
2769 + phys_addr_t phys_addr, u64 pci_addr, size_t size)
2770 {
2771 int ret;
2772 unsigned long flags;
2773
2774 - if (IS_ERR(epc))
2775 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2776 return -EINVAL;
2777
2778 if (!epc->ops->map_addr)
2779 return 0;
2780
2781 spin_lock_irqsave(&epc->lock, flags);
2782 - ret = epc->ops->map_addr(epc, phys_addr, pci_addr, size);
2783 + ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size);
2784 spin_unlock_irqrestore(&epc->lock, flags);
2785
2786 return ret;
2787 @@ -280,22 +333,26 @@ EXPORT_SYMBOL_GPL(pci_epc_map_addr);
2788 /**
2789 * pci_epc_clear_bar() - reset the BAR
2790 * @epc: the EPC device for which the BAR has to be cleared
2791 - * @bar: the BAR number that has to be reset
2792 + * @func_no: the endpoint function number in the EPC device
2793 + * @epf_bar: the struct epf_bar that contains the BAR information
2794 *
2795 * Invoke to reset the BAR of the endpoint device.
2796 */
2797 -void pci_epc_clear_bar(struct pci_epc *epc, int bar)
2798 +void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
2799 + struct pci_epf_bar *epf_bar)
2800 {
2801 unsigned long flags;
2802
2803 - if (IS_ERR(epc))
2804 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2805 + (epf_bar->barno == BAR_5 &&
2806 + epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
2807 return;
2808
2809 if (!epc->ops->clear_bar)
2810 return;
2811
2812 spin_lock_irqsave(&epc->lock, flags);
2813 - epc->ops->clear_bar(epc, bar);
2814 + epc->ops->clear_bar(epc, func_no, epf_bar);
2815 spin_unlock_irqrestore(&epc->lock, flags);
2816 }
2817 EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
2818 @@ -303,26 +360,32 @@ EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
2819 /**
2820 * pci_epc_set_bar() - configure BAR in order for host to assign PCI addr space
2821 * @epc: the EPC device on which BAR has to be configured
2822 - * @bar: the BAR number that has to be configured
2823 - * @size: the size of the addr space
2824 - * @flags: specify memory allocation/io allocation/32bit address/64 bit address
2825 + * @func_no: the endpoint function number in the EPC device
2826 + * @epf_bar: the struct epf_bar that contains the BAR information
2827 *
2828 * Invoke to configure the BAR of the endpoint device.
2829 */
2830 -int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
2831 - dma_addr_t bar_phys, size_t size, int flags)
2832 +int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
2833 + struct pci_epf_bar *epf_bar)
2834 {
2835 int ret;
2836 unsigned long irq_flags;
2837 + int flags = epf_bar->flags;
2838
2839 - if (IS_ERR(epc))
2840 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
2841 + (epf_bar->barno == BAR_5 &&
2842 + flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ||
2843 + (flags & PCI_BASE_ADDRESS_SPACE_IO &&
2844 + flags & PCI_BASE_ADDRESS_IO_MASK) ||
2845 + (upper_32_bits(epf_bar->size) &&
2846 + !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
2847 return -EINVAL;
2848
2849 if (!epc->ops->set_bar)
2850 return 0;
2851
2852 spin_lock_irqsave(&epc->lock, irq_flags);
2853 - ret = epc->ops->set_bar(epc, bar, bar_phys, size, flags);
2854 + ret = epc->ops->set_bar(epc, func_no, epf_bar);
2855 spin_unlock_irqrestore(&epc->lock, irq_flags);
2856
2857 return ret;
2858 @@ -332,6 +395,7 @@ EXPORT_SYMBOL_GPL(pci_epc_set_bar);
2859 /**
2860 * pci_epc_write_header() - write standard configuration header
2861 * @epc: the EPC device to which the configuration header should be written
2862 + * @func_no: the endpoint function number in the EPC device
2863 * @header: standard configuration header fields
2864 *
2865 * Invoke to write the configuration header to the endpoint controller. Every
2866 @@ -339,19 +403,20 @@ EXPORT_SYMBOL_GPL(pci_epc_set_bar);
2867 * configuration header would be written. The callback function should write
2868 * the header fields to this dedicated location.
2869 */
2870 -int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *header)
2871 +int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
2872 + struct pci_epf_header *header)
2873 {
2874 int ret;
2875 unsigned long flags;
2876
2877 - if (IS_ERR(epc))
2878 + if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
2879 return -EINVAL;
2880
2881 if (!epc->ops->write_header)
2882 return 0;
2883
2884 spin_lock_irqsave(&epc->lock, flags);
2885 - ret = epc->ops->write_header(epc, header);
2886 + ret = epc->ops->write_header(epc, func_no, header);
2887 spin_unlock_irqrestore(&epc->lock, flags);
2888
2889 return ret;
2890 --- a/drivers/pci/endpoint/pci-epc-mem.c
2891 +++ b/drivers/pci/endpoint/pci-epc-mem.c
2892 @@ -1,20 +1,9 @@
2893 +// SPDX-License-Identifier: GPL-2.0
2894 /**
2895 * PCI Endpoint *Controller* Address Space Management
2896 *
2897 * Copyright (C) 2017 Texas Instruments
2898 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2899 - *
2900 - * This program is free software: you can redistribute it and/or modify
2901 - * it under the terms of the GNU General Public License version 2 of
2902 - * the License as published by the Free Software Foundation.
2903 - *
2904 - * This program is distributed in the hope that it will be useful,
2905 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2906 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2907 - * GNU General Public License for more details.
2908 - *
2909 - * You should have received a copy of the GNU General Public License
2910 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2911 */
2912
2913 #include <linux/io.h>
2914 --- a/drivers/pci/endpoint/pci-epf-core.c
2915 +++ b/drivers/pci/endpoint/pci-epf-core.c
2916 @@ -1,20 +1,9 @@
2917 +// SPDX-License-Identifier: GPL-2.0
2918 /**
2919 * PCI Endpoint *Function* (EPF) library
2920 *
2921 * Copyright (C) 2017 Texas Instruments
2922 * Author: Kishon Vijay Abraham I <kishon@ti.com>
2923 - *
2924 - * This program is free software: you can redistribute it and/or modify
2925 - * it under the terms of the GNU General Public License version 2 of
2926 - * the License as published by the Free Software Foundation.
2927 - *
2928 - * This program is distributed in the hope that it will be useful,
2929 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
2930 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2931 - * GNU General Public License for more details.
2932 - *
2933 - * You should have received a copy of the GNU General Public License
2934 - * along with this program. If not, see <http://www.gnu.org/licenses/>.
2935 */
2936
2937 #include <linux/device.h>
2938 @@ -26,6 +15,8 @@
2939 #include <linux/pci-epf.h>
2940 #include <linux/pci-ep-cfs.h>
2941
2942 +static DEFINE_MUTEX(pci_epf_mutex);
2943 +
2944 static struct bus_type pci_epf_bus_type;
2945 static const struct device_type pci_epf_type;
2946
2947 @@ -109,6 +100,8 @@ void pci_epf_free_space(struct pci_epf *
2948
2949 epf->bar[bar].phys_addr = 0;
2950 epf->bar[bar].size = 0;
2951 + epf->bar[bar].barno = 0;
2952 + epf->bar[bar].flags = 0;
2953 }
2954 EXPORT_SYMBOL_GPL(pci_epf_free_space);
2955
2956 @@ -137,11 +130,27 @@ void *pci_epf_alloc_space(struct pci_epf
2957
2958 epf->bar[bar].phys_addr = phys_addr;
2959 epf->bar[bar].size = size;
2960 + epf->bar[bar].barno = bar;
2961 + epf->bar[bar].flags = PCI_BASE_ADDRESS_SPACE_MEMORY;
2962
2963 return space;
2964 }
2965 EXPORT_SYMBOL_GPL(pci_epf_alloc_space);
2966
2967 +static void pci_epf_remove_cfs(struct pci_epf_driver *driver)
2968 +{
2969 + struct config_group *group, *tmp;
2970 +
2971 + if (!IS_ENABLED(CONFIG_PCI_ENDPOINT_CONFIGFS))
2972 + return;
2973 +
2974 + mutex_lock(&pci_epf_mutex);
2975 + list_for_each_entry_safe(group, tmp, &driver->epf_group, group_entry)
2976 + pci_ep_cfs_remove_epf_group(group);
2977 + list_del(&driver->epf_group);
2978 + mutex_unlock(&pci_epf_mutex);
2979 +}
2980 +
2981 /**
2982 * pci_epf_unregister_driver() - unregister the PCI EPF driver
2983 * @driver: the PCI EPF driver that has to be unregistered
2984 @@ -150,11 +159,38 @@ EXPORT_SYMBOL_GPL(pci_epf_alloc_space);
2985 */
2986 void pci_epf_unregister_driver(struct pci_epf_driver *driver)
2987 {
2988 - pci_ep_cfs_remove_epf_group(driver->group);
2989 + pci_epf_remove_cfs(driver);
2990 driver_unregister(&driver->driver);
2991 }
2992 EXPORT_SYMBOL_GPL(pci_epf_unregister_driver);
2993
2994 +static int pci_epf_add_cfs(struct pci_epf_driver *driver)
2995 +{
2996 + struct config_group *group;
2997 + const struct pci_epf_device_id *id;
2998 +
2999 + if (!IS_ENABLED(CONFIG_PCI_ENDPOINT_CONFIGFS))
3000 + return 0;
3001 +
3002 + INIT_LIST_HEAD(&driver->epf_group);
3003 +
3004 + id = driver->id_table;
3005 + while (id->name[0]) {
3006 + group = pci_ep_cfs_add_epf_group(id->name);
3007 + if (IS_ERR(group)) {
3008 + pci_epf_remove_cfs(driver);
3009 + return PTR_ERR(group);
3010 + }
3011 +
3012 + mutex_lock(&pci_epf_mutex);
3013 + list_add_tail(&group->group_entry, &driver->epf_group);
3014 + mutex_unlock(&pci_epf_mutex);
3015 + id++;
3016 + }
3017 +
3018 + return 0;
3019 +}
3020 +
3021 /**
3022 * __pci_epf_register_driver() - register a new PCI EPF driver
3023 * @driver: structure representing PCI EPF driver
3024 @@ -180,7 +216,7 @@ int __pci_epf_register_driver(struct pci
3025 if (ret)
3026 return ret;
3027
3028 - driver->group = pci_ep_cfs_add_epf_group(driver->driver.name);
3029 + pci_epf_add_cfs(driver);
3030
3031 return 0;
3032 }
3033 @@ -211,29 +247,17 @@ struct pci_epf *pci_epf_create(const cha
3034 int ret;
3035 struct pci_epf *epf;
3036 struct device *dev;
3037 - char *func_name;
3038 - char *buf;
3039 + int len;
3040
3041 epf = kzalloc(sizeof(*epf), GFP_KERNEL);
3042 - if (!epf) {
3043 - ret = -ENOMEM;
3044 - goto err_ret;
3045 - }
3046 + if (!epf)
3047 + return ERR_PTR(-ENOMEM);
3048
3049 - buf = kstrdup(name, GFP_KERNEL);
3050 - if (!buf) {
3051 - ret = -ENOMEM;
3052 - goto free_epf;
3053 - }
3054 -
3055 - func_name = buf;
3056 - buf = strchrnul(buf, '.');
3057 - *buf = '\0';
3058 -
3059 - epf->name = kstrdup(func_name, GFP_KERNEL);
3060 + len = strchrnul(name, '.') - name;
3061 + epf->name = kstrndup(name, len, GFP_KERNEL);
3062 if (!epf->name) {
3063 - ret = -ENOMEM;
3064 - goto free_func_name;
3065 + kfree(epf);
3066 + return ERR_PTR(-ENOMEM);
3067 }
3068
3069 dev = &epf->dev;
3070 @@ -242,28 +266,18 @@ struct pci_epf *pci_epf_create(const cha
3071 dev->type = &pci_epf_type;
3072
3073 ret = dev_set_name(dev, "%s", name);
3074 - if (ret)
3075 - goto put_dev;
3076 + if (ret) {
3077 + put_device(dev);
3078 + return ERR_PTR(ret);
3079 + }
3080
3081 ret = device_add(dev);
3082 - if (ret)
3083 - goto put_dev;
3084 + if (ret) {
3085 + put_device(dev);
3086 + return ERR_PTR(ret);
3087 + }
3088
3089 - kfree(func_name);
3090 return epf;
3091 -
3092 -put_dev:
3093 - put_device(dev);
3094 - kfree(epf->name);
3095 -
3096 -free_func_name:
3097 - kfree(func_name);
3098 -
3099 -free_epf:
3100 - kfree(epf);
3101 -
3102 -err_ret:
3103 - return ERR_PTR(ret);
3104 }
3105 EXPORT_SYMBOL_GPL(pci_epf_create);
3106
3107 --- a/drivers/pci/host/pci-host-common.c
3108 +++ b/drivers/pci/host/pci-host-common.c
3109 @@ -113,9 +113,7 @@ err_out:
3110 int pci_host_common_probe(struct platform_device *pdev,
3111 struct pci_ecam_ops *ops)
3112 {
3113 - const char *type;
3114 struct device *dev = &pdev->dev;
3115 - struct device_node *np = dev->of_node;
3116 struct pci_bus *bus, *child;
3117 struct pci_host_bridge *bridge;
3118 struct pci_config_window *cfg;
3119 @@ -126,12 +124,6 @@ int pci_host_common_probe(struct platfor
3120 if (!bridge)
3121 return -ENOMEM;
3122
3123 - type = of_get_property(np, "device_type", NULL);
3124 - if (!type || strcmp(type, "pci")) {
3125 - dev_err(dev, "invalid \"device_type\" %s\n", type);
3126 - return -EINVAL;
3127 - }
3128 -
3129 of_pci_check_probe_only();
3130
3131 /* Parse and map our Configuration Space windows */
3132 --- a/drivers/pci/host/pcie-xilinx-nwl.c
3133 +++ b/drivers/pci/host/pcie-xilinx-nwl.c
3134 @@ -778,16 +778,7 @@ static int nwl_pcie_parse_dt(struct nwl_
3135 struct platform_device *pdev)
3136 {
3137 struct device *dev = pcie->dev;
3138 - struct device_node *node = dev->of_node;
3139 struct resource *res;
3140 - const char *type;
3141 -
3142 - /* Check for device type */
3143 - type = of_get_property(node, "device_type", NULL);
3144 - if (!type || strcmp(type, "pci")) {
3145 - dev_err(dev, "invalid \"device_type\" %s\n", type);
3146 - return -EINVAL;
3147 - }
3148
3149 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
3150 pcie->breg_base = devm_ioremap_resource(dev, res);
3151 --- a/drivers/pci/host/pcie-xilinx.c
3152 +++ b/drivers/pci/host/pcie-xilinx.c
3153 @@ -584,15 +584,8 @@ static int xilinx_pcie_parse_dt(struct x
3154 struct device *dev = port->dev;
3155 struct device_node *node = dev->of_node;
3156 struct resource regs;
3157 - const char *type;
3158 int err;
3159
3160 - type = of_get_property(node, "device_type", NULL);
3161 - if (!type || strcmp(type, "pci")) {
3162 - dev_err(dev, "invalid \"device_type\" %s\n", type);
3163 - return -EINVAL;
3164 - }
3165 -
3166 err = of_address_to_resource(node, 0, &regs);
3167 if (err) {
3168 dev_err(dev, "missing \"reg\" property\n");
3169 --- /dev/null
3170 +++ b/drivers/pci/mobiveil/Kconfig
3171 @@ -0,0 +1,50 @@
3172 +# SPDX-License-Identifier: GPL-2.0
3173 +
3174 +menu "Mobiveil PCIe Core Support"
3175 + depends on PCI
3176 +
3177 +config PCIE_MOBIVEIL
3178 + bool
3179 +
3180 +config PCIE_MOBIVEIL_HOST
3181 + bool
3182 + depends on PCI_MSI_IRQ_DOMAIN
3183 + select PCIE_MOBIVEIL
3184 +
3185 +config PCIE_MOBIVEIL_EP
3186 + bool
3187 + depends on PCI_ENDPOINT
3188 + select PCIE_MOBIVEIL
3189 +
3190 +config PCIE_MOBIVEIL_PLAT
3191 + bool "Mobiveil AXI PCIe controller"
3192 + depends on ARCH_ZYNQMP || COMPILE_TEST
3193 + depends on OF
3194 + select PCIE_MOBIVEIL_HOST
3195 + help
3196 + Say Y here if you want to enable support for the Mobiveil AXI PCIe
3197 + Soft IP. It has up to 8 outbound and inbound windows
3198 + for address translation and it is a PCIe Gen4 IP.
3199 +
3200 +config PCI_LAYERSCAPE_GEN4
3201 + bool "Freescale Layerscpe PCIe Gen4 controller in RC mode"
3202 + depends on PCI
3203 + depends on OF && (ARM64 || ARCH_LAYERSCAPE)
3204 + depends on PCI_MSI_IRQ_DOMAIN
3205 + select PCIE_MOBIVEIL_HOST
3206 + help
3207 + Say Y here if you want PCIe Gen4 controller support on
3208 + Layerscape SoCs. And the PCIe controller work in RC mode
3209 + by setting the RCW[HOST_AGT_PEX] to 0.
3210 +
3211 +config PCI_LAYERSCAPE_GEN4_EP
3212 + bool "Freescale Layerscpe PCIe Gen4 controller in EP mode"
3213 + depends on PCI
3214 + depends on OF && (ARM64 || ARCH_LAYERSCAPE)
3215 + depends on PCI_ENDPOINT
3216 + select PCIE_MOBIVEIL_EP
3217 + help
3218 + Say Y here if you want PCIe Gen4 controller support on
3219 + Layerscape SoCs. And the PCIe controller work in EP mode
3220 + by setting the RCW[HOST_AGT_PEX] to 1.
3221 +endmenu
3222 --- /dev/null
3223 +++ b/drivers/pci/mobiveil/Makefile
3224 @@ -0,0 +1,7 @@
3225 +# SPDX-License-Identifier: GPL-2.0
3226 +obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
3227 +obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
3228 +obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
3229 +obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
3230 +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4) += pci-layerscape-gen4.o
3231 +obj-$(CONFIG_PCI_LAYERSCAPE_GEN4_EP) += pci-layerscape-gen4-ep.o
3232 --- /dev/null
3233 +++ b/drivers/pci/mobiveil/pci-layerscape-gen4-ep.c
3234 @@ -0,0 +1,178 @@
3235 +// SPDX-License-Identifier: GPL-2.0
3236 +/*
3237 + * PCIe controller EP driver for Freescale Layerscape SoCs
3238 + *
3239 + * Copyright (C) 2018 NXP Semiconductor.
3240 + *
3241 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
3242 + */
3243 +
3244 +#include <linux/kernel.h>
3245 +#include <linux/init.h>
3246 +#include <linux/of_pci.h>
3247 +#include <linux/of_platform.h>
3248 +#include <linux/of_address.h>
3249 +#include <linux/pci.h>
3250 +#include <linux/platform_device.h>
3251 +#include <linux/resource.h>
3252 +
3253 +#include "pcie-mobiveil.h"
3254 +
3255 +struct ls_pcie_g4_ep {
3256 + struct mobiveil_pcie *mv_pci;
3257 +};
3258 +
3259 +#define to_ls_pcie_g4_ep(x) dev_get_drvdata((x)->dev)
3260 +
3261 +static const struct of_device_id ls_pcie_g4_ep_of_match[] = {
3262 + { .compatible = "fsl,lx2160a-pcie-ep",},
3263 + { },
3264 +};
3265 +
3266 +static void ls_pcie_g4_get_bar_num(struct mobiveil_pcie_ep *ep)
3267 +{
3268 + struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
3269 + u32 type, reg;
3270 + u8 bar;
3271 +
3272 + ep->bar_num = BAR_5 + 1;
3273 +
3274 + for (bar = BAR_0; bar <= BAR_5; bar++) {
3275 + reg = PCI_BASE_ADDRESS_0 + (4 * bar);
3276 + type = csr_readl(mv_pci, reg) &
3277 + PCI_BASE_ADDRESS_MEM_TYPE_MASK;
3278 + if (type & PCI_BASE_ADDRESS_MEM_TYPE_64)
3279 + ep->bar_num--;
3280 + }
3281 +}
3282 +
3283 +static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
3284 +{
3285 + struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
3286 + struct pci_epc *epc = ep->epc;
3287 + enum pci_barno bar;
3288 + int win_idx, val;
3289 +
3290 + /*
3291 + * Errata: unsupported request error on inbound posted write
3292 + * transaction, PCIe controller reports advisory error instead
3293 + * of uncorrectable error message to RC.
3294 + * workaround: set the bit20(unsupported_request_Error_severity) with
3295 + * value 1 in uncorrectable_Error_Severity_Register, make the
3296 + * unsupported request error generate the fatal error.
3297 + */
3298 + val = csr_readl(mv_pci, CFG_UNCORRECTABLE_ERROR_SEVERITY);
3299 + val |= 1 << UNSUPPORTED_REQUEST_ERROR_SHIFT;
3300 + csr_writel(mv_pci, val, CFG_UNCORRECTABLE_ERROR_SEVERITY);
3301 +
3302 + ls_pcie_g4_get_bar_num(ep);
3303 +
3304 + for (bar = BAR_0; bar < (ep->bar_num * ep->pf_num); bar++)
3305 + mobiveil_pcie_ep_reset_bar(mv_pci, bar);
3306 +
3307 + for (win_idx = 0; win_idx < MAX_IATU_OUT; win_idx++)
3308 + mobiveil_pcie_disable_ob_win(mv_pci, win_idx);
3309 +
3310 + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
3311 + epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
3312 +}
3313 +
3314 +static int ls_pcie_g4_ep_raise_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
3315 + enum pci_epc_irq_type type,
3316 + u16 interrupt_num)
3317 +{
3318 + struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
3319 +
3320 + switch (type) {
3321 + case PCI_EPC_IRQ_LEGACY:
3322 + return mobiveil_pcie_ep_raise_legacy_irq(ep, func_no);
3323 + case PCI_EPC_IRQ_MSI:
3324 + return mobiveil_pcie_ep_raise_msi_irq(ep, func_no,
3325 + interrupt_num);
3326 + case PCI_EPC_IRQ_MSIX:
3327 + return mobiveil_pcie_ep_raise_msix_irq(ep, func_no,
3328 + interrupt_num);
3329 + default:
3330 + dev_err(&mv_pci->pdev->dev, "UNKNOWN IRQ type\n");
3331 + }
3332 +
3333 + return 0;
3334 +}
3335 +
3336 +static struct mobiveil_pcie_ep_ops pcie_ep_ops = {
3337 + .ep_init = ls_pcie_g4_ep_init,
3338 + .raise_irq = ls_pcie_g4_ep_raise_irq,
3339 +};
3340 +
3341 +static int __init ls_pcie_gen4_add_pcie_ep(struct ls_pcie_g4_ep *ls_pcie_g4_ep,
3342 + struct platform_device *pdev)
3343 +{
3344 + struct mobiveil_pcie *mv_pci = ls_pcie_g4_ep->mv_pci;
3345 + struct device *dev = &pdev->dev;
3346 + struct mobiveil_pcie_ep *ep;
3347 + struct resource *res;
3348 + int ret;
3349 + struct device_node *np = dev->of_node;
3350 +
3351 + ep = &mv_pci->ep;
3352 + ep->ops = &pcie_ep_ops;
3353 +
3354 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
3355 + if (!res)
3356 + return -EINVAL;
3357 +
3358 + ep->phys_base = res->start;
3359 + ep->addr_size = resource_size(res);
3360 +
3361 + ret = of_property_read_u32(np, "max-functions", &ep->pf_num);
3362 + if (ret < 0)
3363 + ep->pf_num = 1;
3364 +
3365 + ret = mobiveil_pcie_ep_init(ep);
3366 + if (ret) {
3367 + dev_err(dev, "failed to initialize endpoint\n");
3368 + return ret;
3369 + }
3370 +
3371 + return 0;
3372 +}
3373 +
3374 +static int __init ls_pcie_g4_ep_probe(struct platform_device *pdev)
3375 +{
3376 + struct device *dev = &pdev->dev;
3377 + struct mobiveil_pcie *mv_pci;
3378 + struct ls_pcie_g4_ep *ls_pcie_g4_ep;
3379 + struct resource *res;
3380 + int ret;
3381 +
3382 + ls_pcie_g4_ep = devm_kzalloc(dev, sizeof(*ls_pcie_g4_ep), GFP_KERNEL);
3383 + if (!ls_pcie_g4_ep)
3384 + return -ENOMEM;
3385 +
3386 + mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
3387 + if (!mv_pci)
3388 + return -ENOMEM;
3389 +
3390 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
3391 + mv_pci->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
3392 + if (IS_ERR(mv_pci->csr_axi_slave_base))
3393 + return PTR_ERR(mv_pci->csr_axi_slave_base);
3394 +
3395 + mv_pci->pdev = pdev;
3396 + ls_pcie_g4_ep->mv_pci = mv_pci;
3397 +
3398 + platform_set_drvdata(pdev, ls_pcie_g4_ep);
3399 +
3400 + ret = ls_pcie_gen4_add_pcie_ep(ls_pcie_g4_ep, pdev);
3401 +
3402 + return ret;
3403 +}
3404 +
3405 +static struct platform_driver ls_pcie_g4_ep_driver = {
3406 + .driver = {
3407 + .name = "layerscape-pcie-gen4-ep",
3408 + .of_match_table = ls_pcie_g4_ep_of_match,
3409 + .suppress_bind_attrs = true,
3410 + },
3411 +};
3412 +builtin_platform_driver_probe(ls_pcie_g4_ep_driver, ls_pcie_g4_ep_probe);
3413 --- /dev/null
3414 +++ b/drivers/pci/mobiveil/pci-layerscape-gen4.c
3415 @@ -0,0 +1,292 @@
3416 +// SPDX-License-Identifier: GPL-2.0
3417 +/*
3418 + * PCIe host controller driver for NXP Layerscape SoCs
3419 + *
3420 + * Copyright 2018 NXP
3421 + *
3422 + * Author: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
3423 + */
3424 +
3425 +#include <linux/kernel.h>
3426 +#include <linux/interrupt.h>
3427 +#include <linux/init.h>
3428 +#include <linux/of_pci.h>
3429 +#include <linux/of_platform.h>
3430 +#include <linux/of_irq.h>
3431 +#include <linux/of_address.h>
3432 +#include <linux/pci.h>
3433 +#include <linux/platform_device.h>
3434 +#include <linux/resource.h>
3435 +#include <linux/mfd/syscon.h>
3436 +#include <linux/regmap.h>
3437 +
3438 +#include "pcie-mobiveil.h"
3439 +
3440 +/* LUT and PF control registers */
3441 +#define PCIE_LUT_OFF (0x80000)
3442 +#define PCIE_LUT_GCR (0x28)
3443 +#define PCIE_LUT_GCR_RRE (0)
3444 +
3445 +#define PCIE_PF_OFF (0xc0000)
3446 +#define PCIE_PF_INT_STAT (0x18)
3447 +#define PF_INT_STAT_PABRST (31)
3448 +
3449 +#define PCIE_PF_DBG (0x7fc)
3450 +#define PF_DBG_LTSSM_MASK (0x3f)
3451 +#define PF_DBG_WE (31)
3452 +#define PF_DBG_PABR (27)
3453 +
3454 +#define LS_PCIE_G4_LTSSM_L0 0x2d /* L0 state */
3455 +
3456 +#define to_ls_pcie_g4(x) platform_get_drvdata((x)->pdev)
3457 +
3458 +struct ls_pcie_g4 {
3459 + struct mobiveil_pcie *pci;
3460 + struct delayed_work dwork;
3461 + int irq;
3462 +};
3463 +
3464 +static inline u32 ls_pcie_g4_lut_readl(struct ls_pcie_g4 *pcie, u32 off)
3465 +{
3466 + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
3467 +}
3468 +
3469 +static inline void ls_pcie_g4_lut_writel(struct ls_pcie_g4 *pcie,
3470 + u32 off, u32 val)
3471 +{
3472 + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_LUT_OFF + off);
3473 +}
3474 +
3475 +static inline u32 ls_pcie_g4_pf_readl(struct ls_pcie_g4 *pcie, u32 off)
3476 +{
3477 + return ioread32(pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
3478 +}
3479 +
3480 +static inline void ls_pcie_g4_pf_writel(struct ls_pcie_g4 *pcie,
3481 + u32 off, u32 val)
3482 +{
3483 + iowrite32(val, pcie->pci->csr_axi_slave_base + PCIE_PF_OFF + off);
3484 +}
3485 +
3486 +static bool ls_pcie_g4_is_bridge(struct ls_pcie_g4 *pcie)
3487 +{
3488 + struct mobiveil_pcie *mv_pci = pcie->pci;
3489 + u32 header_type;
3490 +
3491 + header_type = csr_readb(mv_pci, PCI_HEADER_TYPE);
3492 + header_type &= 0x7f;
3493 +
3494 + return header_type == PCI_HEADER_TYPE_BRIDGE;
3495 +}
3496 +
3497 +static int ls_pcie_g4_link_up(struct mobiveil_pcie *pci)
3498 +{
3499 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
3500 + u32 state;
3501 +
3502 + state = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3503 + state = state & PF_DBG_LTSSM_MASK;
3504 +
3505 + if (state == LS_PCIE_G4_LTSSM_L0)
3506 + return 1;
3507 +
3508 + return 0;
3509 +}
3510 +
3511 +static void ls_pcie_g4_reinit_hw(struct ls_pcie_g4 *pcie)
3512 +{
3513 + struct mobiveil_pcie *mv_pci = pcie->pci;
3514 + u32 val, act_stat;
3515 + int to = 100;
3516 +
3517 + /* Poll for pab_csb_reset to set and PAB activity to clear */
3518 + do {
3519 + usleep_range(10, 15);
3520 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_INT_STAT);
3521 + act_stat = csr_readl(mv_pci, PAB_ACTIVITY_STAT);
3522 + } while (((val & 1 << PF_INT_STAT_PABRST) == 0 || act_stat) && to--);
3523 + if (to < 0) {
3524 + dev_err(&mv_pci->pdev->dev, "poll PABRST&PABACT timeout\n");
3525 + return;
3526 + }
3527 +
3528 + /* clear PEX_RESET bit in PEX_PF0_DBG register */
3529 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3530 + val |= 1 << PF_DBG_WE;
3531 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
3532 +
3533 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3534 + val |= 1 << PF_DBG_PABR;
3535 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
3536 +
3537 + val = ls_pcie_g4_pf_readl(pcie, PCIE_PF_DBG);
3538 + val &= ~(1 << PF_DBG_WE);
3539 + ls_pcie_g4_pf_writel(pcie, PCIE_PF_DBG, val);
3540 +
3541 + mobiveil_host_init(mv_pci, true);
3542 +
3543 + to = 100;
3544 + while (!ls_pcie_g4_link_up(mv_pci) && to--)
3545 + usleep_range(200, 250);
3546 + if (to < 0)
3547 + dev_err(&mv_pci->pdev->dev, "PCIe link trainning timeout\n");
3548 +}
3549 +
3550 +static irqreturn_t ls_pcie_g4_handler(int irq, void *dev_id)
3551 +{
3552 + struct ls_pcie_g4 *pcie = (struct ls_pcie_g4 *)dev_id;
3553 + struct mobiveil_pcie *mv_pci = pcie->pci;
3554 + u32 val;
3555 +
3556 + val = csr_readl(mv_pci, PAB_INTP_AMBA_MISC_STAT);
3557 + if (!val)
3558 + return IRQ_NONE;
3559 +
3560 + if (val & PAB_INTP_RESET)
3561 + schedule_delayed_work(&pcie->dwork, msecs_to_jiffies(1));
3562 +
3563 + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_STAT);
3564 +
3565 + return IRQ_HANDLED;
3566 +}
3567 +
3568 +static int ls_pcie_g4_interrupt_init(struct mobiveil_pcie *mv_pci)
3569 +{
3570 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(mv_pci);
3571 + u32 val;
3572 + int ret;
3573 +
3574 + pcie->irq = platform_get_irq_byname(mv_pci->pdev, "intr");
3575 + if (pcie->irq < 0) {
3576 + dev_err(&mv_pci->pdev->dev, "Can't get 'intr' irq.\n");
3577 + return pcie->irq;
3578 + }
3579 + ret = devm_request_irq(&mv_pci->pdev->dev, pcie->irq,
3580 + ls_pcie_g4_handler, IRQF_SHARED,
3581 + mv_pci->pdev->name, pcie);
3582 + if (ret) {
3583 + dev_err(&mv_pci->pdev->dev, "Can't register PCIe IRQ.\n");
3584 + return ret;
3585 + }
3586 +
3587 + /* Enable interrupts */
3588 + val = PAB_INTP_INTX_MASK | PAB_INTP_MSI | PAB_INTP_RESET |
3589 + PAB_INTP_PCIE_UE | PAB_INTP_IE_PMREDI | PAB_INTP_IE_EC;
3590 + csr_writel(mv_pci, val, PAB_INTP_AMBA_MISC_ENB);
3591 +
3592 + return 0;
3593 +}
3594 +
3595 +static void ls_pcie_g4_reset(struct work_struct *work)
3596 +{
3597 + struct delayed_work *dwork = container_of(work, struct delayed_work,
3598 + work);
3599 + struct ls_pcie_g4 *pcie = container_of(dwork, struct ls_pcie_g4, dwork);
3600 + struct mobiveil_pcie *mv_pci = pcie->pci;
3601 + u16 ctrl;
3602 +
3603 + ctrl = csr_readw(mv_pci, PCI_BRIDGE_CONTROL);
3604 + ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3605 + csr_writew(mv_pci, ctrl, PCI_BRIDGE_CONTROL);
3606 + ls_pcie_g4_reinit_hw(pcie);
3607 +}
3608 +
3609 +static int ls_pcie_g4_read_other_conf(struct pci_bus *bus, unsigned int devfn,
3610 + int where, int size, u32 *val)
3611 +{
3612 + struct mobiveil_pcie *pci = bus->sysdata;
3613 + struct ls_pcie_g4 *pcie = to_ls_pcie_g4(pci);
3614 + int ret;
3615 +
3616 + if (where == PCI_VENDOR_ID)
3617 + ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR,
3618 + 0 << PCIE_LUT_GCR_RRE);
3619 +
3620 + ret = pci_generic_config_read(bus, devfn, where, size, val);
3621 +
3622 + if (where == PCI_VENDOR_ID)
3623 + ls_pcie_g4_lut_writel(pcie, PCIE_LUT_GCR,
3624 + 1 << PCIE_LUT_GCR_RRE);
3625 +
3626 + return ret;
3627 +}
3628 +
3629 +static struct mobiveil_rp_ops ls_pcie_g4_rp_ops = {
3630 + .interrupt_init = ls_pcie_g4_interrupt_init,
3631 + .read_other_conf = ls_pcie_g4_read_other_conf,
3632 +};
3633 +
3634 +static const struct mobiveil_pab_ops ls_pcie_g4_pab_ops = {
3635 + .link_up = ls_pcie_g4_link_up,
3636 +};
3637 +
3638 +static void workaround_tkt381274(struct ls_pcie_g4 *pcie)
3639 +{
3640 + struct mobiveil_pcie *mv_pci = pcie->pci;
3641 + u32 val;
3642 +
3643 + /* Set ACK latency timeout */
3644 + val = csr_readl(mv_pci, GPEX_ACK_REPLAY_TO);
3645 + val &= ~(ACK_LAT_TO_VAL_MASK << ACK_LAT_TO_VAL_SHIFT);
3646 + val |= (4 << ACK_LAT_TO_VAL_SHIFT);
3647 + csr_writel(mv_pci, val, GPEX_ACK_REPLAY_TO);
3648 +}
3649 +
3650 +static int __init ls_pcie_g4_probe(struct platform_device *pdev)
3651 +{
3652 + struct device *dev = &pdev->dev;
3653 + struct mobiveil_pcie *mv_pci;
3654 + struct ls_pcie_g4 *pcie;
3655 + struct device_node *np = dev->of_node;
3656 + int ret;
3657 +
3658 + if (!of_parse_phandle(np, "msi-parent", 0)) {
3659 + dev_err(dev, "failed to find msi-parent\n");
3660 + return -EINVAL;
3661 + }
3662 +
3663 + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
3664 + if (!pcie)
3665 + return -ENOMEM;
3666 +
3667 + mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
3668 + if (!mv_pci)
3669 + return -ENOMEM;
3670 +
3671 + mv_pci->pdev = pdev;
3672 + mv_pci->ops = &ls_pcie_g4_pab_ops;
3673 + mv_pci->rp.ops = &ls_pcie_g4_rp_ops;
3674 + pcie->pci = mv_pci;
3675 +
3676 + platform_set_drvdata(pdev, pcie);
3677 +
3678 + INIT_DELAYED_WORK(&pcie->dwork, ls_pcie_g4_reset);
3679 +
3680 + ret = mobiveil_pcie_host_probe(mv_pci);
3681 + if (ret) {
3682 + dev_err(dev, "fail to probe!\n");
3683 + return ret;
3684 + }
3685 +
3686 + if (!ls_pcie_g4_is_bridge(pcie))
3687 + return -ENODEV;
3688 +
3689 + workaround_tkt381274(pcie);
3690 +
3691 + return 0;
3692 +}
3693 +
3694 +static const struct of_device_id ls_pcie_g4_of_match[] = {
3695 + { .compatible = "fsl,lx2160a-pcie", },
3696 + { },
3697 +};
3698 +
3699 +static struct platform_driver ls_pcie_g4_driver = {
3700 + .driver = {
3701 + .name = "layerscape-pcie-gen4",
3702 + .of_match_table = ls_pcie_g4_of_match,
3703 + .suppress_bind_attrs = true,
3704 + },
3705 +};
3706 +
3707 +builtin_platform_driver_probe(ls_pcie_g4_driver, ls_pcie_g4_probe);
3708 --- /dev/null
3709 +++ b/drivers/pci/mobiveil/pcie-mobiveil-ep.c
3710 @@ -0,0 +1,512 @@
3711 +// SPDX-License-Identifier: GPL-2.0
3712 +/**
3713 + * Mobiveil PCIe Endpoint controller driver
3714 + *
3715 + * Copyright (C) 2018 NXP Semiconductor.
3716 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
3717 + */
3718 +
3719 +#include <linux/of.h>
3720 +#include <linux/pci-epc.h>
3721 +#include <linux/pci-epf.h>
3722 +#include <linux/platform_device.h>
3723 +#include "pcie-mobiveil.h"
3724 +
3725 +void mobiveil_pcie_ep_linkup(struct mobiveil_pcie_ep *ep)
3726 +{
3727 + struct pci_epc *epc = ep->epc;
3728 +
3729 + pci_epc_linkup(epc);
3730 +}
3731 +
3732 +static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
3733 + enum pci_barno bar)
3734 +{
3735 + csr_writel(pcie, bar, GPEX_BAR_SELECT);
3736 + csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
3737 + csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW);
3738 +}
3739 +
3740 +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie,
3741 + enum pci_barno bar)
3742 +{
3743 + __mobiveil_pcie_ep_reset_bar(pcie, bar);
3744 +}
3745 +
3746 +static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
3747 + u8 cap_ptr, u8 cap)
3748 +{
3749 + u8 cap_id, next_cap_ptr;
3750 + u16 reg;
3751 +
3752 + reg = csr_readw(pcie, cap_ptr);
3753 + next_cap_ptr = (reg & 0xff00) >> 8;
3754 + cap_id = (reg & 0x00ff);
3755 +
3756 + if (cap_id == cap)
3757 + return cap_ptr;
3758 +
3759 + if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX)
3760 + return 0;
3761 +
3762 + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
3763 +}
3764 +
3765 +static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie *pcie,
3766 + u8 cap)
3767 +{
3768 + u8 next_cap_ptr;
3769 + u16 reg;
3770 +
3771 + reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
3772 + next_cap_ptr = (reg & 0x00ff);
3773 +
3774 + if (!next_cap_ptr)
3775 + return 0;
3776 +
3777 + return __mobiveil_pcie_ep_find_next_cap(pcie, next_cap_ptr, cap);
3778 +}
3779 +
3780 +static int mobiveil_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
3781 + struct pci_epf_header *hdr)
3782 +{
3783 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3784 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3785 +
3786 + csr_writew(pcie, hdr->vendorid, PCI_VENDOR_ID);
3787 + csr_writew(pcie, hdr->deviceid, PCI_DEVICE_ID);
3788 + csr_writeb(pcie, hdr->revid, PCI_REVISION_ID);
3789 + csr_writeb(pcie, hdr->progif_code, PCI_CLASS_PROG);
3790 + csr_writew(pcie, hdr->subclass_code | hdr->baseclass_code << 8,
3791 + PCI_CLASS_DEVICE);
3792 + csr_writeb(pcie, hdr->cache_line_size, PCI_CACHE_LINE_SIZE);
3793 + csr_writew(pcie, hdr->subsys_vendor_id, PCI_SUBSYSTEM_VENDOR_ID);
3794 + csr_writew(pcie, hdr->subsys_id, PCI_SUBSYSTEM_ID);
3795 + csr_writeb(pcie, hdr->interrupt_pin, PCI_INTERRUPT_PIN);
3796 +
3797 + return 0;
3798 +}
3799 +
3800 +static int mobiveil_pcie_ep_inbound_atu(struct mobiveil_pcie_ep *ep,
3801 + u8 func_no, enum pci_barno bar,
3802 + dma_addr_t cpu_addr)
3803 +{
3804 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3805 +
3806 + program_ib_windows_ep(pcie, func_no, bar, cpu_addr);
3807 +
3808 + return 0;
3809 +}
3810 +
3811 +static int mobiveil_pcie_ep_outbound_atu(struct mobiveil_pcie_ep *ep,
3812 + phys_addr_t phys_addr,
3813 + u64 pci_addr, u8 func_no,
3814 + size_t size)
3815 +{
3816 + int ret;
3817 + u32 free_win;
3818 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3819 +
3820 + free_win = find_first_zero_bit(ep->ob_window_map, ep->num_ob_windows);
3821 + if (free_win >= ep->num_ob_windows) {
3822 + dev_err(&pcie->pdev->dev, "No free outbound window\n");
3823 + return -EINVAL;
3824 + }
3825 +
3826 + ret = program_ob_windows_ep(pcie, free_win, MEM_WINDOW_TYPE,
3827 + phys_addr, pci_addr, func_no, size);
3828 + if (ret < 0) {
3829 + dev_err(&pcie->pdev->dev, "Failed to program IB window\n");
3830 + return ret;
3831 + }
3832 +
3833 + set_bit(free_win, ep->ob_window_map);
3834 + ep->outbound_addr[free_win] = phys_addr;
3835 +
3836 + return 0;
3837 +}
3838 +
3839 +static void mobiveil_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
3840 + struct pci_epf_bar *epf_bar)
3841 +{
3842 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3843 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3844 + enum pci_barno bar = epf_bar->barno;
3845 +
3846 + if (bar < ep->bar_num) {
3847 + __mobiveil_pcie_ep_reset_bar(pcie,
3848 + func_no * ep->bar_num + bar);
3849 +
3850 + mobiveil_pcie_disable_ib_win_ep(pcie, func_no, bar);
3851 + }
3852 +}
3853 +
3854 +static int mobiveil_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
3855 + struct pci_epf_bar *epf_bar)
3856 +{
3857 + int ret;
3858 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3859 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3860 + enum pci_barno bar = epf_bar->barno;
3861 + size_t size = epf_bar->size;
3862 +
3863 + if (bar < ep->bar_num) {
3864 + ret = mobiveil_pcie_ep_inbound_atu(ep, func_no, bar,
3865 + epf_bar->phys_addr);
3866 + if (ret)
3867 + return ret;
3868 +
3869 + csr_writel(pcie, func_no * ep->bar_num + bar,
3870 + GPEX_BAR_SELECT);
3871 + csr_writel(pcie, lower_32_bits(~(size - 1)),
3872 + GPEX_BAR_SIZE_LDW);
3873 + csr_writel(pcie, upper_32_bits(~(size - 1)),
3874 + GPEX_BAR_SIZE_UDW);
3875 + }
3876 +
3877 + return 0;
3878 +}
3879 +
3880 +static int mobiveil_pcie_find_index(struct mobiveil_pcie_ep *ep,
3881 + phys_addr_t addr,
3882 + u32 *atu_index)
3883 +{
3884 + u32 index;
3885 +
3886 + for (index = 0; index < ep->num_ob_windows; index++) {
3887 + if (ep->outbound_addr[index] != addr)
3888 + continue;
3889 + *atu_index = index;
3890 + return 0;
3891 + }
3892 +
3893 + return -EINVAL;
3894 +}
3895 +
3896 +static void mobiveil_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
3897 + phys_addr_t addr)
3898 +{
3899 + int ret;
3900 + u32 atu_index;
3901 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3902 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3903 +
3904 + ret = mobiveil_pcie_find_index(ep, addr, &atu_index);
3905 + if (ret < 0)
3906 + return;
3907 +
3908 + mobiveil_pcie_disable_ob_win(pcie, atu_index);
3909 + clear_bit(atu_index, ep->ob_window_map);
3910 +}
3911 +
3912 +static int mobiveil_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
3913 + phys_addr_t addr,
3914 + u64 pci_addr, size_t size)
3915 +{
3916 + int ret;
3917 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3918 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3919 +
3920 + ret = mobiveil_pcie_ep_outbound_atu(ep, addr, pci_addr, func_no, size);
3921 + if (ret) {
3922 + dev_err(&pcie->pdev->dev, "Failed to enable address\n");
3923 + return ret;
3924 + }
3925 +
3926 + return 0;
3927 +}
3928 +
3929 +static int mobiveil_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
3930 +{
3931 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3932 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3933 + u32 val, reg;
3934 +
3935 + if (!ep->msi_cap)
3936 + return -EINVAL;
3937 +
3938 + reg = ep->msi_cap + PCI_MSI_FLAGS;
3939 + val = csr_readw(pcie, reg);
3940 + if (!(val & PCI_MSI_FLAGS_ENABLE))
3941 + return -EINVAL;
3942 +
3943 + val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
3944 +
3945 + return val;
3946 +}
3947 +
3948 +static int mobiveil_pcie_ep_set_msi(struct pci_epc *epc,
3949 + u8 func_no, u8 interrupts)
3950 +{
3951 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3952 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3953 + u32 val, reg;
3954 +
3955 + if (!ep->msi_cap)
3956 + return -EINVAL;
3957 +
3958 + reg = ep->msi_cap + PCI_MSI_FLAGS;
3959 + val = csr_readw(pcie, reg);
3960 + val &= ~PCI_MSI_FLAGS_QMASK;
3961 + val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
3962 + csr_writew(pcie, val, reg);
3963 +
3964 + return 0;
3965 +}
3966 +
3967 +static int mobiveil_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
3968 +{
3969 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3970 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3971 + u32 val, reg;
3972 +
3973 + if (!ep->msix_cap)
3974 + return -EINVAL;
3975 +
3976 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
3977 + val = csr_readw(pcie, reg);
3978 + if (!(val & PCI_MSIX_FLAGS_ENABLE))
3979 + return -EINVAL;
3980 +
3981 + val &= PCI_MSIX_FLAGS_QSIZE;
3982 +
3983 + return val;
3984 +}
3985 +
3986 +static int mobiveil_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no,
3987 + u16 interrupts)
3988 +{
3989 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
3990 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
3991 + u32 val, reg;
3992 +
3993 + if (!ep->msix_cap)
3994 + return -EINVAL;
3995 +
3996 + reg = ep->msix_cap + PCI_MSIX_FLAGS;
3997 + val = csr_readw(pcie, reg);
3998 + val &= ~PCI_MSIX_FLAGS_QSIZE;
3999 + val |= interrupts;
4000 + csr_writew(pcie, val, reg);
4001 +
4002 + return 0;
4003 +}
4004 +
4005 +static int mobiveil_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
4006 + enum pci_epc_irq_type type,
4007 + u16 interrupt_num)
4008 +{
4009 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
4010 +
4011 + if (!ep->ops->raise_irq)
4012 + return -EINVAL;
4013 +
4014 + return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
4015 +}
4016 +
4017 +static const struct pci_epc_ops epc_ops = {
4018 + .write_header = mobiveil_pcie_ep_write_header,
4019 + .set_bar = mobiveil_pcie_ep_set_bar,
4020 + .clear_bar = mobiveil_pcie_ep_clear_bar,
4021 + .map_addr = mobiveil_pcie_ep_map_addr,
4022 + .unmap_addr = mobiveil_pcie_ep_unmap_addr,
4023 + .set_msi = mobiveil_pcie_ep_set_msi,
4024 + .get_msi = mobiveil_pcie_ep_get_msi,
4025 + .set_msix = mobiveil_pcie_ep_set_msix,
4026 + .get_msix = mobiveil_pcie_ep_get_msix,
4027 + .raise_irq = mobiveil_pcie_ep_raise_irq,
4028 +};
4029 +
4030 +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no)
4031 +{
4032 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4033 +
4034 + dev_err(&pcie->pdev->dev, "EP cannot trigger legacy IRQs\n");
4035 +
4036 + return -EINVAL;
4037 +}
4038 +
4039 +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
4040 + u8 interrupt_num)
4041 +{
4042 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4043 + struct pci_epc *epc = ep->epc;
4044 + u16 msg_ctrl, msg_data;
4045 + u32 msg_addr_lower, msg_addr_upper, reg;
4046 + u64 msg_addr;
4047 + u32 func_num;
4048 + bool has_upper;
4049 + int ret;
4050 +
4051 + if (!ep->msi_cap)
4052 + return -EINVAL;
4053 +
4054 + func_num = csr_readl(pcie, PAB_CTRL);
4055 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4056 + func_num |= (func_no & FUNC_SEL_MASK) << FUNC_SEL_SHIFT;
4057 + csr_writel(pcie, func_num, PAB_CTRL);
4058 +
4059 + /* Raise MSI per the PCI Local Bus Specification Revision 3.0, 6.8.1. */
4060 + reg = ep->msi_cap + PCI_MSI_FLAGS;
4061 + msg_ctrl = csr_readw(pcie, reg);
4062 + has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
4063 + reg = ep->msi_cap + PCI_MSI_ADDRESS_LO;
4064 + msg_addr_lower = csr_readl(pcie, reg);
4065 + if (has_upper) {
4066 + reg = ep->msi_cap + PCI_MSI_ADDRESS_HI;
4067 + msg_addr_upper = csr_readl(pcie, reg);
4068 + reg = ep->msi_cap + PCI_MSI_DATA_64;
4069 + msg_data = csr_readw(pcie, reg);
4070 + } else {
4071 + msg_addr_upper = 0;
4072 + reg = ep->msi_cap + PCI_MSI_DATA_32;
4073 + msg_data = csr_readw(pcie, reg);
4074 + }
4075 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
4076 +
4077 + func_num = csr_readl(pcie, PAB_CTRL);
4078 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4079 + csr_writel(pcie, func_num, PAB_CTRL);
4080 +
4081 + ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
4082 + msg_addr, epc->mem->page_size);
4083 + if (ret)
4084 + return ret;
4085 +
4086 + writel(msg_data | (interrupt_num - 1), ep->msi_mem);
4087 +
4088 + mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
4089 +
4090 + return 0;
4091 +}
4092 +
4093 +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
4094 + u16 interrupt_num)
4095 +{
4096 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4097 + struct pci_epc *epc = ep->epc;
4098 + u32 msg_addr_upper, msg_addr_lower;
4099 + u32 msg_data;
4100 + u64 msg_addr;
4101 + u32 func_num;
4102 + int ret;
4103 +
4104 + func_num = csr_readl(pcie, PAB_CTRL);
4105 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4106 + func_num |= (func_no & FUNC_SEL_MASK) << FUNC_SEL_SHIFT;
4107 + csr_writel(pcie, func_num, PAB_CTRL);
4108 +
4109 + msg_addr_lower = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
4110 + PCI_MSIX_ENTRY_LOWER_ADDR +
4111 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
4112 + msg_addr_upper = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
4113 + PCI_MSIX_ENTRY_UPPER_ADDR +
4114 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
4115 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
4116 + msg_data = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
4117 + PCI_MSIX_ENTRY_DATA +
4118 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
4119 +
4120 + func_num = csr_readl(pcie, PAB_CTRL);
4121 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
4122 + csr_writel(pcie, func_num, PAB_CTRL);
4123 +
4124 + ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
4125 + msg_addr, epc->mem->page_size);
4126 + if (ret)
4127 + return ret;
4128 +
4129 + writel(msg_data, ep->msi_mem);
4130 +
4131 + mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
4132 +
4133 + return 0;
4134 +}
4135 +
4136 +void mobiveil_pcie_ep_exit(struct mobiveil_pcie_ep *ep)
4137 +{
4138 + struct pci_epc *epc = ep->epc;
4139 +
4140 + pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
4141 + epc->mem->page_size);
4142 +
4143 + pci_epc_mem_exit(epc);
4144 +}
4145 +
4146 +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep)
4147 +{
4148 + int ret;
4149 + void *addr;
4150 + struct pci_epc *epc;
4151 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
4152 + struct device *dev = &pcie->pdev->dev;
4153 + struct device_node *np = dev->of_node;
4154 +
4155 + if (!pcie->csr_axi_slave_base) {
4156 + dev_err(dev, "csr_base is not populated\n");
4157 + return -EINVAL;
4158 + }
4159 +
4160 + ret = of_property_read_u32(np, "num-ob-windows", &ep->num_ob_windows);
4161 + if (ret < 0) {
4162 + dev_err(dev, "Unable to read *num-ob-windows* property\n");
4163 + return ret;
4164 + }
4165 +
4166 + if (ep->num_ob_windows > MAX_IATU_OUT) {
4167 + dev_err(dev, "Invalid *num-ob-windows*\n");
4168 + return -EINVAL;
4169 + }
4170 + ep->ob_window_map = devm_kcalloc(dev,
4171 + BITS_TO_LONGS(ep->num_ob_windows),
4172 + sizeof(long),
4173 + GFP_KERNEL);
4174 + if (!ep->ob_window_map)
4175 + return -ENOMEM;
4176 +
4177 + addr = devm_kcalloc(dev, ep->num_ob_windows, sizeof(phys_addr_t),
4178 + GFP_KERNEL);
4179 + if (!addr)
4180 + return -ENOMEM;
4181 + ep->outbound_addr = addr;
4182 +
4183 + mobiveil_pcie_enable_bridge_pio(pcie);
4184 + mobiveil_pcie_enable_engine_apio(pcie);
4185 + mobiveil_pcie_enable_engine_ppio(pcie);
4186 + mobiveil_pcie_enable_msi_ep(pcie);
4187 +
4188 + epc = devm_pci_epc_create(dev, &epc_ops);
4189 + if (IS_ERR(epc)) {
4190 + dev_err(dev, "Failed to create epc device\n");
4191 + return PTR_ERR(epc);
4192 + }
4193 +
4194 + ep->epc = epc;
4195 + epc_set_drvdata(epc, ep);
4196 +
4197 + ep->msi_cap = mobiveil_pcie_ep_find_capability(pcie, PCI_CAP_ID_MSI);
4198 +
4199 + ep->msix_cap = mobiveil_pcie_ep_find_capability(pcie,
4200 + PCI_CAP_ID_MSIX);
4201 +
4202 + if (ep->ops->ep_init)
4203 + ep->ops->ep_init(ep);
4204 +
4205 + epc->max_functions = ep->pf_num;
4206 +
4207 + ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
4208 + ep->page_size);
4209 + if (ret < 0) {
4210 + dev_err(dev, "Failed to initialize address space\n");
4211 + return ret;
4212 + }
4213 +
4214 + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
4215 + epc->mem->page_size);
4216 + if (!ep->msi_mem) {
4217 + dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
4218 + return -ENOMEM;
4219 + }
4220 +
4221 + return 0;
4222 +}
4223 --- /dev/null
4224 +++ b/drivers/pci/mobiveil/pcie-mobiveil-host.c
4225 @@ -0,0 +1,640 @@
4226 +// SPDX-License-Identifier: GPL-2.0
4227 +/*
4228 + * PCIe host controller driver for Mobiveil PCIe Host controller
4229 + *
4230 + * Copyright (c) 2018 Mobiveil Inc.
4231 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
4232 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
4233 + */
4234 +
4235 +#include <linux/init.h>
4236 +#include <linux/interrupt.h>
4237 +#include <linux/irq.h>
4238 +#include <linux/irqchip/chained_irq.h>
4239 +#include <linux/irqdomain.h>
4240 +#include <linux/kernel.h>
4241 +#include <linux/module.h>
4242 +#include <linux/msi.h>
4243 +#include <linux/of_address.h>
4244 +#include <linux/of_irq.h>
4245 +#include <linux/of_platform.h>
4246 +#include <linux/of_pci.h>
4247 +#include <linux/pci.h>
4248 +#include <linux/platform_device.h>
4249 +#include <linux/slab.h>
4250 +
4251 +#include "pcie-mobiveil.h"
4252 +
4253 +static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
4254 +{
4255 + struct mobiveil_pcie *pcie = bus->sysdata;
4256 +
4257 + /* If there is no link, then there is no device */
4258 + if (bus->number > pcie->rp.root_bus_nr && !mobiveil_pcie_link_up(pcie))
4259 + return false;
4260 +
4261 + /* Only one device down on each root port */
4262 + if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
4263 + return false;
4264 +
4265 + /*
4266 + * Do not read more than one device on the bus directly
4267 + * attached to RC
4268 + */
4269 + if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0))
4270 + return false;
4271 +
4272 + return true;
4273 +}
4274 +
4275 +/*
4276 + * mobiveil_pcie_map_bus - routine to get the configuration base of either
4277 + * root port or endpoint
4278 + */
4279 +static void __iomem *mobiveil_pcie_map_bus(struct pci_bus *bus,
4280 + unsigned int devfn, int where)
4281 +{
4282 + struct mobiveil_pcie *pcie = bus->sysdata;
4283 + u32 value;
4284 +
4285 + if (!mobiveil_pcie_valid_device(bus, devfn))
4286 + return NULL;
4287 +
4288 + /* RC config access */
4289 + if (bus->number == pcie->rp.root_bus_nr)
4290 + return pcie->csr_axi_slave_base + where;
4291 +
4292 + /*
4293 + * EP config access (in Config/APIO space)
4294 + * Program PEX Address base (31..16 bits) with appropriate value
4295 + * (BDF) in PAB_AXI_AMAP_PEX_WIN_L0 Register.
4296 + * Relies on pci_lock serialization
4297 + */
4298 + value = bus->number << PAB_BUS_SHIFT |
4299 + PCI_SLOT(devfn) << PAB_DEVICE_SHIFT |
4300 + PCI_FUNC(devfn) << PAB_FUNCTION_SHIFT;
4301 +
4302 + csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0));
4303 +
4304 + return pcie->rp.config_axi_slave_base + where;
4305 +}
4306 +
4307 +static int mobiveil_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
4308 + int where, int size, u32 *val)
4309 +{
4310 + struct mobiveil_pcie *pcie = bus->sysdata;
4311 + struct root_port *rp = &pcie->rp;
4312 +
4313 + if (bus->number > rp->root_bus_nr && rp->ops->read_other_conf)
4314 + return rp->ops->read_other_conf(bus, devfn, where, size, val);
4315 +
4316 + return pci_generic_config_read(bus, devfn, where, size, val);
4317 +}
4318 +static struct pci_ops mobiveil_pcie_ops = {
4319 + .map_bus = mobiveil_pcie_map_bus,
4320 + .read = mobiveil_pcie_config_read,
4321 + .write = pci_generic_config_write,
4322 +};
4323 +
4324 +static void mobiveil_pcie_isr(struct irq_desc *desc)
4325 +{
4326 + struct irq_chip *chip = irq_desc_get_chip(desc);
4327 + struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc);
4328 + struct device *dev = &pcie->pdev->dev;
4329 + struct mobiveil_msi *msi = &pcie->rp.msi;
4330 + u32 msi_data, msi_addr_lo, msi_addr_hi;
4331 + u32 intr_status, msi_status;
4332 + unsigned long shifted_status;
4333 + u32 bit, virq, val, mask;
4334 +
4335 + /*
4336 + * The core provides a single interrupt for both INTx/MSI messages.
4337 + * So we'll read both INTx and MSI status
4338 + */
4339 +
4340 + chained_irq_enter(chip, desc);
4341 +
4342 + /* read INTx status */
4343 + val = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
4344 + mask = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
4345 + intr_status = val & mask;
4346 +
4347 + /* Handle INTx */
4348 + if (intr_status & PAB_INTP_INTX_MASK) {
4349 + shifted_status = csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT);
4350 + shifted_status &= PAB_INTP_INTX_MASK;
4351 + shifted_status >>= PAB_INTX_START;
4352 + do {
4353 + for_each_set_bit(bit, &shifted_status, PCI_NUM_INTX) {
4354 + virq = irq_find_mapping(pcie->rp.intx_domain,
4355 + bit + 1);
4356 + if (virq)
4357 + generic_handle_irq(virq);
4358 + else
4359 + dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n",
4360 + bit);
4361 +
4362 + /* clear interrupt handled */
4363 + csr_writel(pcie, 1 << (PAB_INTX_START + bit),
4364 + PAB_INTP_AMBA_MISC_STAT);
4365 + }
4366 +
4367 + shifted_status = csr_readl(pcie,
4368 + PAB_INTP_AMBA_MISC_STAT);
4369 + shifted_status &= PAB_INTP_INTX_MASK;
4370 + shifted_status >>= PAB_INTX_START;
4371 + } while (shifted_status != 0);
4372 + }
4373 +
4374 + /* read extra MSI status register */
4375 + msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET);
4376 +
4377 + /* handle MSI interrupts */
4378 + while (msi_status & 1) {
4379 + msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET);
4380 +
4381 + /*
4382 + * MSI_STATUS_OFFSET register gets updated to zero
4383 + * once we pop not only the MSI data but also address
4384 + * from MSI hardware FIFO. So keeping these following
4385 + * two dummy reads.
4386 + */
4387 + msi_addr_lo = readl_relaxed(pcie->apb_csr_base +
4388 + MSI_ADDR_L_OFFSET);
4389 + msi_addr_hi = readl_relaxed(pcie->apb_csr_base +
4390 + MSI_ADDR_H_OFFSET);
4391 + dev_dbg(dev, "MSI registers, data: %08x, addr: %08x:%08x\n",
4392 + msi_data, msi_addr_hi, msi_addr_lo);
4393 +
4394 + virq = irq_find_mapping(msi->dev_domain, msi_data);
4395 + if (virq)
4396 + generic_handle_irq(virq);
4397 +
4398 + msi_status = readl_relaxed(pcie->apb_csr_base +
4399 + MSI_STATUS_OFFSET);
4400 + }
4401 +
4402 + /* Clear the interrupt status */
4403 + csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT);
4404 + chained_irq_exit(chip, desc);
4405 +}
4406 +
4407 +static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie)
4408 +{
4409 + struct device *dev = &pcie->pdev->dev;
4410 + struct platform_device *pdev = pcie->pdev;
4411 + struct device_node *node = dev->of_node;
4412 + struct resource *res;
4413 +
4414 + /* map config resource */
4415 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4416 + "config_axi_slave");
4417 + pcie->rp.config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
4418 + if (IS_ERR(pcie->rp.config_axi_slave_base))
4419 + return PTR_ERR(pcie->rp.config_axi_slave_base);
4420 + pcie->rp.ob_io_res = res;
4421 +
4422 + /* map csr resource */
4423 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4424 + "csr_axi_slave");
4425 + pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
4426 + if (IS_ERR(pcie->csr_axi_slave_base))
4427 + return PTR_ERR(pcie->csr_axi_slave_base);
4428 + pcie->pcie_reg_base = res->start;
4429 +
4430 + /* read the number of windows requested */
4431 + if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins))
4432 + pcie->apio_wins = MAX_PIO_WINDOWS;
4433 +
4434 + if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins))
4435 + pcie->ppio_wins = MAX_PIO_WINDOWS;
4436 +
4437 + return 0;
4438 +}
4439 +
4440 +static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie)
4441 +{
4442 + phys_addr_t msg_addr = pcie->pcie_reg_base;
4443 + struct mobiveil_msi *msi = &pcie->rp.msi;
4444 +
4445 + msi->num_of_vectors = PCI_NUM_MSI;
4446 + msi->msi_pages_phys = (phys_addr_t)msg_addr;
4447 +
4448 + writel_relaxed(lower_32_bits(msg_addr),
4449 + pcie->apb_csr_base + MSI_BASE_LO_OFFSET);
4450 + writel_relaxed(upper_32_bits(msg_addr),
4451 + pcie->apb_csr_base + MSI_BASE_HI_OFFSET);
4452 + writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET);
4453 + writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET);
4454 +}
4455 +
4456 +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit)
4457 +{
4458 + u32 value, pab_ctrl, type;
4459 + struct resource_entry *win;
4460 + int i;
4461 +
4462 + /* Disable all inbound/outbound windows */
4463 + for (i = 0; i < pcie->apio_wins; i++)
4464 + mobiveil_pcie_disable_ob_win(pcie, i);
4465 + for (i = 0; i < pcie->ppio_wins; i++)
4466 + mobiveil_pcie_disable_ib_win(pcie, i);
4467 +
4468 + pcie->ib_wins_configured = 0;
4469 + pcie->ob_wins_configured = 0;
4470 +
4471 + if (!reinit) {
4472 + /* setup bus numbers */
4473 + value = csr_readl(pcie, PCI_PRIMARY_BUS);
4474 + value &= 0xff000000;
4475 + value |= 0x00ff0100;
4476 + csr_writel(pcie, value, PCI_PRIMARY_BUS);
4477 + }
4478 +
4479 + /*
4480 + * program Bus Master Enable Bit in Command Register in PAB Config
4481 + * Space
4482 + */
4483 + value = csr_readl(pcie, PCI_COMMAND);
4484 + value |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
4485 + csr_writel(pcie, value, PCI_COMMAND);
4486 +
4487 + /*
4488 + * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL
4489 + * register
4490 + */
4491 + pab_ctrl = csr_readl(pcie, PAB_CTRL);
4492 + pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT);
4493 + csr_writel(pcie, pab_ctrl, PAB_CTRL);
4494 +
4495 + /*
4496 + * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in
4497 + * PAB_AXI_PIO_CTRL Register
4498 + */
4499 + value = csr_readl(pcie, PAB_AXI_PIO_CTRL);
4500 + value |= APIO_EN_MASK;
4501 + csr_writel(pcie, value, PAB_AXI_PIO_CTRL);
4502 +
4503 + /* Enable PCIe PIO master */
4504 + value = csr_readl(pcie, PAB_PEX_PIO_CTRL);
4505 + value |= 1 << PIO_ENABLE_SHIFT;
4506 + csr_writel(pcie, value, PAB_PEX_PIO_CTRL);
4507 +
4508 + /*
4509 + * we'll program one outbound window for config reads and
4510 + * another default inbound window for all the upstream traffic
4511 + * rest of the outbound windows will be configured according to
4512 + * the "ranges" field defined in device tree
4513 + */
4514 +
4515 + /* config outbound translation window */
4516 + program_ob_windows(pcie, WIN_NUM_0, pcie->rp.ob_io_res->start, 0,
4517 + CFG_WINDOW_TYPE, resource_size(pcie->rp.ob_io_res));
4518 +
4519 + /* memory inbound translation window */
4520 + program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE);
4521 +
4522 + /* Get the I/O and memory ranges from DT */
4523 + resource_list_for_each_entry(win, pcie->resources) {
4524 + if (resource_type(win->res) == IORESOURCE_MEM) {
4525 + type = MEM_WINDOW_TYPE;
4526 + } else if (resource_type(win->res) == IORESOURCE_IO) {
4527 + type = IO_WINDOW_TYPE;
4528 + } else if (resource_type(win->res) == IORESOURCE_BUS) {
4529 + pcie->rp.root_bus_nr = win->res->start;
4530 + continue;
4531 + } else {
4532 + continue;
4533 + }
4534 +
4535 + /* configure outbound translation window */
4536 + program_ob_windows(pcie, pcie->ob_wins_configured,
4537 + win->res->start,
4538 + win->res->start - win->offset,
4539 + type, resource_size(win->res));
4540 + }
4541 +
4542 + /* fixup for PCIe class register */
4543 + value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
4544 + value &= 0xff;
4545 + value |= (PCI_CLASS_BRIDGE_PCI << 16);
4546 + csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
4547 +
4548 + return 0;
4549 +}
4550 +
4551 +static void mobiveil_mask_intx_irq(struct irq_data *data)
4552 +{
4553 + struct irq_desc *desc = irq_to_desc(data->irq);
4554 + struct mobiveil_pcie *pcie;
4555 + unsigned long flags;
4556 + u32 mask, shifted_val;
4557 +
4558 + pcie = irq_desc_get_chip_data(desc);
4559 + mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
4560 + raw_spin_lock_irqsave(&pcie->rp.intx_mask_lock, flags);
4561 + shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
4562 + shifted_val &= ~mask;
4563 + csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
4564 + raw_spin_unlock_irqrestore(&pcie->rp.intx_mask_lock, flags);
4565 +}
4566 +
4567 +static void mobiveil_unmask_intx_irq(struct irq_data *data)
4568 +{
4569 + struct irq_desc *desc = irq_to_desc(data->irq);
4570 + struct mobiveil_pcie *pcie;
4571 + unsigned long flags;
4572 + u32 shifted_val, mask;
4573 +
4574 + pcie = irq_desc_get_chip_data(desc);
4575 + mask = 1 << ((data->hwirq + PAB_INTX_START) - 1);
4576 + raw_spin_lock_irqsave(&pcie->rp.intx_mask_lock, flags);
4577 + shifted_val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
4578 + shifted_val |= mask;
4579 + csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB);
4580 + raw_spin_unlock_irqrestore(&pcie->rp.intx_mask_lock, flags);
4581 +}
4582 +
4583 +static struct irq_chip intx_irq_chip = {
4584 + .name = "mobiveil_pcie:intx",
4585 + .irq_enable = mobiveil_unmask_intx_irq,
4586 + .irq_disable = mobiveil_mask_intx_irq,
4587 + .irq_mask = mobiveil_mask_intx_irq,
4588 + .irq_unmask = mobiveil_unmask_intx_irq,
4589 +};
4590 +
4591 +/* routine to setup the INTx related data */
4592 +static int mobiveil_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
4593 + irq_hw_number_t hwirq)
4594 +{
4595 + irq_set_chip_and_handler(irq, &intx_irq_chip, handle_level_irq);
4596 + irq_set_chip_data(irq, domain->host_data);
4597 +
4598 + return 0;
4599 +}
4600 +
4601 +/* INTx domain operations structure */
4602 +static const struct irq_domain_ops intx_domain_ops = {
4603 + .map = mobiveil_pcie_intx_map,
4604 +};
4605 +
4606 +static struct irq_chip mobiveil_msi_irq_chip = {
4607 + .name = "Mobiveil PCIe MSI",
4608 + .irq_mask = pci_msi_mask_irq,
4609 + .irq_unmask = pci_msi_unmask_irq,
4610 +};
4611 +
4612 +static struct msi_domain_info mobiveil_msi_domain_info = {
4613 + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
4614 + MSI_FLAG_PCI_MSIX),
4615 + .chip = &mobiveil_msi_irq_chip,
4616 +};
4617 +
4618 +static void mobiveil_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
4619 +{
4620 + struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data);
4621 + phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int));
4622 +
4623 + msg->address_lo = lower_32_bits(addr);
4624 + msg->address_hi = upper_32_bits(addr);
4625 + msg->data = data->hwirq;
4626 +
4627 + dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
4628 + (int)data->hwirq, msg->address_hi, msg->address_lo);
4629 +}
4630 +
4631 +static int mobiveil_msi_set_affinity(struct irq_data *irq_data,
4632 + const struct cpumask *mask, bool force)
4633 +{
4634 + return -EINVAL;
4635 +}
4636 +
4637 +static struct irq_chip mobiveil_msi_bottom_irq_chip = {
4638 + .name = "Mobiveil MSI",
4639 + .irq_compose_msi_msg = mobiveil_compose_msi_msg,
4640 + .irq_set_affinity = mobiveil_msi_set_affinity,
4641 +};
4642 +
4643 +static int mobiveil_irq_msi_domain_alloc(struct irq_domain *domain,
4644 + unsigned int virq,
4645 + unsigned int nr_irqs, void *args)
4646 +{
4647 + struct mobiveil_pcie *pcie = domain->host_data;
4648 + struct mobiveil_msi *msi = &pcie->rp.msi;
4649 + unsigned long bit;
4650 +
4651 + WARN_ON(nr_irqs != 1);
4652 + mutex_lock(&msi->lock);
4653 +
4654 + bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors);
4655 + if (bit >= msi->num_of_vectors) {
4656 + mutex_unlock(&msi->lock);
4657 + return -ENOSPC;
4658 + }
4659 +
4660 + set_bit(bit, msi->msi_irq_in_use);
4661 +
4662 + mutex_unlock(&msi->lock);
4663 +
4664 + irq_domain_set_info(domain, virq, bit, &mobiveil_msi_bottom_irq_chip,
4665 + domain->host_data, handle_level_irq, NULL, NULL);
4666 + return 0;
4667 +}
4668 +
4669 +static void mobiveil_irq_msi_domain_free(struct irq_domain *domain,
4670 + unsigned int virq,
4671 + unsigned int nr_irqs)
4672 +{
4673 + struct irq_data *d = irq_domain_get_irq_data(domain, virq);
4674 + struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d);
4675 + struct mobiveil_msi *msi = &pcie->rp.msi;
4676 +
4677 + mutex_lock(&msi->lock);
4678 +
4679 + if (!test_bit(d->hwirq, msi->msi_irq_in_use))
4680 + dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n",
4681 + d->hwirq);
4682 + else
4683 + __clear_bit(d->hwirq, msi->msi_irq_in_use);
4684 +
4685 + mutex_unlock(&msi->lock);
4686 +}
4687 +static const struct irq_domain_ops msi_domain_ops = {
4688 + .alloc = mobiveil_irq_msi_domain_alloc,
4689 + .free = mobiveil_irq_msi_domain_free,
4690 +};
4691 +
4692 +static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie)
4693 +{
4694 + struct device *dev = &pcie->pdev->dev;
4695 + struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
4696 + struct mobiveil_msi *msi = &pcie->rp.msi;
4697 +
4698 + mutex_init(&msi->lock);
4699 + msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors,
4700 + &msi_domain_ops, pcie);
4701 + if (!msi->dev_domain) {
4702 + dev_err(dev, "failed to create IRQ domain\n");
4703 + return -ENOMEM;
4704 + }
4705 +
4706 + msi->msi_domain = pci_msi_create_irq_domain(fwnode,
4707 + &mobiveil_msi_domain_info,
4708 + msi->dev_domain);
4709 + if (!msi->msi_domain) {
4710 + dev_err(dev, "failed to create MSI domain\n");
4711 + irq_domain_remove(msi->dev_domain);
4712 + return -ENOMEM;
4713 + }
4714 +
4715 + return 0;
4716 +}
4717 +
4718 +static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie)
4719 +{
4720 + struct device *dev = &pcie->pdev->dev;
4721 + struct device_node *node = dev->of_node;
4722 + int ret;
4723 +
4724 + /* setup INTx */
4725 + pcie->rp.intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
4726 + &intx_domain_ops, pcie);
4727 +
4728 + if (!pcie->rp.intx_domain) {
4729 + dev_err(dev, "Failed to get a INTx IRQ domain\n");
4730 + return -ENOMEM;
4731 + }
4732 +
4733 + raw_spin_lock_init(&pcie->rp.intx_mask_lock);
4734 +
4735 + /* setup MSI */
4736 + ret = mobiveil_allocate_msi_domains(pcie);
4737 + if (ret)
4738 + return ret;
4739 +
4740 + return 0;
4741 +}
4742 +
4743 +static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie)
4744 +{
4745 + struct device *dev = &pcie->pdev->dev;
4746 + struct resource *res;
4747 + int ret;
4748 +
4749 + if (pcie->rp.ops->interrupt_init)
4750 + return pcie->rp.ops->interrupt_init(pcie);
4751 +
4752 + /* map MSI config resource */
4753 + res = platform_get_resource_byname(pcie->pdev, IORESOURCE_MEM,
4754 + "apb_csr");
4755 + pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res);
4756 + if (IS_ERR(pcie->apb_csr_base))
4757 + return PTR_ERR(pcie->apb_csr_base);
4758 +
4759 + /* setup MSI hardware registers */
4760 + mobiveil_pcie_enable_msi(pcie);
4761 +
4762 + pcie->rp.irq = platform_get_irq(pcie->pdev, 0);
4763 + if (pcie->rp.irq <= 0) {
4764 + dev_err(dev, "failed to map IRQ: %d\n", pcie->rp.irq);
4765 + return -ENODEV;
4766 + }
4767 +
4768 + /* initialize the IRQ domains */
4769 + ret = mobiveil_pcie_init_irq_domain(pcie);
4770 + if (ret) {
4771 + dev_err(dev, "Failed creating IRQ Domain\n");
4772 + return ret;
4773 + }
4774 +
4775 + irq_set_chained_handler_and_data(pcie->rp.irq,
4776 + mobiveil_pcie_isr, pcie);
4777 +
4778 + /* Enable interrupts */
4779 + csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK),
4780 + PAB_INTP_AMBA_MISC_ENB);
4781 +
4782 + return 0;
4783 +}
4784 +
4785 +int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie)
4786 +{
4787 + struct pci_bus *bus;
4788 + struct pci_bus *child;
4789 + struct pci_host_bridge *bridge;
4790 + struct device *dev = &pcie->pdev->dev;
4791 + struct device_node *np = dev->of_node;
4792 + resource_size_t iobase;
4793 + int ret;
4794 +
4795 + ret = mobiveil_pcie_parse_dt(pcie);
4796 + if (ret) {
4797 + dev_err(dev, "Parsing DT failed, ret: %x\n", ret);
4798 + return ret;
4799 + }
4800 +
4801 + /* allocate the PCIe port */
4802 + bridge = devm_pci_alloc_host_bridge(dev, 0);
4803 + if (!bridge)
4804 + return -ENOMEM;
4805 +
4806 + /* parse the host bridge base addresses from the device tree file */
4807 + ret = of_pci_get_host_bridge_resources(np, 0, 0xff,
4808 + &bridge->windows, &iobase);
4809 + if (ret) {
4810 + dev_err(dev, "Getting bridge resources failed\n");
4811 + return ret;
4812 + }
4813 +
4814 + pcie->resources = &bridge->windows;
4815 +
4816 + /*
4817 + * configure all inbound and outbound windows and prepare the RC for
4818 + * config access
4819 + */
4820 + ret = mobiveil_host_init(pcie, false);
4821 + if (ret) {
4822 + dev_err(dev, "Failed to initialize host\n");
4823 + goto error;
4824 + }
4825 +
4826 + ret = mobiveil_pcie_interrupt_init(pcie);
4827 + if (ret) {
4828 + dev_err(dev, "Interrupt init failed\n");
4829 + goto error;
4830 + }
4831 +
4832 + ret = devm_request_pci_bus_resources(dev, pcie->resources);
4833 + if (ret)
4834 + goto error;
4835 +
4836 + /* Initialize bridge */
4837 + bridge->dev.parent = dev;
4838 + bridge->sysdata = pcie;
4839 + bridge->busnr = pcie->rp.root_bus_nr;
4840 + bridge->ops = &mobiveil_pcie_ops;
4841 + bridge->map_irq = of_irq_parse_and_map_pci;
4842 + bridge->swizzle_irq = pci_common_swizzle;
4843 +
4844 + ret = mobiveil_bringup_link(pcie);
4845 + if (ret) {
4846 + dev_info(dev, "link bring-up failed\n");
4847 + }
4848 +
4849 + /* setup the kernel resources for the newly added PCIe root bus */
4850 + ret = pci_scan_root_bus_bridge(bridge);
4851 + if (ret)
4852 + goto error;
4853 +
4854 + bus = bridge->bus;
4855 +
4856 + pci_assign_unassigned_bus_resources(bus);
4857 + list_for_each_entry(child, &bus->children, node)
4858 + pcie_bus_configure_settings(child);
4859 + pci_bus_add_devices(bus);
4860 +
4861 + return 0;
4862 +error:
4863 + pci_free_resource_list(pcie->resources);
4864 + return ret;
4865 +}
4866 --- /dev/null
4867 +++ b/drivers/pci/mobiveil/pcie-mobiveil-plat.c
4868 @@ -0,0 +1,54 @@
4869 +// SPDX-License-Identifier: GPL-2.0
4870 +/*
4871 + * PCIe host controller driver for Mobiveil PCIe Host controller
4872 + *
4873 + * Copyright (c) 2018 Mobiveil Inc.
4874 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
4875 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
4876 + */
4877 +
4878 +#include <linux/init.h>
4879 +#include <linux/kernel.h>
4880 +#include <linux/module.h>
4881 +#include <linux/of_pci.h>
4882 +#include <linux/pci.h>
4883 +#include <linux/platform_device.h>
4884 +#include <linux/slab.h>
4885 +
4886 +#include "pcie-mobiveil.h"
4887 +
4888 +static int mobiveil_pcie_probe(struct platform_device *pdev)
4889 +{
4890 + struct mobiveil_pcie *pcie;
4891 + struct device *dev = &pdev->dev;
4892 +
4893 + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
4894 + if (!pcie)
4895 + return -ENOMEM;
4896 +
4897 + pcie->pdev = pdev;
4898 +
4899 + return mobiveil_pcie_host_probe(pcie);
4900 +}
4901 +
4902 +static const struct of_device_id mobiveil_pcie_of_match[] = {
4903 + {.compatible = "mbvl,gpex40-pcie",},
4904 + {},
4905 +};
4906 +
4907 +MODULE_DEVICE_TABLE(of, mobiveil_pcie_of_match);
4908 +
4909 +static struct platform_driver mobiveil_pcie_driver = {
4910 + .probe = mobiveil_pcie_probe,
4911 + .driver = {
4912 + .name = "mobiveil-pcie",
4913 + .of_match_table = mobiveil_pcie_of_match,
4914 + .suppress_bind_attrs = true,
4915 + },
4916 +};
4917 +
4918 +builtin_platform_driver(mobiveil_pcie_driver);
4919 +
4920 +MODULE_LICENSE("GPL v2");
4921 +MODULE_DESCRIPTION("Mobiveil PCIe host controller driver");
4922 +MODULE_AUTHOR("Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>");
4923 --- /dev/null
4924 +++ b/drivers/pci/mobiveil/pcie-mobiveil.c
4925 @@ -0,0 +1,334 @@
4926 +// SPDX-License-Identifier: GPL-2.0
4927 +/*
4928 + * PCIe host controller driver for Mobiveil PCIe Host controller
4929 + *
4930 + * Copyright (c) 2018 Mobiveil Inc.
4931 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
4932 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
4933 + */
4934 +
4935 +#include <linux/delay.h>
4936 +#include <linux/init.h>
4937 +#include <linux/kernel.h>
4938 +#include <linux/pci.h>
4939 +#include <linux/platform_device.h>
4940 +
4941 +#include "pcie-mobiveil.h"
4942 +
4943 +/*
4944 + * mobiveil_pcie_sel_page - routine to access paged register
4945 + *
4946 + * Registers whose address greater than PAGED_ADDR_BNDRY (0xc00) are paged,
4947 + * for this scheme to work extracted higher 6 bits of the offset will be
4948 + * written to pg_sel field of PAB_CTRL register and rest of the lower 10
4949 + * bits enabled with PAGED_ADDR_BNDRY are used as offset of the register.
4950 + */
4951 +static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx)
4952 +{
4953 + u32 val;
4954 +
4955 + val = readl(pcie->csr_axi_slave_base + PAB_CTRL);
4956 + val &= ~(PAGE_SEL_MASK << PAGE_SEL_SHIFT);
4957 + val |= (pg_idx & PAGE_SEL_MASK) << PAGE_SEL_SHIFT;
4958 +
4959 + writel(val, pcie->csr_axi_slave_base + PAB_CTRL);
4960 +}
4961 +
4962 +static void *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, u32 off)
4963 +{
4964 + if (off < PAGED_ADDR_BNDRY) {
4965 + /* For directly accessed registers, clear the pg_sel field */
4966 + mobiveil_pcie_sel_page(pcie, 0);
4967 + return pcie->csr_axi_slave_base + off;
4968 + }
4969 +
4970 + mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off));
4971 + return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off);
4972 +}
4973 +
4974 +static int mobiveil_pcie_read(void __iomem *addr, int size, u32 *val)
4975 +{
4976 + if ((uintptr_t)addr & (size - 1)) {
4977 + *val = 0;
4978 + return PCIBIOS_BAD_REGISTER_NUMBER;
4979 + }
4980 +
4981 + switch (size) {
4982 + case 4:
4983 + *val = readl(addr);
4984 + break;
4985 + case 2:
4986 + *val = readw(addr);
4987 + break;
4988 + case 1:
4989 + *val = readb(addr);
4990 + break;
4991 + default:
4992 + *val = 0;
4993 + return PCIBIOS_BAD_REGISTER_NUMBER;
4994 + }
4995 +
4996 + return PCIBIOS_SUCCESSFUL;
4997 +}
4998 +
4999 +static int mobiveil_pcie_write(void __iomem *addr, int size, u32 val)
5000 +{
5001 + if ((uintptr_t)addr & (size - 1))
5002 + return PCIBIOS_BAD_REGISTER_NUMBER;
5003 +
5004 + switch (size) {
5005 + case 4:
5006 + writel(val, addr);
5007 + break;
5008 + case 2:
5009 + writew(val, addr);
5010 + break;
5011 + case 1:
5012 + writeb(val, addr);
5013 + break;
5014 + default:
5015 + return PCIBIOS_BAD_REGISTER_NUMBER;
5016 + }
5017 +
5018 + return PCIBIOS_SUCCESSFUL;
5019 +}
5020 +
5021 +u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size)
5022 +{
5023 + void *addr;
5024 + u32 val;
5025 + int ret;
5026 +
5027 + addr = mobiveil_pcie_comp_addr(pcie, off);
5028 +
5029 + ret = mobiveil_pcie_read(addr, size, &val);
5030 + if (ret)
5031 + dev_err(&pcie->pdev->dev, "read CSR address failed\n");
5032 +
5033 + return val;
5034 +}
5035 +
5036 +void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size)
5037 +{
5038 + void *addr;
5039 + int ret;
5040 +
5041 + addr = mobiveil_pcie_comp_addr(pcie, off);
5042 +
5043 + ret = mobiveil_pcie_write(addr, size, val);
5044 + if (ret)
5045 + dev_err(&pcie->pdev->dev, "write CSR address failed\n");
5046 +}
5047 +
5048 +bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie)
5049 +{
5050 + if (pcie->ops->link_up)
5051 + return pcie->ops->link_up(pcie);
5052 +
5053 + return (csr_readl(pcie, LTSSM_STATUS) &
5054 + LTSSM_STATUS_L0_MASK) == LTSSM_STATUS_L0;
5055 +}
5056 +
5057 +void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5058 + u64 pci_addr, u32 type, u64 size)
5059 +{
5060 + u32 value;
5061 + u64 size64 = ~(size - 1);
5062 +
5063 + if (win_num >= pcie->ppio_wins) {
5064 + dev_err(&pcie->pdev->dev,
5065 + "ERROR: max inbound windows reached !\n");
5066 + return;
5067 + }
5068 +
5069 + value = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
5070 + value &= ~(AMAP_CTRL_TYPE_MASK << AMAP_CTRL_TYPE_SHIFT |
5071 + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5072 + value |= (type << AMAP_CTRL_TYPE_SHIFT) | (1 << AMAP_CTRL_EN_SHIFT) |
5073 + (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5074 + csr_writel(pcie, value, PAB_PEX_AMAP_CTRL(win_num));
5075 +
5076 + csr_writel(pcie, upper_32_bits(size64),
5077 + PAB_EXT_PEX_AMAP_SIZEN(win_num));
5078 +
5079 + csr_writel(pcie, lower_32_bits(cpu_addr),
5080 + PAB_PEX_AMAP_AXI_WIN(win_num));
5081 + csr_writel(pcie, upper_32_bits(cpu_addr),
5082 + PAB_EXT_PEX_AMAP_AXI_WIN(win_num));
5083 +
5084 + csr_writel(pcie, lower_32_bits(pci_addr),
5085 + PAB_PEX_AMAP_PEX_WIN_L(win_num));
5086 + csr_writel(pcie, upper_32_bits(pci_addr),
5087 + PAB_PEX_AMAP_PEX_WIN_H(win_num));
5088 +
5089 + pcie->ib_wins_configured++;
5090 +}
5091 +
5092 +/*
5093 + * routine to program the outbound windows
5094 + */
5095 +void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5096 + u64 pci_addr, u32 type, u64 size)
5097 +{
5098 +
5099 + u32 value;
5100 + u64 size64 = ~(size - 1);
5101 +
5102 + if (win_num >= pcie->apio_wins) {
5103 + dev_err(&pcie->pdev->dev,
5104 + "ERROR: max outbound windows reached !\n");
5105 + return;
5106 + }
5107 +
5108 + /*
5109 + * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
5110 + * to 4 KB in PAB_AXI_AMAP_CTRL register
5111 + */
5112 + value = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
5113 + value &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
5114 + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5115 + value |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
5116 + (lower_32_bits(size64) & WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5117 + csr_writel(pcie, value, PAB_AXI_AMAP_CTRL(win_num));
5118 +
5119 + csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
5120 +
5121 + /*
5122 + * program AXI window base with appropriate value in
5123 + * PAB_AXI_AMAP_AXI_WIN0 register
5124 + */
5125 + csr_writel(pcie, lower_32_bits(cpu_addr) & (~AXI_WINDOW_ALIGN_MASK),
5126 + PAB_AXI_AMAP_AXI_WIN(win_num));
5127 + csr_writel(pcie, upper_32_bits(cpu_addr),
5128 + PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
5129 +
5130 + csr_writel(pcie, lower_32_bits(pci_addr),
5131 + PAB_AXI_AMAP_PEX_WIN_L(win_num));
5132 + csr_writel(pcie, upper_32_bits(pci_addr),
5133 + PAB_AXI_AMAP_PEX_WIN_H(win_num));
5134 +
5135 + pcie->ob_wins_configured++;
5136 +}
5137 +
5138 +int program_ob_windows_ep(struct mobiveil_pcie *pcie, int win_num, int type,
5139 + u64 phys, u64 bus_addr, u8 func, u64 size)
5140 +{
5141 + u32 val;
5142 + u32 size_h, size_l;
5143 +
5144 + if (size & (size - 1))
5145 + size = 1 << (1 + ilog2(size));
5146 +
5147 + size_h = upper_32_bits(~(size - 1));
5148 + size_l = lower_32_bits(~(size - 1));
5149 +
5150 + val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
5151 + val &= ~(WIN_TYPE_MASK << WIN_TYPE_SHIFT |
5152 + WIN_SIZE_MASK << WIN_SIZE_SHIFT);
5153 + val |= 1 << WIN_ENABLE_SHIFT | type << WIN_TYPE_SHIFT |
5154 + (size_l & (WIN_SIZE_MASK << WIN_SIZE_SHIFT));
5155 + csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(win_num));
5156 +
5157 + csr_writel(pcie, func, PAB_AXI_AMAP_PCI_HDR_PARAM(win_num));
5158 + csr_writel(pcie, lower_32_bits(phys), PAB_AXI_AMAP_AXI_WIN(win_num));
5159 + csr_writel(pcie, upper_32_bits(phys),
5160 + PAB_EXT_AXI_AMAP_AXI_WIN(win_num));
5161 + csr_writel(pcie, lower_32_bits(bus_addr),
5162 + PAB_AXI_AMAP_PEX_WIN_L(win_num));
5163 + csr_writel(pcie, upper_32_bits(bus_addr),
5164 + PAB_AXI_AMAP_PEX_WIN_H(win_num));
5165 + csr_writel(pcie, size_h, PAB_EXT_AXI_AMAP_SIZE(win_num));
5166 +
5167 + return 0;
5168 +}
5169 +
5170 +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
5171 + int bar, u64 phys)
5172 +{
5173 + csr_writel(pcie, upper_32_bits(phys),
5174 + PAB_EXT_PEX_BAR_AMAP(func_no, bar));
5175 + csr_writel(pcie, lower_32_bits(phys) | PEX_BAR_AMAP_EN,
5176 + PAB_PEX_BAR_AMAP(func_no, bar));
5177 +}
5178 +
5179 +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pcie,
5180 + u8 func_no, u8 bar)
5181 +{
5182 + u32 val;
5183 +
5184 + val = csr_readl(pcie, PAB_PEX_BAR_AMAP(func_no, bar));
5185 + val &= ~(1 << 0);
5186 + csr_writel(pcie, val, PAB_PEX_BAR_AMAP(func_no, bar));
5187 +}
5188 +
5189 +int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
5190 +{
5191 + int retries;
5192 +
5193 + /* check if the link is up or not */
5194 + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
5195 + if (mobiveil_pcie_link_up(pcie))
5196 + return 0;
5197 +
5198 + usleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);
5199 + }
5200 +
5201 + dev_info(&pcie->pdev->dev, "link never came up\n");
5202 +
5203 + return -ETIMEDOUT;
5204 +}
5205 +
5206 +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pcie, int win_num)
5207 +{
5208 + u32 val;
5209 +
5210 + val = csr_readl(pcie, PAB_PEX_AMAP_CTRL(win_num));
5211 + val &= ~(1 << AMAP_CTRL_EN_SHIFT);
5212 + csr_writel(pcie, val, PAB_PEX_AMAP_CTRL(win_num));
5213 +}
5214 +
5215 +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int win_num)
5216 +{
5217 + u32 val;
5218 +
5219 + val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
5220 + val &= ~(1 << WIN_ENABLE_SHIFT);
5221 + csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(win_num));
5222 +}
5223 +
5224 +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pcie)
5225 +{
5226 + u32 val;
5227 +
5228 + val = csr_readl(pcie, PAB_CTRL);
5229 + val |= 1 << AMBA_PIO_ENABLE_SHIFT;
5230 + val |= 1 << PEX_PIO_ENABLE_SHIFT;
5231 + csr_writel(pcie, val, PAB_CTRL);
5232 +}
5233 +
5234 +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pcie)
5235 +{
5236 + u32 val;
5237 +
5238 + val = csr_readl(pcie, PAB_AXI_PIO_CTRL);
5239 + val |= APIO_EN_MASK;
5240 + csr_writel(pcie, val, PAB_AXI_PIO_CTRL);
5241 +}
5242 +
5243 +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pcie)
5244 +{
5245 + u32 val;
5246 +
5247 + val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
5248 + val |= 1 << PIO_ENABLE_SHIFT;
5249 + csr_writel(pcie, val, PAB_PEX_PIO_CTRL);
5250 +}
5251 +
5252 +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pcie)
5253 +{
5254 + u32 val;
5255 +
5256 + val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
5257 + val |= 1 << 0;
5258 + csr_writel(pcie, val, PAB_INTP_AMBA_MISC_ENB);
5259 +}
5260 --- /dev/null
5261 +++ b/drivers/pci/mobiveil/pcie-mobiveil.h
5262 @@ -0,0 +1,296 @@
5263 +/* SPDX-License-Identifier: GPL-2.0 */
5264 +/*
5265 + * PCIe host controller driver for Mobiveil PCIe Host controller
5266 + *
5267 + * Copyright (c) 2018 Mobiveil Inc.
5268 + * Author: Subrahmanya Lingappa <l.subrahmanya@mobiveil.co.in>
5269 + * Refactor: Zhiqiang Hou <Zhiqiang.Hou@nxp.com>
5270 + */
5271 +
5272 +#ifndef _PCIE_MOBIVEIL_H
5273 +#define _PCIE_MOBIVEIL_H
5274 +
5275 +#include <linux/pci.h>
5276 +#include <linux/irq.h>
5277 +#include <linux/msi.h>
5278 +#include "../pci.h"
5279 +
5280 +#include <linux/pci-epc.h>
5281 +#include <linux/pci-epf.h>
5282 +
5283 +#define MAX_IATU_OUT 256
5284 +/* register offsets and bit positions */
5285 +
5286 +/*
5287 + * translation tables are grouped into windows, each window registers are
5288 + * grouped into blocks of 4 or 16 registers each
5289 + */
5290 +#define PAB_REG_BLOCK_SIZE 16
5291 +#define PAB_EXT_REG_BLOCK_SIZE 4
5292 +
5293 +#define PAB_REG_ADDR(offset, win) \
5294 + (offset + (win * PAB_REG_BLOCK_SIZE))
5295 +#define PAB_EXT_REG_ADDR(offset, win) \
5296 + (offset + (win * PAB_EXT_REG_BLOCK_SIZE))
5297 +
5298 +#define LTSSM_STATUS 0x0404
5299 +#define LTSSM_STATUS_L0_MASK 0x3f
5300 +#define LTSSM_STATUS_L0 0x2d
5301 +
5302 +#define PAB_CTRL 0x0808
5303 +#define AMBA_PIO_ENABLE_SHIFT 0
5304 +#define PEX_PIO_ENABLE_SHIFT 1
5305 +#define PAGE_SEL_SHIFT 13
5306 +#define PAGE_SEL_MASK 0x3f
5307 +#define PAGE_LO_MASK 0x3ff
5308 +#define PAGE_SEL_OFFSET_SHIFT 10
5309 +#define FUNC_SEL_SHIFT 19
5310 +#define FUNC_SEL_MASK 0x1ff
5311 +#define MSI_SW_CTRL_EN (1 << 29)
5312 +
5313 +#define PAB_ACTIVITY_STAT 0x81c
5314 +
5315 +#define PAB_AXI_PIO_CTRL 0x0840
5316 +#define APIO_EN_MASK 0xf
5317 +
5318 +#define PAB_PEX_PIO_CTRL 0x08c0
5319 +#define PIO_ENABLE_SHIFT 0
5320 +
5321 +#define PAB_INTP_AMBA_MISC_ENB 0x0b0c
5322 +#define PAB_INTP_AMBA_MISC_STAT 0x0b1c
5323 +#define PAB_INTP_RESET (0x1 << 1)
5324 +#define PAB_INTP_MSI (0x1 << 3)
5325 +#define PAB_INTP_INTA (0x1 << 5)
5326 +#define PAB_INTP_INTB (0x1 << 6)
5327 +#define PAB_INTP_INTC (0x1 << 7)
5328 +#define PAB_INTP_INTD (0x1 << 8)
5329 +#define PAB_INTP_PCIE_UE (0x1 << 9)
5330 +#define PAB_INTP_IE_PMREDI (0x1 << 29)
5331 +#define PAB_INTP_IE_EC (0x1 << 30)
5332 +#define PAB_INTP_MSI_MASK PAB_INTP_MSI
5333 +#define PAB_INTP_INTX_MASK (PAB_INTP_INTA | PAB_INTP_INTB |\
5334 + PAB_INTP_INTC | PAB_INTP_INTD)
5335 +
5336 +#define PAB_AXI_AMAP_CTRL(win) PAB_REG_ADDR(0x0ba0, win)
5337 +#define WIN_ENABLE_SHIFT 0
5338 +#define WIN_TYPE_SHIFT 1
5339 +#define WIN_TYPE_MASK 0x3
5340 +#define WIN_SIZE_SHIFT 10
5341 +#define WIN_SIZE_MASK 0x3fffff
5342 +
5343 +#define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
5344 +
5345 +#define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
5346 +#define PAB_AXI_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x0ba4, win)
5347 +#define AXI_WINDOW_ALIGN_MASK 3
5348 +
5349 +#define PAB_AXI_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x0ba8, win)
5350 +#define PAB_BUS_SHIFT 24
5351 +#define PAB_DEVICE_SHIFT 19
5352 +#define PAB_FUNCTION_SHIFT 16
5353 +
5354 +#define PAB_AXI_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x0bac, win)
5355 +#define PAB_INTP_AXI_PIO_CLASS 0x474
5356 +
5357 +#define GPEX_ACK_REPLAY_TO 0x438
5358 +#define ACK_LAT_TO_VAL_MASK 0x1fff
5359 +#define ACK_LAT_TO_VAL_SHIFT 0
5360 +
5361 +#define PAB_PEX_AMAP_CTRL(win) PAB_REG_ADDR(0x4ba0, win)
5362 +#define AMAP_CTRL_EN_SHIFT 0
5363 +#define AMAP_CTRL_TYPE_SHIFT 1
5364 +#define AMAP_CTRL_TYPE_MASK 3
5365 +
5366 +#define PAB_EXT_PEX_AMAP_SIZEN(win) PAB_EXT_REG_ADDR(0xbef0, win)
5367 +#define PAB_EXT_PEX_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0xb4a0, win)
5368 +#define PAB_PEX_AMAP_AXI_WIN(win) PAB_REG_ADDR(0x4ba4, win)
5369 +#define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
5370 +#define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
5371 +
5372 +/* PPIO WINs EP mode */
5373 +#define PAB_PEX_BAR_AMAP(func, bar) (0x1ba0 + 0x20 * func + 4 * bar)
5374 +#define PAB_EXT_PEX_BAR_AMAP(func, bar) (0x84a0 + 0x20 * func + 4 * bar)
5375 +#define PEX_BAR_AMAP_EN (1 << 0)
5376 +
5377 +#define PAB_AXI_AMAP_PCI_HDR_PARAM(idx) (0x5ba0 + 0x04 * idx)
5378 +#define PAB_MSIX_TABLE_PBA_ACCESS 0xD000
5379 +
5380 +#define GPEX_BAR_ENABLE 0x4D4
5381 +#define GPEX_BAR_SIZE_LDW 0x4D8
5382 +#define GPEX_BAR_SIZE_UDW 0x4DC
5383 +#define GPEX_BAR_SELECT 0x4E0
5384 +
5385 +#define CFG_UNCORRECTABLE_ERROR_SEVERITY 0x10c
5386 +#define UNSUPPORTED_REQUEST_ERROR_SHIFT 20
5387 +#define CFG_UNCORRECTABLE_ERROR_MASK 0x108
5388 +
5389 +/* starting offset of INTX bits in status register */
5390 +#define PAB_INTX_START 5
5391 +
5392 +/* supported number of MSI interrupts */
5393 +#define PCI_NUM_MSI 16
5394 +
5395 +/* MSI registers */
5396 +#define MSI_BASE_LO_OFFSET 0x04
5397 +#define MSI_BASE_HI_OFFSET 0x08
5398 +#define MSI_SIZE_OFFSET 0x0c
5399 +#define MSI_ENABLE_OFFSET 0x14
5400 +#define MSI_STATUS_OFFSET 0x18
5401 +#define MSI_DATA_OFFSET 0x20
5402 +#define MSI_ADDR_L_OFFSET 0x24
5403 +#define MSI_ADDR_H_OFFSET 0x28
5404 +
5405 +/* outbound and inbound window definitions */
5406 +#define WIN_NUM_0 0
5407 +#define WIN_NUM_1 1
5408 +#define CFG_WINDOW_TYPE 0
5409 +#define IO_WINDOW_TYPE 1
5410 +#define MEM_WINDOW_TYPE 2
5411 +#define IB_WIN_SIZE ((u64)256 * 1024 * 1024 * 1024)
5412 +#define MAX_PIO_WINDOWS 8
5413 +
5414 +/* Parameters for the waiting for link up routine */
5415 +#define LINK_WAIT_MAX_RETRIES 10
5416 +#define LINK_WAIT_MIN 90000
5417 +#define LINK_WAIT_MAX 100000
5418 +
5419 +#define PAGED_ADDR_BNDRY 0xc00
5420 +#define OFFSET_TO_PAGE_ADDR(off) \
5421 + ((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)
5422 +#define OFFSET_TO_PAGE_IDX(off) \
5423 + ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
5424 +
5425 +struct mobiveil_pcie;
5426 +struct mobiveil_pcie_ep;
5427 +
5428 +struct mobiveil_msi { /* MSI information */
5429 + struct mutex lock; /* protect bitmap variable */
5430 + struct irq_domain *msi_domain;
5431 + struct irq_domain *dev_domain;
5432 + phys_addr_t msi_pages_phys;
5433 + int num_of_vectors;
5434 + DECLARE_BITMAP(msi_irq_in_use, PCI_NUM_MSI);
5435 +};
5436 +
5437 +struct mobiveil_rp_ops {
5438 + int (*interrupt_init)(struct mobiveil_pcie *pcie);
5439 + int (*read_other_conf)(struct pci_bus *bus, unsigned int devfn,
5440 + int where, int size, u32 *val);
5441 +};
5442 +
5443 +struct root_port {
5444 + u8 root_bus_nr;
5445 + void __iomem *config_axi_slave_base; /* endpoint config base */
5446 + struct resource *ob_io_res;
5447 + struct mobiveil_rp_ops *ops;
5448 + int irq;
5449 + raw_spinlock_t intx_mask_lock;
5450 + struct irq_domain *intx_domain;
5451 + struct mobiveil_msi msi;
5452 +};
5453 +
5454 +struct mobiveil_pab_ops {
5455 + int (*link_up)(struct mobiveil_pcie *pcie);
5456 +};
5457 +
5458 +struct mobiveil_pcie_ep_ops {
5459 + void (*ep_init)(struct mobiveil_pcie_ep *ep);
5460 + int (*raise_irq)(struct mobiveil_pcie_ep *ep, u8 func_no,
5461 + enum pci_epc_irq_type type, u16 interrupt_num);
5462 +};
5463 +
5464 +struct mobiveil_pcie_ep {
5465 + struct pci_epc *epc;
5466 + struct mobiveil_pcie_ep_ops *ops;
5467 + phys_addr_t phys_base;
5468 + size_t addr_size;
5469 + size_t page_size;
5470 + phys_addr_t *outbound_addr;
5471 + unsigned long *ob_window_map;
5472 + u32 num_ob_windows;
5473 + void __iomem *msi_mem;
5474 + phys_addr_t msi_mem_phys;
5475 + u8 msi_cap; /* MSI capability offset */
5476 + u8 msix_cap; /* MSI-X capability offset */
5477 + u8 bar_num;
5478 + u32 pf_num;
5479 +};
5480 +
5481 +struct mobiveil_pcie {
5482 + struct platform_device *pdev;
5483 + struct list_head *resources;
5484 + void __iomem *csr_axi_slave_base; /* PAB registers base */
5485 + phys_addr_t pcie_reg_base; /* Physical PCIe Controller Base */
5486 + void __iomem *apb_csr_base; /* MSI register base */
5487 + u32 apio_wins;
5488 + u32 ppio_wins;
5489 + u32 ob_wins_configured; /* configured outbound windows */
5490 + u32 ib_wins_configured; /* configured inbound windows */
5491 + const struct mobiveil_pab_ops *ops;
5492 + struct root_port rp;
5493 + struct mobiveil_pcie_ep ep;
5494 +};
5495 +#define to_mobiveil_pcie_from_ep(endpoint) \
5496 + container_of((endpoint), struct mobiveil_pcie, ep)
5497 +
5498 +int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
5499 +int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
5500 +bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
5501 +int mobiveil_bringup_link(struct mobiveil_pcie *pcie);
5502 +void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5503 + u64 pci_addr, u32 type, u64 size);
5504 +void program_ib_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
5505 + u64 pci_addr, u32 type, u64 size);
5506 +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pci, int win_num);
5507 +void mobiveil_pcie_disable_ib_win(struct mobiveil_pcie *pci, int win_num);
5508 +u32 csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size);
5509 +void csr_write(struct mobiveil_pcie *pcie, u32 val, u32 off, size_t size);
5510 +
5511 +static inline u32 csr_readl(struct mobiveil_pcie *pcie, u32 off)
5512 +{
5513 + return csr_read(pcie, off, 0x4);
5514 +}
5515 +
5516 +static inline u32 csr_readw(struct mobiveil_pcie *pcie, u32 off)
5517 +{
5518 + return csr_read(pcie, off, 0x2);
5519 +}
5520 +
5521 +static inline u32 csr_readb(struct mobiveil_pcie *pcie, u32 off)
5522 +{
5523 + return csr_read(pcie, off, 0x1);
5524 +}
5525 +
5526 +static inline void csr_writel(struct mobiveil_pcie *pcie, u32 val, u32 off)
5527 +{
5528 + csr_write(pcie, val, off, 0x4);
5529 +}
5530 +
5531 +static inline void csr_writew(struct mobiveil_pcie *pcie, u32 val, u32 off)
5532 +{
5533 + csr_write(pcie, val, off, 0x2);
5534 +}
5535 +
5536 +static inline void csr_writeb(struct mobiveil_pcie *pcie, u32 val, u32 off)
5537 +{
5538 + csr_write(pcie, val, off, 0x1);
5539 +}
5540 +
5541 +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
5542 + int bar, u64 phys);
5543 +int program_ob_windows_ep(struct mobiveil_pcie *pcie, int win_num, int type,
5544 + u64 phys, u64 bus_addr, u8 func, u64 size);
5545 +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pci,
5546 + u8 func_no, u8 bar);
5547 +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep);
5548 +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no);
5549 +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
5550 + u8 interrupt_num);
5551 +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
5552 + u16 interrupt_num);
5553 +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pci, enum pci_barno bar);
5554 +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pci);
5555 +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pci);
5556 +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pci);
5557 +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pci);
5558 +#endif /* _PCIE_MOBIVEIL_H */
5559 --- a/drivers/pci/pcie/portdrv_core.c
5560 +++ b/drivers/pci/pcie/portdrv_core.c
5561 @@ -45,6 +45,20 @@ static void release_pcie_device(struct d
5562 }
5563
5564 /**
5565 + * pcibios_check_service_irqs - check irqs in the device tree
5566 + * @dev: PCI Express port to handle
5567 + * @irqs: Array of irqs to populate
5568 + * @mask: Bitmask of port capabilities returned by get_port_device_capability()
5569 + *
5570 + * Return value: 0 means no service irqs in the device tree
5571 + *
5572 + */
5573 +int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
5574 +{
5575 + return 0;
5576 +}
5577 +
5578 +/**
5579 * pcie_port_enable_irq_vec - try to set up MSI-X or MSI as interrupt mode
5580 * for given port
5581 * @dev: PCI Express port to handle
5582 @@ -185,10 +199,25 @@ out_free_irqs:
5583 static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
5584 {
5585 int ret, i;
5586 + int irq = -1;
5587
5588 for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
5589 irqs[i] = -1;
5590
5591 + /* Check if some platforms owns independent irq pins for AER/PME etc.
5592 + * Some platforms may own independent AER/PME interrupts and set
5593 + * them in the device tree file.
5594 + */
5595 + ret = pcibios_check_service_irqs(dev, irqs, mask);
5596 + if (ret) {
5597 + if (dev->irq)
5598 + irq = dev->irq;
5599 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
5600 + if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
5601 + irqs[i] = irq;
5602 + return 0;
5603 + }
5604 +
5605 /*
5606 * If we support PME or hotplug, but we can't use MSI/MSI-X for
5607 * them, we have to fall back to INTx or other interrupts, e.g., a
5608 --- a/drivers/pci/quirks.c
5609 +++ b/drivers/pci/quirks.c
5610 @@ -3394,6 +3394,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_A
5611 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
5612 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset);
5613
5614 +/*
5615 + * NXP (Freescale Vendor ID) LS1088 chips do not behave correctly after
5616 + * bus reset. Link state of device does not comes UP and so config space
5617 + * never accessible again.
5618 + */
5619 +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x80c0, quirk_no_bus_reset);
5620 +
5621 static void quirk_no_pm_reset(struct pci_dev *dev)
5622 {
5623 /*
5624 @@ -4878,3 +4885,11 @@ static void quirk_no_ats(struct pci_dev
5625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
5626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_no_ats);
5627 #endif /* CONFIG_PCI_ATS */
5628 +
5629 +/* Freescale PCIe doesn't support MSI in RC mode */
5630 +static void quirk_fsl_no_msi(struct pci_dev *pdev)
5631 +{
5632 + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
5633 + pdev->no_msi = 1;
5634 +}
5635 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
5636 --- a/include/linux/pci-ep-cfs.h
5637 +++ b/include/linux/pci-ep-cfs.h
5638 @@ -1,12 +1,9 @@
5639 +/* SPDX-License-Identifier: GPL-2.0+ */
5640 /**
5641 * PCI Endpoint ConfigFS header file
5642 *
5643 * Copyright (C) 2017 Texas Instruments
5644 * Author: Kishon Vijay Abraham I <kishon@ti.com>
5645 - *
5646 - * This program is free software: you can redistribute it and/or modify
5647 - * it under the terms of the GNU General Public License version 2 of
5648 - * the License as published by the Free Software Foundation.
5649 */
5650
5651 #ifndef __LINUX_PCI_EP_CFS_H
5652 --- a/include/linux/pci-epc.h
5653 +++ b/include/linux/pci-epc.h
5654 @@ -1,12 +1,9 @@
5655 +/* SPDX-License-Identifier: GPL-2.0+ */
5656 /**
5657 * PCI Endpoint *Controller* (EPC) header file
5658 *
5659 * Copyright (C) 2017 Texas Instruments
5660 * Author: Kishon Vijay Abraham I <kishon@ti.com>
5661 - *
5662 - * This program is free software: you can redistribute it and/or modify
5663 - * it under the terms of the GNU General Public License version 2 of
5664 - * the License as published by the Free Software Foundation.
5665 */
5666
5667 #ifndef __LINUX_PCI_EPC_H
5668 @@ -20,6 +17,7 @@ enum pci_epc_irq_type {
5669 PCI_EPC_IRQ_UNKNOWN,
5670 PCI_EPC_IRQ_LEGACY,
5671 PCI_EPC_IRQ_MSI,
5672 + PCI_EPC_IRQ_MSIX,
5673 };
5674
5675 /**
5676 @@ -33,24 +31,32 @@ enum pci_epc_irq_type {
5677 * capability register
5678 * @get_msi: ops to get the number of MSI interrupts allocated by the RC from
5679 * the MSI capability register
5680 - * @raise_irq: ops to raise a legacy or MSI interrupt
5681 + * @set_msix: ops to set the requested number of MSI-X interrupts in the
5682 + * MSI-X capability register
5683 + * @get_msix: ops to get the number of MSI-X interrupts allocated by the RC
5684 + * from the MSI-X capability register
5685 + * @raise_irq: ops to raise a legacy, MSI or MSI-X interrupt
5686 * @start: ops to start the PCI link
5687 * @stop: ops to stop the PCI link
5688 * @owner: the module owner containing the ops
5689 */
5690 struct pci_epc_ops {
5691 - int (*write_header)(struct pci_epc *pci_epc,
5692 + int (*write_header)(struct pci_epc *epc, u8 func_no,
5693 struct pci_epf_header *hdr);
5694 - int (*set_bar)(struct pci_epc *epc, enum pci_barno bar,
5695 - dma_addr_t bar_phys, size_t size, int flags);
5696 - void (*clear_bar)(struct pci_epc *epc, enum pci_barno bar);
5697 - int (*map_addr)(struct pci_epc *epc, phys_addr_t addr,
5698 - u64 pci_addr, size_t size);
5699 - void (*unmap_addr)(struct pci_epc *epc, phys_addr_t addr);
5700 - int (*set_msi)(struct pci_epc *epc, u8 interrupts);
5701 - int (*get_msi)(struct pci_epc *epc);
5702 - int (*raise_irq)(struct pci_epc *pci_epc,
5703 - enum pci_epc_irq_type type, u8 interrupt_num);
5704 + int (*set_bar)(struct pci_epc *epc, u8 func_no,
5705 + struct pci_epf_bar *epf_bar);
5706 + void (*clear_bar)(struct pci_epc *epc, u8 func_no,
5707 + struct pci_epf_bar *epf_bar);
5708 + int (*map_addr)(struct pci_epc *epc, u8 func_no,
5709 + phys_addr_t addr, u64 pci_addr, size_t size);
5710 + void (*unmap_addr)(struct pci_epc *epc, u8 func_no,
5711 + phys_addr_t addr);
5712 + int (*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
5713 + int (*get_msi)(struct pci_epc *epc, u8 func_no);
5714 + int (*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts);
5715 + int (*get_msix)(struct pci_epc *epc, u8 func_no);
5716 + int (*raise_irq)(struct pci_epc *epc, u8 func_no,
5717 + enum pci_epc_irq_type type, u16 interrupt_num);
5718 int (*start)(struct pci_epc *epc);
5719 void (*stop)(struct pci_epc *epc);
5720 struct module *owner;
5721 @@ -91,8 +97,17 @@ struct pci_epc {
5722 struct config_group *group;
5723 /* spinlock to protect against concurrent access of EP controller */
5724 spinlock_t lock;
5725 + unsigned int features;
5726 };
5727
5728 +#define EPC_FEATURE_NO_LINKUP_NOTIFIER BIT(0)
5729 +#define EPC_FEATURE_BAR_MASK (BIT(1) | BIT(2) | BIT(3))
5730 +#define EPC_FEATURE_MSIX_AVAILABLE BIT(4)
5731 +#define EPC_FEATURE_SET_BAR(features, bar) \
5732 + (features |= (EPC_FEATURE_BAR_MASK & (bar << 1)))
5733 +#define EPC_FEATURE_GET_BAR(features) \
5734 + ((features & EPC_FEATURE_BAR_MASK) >> 1)
5735 +
5736 #define to_pci_epc(device) container_of((device), struct pci_epc, dev)
5737
5738 #define pci_epc_create(dev, ops) \
5739 @@ -124,17 +139,23 @@ void pci_epc_destroy(struct pci_epc *epc
5740 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
5741 void pci_epc_linkup(struct pci_epc *epc);
5742 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
5743 -int pci_epc_write_header(struct pci_epc *epc, struct pci_epf_header *hdr);
5744 -int pci_epc_set_bar(struct pci_epc *epc, enum pci_barno bar,
5745 - dma_addr_t bar_phys, size_t size, int flags);
5746 -void pci_epc_clear_bar(struct pci_epc *epc, int bar);
5747 -int pci_epc_map_addr(struct pci_epc *epc, phys_addr_t phys_addr,
5748 +int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
5749 + struct pci_epf_header *hdr);
5750 +int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
5751 + struct pci_epf_bar *epf_bar);
5752 +void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
5753 + struct pci_epf_bar *epf_bar);
5754 +int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
5755 + phys_addr_t phys_addr,
5756 u64 pci_addr, size_t size);
5757 -void pci_epc_unmap_addr(struct pci_epc *epc, phys_addr_t phys_addr);
5758 -int pci_epc_set_msi(struct pci_epc *epc, u8 interrupts);
5759 -int pci_epc_get_msi(struct pci_epc *epc);
5760 -int pci_epc_raise_irq(struct pci_epc *epc, enum pci_epc_irq_type type,
5761 - u8 interrupt_num);
5762 +void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
5763 + phys_addr_t phys_addr);
5764 +int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
5765 +int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
5766 +int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts);
5767 +int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
5768 +int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
5769 + enum pci_epc_irq_type type, u16 interrupt_num);
5770 int pci_epc_start(struct pci_epc *epc);
5771 void pci_epc_stop(struct pci_epc *epc);
5772 struct pci_epc *pci_epc_get(const char *epc_name);
5773 --- a/include/linux/pci-epf.h
5774 +++ b/include/linux/pci-epf.h
5775 @@ -1,12 +1,9 @@
5776 +/* SPDX-License-Identifier: GPL-2.0+ */
5777 /**
5778 * PCI Endpoint *Function* (EPF) header file
5779 *
5780 * Copyright (C) 2017 Texas Instruments
5781 * Author: Kishon Vijay Abraham I <kishon@ti.com>
5782 - *
5783 - * This program is free software: you can redistribute it and/or modify
5784 - * it under the terms of the GNU General Public License version 2 of
5785 - * the License as published by the Free Software Foundation.
5786 */
5787
5788 #ifndef __LINUX_PCI_EPF_H
5789 @@ -75,7 +72,7 @@ struct pci_epf_ops {
5790 * @driver: PCI EPF driver
5791 * @ops: set of function pointers for performing EPF operations
5792 * @owner: the owner of the module that registers the PCI EPF driver
5793 - * @group: configfs group corresponding to the PCI EPF driver
5794 + * @epf_group: list of configfs group corresponding to the PCI EPF driver
5795 * @id_table: identifies EPF devices for probing
5796 */
5797 struct pci_epf_driver {
5798 @@ -85,7 +82,7 @@ struct pci_epf_driver {
5799 struct device_driver driver;
5800 struct pci_epf_ops *ops;
5801 struct module *owner;
5802 - struct config_group *group;
5803 + struct list_head epf_group;
5804 const struct pci_epf_device_id *id_table;
5805 };
5806
5807 @@ -100,6 +97,8 @@ struct pci_epf_driver {
5808 struct pci_epf_bar {
5809 dma_addr_t phys_addr;
5810 size_t size;
5811 + enum pci_barno barno;
5812 + int flags;
5813 };
5814
5815 /**
5816 @@ -120,6 +119,7 @@ struct pci_epf {
5817 struct pci_epf_header *header;
5818 struct pci_epf_bar bar[6];
5819 u8 msi_interrupts;
5820 + u16 msix_interrupts;
5821 u8 func_no;
5822
5823 struct pci_epc *epc;
5824 --- a/include/linux/pci.h
5825 +++ b/include/linux/pci.h
5826 @@ -1946,6 +1946,7 @@ void pcibios_release_device(struct pci_d
5827 void pcibios_penalize_isa_irq(int irq, int active);
5828 int pcibios_alloc_irq(struct pci_dev *dev);
5829 void pcibios_free_irq(struct pci_dev *dev);
5830 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
5831
5832 #ifdef CONFIG_HIBERNATE_CALLBACKS
5833 extern struct dev_pm_ops pcibios_pm_ops;
5834 --- a/include/uapi/linux/pcitest.h
5835 +++ b/include/uapi/linux/pcitest.h
5836 @@ -16,5 +16,8 @@
5837 #define PCITEST_WRITE _IOW('P', 0x4, unsigned long)
5838 #define PCITEST_READ _IOW('P', 0x5, unsigned long)
5839 #define PCITEST_COPY _IOW('P', 0x6, unsigned long)
5840 +#define PCITEST_MSIX _IOW('P', 0x7, int)
5841 +#define PCITEST_SET_IRQTYPE _IOW('P', 0x8, int)
5842 +#define PCITEST_GET_IRQTYPE _IO('P', 0x9)
5843
5844 #endif /* __UAPI_LINUX_PCITEST_H */
5845 --- a/tools/pci/pcitest.c
5846 +++ b/tools/pci/pcitest.c
5847 @@ -31,12 +31,17 @@
5848 #define BILLION 1E9
5849
5850 static char *result[] = { "NOT OKAY", "OKAY" };
5851 +static char *irq[] = { "LEGACY", "MSI", "MSI-X" };
5852
5853 struct pci_test {
5854 char *device;
5855 char barnum;
5856 bool legacyirq;
5857 unsigned int msinum;
5858 + unsigned int msixnum;
5859 + int irqtype;
5860 + bool set_irqtype;
5861 + bool get_irqtype;
5862 bool read;
5863 bool write;
5864 bool copy;
5865 @@ -65,6 +70,24 @@ static int run_test(struct pci_test *tes
5866 fprintf(stdout, "%s\n", result[ret]);
5867 }
5868
5869 + if (test->set_irqtype) {
5870 + ret = ioctl(fd, PCITEST_SET_IRQTYPE, test->irqtype);
5871 + fprintf(stdout, "SET IRQ TYPE TO %s:\t\t", irq[test->irqtype]);
5872 + if (ret < 0)
5873 + fprintf(stdout, "FAILED\n");
5874 + else
5875 + fprintf(stdout, "%s\n", result[ret]);
5876 + }
5877 +
5878 + if (test->get_irqtype) {
5879 + ret = ioctl(fd, PCITEST_GET_IRQTYPE);
5880 + fprintf(stdout, "GET IRQ TYPE:\t\t");
5881 + if (ret < 0)
5882 + fprintf(stdout, "FAILED\n");
5883 + else
5884 + fprintf(stdout, "%s\n", irq[ret]);
5885 + }
5886 +
5887 if (test->legacyirq) {
5888 ret = ioctl(fd, PCITEST_LEGACY_IRQ, 0);
5889 fprintf(stdout, "LEGACY IRQ:\t");
5890 @@ -83,6 +106,15 @@ static int run_test(struct pci_test *tes
5891 fprintf(stdout, "%s\n", result[ret]);
5892 }
5893
5894 + if (test->msixnum > 0 && test->msixnum <= 2048) {
5895 + ret = ioctl(fd, PCITEST_MSIX, test->msixnum);
5896 + fprintf(stdout, "MSI-X%d:\t\t", test->msixnum);
5897 + if (ret < 0)
5898 + fprintf(stdout, "TEST FAILED\n");
5899 + else
5900 + fprintf(stdout, "%s\n", result[ret]);
5901 + }
5902 +
5903 if (test->write) {
5904 ret = ioctl(fd, PCITEST_WRITE, test->size);
5905 fprintf(stdout, "WRITE (%7ld bytes):\t\t", test->size);
5906 @@ -133,7 +165,7 @@ int main(int argc, char **argv)
5907 /* set default endpoint device */
5908 test->device = "/dev/pci-endpoint-test.0";
5909
5910 - while ((c = getopt(argc, argv, "D:b:m:lrwcs:")) != EOF)
5911 + while ((c = getopt(argc, argv, "D:b:m:x:i:Ilrwcs:")) != EOF)
5912 switch (c) {
5913 case 'D':
5914 test->device = optarg;
5915 @@ -151,6 +183,20 @@ int main(int argc, char **argv)
5916 if (test->msinum < 1 || test->msinum > 32)
5917 goto usage;
5918 continue;
5919 + case 'x':
5920 + test->msixnum = atoi(optarg);
5921 + if (test->msixnum < 1 || test->msixnum > 2048)
5922 + goto usage;
5923 + continue;
5924 + case 'i':
5925 + test->irqtype = atoi(optarg);
5926 + if (test->irqtype < 0 || test->irqtype > 2)
5927 + goto usage;
5928 + test->set_irqtype = true;
5929 + continue;
5930 + case 'I':
5931 + test->get_irqtype = true;
5932 + continue;
5933 case 'r':
5934 test->read = true;
5935 continue;
5936 @@ -173,6 +219,9 @@ usage:
5937 "\t-D <dev> PCI endpoint test device {default: /dev/pci-endpoint-test.0}\n"
5938 "\t-b <bar num> BAR test (bar number between 0..5)\n"
5939 "\t-m <msi num> MSI test (msi number between 1..32)\n"
5940 + "\t-x <msix num> \tMSI-X test (msix number between 1..2048)\n"
5941 + "\t-i <irq type> \tSet IRQ type (0 - Legacy, 1 - MSI, 2 - MSI-X)\n"
5942 + "\t-I Get current IRQ type configured\n"
5943 "\t-l Legacy IRQ test\n"
5944 "\t-r Read buffer test\n"
5945 "\t-w Write buffer test\n"
5946 --- a/tools/pci/pcitest.sh
5947 +++ b/tools/pci/pcitest.sh
5948 @@ -16,7 +16,10 @@ echo
5949 echo "Interrupt tests"
5950 echo
5951
5952 +pcitest -i 0
5953 pcitest -l
5954 +
5955 +pcitest -i 1
5956 msi=1
5957
5958 while [ $msi -lt 33 ]
5959 @@ -26,9 +29,21 @@ do
5960 done
5961 echo
5962
5963 +pcitest -i 2
5964 +msix=1
5965 +
5966 +while [ $msix -lt 2049 ]
5967 +do
5968 + pcitest -x $msix
5969 + msix=`expr $msix + 1`
5970 +done
5971 +echo
5972 +
5973 echo "Read Tests"
5974 echo
5975
5976 +pcitest -i 1
5977 +
5978 pcitest -r -s 1
5979 pcitest -r -s 1024
5980 pcitest -r -s 1025
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