target/linux/layerscape/patches-4.4/1106-mtd-fsl-quadspi-add-DDR-quad-read-for-Spansion.patch

   1 From 16eb35ceea5b43e6f64c1a869721ea86c0da5260 Mon Sep 17 00:00:00 2001
   2 From: Yunhui Cui <yunhui.cui@nxp.com>
   3 Date: Thu, 25 Feb 2016 10:19:15 +0800
   4 Subject: [PATCH 106/113] mtd: fsl-quadspi: add DDR quad read for Spansion
   5
   6 Add the DDR quad read support for the fsl-quadspi driver.
   7 And, add the Spansion s25fl128s NOR flash ddr quad mode
   8 support.
   9
  10 Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
  11 ---
  12  drivers/mtd/spi-nor/fsl-quadspi.c |   57 +++++++++++++++++++++++++++++++++++++
  13  1 file changed, 57 insertions(+)
  14
  15 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
  16 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
  17 @@ -296,6 +296,7 @@ struct fsl_qspi {
  18         u32 nor_size;
  19         u32 nor_num;
  20         u32 clk_rate;
  21 +       u32 ddr_smp;
  22         unsigned int chip_base_addr; /* We may support two chips. */
  23         bool has_second_chip;
  24         bool big_endian;
  25 @@ -423,6 +424,19 @@ static void fsl_qspi_init_lut(struct fsl
  26                 qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
  27                             LUT1(FSL_READ, PAD4, rxfifo),
  28                                 base + QUADSPI_LUT(lut_base + 1));
  29 +       } else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
  30 +               /* read mode : 1-4-4, such as Spansion s25fl128s. */
  31 +               qspi_writel(q, LUT0(CMD, PAD1, read_op)
  32 +                       | LUT1(ADDR_DDR, PAD4, addrlen),
  33 +                       base + QUADSPI_LUT(lut_base));
  34 +
  35 +               qspi_writel(q, LUT0(MODE_DDR, PAD4, 0xff)
  36 +                       | LUT1(DUMMY, PAD1, read_dm),
  37 +                       base + QUADSPI_LUT(lut_base + 1));
  38 +
  39 +               qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo)
  40 +                       | LUT1(JMP_ON_CS, PAD1, 0),
  41 +                       base + QUADSPI_LUT(lut_base + 2));
  42         }
  43
  44         /* Write enable */
  45 @@ -534,6 +548,8 @@ static void fsl_qspi_init_lut(struct fsl
  46  static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
  47  {
  48         switch (cmd) {
  49 +       case SPINOR_OP_READ_1_4_4_D:
  50 +       case SPINOR_OP_READ4_1_4_4_D:
  51         case SPINOR_OP_READ4_1_1_4:
  52         case SPINOR_OP_READ_1_1_4:
  53         case SPINOR_OP_READ_FAST:
  54 @@ -736,6 +752,32 @@ static void fsl_qspi_set_map_addr(struct
  55  }
  56
  57  /*
  58 + * enable controller ddr quad mode to support different
  59 + * vender flashes ddr quad mode.
  60 + */
  61 +static void set_ddr_quad_mode(struct fsl_qspi *q)
  62 +{
  63 +       u32 reg, reg2;
  64 +
  65 +       reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
  66 +
  67 +       /* Firstly, disable the module */
  68 +       qspi_writel(q, reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
  69 +
  70 +       /* Set the Sampling Register for DDR */
  71 +       reg2 = qspi_readl(q, q->iobase + QUADSPI_SMPR);
  72 +       reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
  73 +       reg2 |= (((q->ddr_smp) << QUADSPI_SMPR_DDRSMP_SHIFT) &
  74 +                       QUADSPI_SMPR_DDRSMP_MASK);
  75 +       qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR);
  76 +
  77 +       /* Enable the module again (enable the DDR too) */
  78 +       reg |= QUADSPI_MCR_DDR_EN_MASK;
  79 +       qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
  80 +
  81 +}
  82 +
  83 +/*
  84   * There are two different ways to read out the data from the flash:
  85   *  the "IP Command Read" and the "AHB Command Read".
  86   *
  87 @@ -775,6 +817,11 @@ static void fsl_qspi_init_abh_read(struc
  88         seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
  89         qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
  90                 q->iobase + QUADSPI_BFGENCR);
  91 +
  92 +       /* enable the DDR quad read */
  93 +       if (q->nor->flash_read == SPI_NOR_DDR_QUAD)
  94 +               set_ddr_quad_mode(q);
  95 +
  96  }
  97
  98  /* This function was used to prepare and enable QSPI clock */
  99 @@ -1108,6 +1155,12 @@ static int fsl_qspi_probe(struct platfor
 100                 goto clk_failed;
 101         }
 102
 103 +       /* find ddrsmp value */
 104 +       ret = of_property_read_u32(dev->of_node, "fsl,ddr-sampling-point",
 105 +                               &q->ddr_smp);
 106 +       if (ret)
 107 +               q->ddr_smp = 0;
 108 +
 109         /* find the irq */
 110         ret = platform_get_irq(pdev, 0);
 111         if (ret < 0) {
 112 @@ -1164,6 +1217,10 @@ static int fsl_qspi_probe(struct platfor
 113
 114                 ret = of_property_read_bool(np, "m25p,fast-read");
 115                 mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
 116 +               /* Can we enable the DDR Quad Read? */
 117 +               ret = of_property_read_bool(np, "ddr-quad-read");
 118 +               if (ret)
 119 +                       mode = SPI_NOR_DDR_QUAD;
 120
 121                 ret = spi_nor_scan(nor, NULL, mode);
 122                 if (ret)