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layerscape: make uImage with zImage for 32-bit kernel
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.4 / 3028-dts-ls1043-update-dts-for-ls1043.patch
1 From ad6176d72132d020317db1496be1485056ac88d7 Mon Sep 17 00:00:00 2001
2 From: Liu Gang <Gang.Liu@nxp.com>
3 Date: Mon, 6 Jun 2016 15:46:00 +0800
4 Subject: [PATCH 28/70] dts/ls1043: update dts for ls1043
5
6 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
7 ---
8 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 59 +++++
9 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 264 +++++++++++++++++++-
10 .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 10 +-
11 3 files changed, 321 insertions(+), 12 deletions(-)
12
13 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
14 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
15 @@ -50,6 +50,10 @@
16 / {
17 model = "LS1043A RDB Board";
18 compatible = "fsl,ls1043a-rdb", "fsl,ls1043a";
19 +
20 + aliases {
21 + crypto = &crypto;
22 + };
23 };
24
25 &i2c0 {
26 @@ -108,6 +112,35 @@
27 };
28 };
29
30 +&dspi0 {
31 + bus-num = <0>;
32 + status = "okay";
33 +
34 + flash@0 {
35 + #address-cells = <1>;
36 + #size-cells = <1>;
37 + compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */
38 + reg = <0>;
39 + spi-max-frequency = <1000000>; /* input clock */
40 + };
41 +
42 + slic@2 {
43 + compatible = "maxim,ds26522";
44 + reg = <2>;
45 + spi-max-frequency = <2000000>;
46 + fsl,spi-cs-sck-delay = <100>;
47 + fsl,spi-sck-cs-delay = <50>;
48 + };
49 +
50 + slic@3 {
51 + compatible = "maxim,ds26522";
52 + reg = <3>;
53 + spi-max-frequency = <2000000>;
54 + fsl,spi-cs-sck-delay = <100>;
55 + fsl,spi-sck-cs-delay = <50>;
56 + };
57 +};
58 +
59 &duart0 {
60 status = "okay";
61 };
62 @@ -176,7 +209,33 @@
63 mdio@fd000 {
64 aqr105_phy: ethernet-phy@c {
65 compatible = "ethernet-phy-ieee802.3-c45";
66 + interrupts = <0 132 4>;
67 reg = <0x1>;
68 };
69 };
70 };
71 +
72 +&uqe {
73 + ucc_hdlc: ucc@2000 {
74 + compatible = "fsl,ucc_hdlc";
75 + rx-clock-name = "clk8";
76 + tx-clock-name = "clk9";
77 + fsl,rx-sync-clock = "rsync_pin";
78 + fsl,tx-sync-clock = "tsync_pin";
79 + fsl,tx-timeslot = <0xfffffffe>;
80 + fsl,rx-timeslot = <0xfffffffe>;
81 + fsl,tdm-framer-type = "e1";
82 + fsl,tdm-mode = "normal";
83 + fsl,tdm-id = <0>;
84 + fsl,siram-entry-id = <0>;
85 + fsl,tdm-interface;
86 + };
87 +
88 + ucc_serial: ucc@2200 {
89 + device_type = "serial";
90 + compatible = "ucc_uart";
91 + port-number = <0>;
92 + rx-clock-name = "brg2";
93 + tx-clock-name = "brg2";
94 + };
95 +};
96 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
97 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
98 @@ -44,6 +44,8 @@
99 * OTHER DEALINGS IN THE SOFTWARE.
100 */
101
102 +#include <dt-bindings/thermal/thermal.h>
103 +
104 / {
105 compatible = "fsl,ls1043a";
106 interrupt-parent = <&gic>;
107 @@ -75,6 +77,7 @@
108 compatible = "arm,cortex-a53";
109 reg = <0x0>;
110 clocks = <&clockgen 1 0>;
111 + #cooling-cells = <2>;
112 };
113
114 cpu1: cpu@1 {
115 @@ -118,6 +121,8 @@
116 <1 14 0x1>, /* Physical Non-Secure PPI */
117 <1 11 0x1>, /* Virtual PPI */
118 <1 10 0x1>; /* Hypervisor PPI */
119 + arm,reread-timer;
120 + fsl,erratum-a008585;
121 };
122
123 pmu {
124 @@ -162,11 +167,64 @@
125 big-endian;
126 };
127
128 + crypto: crypto@1700000 {
129 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
130 + "fsl,sec-v4.0";
131 + fsl,sec-era = <3>;
132 + #address-cells = <1>;
133 + #size-cells = <1>;
134 + ranges = <0x0 0x00 0x1700000 0x100000>;
135 + reg = <0x00 0x1700000 0x0 0x100000>;
136 + interrupts = <0 75 0x4>;
137 +
138 + sec_jr0: jr@10000 {
139 + compatible = "fsl,sec-v5.4-job-ring",
140 + "fsl,sec-v5.0-job-ring",
141 + "fsl,sec-v4.0-job-ring";
142 + reg = <0x10000 0x10000>;
143 + interrupts = <0 71 0x4>;
144 + };
145 +
146 + sec_jr1: jr@20000 {
147 + compatible = "fsl,sec-v5.4-job-ring",
148 + "fsl,sec-v5.0-job-ring",
149 + "fsl,sec-v4.0-job-ring";
150 + reg = <0x20000 0x10000>;
151 + interrupts = <0 72 0x4>;
152 + };
153 +
154 + sec_jr2: jr@30000 {
155 + compatible = "fsl,sec-v5.4-job-ring",
156 + "fsl,sec-v5.0-job-ring",
157 + "fsl,sec-v4.0-job-ring";
158 + interrupts = <0 73 0x4>;
159 + };
160 +
161 + sec_jr3: jr@40000 {
162 + compatible = "fsl,sec-v5.4-job-ring",
163 + "fsl,sec-v5.0-job-ring",
164 + "fsl,sec-v4.0-job-ring";
165 + reg = <0x40000 0x10000>;
166 + interrupts = <0 74 0x4>;
167 + };
168 + };
169 +
170 dcfg: dcfg@1ee0000 {
171 compatible = "fsl,ls1043a-dcfg", "syscon";
172 reg = <0x0 0x1ee0000 0x0 0x10000>;
173 };
174
175 + reset: reset@1EE00B0 {
176 + compatible = "fsl,ls-reset";
177 + reg = <0x0 0x1EE00B0 0x0 0x4>;
178 + big-endian;
179 + };
180 +
181 + rcpm: rcpm@1ee2000 {
182 + compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1";
183 + reg = <0x0 0x1ee2000 0x0 0x10000>;
184 + };
185 +
186 ifc: ifc@1530000 {
187 compatible = "fsl,ifc", "simple-bus";
188 reg = <0x0 0x1530000 0x0 0x10000>;
189 @@ -501,6 +559,82 @@
190 };
191 };
192
193 + tmu: tmu@1f00000 {
194 + compatible = "fsl,qoriq-tmu", "fsl,ls1043a-tmu";
195 + reg = <0x0 0x1f00000 0x0 0x10000>;
196 + interrupts = <0 33 0x4>;
197 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
198 + fsl,tmu-calibration = <0x00000000 0x00000026
199 + 0x00000001 0x0000002d
200 + 0x00000002 0x00000032
201 + 0x00000003 0x00000039
202 + 0x00000004 0x0000003f
203 + 0x00000005 0x00000046
204 + 0x00000006 0x0000004d
205 + 0x00000007 0x00000054
206 + 0x00000008 0x0000005a
207 + 0x00000009 0x00000061
208 + 0x0000000a 0x0000006a
209 + 0x0000000b 0x00000071
210 +
211 + 0x00010000 0x00000025
212 + 0x00010001 0x0000002c
213 + 0x00010002 0x00000035
214 + 0x00010003 0x0000003d
215 + 0x00010004 0x00000045
216 + 0x00010005 0x0000004e
217 + 0x00010006 0x00000057
218 + 0x00010007 0x00000061
219 + 0x00010008 0x0000006b
220 + 0x00010009 0x00000076
221 +
222 + 0x00020000 0x00000029
223 + 0x00020001 0x00000033
224 + 0x00020002 0x0000003d
225 + 0x00020003 0x00000049
226 + 0x00020004 0x00000056
227 + 0x00020005 0x00000061
228 + 0x00020006 0x0000006d
229 +
230 + 0x00030000 0x00000021
231 + 0x00030001 0x0000002a
232 + 0x00030002 0x0000003c
233 + 0x00030003 0x0000004e>;
234 + big-endian;
235 + #thermal-sensor-cells = <1>;
236 + };
237 +
238 + thermal-zones {
239 + cpu_thermal: cpu-thermal {
240 + polling-delay-passive = <1000>;
241 + polling-delay = <5000>;
242 +
243 + thermal-sensors = <&tmu 3>;
244 +
245 + trips {
246 + cpu_alert: cpu-alert {
247 + temperature = <85000>;
248 + hysteresis = <2000>;
249 + type = "passive";
250 + };
251 + cpu_crit: cpu-crit {
252 + temperature = <95000>;
253 + hysteresis = <2000>;
254 + type = "critical";
255 + };
256 + };
257 +
258 + cooling-maps {
259 + map0 {
260 + trip = <&cpu_alert>;
261 + cooling-device =
262 + <&cpu0 THERMAL_NO_LIMIT
263 + THERMAL_NO_LIMIT>;
264 + };
265 + };
266 + };
267 + };
268 +
269 dspi0: dspi@2100000 {
270 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
271 #address-cells = <1>;
272 @@ -527,6 +661,20 @@
273 status = "disabled";
274 };
275
276 + qspi: quadspi@1550000 {
277 + compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
278 + #address-cells = <1>;
279 + #size-cells = <0>;
280 + reg = <0x0 0x1550000 0x0 0x10000>,
281 + <0x0 0x40000000 0x0 0x4000000>;
282 + reg-names = "QuadSPI", "QuadSPI-memory";
283 + interrupts = <0 99 0x4>;
284 + clock-names = "qspi_en", "qspi";
285 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
286 + big-endian;
287 + status = "disabled";
288 + };
289 +
290 i2c0: i2c@2180000 {
291 compatible = "fsl,vf610-i2c";
292 #address-cells = <1>;
293 @@ -602,8 +750,8 @@
294 clocks = <&clockgen 4 0>;
295 };
296
297 - gpio1: gpio@2300000 {
298 - compatible = "fsl,ls1043a-gpio";
299 + gpio0: gpio@2300000 {
300 + compatible = "fsl,qoriq-gpio";
301 reg = <0x0 0x2300000 0x0 0x10000>;
302 interrupts = <0 66 0x4>;
303 gpio-controller;
304 @@ -612,8 +760,8 @@
305 #interrupt-cells = <2>;
306 };
307
308 - gpio2: gpio@2310000 {
309 - compatible = "fsl,ls1043a-gpio";
310 + gpio1: gpio@2310000 {
311 + compatible = "fsl,qoriq-gpio";
312 reg = <0x0 0x2310000 0x0 0x10000>;
313 interrupts = <0 67 0x4>;
314 gpio-controller;
315 @@ -622,8 +770,8 @@
316 #interrupt-cells = <2>;
317 };
318
319 - gpio3: gpio@2320000 {
320 - compatible = "fsl,ls1043a-gpio";
321 + gpio2: gpio@2320000 {
322 + compatible = "fsl,qoriq-gpio";
323 reg = <0x0 0x2320000 0x0 0x10000>;
324 interrupts = <0 68 0x4>;
325 gpio-controller;
326 @@ -632,8 +780,8 @@
327 #interrupt-cells = <2>;
328 };
329
330 - gpio4: gpio@2330000 {
331 - compatible = "fsl,ls1043a-gpio";
332 + gpio3: gpio@2330000 {
333 + compatible = "fsl,qoriq-gpio";
334 reg = <0x0 0x2330000 0x0 0x10000>;
335 interrupts = <0 134 0x4>;
336 gpio-controller;
337 @@ -642,6 +790,70 @@
338 #interrupt-cells = <2>;
339 };
340
341 + uqe: uqe@2400000 {
342 + #address-cells = <1>;
343 + #size-cells = <1>;
344 + device_type = "qe";
345 + compatible = "fsl,qe", "simple-bus";
346 + ranges = <0x0 0x0 0x2400000 0x40000>;
347 + reg = <0x0 0x2400000 0x0 0x480>;
348 + brg-frequency = <100000000>;
349 + bus-frequency = <200000000>;
350 +
351 + fsl,qe-num-riscs = <1>;
352 + fsl,qe-num-snums = <28>;
353 +
354 + qeic: qeic@80 {
355 + compatible = "fsl,qe-ic";
356 + reg = <0x80 0x80>;
357 + #address-cells = <0>;
358 + interrupt-controller;
359 + #interrupt-cells = <1>;
360 + interrupts = <0 77 0x04 0 77 0x04>;
361 + };
362 +
363 + si1: si@700 {
364 + #address-cells = <1>;
365 + #size-cells = <0>;
366 + compatible = "fsl,qe-si";
367 + reg = <0x700 0x80>;
368 + };
369 +
370 + siram1: siram@1000 {
371 + #address-cells = <1>;
372 + #size-cells = <1>;
373 + compatible = "fsl,qe-siram";
374 + reg = <0x1000 0x800>;
375 + };
376 +
377 + ucc@2000 {
378 + cell-index = <1>;
379 + reg = <0x2000 0x200>;
380 + interrupts = <32>;
381 + interrupt-parent = <&qeic>;
382 + };
383 +
384 + ucc@2200 {
385 + cell-index = <3>;
386 + reg = <0x2200 0x200>;
387 + interrupts = <34>;
388 + interrupt-parent = <&qeic>;
389 + };
390 +
391 + muram@10000 {
392 + #address-cells = <1>;
393 + #size-cells = <1>;
394 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
395 + ranges = <0x0 0x10000 0x6000>;
396 +
397 + data-only@0 {
398 + compatible = "fsl,qe-muram-data",
399 + "fsl,cpm-muram-data";
400 + reg = <0x0 0x6000>;
401 + };
402 + };
403 + };
404 +
405 lpuart0: serial@2950000 {
406 compatible = "fsl,ls1021a-lpuart";
407 reg = <0x0 0x2950000 0x0 0x1000>;
408 @@ -696,6 +908,15 @@
409 status = "disabled";
410 };
411
412 + ftm0: ftm0@29d0000 {
413 + compatible = "fsl,ftm-alarm";
414 + reg = <0x0 0x29d0000 0x0 0x10000>;
415 + interrupts = <0 86 0x4>;
416 + big-endian;
417 + rcpm-wakeup = <&rcpm 0x0 0x20000000>;
418 + status = "okay";
419 + };
420 +
421 wdog0: wdog@2ad0000 {
422 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
423 reg = <0x0 0x2ad0000 0x0 0x10000>;
424 @@ -726,6 +947,8 @@
425 reg = <0x0 0x2f00000 0x0 0x10000>;
426 interrupts = <0 60 0x4>;
427 dr_mode = "host";
428 + configure-gfladj;
429 + snps,dis_rxdet_inp3_quirk;
430 };
431
432 usb1: usb3@3000000 {
433 @@ -733,6 +956,8 @@
434 reg = <0x0 0x3000000 0x0 0x10000>;
435 interrupts = <0 61 0x4>;
436 dr_mode = "host";
437 + configure-gfladj;
438 + snps,dis_rxdet_inp3_quirk;
439 };
440
441 usb2: usb3@3100000 {
442 @@ -740,6 +965,8 @@
443 reg = <0x0 0x3100000 0x0 0x10000>;
444 interrupts = <0 63 0x4>;
445 dr_mode = "host";
446 + configure-gfladj;
447 + snps,dis_rxdet_inp3_quirk;
448 };
449
450 sata: sata@3200000 {
451 @@ -749,6 +976,20 @@
452 clocks = <&clockgen 4 0>;
453 };
454
455 + qdma: qdma@8380000 {
456 + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
457 + reg = <0x0 0x838f000 0x0 0x11000 /* Controller regs */
458 + 0x0 0x83a0000 0x0 0x40000>; /* Block regs */
459 + interrupts = <0 152 0x4>,
460 + <0 39 0x4>;
461 + interrupt-names = "qdma-error", "qdma-queue";
462 + channels = <8>;
463 + queues = <2>;
464 + status-sizes = <64>;
465 + queue-sizes = <64 64>;
466 + big-endian;
467 + };
468 +
469 msi1: msi-controller1@1571000 {
470 compatible = "fsl,1s1043a-msi";
471 reg = <0x0 0x1571000 0x0 0x4>,
472 @@ -787,6 +1028,7 @@
473 #address-cells = <3>;
474 #size-cells = <2>;
475 device_type = "pci";
476 + dma-coherent;
477 num-lanes = <4>;
478 bus-range = <0x0 0xff>;
479 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
480 @@ -811,6 +1053,7 @@
481 #address-cells = <3>;
482 #size-cells = <2>;
483 device_type = "pci";
484 + dma-coherent;
485 num-lanes = <2>;
486 bus-range = <0x0 0xff>;
487 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
488 @@ -835,6 +1078,7 @@
489 #address-cells = <3>;
490 #size-cells = <2>;
491 device_type = "pci";
492 + dma-coherent;
493 num-lanes = <2>;
494 bus-range = <0x0 0xff>;
495 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
496 @@ -897,8 +1141,8 @@
497 alignment = <0 0x1000000>;
498 };
499 qman_fqd: qman-fqd {
500 - size = <0 0x400000>;
501 - alignment = <0 0x400000>;
502 + size = <0 0x800000>;
503 + alignment = <0 0x800000>;
504 };
505 qman_pfdr: qman-pfdr {
506 size = <0 0x2000000>;
507 --- a/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
508 +++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
509 @@ -132,5 +132,11 @@
510 compatible = "fsl,cgrid-range";
511 fsl,cgrid-range = <0 256>;
512 };
513 -
514 -};
515 \ No newline at end of file
516 + qman-ceetm@0 {
517 + compatible = "fsl,qman-ceetm";
518 + fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
519 + fsl,ceetm-sp-range = <0 12>;
520 + fsl,ceetm-lni-range = <0 8>;
521 + fsl,ceetm-channel-range = <0 32>;
522 + };
523 +};
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