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kernel: update kernel 4.4 to version 4.4.30
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.4 / 3071-arm64-dts-add-device-tree-for-ls1012a-SoC-and-boards.patch
1 From 70e0080366e76dabf90b713f57fb9fc47aa35557 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Thu, 11 Aug 2016 10:36:05 +0800
4 Subject: [PATCH 071/113] arm64: dts: add device tree for ls1012a SoC and
5 boards
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 This patch is to add device tree for ls1012a SoC and RDB/FREEDOM boards.
11
12 Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
13 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
14 Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
15 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
16 Signed-off-by: Alison Wang <alison.wang@nxp.com>
17 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
18 Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com>
19 Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
20 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
21 Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
22 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
23 [yangbolu: integrate]
24 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
25 ---
26 arch/arm64/boot/dts/freescale/Makefile | 2 +
27 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 186 +++++++
28 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 114 +++++
29 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 526 ++++++++++++++++++++
30 4 files changed, 828 insertions(+)
31 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
32 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
33 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
34
35 --- a/arch/arm64/boot/dts/freescale/Makefile
36 +++ b/arch/arm64/boot/dts/freescale/Makefile
37 @@ -2,6 +2,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2
38 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
39 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
40 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
41 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
42 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
43
44 always := $(dtb-y)
45 subdir-y := $(dts-dirs)
46 --- /dev/null
47 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
48 @@ -0,0 +1,186 @@
49 +/*
50 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
51 + *
52 + * Copyright 2016, Freescale Semiconductor Inc.
53 +
54 + * Redistribution and use in source and binary forms, with or without
55 + * modification, are permitted provided that the following conditions are met:
56 + * * Redistributions of source code must retain the above copyright
57 + * notice, this list of conditions and the following disclaimer.
58 + * * Redistributions in binary form must reproduce the above copyright
59 + * notice, this list of conditions and the following disclaimer in the
60 + * documentation and/or other materials provided with the distribution.
61 + * * Neither the name of Freescale Semiconductor nor the
62 + * names of its contributors may be used to endorse or promote products
63 + * derived from this software without specific prior written permission.
64 + *
65 + *
66 + * ALTERNATIVELY, this software may be distributed under the terms of the
67 + * GNU General Public License ("GPL") as published by the Free Software
68 + * Foundation, either version 2 of that License or (at your option) any
69 + * later version.
70 + *
71 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
72 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
73 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
74 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
75 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
76 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
77 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
78 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
79 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
80 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
81 + */
82 +/dts-v1/;
83 +
84 +#include "fsl-ls1012a.dtsi"
85 +
86 +/ {
87 + model = "LS1012A FREEDOM Board";
88 + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
89 +
90 + aliases {
91 + crypto = &crypto;
92 + };
93 +
94 + sys_mclk: clock-mclk {
95 + compatible = "fixed-clock";
96 + #clock-cells = <0>;
97 + clock-frequency = <25000000>;
98 + };
99 +
100 + regulators {
101 + compatible = "simple-bus";
102 + #address-cells = <1>;
103 + #size-cells = <0>;
104 +
105 + reg_1p8v: regulator@0 {
106 + compatible = "regulator-fixed";
107 + reg = <0>;
108 + regulator-name = "1P8V";
109 + regulator-min-microvolt = <1800000>;
110 + regulator-max-microvolt = <1800000>;
111 + regulator-always-on;
112 + };
113 + };
114 +
115 + sound {
116 + compatible = "simple-audio-card";
117 + simple-audio-card,format = "i2s";
118 + simple-audio-card,widgets =
119 + "Microphone", "Microphone Jack",
120 + "Headphone", "Headphone Jack",
121 + "Speaker", "Speaker Ext",
122 + "Line", "Line In Jack";
123 + simple-audio-card,routing =
124 + "MIC_IN", "Microphone Jack",
125 + "Microphone Jack", "Mic Bias",
126 + "LINE_IN", "Line In Jack",
127 + "Headphone Jack", "HP_OUT",
128 + "Speaker Ext", "LINE_OUT";
129 +
130 + simple-audio-card,cpu {
131 + sound-dai = <&sai2>;
132 + frame-master;
133 + bitclock-master;
134 + };
135 +
136 + simple-audio-card,codec {
137 + sound-dai = <&codec>;
138 + frame-master;
139 + bitclock-master;
140 + system-clock-frequency = <25000000>;
141 + };
142 + };
143 +};
144 +
145 +&qspi {
146 + num-cs = <2>;
147 + bus-num = <0>;
148 + status = "okay";
149 + fsl,ddr-sampling-point = <4>;
150 +
151 + qflash0: s25fs512s@0 {
152 + compatible = "spansion,m25p80";
153 + #address-cells = <1>;
154 + #size-cells = <1>;
155 + spi-max-frequency = <20000000>;
156 + m25p,fast-read;
157 + reg = <0>;
158 + };
159 +};
160 +&ftm0 {
161 + status = "okay";
162 +};
163 +
164 +&i2c0 {
165 + status = "okay";
166 +
167 + codec: sgtl5000@a {
168 + #sound-dai-cells = <0>;
169 + compatible = "fsl,sgtl5000";
170 + reg = <0xa>;
171 + VDDA-supply = <&reg_1p8v>;
172 + VDDIO-supply = <&reg_1p8v>;
173 + clocks = <&sys_mclk 1>;
174 + };
175 +};
176 +
177 +&duart0 {
178 + status = "okay";
179 +};
180 +&pfe {
181 + status = "okay";
182 + ethernet@0 {
183 + compatible = "fsl,pfe-gemac-port";
184 + #address-cells = <1>;
185 + #size-cells = <0>;
186 + reg = < 0x0 >; /* GEM_ID */
187 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
188 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
189 + fsl,mdio-mux-val = <0x0>;
190 + local-mac-address = [ 00 1A 2B 3C 4D 5E ];
191 + phy-mode = "sgmii";
192 + fsl,pfe-gemac-if-name = "eth0";
193 + fsl,pfe-phy-if-flags = <0x0>;
194 + fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */
195 +
196 + mdio@0 {
197 + reg = <0x1>; /* enabled/disabled */
198 + fsl,mdio-phy-mask = <0xFFFFFFF9>;
199 + };
200 + };
201 + ethernet@1 {
202 + compatible = "fsl,pfe-gemac-port";
203 + #address-cells = <1>;
204 + #size-cells = <0>;
205 + reg = < 0x1 >; /* GEM_ID */
206 + fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
207 + fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
208 + fsl,mdio-mux-val = <0x0>;
209 + local-mac-address = [ 00 AA BB CC DD EE ];
210 + phy-mode = "sgmii";
211 + fsl,pfe-gemac-if-name = "eth1";
212 + fsl,pfe-phy-if-flags = <0x0>;
213 + fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */
214 + mdio@0 {
215 + reg = <0x0>; /* enabled/disabled */
216 + fsl,mdio-phy-mask = <0xFFFFFFF9>;
217 + };
218 +
219 + };
220 +
221 +};
222 +
223 +
224 +&esdhc0 {
225 + status = "disabled";
226 +};
227 +
228 +&esdhc1 {
229 + status = "disabled";
230 +};
231 +
232 +&sai2 {
233 + status = "okay";
234 +};
235 --- /dev/null
236 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
237 @@ -0,0 +1,114 @@
238 +/*
239 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
240 + *
241 + * Copyright 2016, Freescale Semiconductor Inc.
242 +
243 + * Redistribution and use in source and binary forms, with or without
244 + * modification, are permitted provided that the following conditions are met:
245 + * * Redistributions of source code must retain the above copyright
246 + * notice, this list of conditions and the following disclaimer.
247 + * * Redistributions in binary form must reproduce the above copyright
248 + * notice, this list of conditions and the following disclaimer in the
249 + * documentation and/or other materials provided with the distribution.
250 + * * Neither the name of Freescale Semiconductor nor the
251 + * names of its contributors may be used to endorse or promote products
252 + * derived from this software without specific prior written permission.
253 + *
254 + *
255 + * ALTERNATIVELY, this software may be distributed under the terms of the
256 + * GNU General Public License ("GPL") as published by the Free Software
257 + * Foundation, either version 2 of that License or (at your option) any
258 + * later version.
259 + *
260 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
261 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
262 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
263 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
264 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
265 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
266 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
267 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
268 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
269 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
270 + */
271 +/dts-v1/;
272 +
273 +#include "fsl-ls1012a.dtsi"
274 +
275 +/ {
276 + model = "LS1012A RDB Board";
277 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
278 +
279 + aliases {
280 + crypto = &crypto;
281 + };
282 +};
283 +
284 +&qspi {
285 + num-cs = <2>;
286 + bus-num = <0>;
287 + status = "okay";
288 + fsl,ddr-sampling-point = <4>;
289 +
290 + qflash0: s25fs512s@0 {
291 + compatible = "spansion,m25p80";
292 + #address-cells = <1>;
293 + #size-cells = <1>;
294 + spi-max-frequency = <20000000>;
295 + m25p,fast-read;
296 + reg = <0>;
297 + };
298 +};
299 +&ftm0 {
300 + status = "okay";
301 +};
302 +
303 +&i2c0 {
304 + status = "okay";
305 +};
306 +
307 +&duart0 {
308 + status = "okay";
309 +};
310 +&pfe {
311 + status = "okay";
312 + ethernet@0 {
313 + compatible = "fsl,pfe-gemac-port";
314 + #address-cells = <1>;
315 + #size-cells = <0>;
316 + reg = < 0x0 >; /* GEM_ID */
317 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
318 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
319 + fsl,mdio-mux-val = <0x0>;
320 + local-mac-address = [ 00 1A 2B 3C 4D 5E ];
321 + phy-mode = "sgmii";
322 + fsl,pfe-gemac-if-name = "eth0";
323 + fsl,pfe-phy-if-flags = <0x0>;
324 + fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */
325 +
326 + mdio@0 {
327 + reg = <0x1>; /* enabled/disabled */
328 + fsl,mdio-phy-mask = <0xFFFFFFF9>;
329 + };
330 + };
331 + ethernet@1 {
332 + compatible = "fsl,pfe-gemac-port";
333 + #address-cells = <1>;
334 + #size-cells = <0>;
335 + reg = < 0x1 >; /* GEM_ID */
336 + fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
337 + fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
338 + fsl,mdio-mux-val = <0x0>;
339 + local-mac-address = [ 00 AA BB CC DD EE ];
340 + phy-mode = "rgmii";
341 + fsl,pfe-gemac-if-name = "eth2";
342 + fsl,pfe-phy-if-flags = <0x0>;
343 + fsl,pfe-gemac-mode = <0x1B00>; /* GEMAC_SW_CONF | GEMAC_SW_FULL_DUPLEX | GEMAC_SW_SPEED_1G */
344 + mdio@0 {
345 + reg = <0x0>; /* enabled/disabled */
346 + fsl,mdio-phy-mask = <0xFFFFFFF9>;
347 + };
348 +
349 + };
350 +
351 +};
352 --- /dev/null
353 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
354 @@ -0,0 +1,526 @@
355 +/*
356 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
357 + *
358 + * Copyright 2016, Freescale Semiconductor
359 + *
360 + * This file is dual-licensed: you can use it either under the terms
361 + * of the GPLv2 or the X11 license, at your option. Note that this dual
362 + * licensing only applies to this file, and not this project as a
363 + * whole.
364 + *
365 + * a) This library is free software; you can redistribute it and/or
366 + * modify it under the terms of the GNU General Public License as
367 + * published by the Free Software Foundation; either version 2 of the
368 + * License, or (at your option) any later version.
369 + *
370 + * This library is distributed in the hope that it will be useful,
371 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
372 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
373 + * GNU General Public License for more details.
374 + *
375 + * Or, alternatively,
376 + *
377 + * b) Permission is hereby granted, free of charge, to any person
378 + * obtaining a copy of this software and associated documentation
379 + * files (the "Software"), to deal in the Software without
380 + * restriction, including without limitation the rights to use,
381 + * copy, modify, merge, publish, distribute, sublicense, and/or
382 + * sell copies of the Software, and to permit persons to whom the
383 + * Software is furnished to do so, subject to the following
384 + * conditions:
385 + *
386 + * The above copyright notice and this permission notice shall be
387 + * included in all copies or substantial portions of the Software.
388 + *
389 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
390 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
391 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
392 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
393 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
394 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
395 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
396 + * OTHER DEALINGS IN THE SOFTWARE.
397 + */
398 +
399 +#include <dt-bindings/thermal/thermal.h>
400 +
401 +/ {
402 + compatible = "fsl,ls1012a";
403 + interrupt-parent = <&gic>;
404 + #address-cells = <2>;
405 + #size-cells = <2>;
406 +
407 + cpus {
408 + #address-cells = <1>;
409 + #size-cells = <0>;
410 +
411 + /*
412 + * We expect the enable-method for cpu's to be "psci", but this
413 + * is dependent on the SoC FW, which will fill this in.
414 + *
415 + * Currently supported enable-method is psci v0.2
416 + */
417 + cpu0: cpu@0 {
418 + device_type = "cpu";
419 + compatible = "arm,cortex-a53";
420 + reg = <0x0>;
421 + clocks = <&clockgen 1 0>;
422 + #cooling-cells = <2>;
423 + };
424 +
425 + };
426 +
427 +
428 + sysclk: sysclk {
429 + compatible = "fixed-clock";
430 + #clock-cells = <0>;
431 + clock-frequency = <100000000>;
432 + clock-output-names = "sysclk";
433 + };
434 +
435 + timer {
436 + compatible = "arm,armv8-timer";
437 + interrupts = <1 13 0x1>, /* Physical Secure PPI */
438 + <1 14 0x1>, /* Physical Non-Secure PPI */
439 + <1 11 0x1>, /* Virtual PPI */
440 + <1 10 0x1>; /* Hypervisor PPI */
441 + arm,reread-timer;
442 + };
443 +
444 + pmu {
445 + compatible = "arm,armv8-pmuv3";
446 + interrupts = <0 106 0x4>;
447 + };
448 +
449 + gic: interrupt-controller@1400000 {
450 + compatible = "arm,gic-400";
451 + #interrupt-cells = <3>;
452 + interrupt-controller;
453 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
454 + <0x0 0x1402000 0 0x2000>, /* GICC */
455 + <0x0 0x1404000 0 0x2000>, /* GICH */
456 + <0x0 0x1406000 0 0x2000>; /* GICV */
457 + interrupts = <1 9 0xf08>;
458 + };
459 +
460 + soc {
461 + compatible = "simple-bus";
462 + #address-cells = <2>;
463 + #size-cells = <2>;
464 + ranges;
465 +
466 + clockgen: clocking@1ee1000 {
467 + compatible = "fsl,ls1012a-clockgen";
468 + reg = <0x0 0x1ee1000 0x0 0x1000>;
469 + #clock-cells = <2>;
470 + clocks = <&sysclk>;
471 + };
472 +
473 + scfg: scfg@1570000 {
474 + compatible = "fsl,ls1012a-scfg",
475 + "fsl,ls1043a-scfg",
476 + "syscon";
477 + reg = <0x0 0x1570000 0x0 0x10000>;
478 + big-endian;
479 + };
480 +
481 + crypto: crypto@1700000 {
482 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
483 + "fsl,sec-v4.0";
484 + fsl,sec-era = <8>;
485 + #address-cells = <1>;
486 + #size-cells = <1>;
487 + ranges = <0x0 0x00 0x1700000 0x100000>;
488 + reg = <0x00 0x1700000 0x0 0x100000>;
489 + interrupts = <0 75 0x4>;
490 +
491 + sec_jr0: jr@10000 {
492 + compatible = "fsl,sec-v5.4-job-ring",
493 + "fsl,sec-v5.0-job-ring",
494 + "fsl,sec-v4.0-job-ring";
495 + reg = <0x10000 0x10000>;
496 + interrupts = <0 71 0x4>;
497 + };
498 +
499 + sec_jr1: jr@20000 {
500 + compatible = "fsl,sec-v5.4-job-ring",
501 + "fsl,sec-v5.0-job-ring",
502 + "fsl,sec-v4.0-job-ring";
503 + reg = <0x20000 0x10000>;
504 + interrupts = <0 72 0x4>;
505 + };
506 +
507 + sec_jr2: jr@30000 {
508 + compatible = "fsl,sec-v5.4-job-ring",
509 + "fsl,sec-v5.0-job-ring",
510 + "fsl,sec-v4.0-job-ring";
511 + reg = <0x30000 0x10000>;
512 + interrupts = <0 73 0x4>;
513 + };
514 +
515 + sec_jr3: jr@40000 {
516 + compatible = "fsl,sec-v5.4-job-ring",
517 + "fsl,sec-v5.0-job-ring",
518 + "fsl,sec-v4.0-job-ring";
519 + reg = <0x40000 0x10000>;
520 + interrupts = <0 74 0x4>;
521 + };
522 + };
523 +
524 +
525 + dcfg: dcfg@1ee0000 {
526 + compatible = "fsl,ls1012a-dcfg",
527 + "fsl,ls1043a-dcfg",
528 + "syscon";
529 + reg = <0x0 0x1ee0000 0x0 0x10000>;
530 + };
531 +
532 + reset: reset@1EE00B0 {
533 + compatible = "fsl,ls-reset";
534 + reg = <0x0 0x1EE00B0 0x0 0x4>;
535 + big-endian;
536 + };
537 +
538 + rcpm: rcpm@1ee2000 {
539 + compatible = "fsl,ls1012a-rcpm",
540 + "fsl,ls1043a-rcpm",
541 + "fsl,qoriq-rcpm-2.1";
542 + reg = <0x0 0x1ee2000 0x0 0x10000>;
543 + };
544 +
545 + ftm0: ftm0@29d0000 {
546 + compatible = "fsl,ftm-alarm";
547 + reg = <0x0 0x29d0000 0x0 0x10000>;
548 + interrupts = <0 86 0x4>;
549 + big-endian;
550 + rcpm-wakeup = <&rcpm 0x00020000 0x0>;
551 + status = "okay";
552 + };
553 +
554 + esdhc0: esdhc@1560000 {
555 + compatible = "fsl,ls1012a-esdhc0", "fsl,esdhc";
556 + reg = <0x0 0x1560000 0x0 0x10000>;
557 + interrupts = <0 62 0x4>;
558 + clock-frequency = <0>;
559 + voltage-ranges = <1800 1800 3300 3300>;
560 + sdhci,auto-cmd12;
561 + big-endian;
562 + bus-width = <4>;
563 + };
564 +
565 + esdhc1: esdhc@1580000 {
566 + compatible = "fsl,ls1012a-esdhc1", "fsl,esdhc";
567 + reg = <0x0 0x1580000 0x0 0x10000>;
568 + interrupts = <0 65 0x4>;
569 + clock-frequency = <0>;
570 + voltage-ranges = <1800 1800 3300 3300>;
571 + sdhci,auto-cmd12;
572 + big-endian;
573 + bus-width = <4>;
574 + };
575 +
576 + dspi0: dspi@2100000 {
577 + compatible = "fsl,ls1012a-dspi",
578 + "fsl,ls1043a-dspi",
579 + "fsl,ls1021a-v1.0-dspi";
580 + #address-cells = <1>;
581 + #size-cells = <0>;
582 + reg = <0x0 0x2100000 0x0 0x10000>;
583 + interrupts = <0 64 0x4>;
584 + clock-names = "dspi";
585 + clocks = <&clockgen 4 0>;
586 + spi-num-chipselects = <5>;
587 + big-endian;
588 + status = "enabled";
589 + };
590 +
591 + qspi: quadspi@1550000 {
592 + compatible = "fsl,ls1012a-qspi",
593 + "fsl,ls1043a-qspi",
594 + "fsl,ls1021a-qspi";
595 + #address-cells = <1>;
596 + #size-cells = <0>;
597 + reg = <0x0 0x1550000 0x0 0x10000>,
598 + <0x0 0x40000000 0x0 0x4000000>;
599 + reg-names = "QuadSPI", "QuadSPI-memory";
600 + interrupts = <0 99 0x4>;
601 + clock-names = "qspi_en", "qspi";
602 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
603 + big-endian;
604 + amba-base = <0x42000000>;
605 + };
606 +
607 + tmu: tmu@1f00000 {
608 + compatible = "fsl,qoriq-tmu", "fsl,ls1012a-tmu";
609 + reg = <0x0 0x1f00000 0x0 0x10000>;
610 + interrupts = <0 33 0x4>;
611 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
612 + fsl,tmu-calibration = <0x00000000 0x00000026
613 + 0x00000001 0x0000002d
614 + 0x00000002 0x00000032
615 + 0x00000003 0x00000039
616 + 0x00000004 0x0000003f
617 + 0x00000005 0x00000046
618 + 0x00000006 0x0000004d
619 + 0x00000007 0x00000054
620 + 0x00000008 0x0000005a
621 + 0x00000009 0x00000061
622 + 0x0000000a 0x0000006a
623 + 0x0000000b 0x00000071
624 +
625 + 0x00010000 0x00000025
626 + 0x00010001 0x0000002c
627 + 0x00010002 0x00000035
628 + 0x00010003 0x0000003d
629 + 0x00010004 0x00000045
630 + 0x00010005 0x0000004e
631 + 0x00010006 0x00000057
632 + 0x00010007 0x00000061
633 + 0x00010008 0x0000006b
634 + 0x00010009 0x00000076
635 +
636 + 0x00020000 0x00000029
637 + 0x00020001 0x00000033
638 + 0x00020002 0x0000003d
639 + 0x00020003 0x00000049
640 + 0x00020004 0x00000056
641 + 0x00020005 0x00000061
642 + 0x00020006 0x0000006d
643 +
644 + 0x00030000 0x00000021
645 + 0x00030001 0x0000002a
646 + 0x00030002 0x0000003c
647 + 0x00030003 0x0000004e>;
648 + big-endian;
649 + #thermal-sensor-cells = <1>;
650 + };
651 +
652 + thermal-zones {
653 + cpu_thermal: cpu-thermal {
654 + polling-delay-passive = <1000>;
655 + polling-delay = <5000>;
656 +
657 + thermal-sensors = <&tmu 0>;
658 +
659 + trips {
660 + cpu_alert: cpu-alert {
661 + temperature = <85000>;
662 + hysteresis = <2000>;
663 + type = "passive";
664 + };
665 + cpu_crit: cpu-crit {
666 + temperature = <95000>;
667 + hysteresis = <2000>;
668 + type = "critical";
669 + };
670 + };
671 +
672 + cooling-maps {
673 + map0 {
674 + trip = <&cpu_alert>;
675 + cooling-device =
676 + <&cpu0 THERMAL_NO_LIMIT
677 + THERMAL_NO_LIMIT>;
678 + };
679 + };
680 + };
681 + };
682 +
683 + i2c0: i2c@2180000 {
684 + compatible = "fsl,vf610-i2c";
685 + #address-cells = <1>;
686 + #size-cells = <0>;
687 + reg = <0x0 0x2180000 0x0 0x10000>;
688 + interrupts = <0 56 0x4>;
689 + clock-names = "i2c";
690 + clocks = <&clockgen 4 0>;
691 + status = "disabled";
692 + };
693 +
694 + i2c1: i2c@2190000 {
695 + compatible = "fsl,vf610-i2c";
696 + #address-cells = <1>;
697 + #size-cells = <0>;
698 + reg = <0x0 0x2190000 0x0 0x10000>;
699 + interrupts = <0 57 0x4>;
700 + clock-names = "i2c";
701 + clocks = <&clockgen 4 0>;
702 + status = "disabled";
703 + };
704 +
705 +
706 + duart0: serial@21c0500 {
707 + compatible = "fsl,ns16550", "ns16550a";
708 + reg = <0x00 0x21c0500 0x0 0x100>;
709 + interrupts = <0 54 0x4>;
710 + clocks = <&clockgen 4 0>;
711 + };
712 +
713 + duart1: serial@21c0600 {
714 + compatible = "fsl,ns16550", "ns16550a";
715 + reg = <0x00 0x21c0600 0x0 0x100>;
716 + interrupts = <0 54 0x4>;
717 + clocks = <&clockgen 4 0>;
718 + };
719 +
720 + gpio0: gpio@2300000 {
721 + compatible = "fsl,qoriq-gpio";
722 + reg = <0x0 0x2300000 0x0 0x10000>;
723 + interrupts = <0 66 0x4>;
724 + gpio-controller;
725 + #gpio-cells = <2>;
726 + interrupt-controller;
727 + #interrupt-cells = <2>;
728 + };
729 +
730 + gpio1: gpio@2310000 {
731 + compatible = "fsl,qoriq-gpio";
732 + reg = <0x0 0x2310000 0x0 0x10000>;
733 + interrupts = <0 67 0x4>;
734 + gpio-controller;
735 + #gpio-cells = <2>;
736 + interrupt-controller;
737 + #interrupt-cells = <2>;
738 + };
739 +
740 + wdog0: wdog@2ad0000 {
741 + compatible = "fsl,ls1012a-wdt",
742 + "fsl,ls1043a-wdt",
743 + "fsl,imx21-wdt";
744 + reg = <0x0 0x2ad0000 0x0 0x10000>;
745 + interrupts = <0 83 0x4>;
746 + clocks = <&clockgen 4 0>;
747 + clock-names = "wdog";
748 + big-endian;
749 + };
750 +
751 + sai1: sai@2b50000 {
752 + #sound-dai-cells = <0>;
753 + compatible = "fsl,vf610-sai";
754 + reg = <0x0 0x2b50000 0x0 0x10000>;
755 + interrupts = <0 148 0x4>;
756 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
757 + <&clockgen 4 3>, <&clockgen 4 3>;
758 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
759 + dma-names = "tx", "rx";
760 + dmas = <&edma0 1 47>,
761 + <&edma0 1 46>;
762 + status = "disabled";
763 + };
764 +
765 + sai2: sai@2b60000 {
766 + #sound-dai-cells = <0>;
767 + compatible = "fsl,vf610-sai";
768 + reg = <0x0 0x2b60000 0x0 0x10000>;
769 + interrupts = <0 149 0x4>;
770 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
771 + <&clockgen 4 3>, <&clockgen 4 3>;
772 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
773 + dma-names = "tx", "rx";
774 + dmas = <&edma0 1 45>,
775 + <&edma0 1 44>;
776 + status = "disabled";
777 + };
778 +
779 + edma0: edma@2c00000 {
780 + #dma-cells = <2>;
781 + compatible = "fsl,vf610-edma";
782 + reg = <0x0 0x2c00000 0x0 0x10000>,
783 + <0x0 0x2c10000 0x0 0x10000>,
784 + <0x0 0x2c20000 0x0 0x10000>;
785 + interrupts = <0 103 0x4>,
786 + <0 103 0x4>;
787 + interrupt-names = "edma-tx", "edma-err";
788 + dma-channels = <32>;
789 + big-endian;
790 + clock-names = "dmamux0", "dmamux1";
791 + clocks = <&clockgen 4 3>,
792 + <&clockgen 4 3>;
793 + };
794 +
795 + sata: sata@3200000 {
796 + compatible = "fsl,ls1012a-ahci";
797 + reg = <0x0 0x3200000 0x0 0x10000>;
798 + interrupts = <0 69 0x4>;
799 + clocks = <&clockgen 4 0>;
800 + };
801 +
802 + msi2: msi-controller2@1572000 {
803 + compatible ="fsl,1s1012a-msi", "fsl,1s1021a-msi";
804 + reg = <0x0 0x1572000 0x0 0x4>,
805 + <0x0 0x1572004 0x0 0x4>;
806 + reg-names = "msiir", "msir";
807 + msi-controller;
808 + interrupts = <0 126 0x4>;
809 + };
810 +
811 + usb@8600000 {
812 + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
813 + reg = <0x0 0x8600000 0x0 0x1000>;
814 + interrupts = <0 139 0x4>;
815 + dr_mode = "host";
816 + phy_type = "ulpi";
817 + fsl,usb-erratum-a005697;
818 + };
819 +
820 + usb0: usb3@2f00000 {
821 + compatible = "snps,dwc3";
822 + reg = <0x0 0x2f00000 0x0 0x10000>;
823 + interrupts = <0 60 0x4>;
824 + dr_mode = "host";
825 + configure-gfladj;
826 + snps,dis_rxdet_inp3_quirk;
827 + };
828 +
829 + pcie@3400000 {
830 + compatible = "fsl,ls1012a-pcie",
831 + "fsl,ls1043a-pcie",
832 + "snps,dw-pcie";
833 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
834 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
835 + reg-names = "regs", "config";
836 + interrupts = <0 118 0x4>, /* controller interrupt */
837 + <0 117 0x4>; /* PME interrupt */
838 + interrupt-names = "intr", "pme";
839 + #address-cells = <3>;
840 + #size-cells = <2>;
841 + device_type = "pci";
842 + num-lanes = <4>;
843 + bus-range = <0x0 0xff>;
844 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
845 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
846 + msi-parent = <&msi2>;
847 + #interrupt-cells = <1>;
848 + interrupt-map-mask = <0 0 0 7>;
849 + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
850 + <0000 0 0 2 &gic 0 111 0x4>,
851 + <0000 0 0 3 &gic 0 112 0x4>,
852 + <0000 0 0 4 &gic 0 113 0x4>;
853 + };
854 + };
855 + reserved-memory {
856 + #address-cells = <2>;
857 + #size-cells = <2>;
858 + ranges;
859 +
860 + pfe_reserved: packetbuffer@83400000 {
861 + reg = <0 0x83400000 0 0xc00000>;
862 + };
863 + };
864 +
865 + pfe: pfe@04000000 {
866 + compatible = "fsl,pfe";
867 + ranges = <0x0 0x00 0x04000000 0xc00000
868 + 0x1 0x00 0x83400000 0xc00000>;
869 + reg = <0x0 0x90500000 0x0 0x10000>, /* APB 64K */
870 + <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
871 + <0x0 0x83400000 0x0 0xc00000>, /* PFE DDR 12M */
872 + <0x0 0x10000000 0x0 0x2000>; /* OCRAM 8K */
873 + fsl,pfe-num-interfaces = < 0x2 >;
874 + interrupts = <0 172 0x4>;
875 + #interrupt-names = "hifirq";
876 + memory-region = <&pfe_reserved>;
877 + fsl,pfe-scfg = <&scfg 0>;
878 + };
879 +
880 +};
OpenWrt Source Repository