828022f1a78e121ca9733674bc9292d127895344
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.4 / 3231-arm-dts-ls1021a-share-all-MSIs.patch
1 From 190ae222ef6ded27021620afdc3f5a36861d3625 Mon Sep 17 00:00:00 2001
2 From: Minghuan Lian <Minghuan.Lian@nxp.com>
3 Date: Tue, 17 Jan 2017 17:32:38 +0800
4 Subject: [PATCH 07/13] arm: dts: ls1021a: share all MSIs
5
6 Cherry-pick patchwork patch.
7
8 In order to maximize the use of MSI, a PCIe controller will share
9 all MSI controllers. The patch changes msi-parent to refer to all
10 MSI controller dts nodes.
11
12 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
13 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
14 ---
15 arch/arm/boot/dts/ls1021a.dtsi | 4 ++--
16 1 file changed, 2 insertions(+), 2 deletions(-)
17
18 diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
19 index a2a3e8e..bf4ffeb 100644
20 --- a/arch/arm/boot/dts/ls1021a.dtsi
21 +++ b/arch/arm/boot/dts/ls1021a.dtsi
22 @@ -568,7 +568,7 @@
23 bus-range = <0x0 0xff>;
24 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
25 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
26 - msi-parent = <&msi1>;
27 + msi-parent = <&msi1>, <&msi2>;
28 #interrupt-cells = <1>;
29 interrupt-map-mask = <0 0 0 7>;
30 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
31 @@ -591,7 +591,7 @@
32 bus-range = <0x0 0xff>;
33 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
34 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
35 - msi-parent = <&msi2>;
36 + msi-parent = <&msi1>, <&msi2>;
37 #interrupt-cells = <1>;
38 interrupt-map-mask = <0 0 0 7>;
39 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
40 --
41 2.1.0.27.g96db324
42