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kernel: bump 4.9 to 4.9.63
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 302-dts-support-layercape.patch
1 From bfa4a794f91162cfeccfa4d59121cde9a84e32a3 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 10:02:10 +0800
4 Subject: [PATCH] dts: support layercape
5
6 This is a integrated patch for layerscape dts support.
7
8 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
9 Signed-off-by: Alison Wang <b18965@freescale.com>
10 Signed-off-by: Li Yang <leoyang.li@nxp.com>
11 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
12 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
15 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
16 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
17 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
18 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
19 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
20 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
21 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
22 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
23 Signed-off-by: Meng Yi <meng.yi@nxp.com>
24 Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
25 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
26 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
27 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
28 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
29 ---
30 arch/arm/boot/dts/alpine.dtsi | 2 +-
31 arch/arm/boot/dts/axm55xx.dtsi | 2 +-
32 arch/arm/boot/dts/ecx-2000.dts | 2 +-
33 arch/arm/boot/dts/imx6ul.dtsi | 4 +-
34 arch/arm/boot/dts/keystone.dtsi | 4 +-
35 arch/arm/boot/dts/ls1021a-qds.dts | 13 +
36 arch/arm/boot/dts/ls1021a-twr.dts | 13 +
37 arch/arm/boot/dts/ls1021a.dtsi | 155 ++--
38 arch/arm/boot/dts/mt6580.dtsi | 2 +-
39 arch/arm/boot/dts/mt6589.dtsi | 2 +-
40 arch/arm/boot/dts/mt8127.dtsi | 2 +-
41 arch/arm/boot/dts/mt8135.dtsi | 2 +-
42 arch/arm/boot/dts/rk3288.dtsi | 2 +-
43 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
44 arch/arm/boot/dts/sun7i-a20.dtsi | 4 +-
45 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
46 arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
47 arch/arm64/boot/dts/freescale/Makefile | 16 +
48 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 177 ++++
49 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 198 +++++
50 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 134 +++
51 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 594 ++++++++++++++
52 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi | 45 +
53 .../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 69 ++
54 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 171 +++-
55 .../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 69 ++
56 .../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++
57 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 113 ++-
58 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 302 ++++++-
59 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi | 48 ++
60 .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 109 +++
61 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 363 ++++++++
62 .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 76 ++
63 .../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++
64 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 218 +++++
65 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 793 ++++++++++++++++++
66 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 173 ++++
67 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 236 ++++++
68 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 818 ++++++++++++++++++
69 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 191 ++---
70 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 169 ++--
71 arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 9 +-
72 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 763 +++--------------
73 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 161 ++++
74 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 162 ++++
75 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 140 ++++
76 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 195 +++++
77 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 198 +++++
78 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 161 ++++
79 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 912 +++++++++++++++++++++
80 .../boot/dts/freescale/qoriq-bman1-portals.dtsi | 81 ++
81 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 66 ++
82 .../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 +
83 .../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 +
84 .../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 +
85 .../boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi | 42 +
86 .../boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi | 42 +
87 .../boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi | 42 +
88 .../boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi | 42 +
89 .../boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi | 42 +
90 .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 ++
91 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi | 130 +++
92 .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 104 +++
93 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 +
94 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
95 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
96 66 files changed, 7988 insertions(+), 1021 deletions(-)
97 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
98 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
99 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
100 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
101 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
102 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
103 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
104 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
105 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
106 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
107 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
108 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
109 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
110 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
111 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
112 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
113 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
114 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
115 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
116 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
117 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
118 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
119 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
120 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
121 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
122 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
123 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
124 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
125 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
126 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
127 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
128 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
129 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
130 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
131 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
132 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
133 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
134 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
135
136 --- a/arch/arm/boot/dts/alpine.dtsi
137 +++ b/arch/arm/boot/dts/alpine.dtsi
138 @@ -93,7 +93,7 @@
139 interrupt-controller;
140 reg = <0x0 0xfb001000 0x0 0x1000>,
141 <0x0 0xfb002000 0x0 0x2000>,
142 - <0x0 0xfb004000 0x0 0x1000>,
143 + <0x0 0xfb004000 0x0 0x2000>,
144 <0x0 0xfb006000 0x0 0x2000>;
145 interrupts =
146 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
147 --- a/arch/arm/boot/dts/axm55xx.dtsi
148 +++ b/arch/arm/boot/dts/axm55xx.dtsi
149 @@ -62,7 +62,7 @@
150 #address-cells = <0>;
151 interrupt-controller;
152 reg = <0x20 0x01001000 0 0x1000>,
153 - <0x20 0x01002000 0 0x1000>,
154 + <0x20 0x01002000 0 0x2000>,
155 <0x20 0x01004000 0 0x2000>,
156 <0x20 0x01006000 0 0x2000>;
157 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
158 --- a/arch/arm/boot/dts/ecx-2000.dts
159 +++ b/arch/arm/boot/dts/ecx-2000.dts
160 @@ -99,7 +99,7 @@
161 interrupt-controller;
162 interrupts = <1 9 0xf04>;
163 reg = <0xfff11000 0x1000>,
164 - <0xfff12000 0x1000>,
165 + <0xfff12000 0x2000>,
166 <0xfff14000 0x2000>,
167 <0xfff16000 0x2000>;
168 };
169 --- a/arch/arm/boot/dts/imx6ul.dtsi
170 +++ b/arch/arm/boot/dts/imx6ul.dtsi
171 @@ -89,11 +89,11 @@
172 };
173
174 intc: interrupt-controller@00a01000 {
175 - compatible = "arm,cortex-a7-gic";
176 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
177 #interrupt-cells = <3>;
178 interrupt-controller;
179 reg = <0x00a01000 0x1000>,
180 - <0x00a02000 0x1000>,
181 + <0x00a02000 0x2000>,
182 <0x00a04000 0x2000>,
183 <0x00a06000 0x2000>;
184 };
185 --- a/arch/arm/boot/dts/keystone.dtsi
186 +++ b/arch/arm/boot/dts/keystone.dtsi
187 @@ -30,12 +30,12 @@
188 };
189
190 gic: interrupt-controller {
191 - compatible = "arm,cortex-a15-gic";
192 + compatible = "arm,gic-400", "arm,cortex-a15-gic";
193 #interrupt-cells = <3>;
194 interrupt-controller;
195 reg = <0x0 0x02561000 0x0 0x1000>,
196 <0x0 0x02562000 0x0 0x2000>,
197 - <0x0 0x02564000 0x0 0x1000>,
198 + <0x0 0x02564000 0x0 0x2000>,
199 <0x0 0x02566000 0x0 0x2000>;
200 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
201 IRQ_TYPE_LEVEL_HIGH)>;
202 --- a/arch/arm/boot/dts/ls1021a-qds.dts
203 +++ b/arch/arm/boot/dts/ls1021a-qds.dts
204 @@ -124,6 +124,19 @@
205 };
206 };
207
208 +&qspi {
209 + num-cs = <2>;
210 + status = "okay";
211 +
212 + qflash0: s25fl128s@0 {
213 + compatible = "spansion,m25p80";
214 + #address-cells = <1>;
215 + #size-cells = <1>;
216 + spi-max-frequency = <20000000>;
217 + reg = <0>;
218 + };
219 +};
220 +
221 &enet0 {
222 tbi-handle = <&tbi0>;
223 phy-handle = <&sgmii_phy1c>;
224 --- a/arch/arm/boot/dts/ls1021a-twr.dts
225 +++ b/arch/arm/boot/dts/ls1021a-twr.dts
226 @@ -142,6 +142,19 @@
227 };
228 };
229
230 +&qspi {
231 + num-cs = <2>;
232 + status = "okay";
233 +
234 + qflash0: n25q128a13@0 {
235 + compatible = "n25q128a13", "jedec,spi-nor";
236 + #address-cells = <1>;
237 + #size-cells = <1>;
238 + spi-max-frequency = <20000000>;
239 + reg = <0>;
240 + };
241 +};
242 +
243 &enet0 {
244 tbi-handle = <&tbi1>;
245 phy-handle = <&sgmii_phy2>;
246 --- a/arch/arm/boot/dts/ls1021a.dtsi
247 +++ b/arch/arm/boot/dts/ls1021a.dtsi
248 @@ -74,17 +74,24 @@
249 compatible = "arm,cortex-a7";
250 device_type = "cpu";
251 reg = <0xf00>;
252 - clocks = <&cluster1_clk>;
253 + clocks = <&clockgen 1 0>;
254 };
255
256 cpu@f01 {
257 compatible = "arm,cortex-a7";
258 device_type = "cpu";
259 reg = <0xf01>;
260 - clocks = <&cluster1_clk>;
261 + clocks = <&clockgen 1 0>;
262 };
263 };
264
265 + sysclk: sysclk {
266 + compatible = "fixed-clock";
267 + #clock-cells = <0>;
268 + clock-frequency = <100000000>;
269 + clock-output-names = "sysclk";
270 + };
271 +
272 timer {
273 compatible = "arm,armv7-timer";
274 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
275 @@ -108,11 +115,11 @@
276 ranges;
277
278 gic: interrupt-controller@1400000 {
279 - compatible = "arm,cortex-a7-gic";
280 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
281 #interrupt-cells = <3>;
282 interrupt-controller;
283 reg = <0x0 0x1401000 0x0 0x1000>,
284 - <0x0 0x1402000 0x0 0x1000>,
285 + <0x0 0x1402000 0x0 0x2000>,
286 <0x0 0x1404000 0x0 0x2000>,
287 <0x0 0x1406000 0x0 0x2000>;
288 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
289 @@ -120,14 +127,14 @@
290 };
291
292 msi1: msi-controller@1570e00 {
293 - compatible = "fsl,1s1021a-msi";
294 + compatible = "fsl,ls1021a-msi";
295 reg = <0x0 0x1570e00 0x0 0x8>;
296 msi-controller;
297 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
298 };
299
300 msi2: msi-controller@1570e08 {
301 - compatible = "fsl,1s1021a-msi";
302 + compatible = "fsl,ls1021a-msi";
303 reg = <0x0 0x1570e08 0x0 0x8>;
304 msi-controller;
305 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
306 @@ -137,11 +144,12 @@
307 compatible = "fsl,ifc", "simple-bus";
308 reg = <0x0 0x1530000 0x0 0x10000>;
309 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
310 + big-endian;
311 };
312
313 dcfg: dcfg@1ee0000 {
314 compatible = "fsl,ls1021a-dcfg", "syscon";
315 - reg = <0x0 0x1ee0000 0x0 0x10000>;
316 + reg = <0x0 0x1ee0000 0x0 0x1000>;
317 big-endian;
318 };
319
320 @@ -163,7 +171,7 @@
321 <0x0 0x20220520 0x0 0x4>;
322 reg-names = "ahci", "sata-ecc";
323 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
324 - clocks = <&platform_clk 1>;
325 + clocks = <&clockgen 4 1>;
326 dma-coherent;
327 status = "disabled";
328 };
329 @@ -214,41 +222,10 @@
330 };
331
332 clockgen: clocking@1ee1000 {
333 - #address-cells = <1>;
334 - #size-cells = <1>;
335 - ranges = <0x0 0x0 0x1ee1000 0x10000>;
336 -
337 - sysclk: sysclk {
338 - compatible = "fixed-clock";
339 - #clock-cells = <0>;
340 - clock-output-names = "sysclk";
341 - };
342 -
343 - cga_pll1: pll@800 {
344 - compatible = "fsl,qoriq-core-pll-2.0";
345 - #clock-cells = <1>;
346 - reg = <0x800 0x10>;
347 - clocks = <&sysclk>;
348 - clock-output-names = "cga-pll1", "cga-pll1-div2",
349 - "cga-pll1-div4";
350 - };
351 -
352 - platform_clk: pll@c00 {
353 - compatible = "fsl,qoriq-core-pll-2.0";
354 - #clock-cells = <1>;
355 - reg = <0xc00 0x10>;
356 - clocks = <&sysclk>;
357 - clock-output-names = "platform-clk", "platform-clk-div2";
358 - };
359 -
360 - cluster1_clk: clk0c0@0 {
361 - compatible = "fsl,qoriq-core-mux-2.0";
362 - #clock-cells = <0>;
363 - reg = <0x0 0x10>;
364 - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
365 - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
366 - clock-output-names = "cluster1-clk";
367 - };
368 + compatible = "fsl,ls1021a-clockgen";
369 + reg = <0x0 0x1ee1000 0x0 0x1000>;
370 + #clock-cells = <2>;
371 + clocks = <&sysclk>;
372 };
373
374 dspi0: dspi@2100000 {
375 @@ -258,7 +235,7 @@
376 reg = <0x0 0x2100000 0x0 0x10000>;
377 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
378 clock-names = "dspi";
379 - clocks = <&platform_clk 1>;
380 + clocks = <&clockgen 4 1>;
381 spi-num-chipselects = <6>;
382 big-endian;
383 status = "disabled";
384 @@ -271,12 +248,27 @@
385 reg = <0x0 0x2110000 0x0 0x10000>;
386 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
387 clock-names = "dspi";
388 - clocks = <&platform_clk 1>;
389 + clocks = <&clockgen 4 1>;
390 spi-num-chipselects = <6>;
391 big-endian;
392 status = "disabled";
393 };
394
395 + qspi: quadspi@1550000 {
396 + compatible = "fsl,ls1021a-qspi";
397 + #address-cells = <1>;
398 + #size-cells = <0>;
399 + reg = <0x0 0x1550000 0x0 0x10000>,
400 + <0x0 0x40000000 0x0 0x4000000>;
401 + reg-names = "QuadSPI", "QuadSPI-memory";
402 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
403 + clock-names = "qspi_en", "qspi";
404 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
405 + big-endian;
406 + amba-base = <0x40000000>;
407 + status = "disabled";
408 + };
409 +
410 i2c0: i2c@2180000 {
411 compatible = "fsl,vf610-i2c";
412 #address-cells = <1>;
413 @@ -284,7 +276,7 @@
414 reg = <0x0 0x2180000 0x0 0x10000>;
415 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
416 clock-names = "i2c";
417 - clocks = <&platform_clk 1>;
418 + clocks = <&clockgen 4 1>;
419 status = "disabled";
420 };
421
422 @@ -295,7 +287,7 @@
423 reg = <0x0 0x2190000 0x0 0x10000>;
424 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
425 clock-names = "i2c";
426 - clocks = <&platform_clk 1>;
427 + clocks = <&clockgen 4 1>;
428 status = "disabled";
429 };
430
431 @@ -306,7 +298,7 @@
432 reg = <0x0 0x21a0000 0x0 0x10000>;
433 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
434 clock-names = "i2c";
435 - clocks = <&platform_clk 1>;
436 + clocks = <&clockgen 4 1>;
437 status = "disabled";
438 };
439
440 @@ -399,7 +391,7 @@
441 compatible = "fsl,ls1021a-lpuart";
442 reg = <0x0 0x2960000 0x0 0x1000>;
443 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
444 - clocks = <&platform_clk 1>;
445 + clocks = <&clockgen 4 1>;
446 clock-names = "ipg";
447 status = "disabled";
448 };
449 @@ -408,7 +400,7 @@
450 compatible = "fsl,ls1021a-lpuart";
451 reg = <0x0 0x2970000 0x0 0x1000>;
452 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
453 - clocks = <&platform_clk 1>;
454 + clocks = <&clockgen 4 1>;
455 clock-names = "ipg";
456 status = "disabled";
457 };
458 @@ -417,7 +409,7 @@
459 compatible = "fsl,ls1021a-lpuart";
460 reg = <0x0 0x2980000 0x0 0x1000>;
461 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
462 - clocks = <&platform_clk 1>;
463 + clocks = <&clockgen 4 1>;
464 clock-names = "ipg";
465 status = "disabled";
466 };
467 @@ -426,7 +418,7 @@
468 compatible = "fsl,ls1021a-lpuart";
469 reg = <0x0 0x2990000 0x0 0x1000>;
470 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
471 - clocks = <&platform_clk 1>;
472 + clocks = <&clockgen 4 1>;
473 clock-names = "ipg";
474 status = "disabled";
475 };
476 @@ -435,16 +427,26 @@
477 compatible = "fsl,ls1021a-lpuart";
478 reg = <0x0 0x29a0000 0x0 0x1000>;
479 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
480 - clocks = <&platform_clk 1>;
481 + clocks = <&clockgen 4 1>;
482 clock-names = "ipg";
483 status = "disabled";
484 };
485
486 + ftm0: ftm0@29d0000 {
487 + compatible = "fsl,ls1021a-ftm";
488 + reg = <0x0 0x29d0000 0x0 0x10000>,
489 + <0x0 0x1ee2140 0x0 0x4>;
490 + reg-names = "ftm", "FlexTimer1";
491 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
492 + big-endian;
493 + status = "okay";
494 + };
495 +
496 wdog0: watchdog@2ad0000 {
497 compatible = "fsl,imx21-wdt";
498 reg = <0x0 0x2ad0000 0x0 0x10000>;
499 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
500 - clocks = <&platform_clk 1>;
501 + clocks = <&clockgen 4 1>;
502 clock-names = "wdog-en";
503 big-endian;
504 };
505 @@ -454,8 +456,8 @@
506 compatible = "fsl,vf610-sai";
507 reg = <0x0 0x2b50000 0x0 0x10000>;
508 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
509 - clocks = <&platform_clk 1>, <&platform_clk 1>,
510 - <&platform_clk 1>, <&platform_clk 1>;
511 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
512 + <&clockgen 4 1>, <&clockgen 4 1>;
513 clock-names = "bus", "mclk1", "mclk2", "mclk3";
514 dma-names = "tx", "rx";
515 dmas = <&edma0 1 47>,
516 @@ -468,8 +470,8 @@
517 compatible = "fsl,vf610-sai";
518 reg = <0x0 0x2b60000 0x0 0x10000>;
519 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
520 - clocks = <&platform_clk 1>, <&platform_clk 1>,
521 - <&platform_clk 1>, <&platform_clk 1>;
522 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
523 + <&clockgen 4 1>, <&clockgen 4 1>;
524 clock-names = "bus", "mclk1", "mclk2", "mclk3";
525 dma-names = "tx", "rx";
526 dmas = <&edma0 1 45>,
527 @@ -489,16 +491,31 @@
528 dma-channels = <32>;
529 big-endian;
530 clock-names = "dmamux0", "dmamux1";
531 - clocks = <&platform_clk 1>,
532 - <&platform_clk 1>;
533 + clocks = <&clockgen 4 1>,
534 + <&clockgen 4 1>;
535 + };
536 +
537 + qdma: qdma@8390000 {
538 + compatible = "fsl,ls1021a-qdma";
539 + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
540 + <0x0 0x8389000 0x0 0x1000>, /* Status regs */
541 + <0x0 0x838a000 0x0 0x2000>; /* Block regs */
542 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
543 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
544 + interrupt-names = "qdma-error", "qdma-queue";
545 + channels = <8>;
546 + queues = <2>;
547 + status-sizes = <64>;
548 + queue-sizes = <64 64>;
549 + big-endian;
550 };
551
552 dcu: dcu@2ce0000 {
553 compatible = "fsl,ls1021a-dcu";
554 reg = <0x0 0x2ce0000 0x0 0x10000>;
555 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
556 - clocks = <&platform_clk 0>,
557 - <&platform_clk 0>;
558 + clocks = <&clockgen 4 0>,
559 + <&clockgen 4 0>;
560 clock-names = "dcu", "pix";
561 big-endian;
562 status = "disabled";
563 @@ -626,6 +643,8 @@
564 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
565 dr_mode = "host";
566 snps,quirk-frame-length-adjustment = <0x20>;
567 + configure-gfladj;
568 + dma-coherent;
569 snps,dis_rxdet_inp3_quirk;
570 };
571
572 @@ -634,7 +653,9 @@
573 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
574 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
575 reg-names = "regs", "config";
576 - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
577 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
578 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
579 + interrupt-names = "pme", "aer";
580 fsl,pcie-scfg = <&scfg 0>;
581 #address-cells = <3>;
582 #size-cells = <2>;
583 @@ -643,7 +664,7 @@
584 bus-range = <0x0 0xff>;
585 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
586 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
587 - msi-parent = <&msi1>;
588 + msi-parent = <&msi1>, <&msi2>;
589 #interrupt-cells = <1>;
590 interrupt-map-mask = <0 0 0 7>;
591 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
592 @@ -657,7 +678,9 @@
593 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
594 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
595 reg-names = "regs", "config";
596 - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
597 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
598 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
599 + interrupt-names = "pme", "aer";
600 fsl,pcie-scfg = <&scfg 1>;
601 #address-cells = <3>;
602 #size-cells = <2>;
603 @@ -666,7 +689,7 @@
604 bus-range = <0x0 0xff>;
605 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
606 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
607 - msi-parent = <&msi2>;
608 + msi-parent = <&msi1>, <&msi2>;
609 #interrupt-cells = <1>;
610 interrupt-map-mask = <0 0 0 7>;
611 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
612 --- a/arch/arm/boot/dts/mt6580.dtsi
613 +++ b/arch/arm/boot/dts/mt6580.dtsi
614 @@ -91,7 +91,7 @@
615 #interrupt-cells = <3>;
616 interrupt-parent = <&gic>;
617 reg = <0x10211000 0x1000>,
618 - <0x10212000 0x1000>,
619 + <0x10212000 0x2000>,
620 <0x10214000 0x2000>,
621 <0x10216000 0x2000>;
622 };
623 --- a/arch/arm/boot/dts/mt6589.dtsi
624 +++ b/arch/arm/boot/dts/mt6589.dtsi
625 @@ -102,7 +102,7 @@
626 #interrupt-cells = <3>;
627 interrupt-parent = <&gic>;
628 reg = <0x10211000 0x1000>,
629 - <0x10212000 0x1000>,
630 + <0x10212000 0x2000>,
631 <0x10214000 0x2000>,
632 <0x10216000 0x2000>;
633 };
634 --- a/arch/arm/boot/dts/mt8127.dtsi
635 +++ b/arch/arm/boot/dts/mt8127.dtsi
636 @@ -129,7 +129,7 @@
637 #interrupt-cells = <3>;
638 interrupt-parent = <&gic>;
639 reg = <0 0x10211000 0 0x1000>,
640 - <0 0x10212000 0 0x1000>,
641 + <0 0x10212000 0 0x2000>,
642 <0 0x10214000 0 0x2000>,
643 <0 0x10216000 0 0x2000>;
644 };
645 --- a/arch/arm/boot/dts/mt8135.dtsi
646 +++ b/arch/arm/boot/dts/mt8135.dtsi
647 @@ -221,7 +221,7 @@
648 #interrupt-cells = <3>;
649 interrupt-parent = <&gic>;
650 reg = <0 0x10211000 0 0x1000>,
651 - <0 0x10212000 0 0x1000>,
652 + <0 0x10212000 0 0x2000>,
653 <0 0x10214000 0 0x2000>,
654 <0 0x10216000 0 0x2000>;
655 };
656 --- a/arch/arm/boot/dts/rk3288.dtsi
657 +++ b/arch/arm/boot/dts/rk3288.dtsi
658 @@ -1109,7 +1109,7 @@
659 #address-cells = <0>;
660
661 reg = <0xffc01000 0x1000>,
662 - <0xffc02000 0x1000>,
663 + <0xffc02000 0x2000>,
664 <0xffc04000 0x2000>,
665 <0xffc06000 0x2000>;
666 interrupts = <GIC_PPI 9 0xf04>;
667 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
668 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
669 @@ -791,7 +791,7 @@
670 gic: interrupt-controller@01c81000 {
671 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
672 reg = <0x01c81000 0x1000>,
673 - <0x01c82000 0x1000>,
674 + <0x01c82000 0x2000>,
675 <0x01c84000 0x2000>,
676 <0x01c86000 0x2000>;
677 interrupt-controller;
678 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
679 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
680 @@ -1685,9 +1685,9 @@
681 };
682
683 gic: interrupt-controller@01c81000 {
684 - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
685 + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
686 reg = <0x01c81000 0x1000>,
687 - <0x01c82000 0x1000>,
688 + <0x01c82000 0x2000>,
689 <0x01c84000 0x2000>,
690 <0x01c86000 0x2000>;
691 interrupt-controller;
692 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
693 +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
694 @@ -488,7 +488,7 @@
695 gic: interrupt-controller@01c81000 {
696 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
697 reg = <0x01c81000 0x1000>,
698 - <0x01c82000 0x1000>,
699 + <0x01c82000 0x2000>,
700 <0x01c84000 0x2000>,
701 <0x01c86000 0x2000>;
702 interrupt-controller;
703 --- a/arch/arm/boot/dts/sun9i-a80.dtsi
704 +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
705 @@ -613,7 +613,7 @@
706 gic: interrupt-controller@01c41000 {
707 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
708 reg = <0x01c41000 0x1000>,
709 - <0x01c42000 0x1000>,
710 + <0x01c42000 0x2000>,
711 <0x01c44000 0x2000>,
712 <0x01c46000 0x2000>;
713 interrupt-controller;
714 --- a/arch/arm64/boot/dts/freescale/Makefile
715 +++ b/arch/arm64/boot/dts/freescale/Makefile
716 @@ -1,8 +1,24 @@
717 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
718 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
719 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
720 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
721 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
722 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
723 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
724 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
725 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
726 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
727 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
728 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
729 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
730 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
731 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
732 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
733 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
734 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
735 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
736 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
737 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
738
739 always := $(dtb-y)
740 subdir-y := $(dts-dirs)
741 --- /dev/null
742 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
743 @@ -0,0 +1,177 @@
744 +/*
745 + * Device Tree file for Freescale LS1012A Freedom Board.
746 + *
747 + * Copyright 2016 Freescale Semiconductor, Inc.
748 + *
749 + * This file is dual-licensed: you can use it either under the terms
750 + * of the GPLv2 or the X11 license, at your option. Note that this dual
751 + * licensing only applies to this file, and not this project as a
752 + * whole.
753 + *
754 + * a) This library is free software; you can redistribute it and/or
755 + * modify it under the terms of the GNU General Public License as
756 + * published by the Free Software Foundation; either version 2 of the
757 + * License, or (at your option) any later version.
758 + *
759 + * This library is distributed in the hope that it will be useful,
760 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
761 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
762 + * GNU General Public License for more details.
763 + *
764 + * Or, alternatively,
765 + *
766 + * b) Permission is hereby granted, free of charge, to any person
767 + * obtaining a copy of this software and associated documentation
768 + * files (the "Software"), to deal in the Software without
769 + * restriction, including without limitation the rights to use,
770 + * copy, modify, merge, publish, distribute, sublicense, and/or
771 + * sell copies of the Software, and to permit persons to whom the
772 + * Software is furnished to do so, subject to the following
773 + * conditions:
774 + *
775 + * The above copyright notice and this permission notice shall be
776 + * included in all copies or substantial portions of the Software.
777 + *
778 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
779 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
780 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
781 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
782 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
783 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
784 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
785 + * OTHER DEALINGS IN THE SOFTWARE.
786 + */
787 +/dts-v1/;
788 +
789 +#include "fsl-ls1012a.dtsi"
790 +
791 +/ {
792 + model = "LS1012A Freedom Board";
793 + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
794 +
795 + aliases {
796 + ethernet0 = &pfe_mac0;
797 + ethernet1 = &pfe_mac1;
798 + };
799 +
800 + sys_mclk: clock-mclk {
801 + compatible = "fixed-clock";
802 + #clock-cells = <0>;
803 + clock-frequency = <25000000>;
804 + };
805 +
806 + reg_1p8v: regulator-1p8v {
807 + compatible = "regulator-fixed";
808 + regulator-name = "1P8V";
809 + regulator-min-microvolt = <1800000>;
810 + regulator-max-microvolt = <1800000>;
811 + regulator-always-on;
812 + };
813 +
814 + sound {
815 + compatible = "simple-audio-card";
816 + simple-audio-card,format = "i2s";
817 + simple-audio-card,widgets =
818 + "Microphone", "Microphone Jack",
819 + "Headphone", "Headphone Jack",
820 + "Speaker", "Speaker Ext",
821 + "Line", "Line In Jack";
822 + simple-audio-card,routing =
823 + "MIC_IN", "Microphone Jack",
824 + "Microphone Jack", "Mic Bias",
825 + "LINE_IN", "Line In Jack",
826 + "Headphone Jack", "HP_OUT",
827 + "Speaker Ext", "LINE_OUT";
828 +
829 + simple-audio-card,cpu {
830 + sound-dai = <&sai2>;
831 + frame-master;
832 + bitclock-master;
833 + };
834 +
835 + simple-audio-card,codec {
836 + sound-dai = <&codec>;
837 + frame-master;
838 + bitclock-master;
839 + system-clock-frequency = <25000000>;
840 + };
841 + };
842 +};
843 +
844 +&duart0 {
845 + status = "okay";
846 +};
847 +
848 +&i2c0 {
849 + status = "okay";
850 +
851 + codec: sgtl5000@a {
852 + #sound-dai-cells = <0>;
853 + compatible = "fsl,sgtl5000";
854 + reg = <0xa>;
855 + VDDA-supply = <&reg_1p8v>;
856 + VDDIO-supply = <&reg_1p8v>;
857 + clocks = <&sys_mclk>;
858 + };
859 +};
860 +
861 +&qspi {
862 + num-cs = <1>;
863 + bus-num = <0>;
864 + status = "okay";
865 +
866 + qflash0: s25fs512s@0 {
867 + compatible = "spansion,m25p80";
868 + #address-cells = <1>;
869 + #size-cells = <1>;
870 + m25p,fast-read;
871 + spi-max-frequency = <20000000>;
872 + reg = <0>;
873 + };
874 +};
875 +
876 +&pfe {
877 + status = "okay";
878 + #address-cells = <1>;
879 + #size-cells = <0>;
880 +
881 + ethernet@0 {
882 + compatible = "fsl,pfe-gemac-port";
883 + #address-cells = <1>;
884 + #size-cells = <0>;
885 + reg = <0x0>; /* GEM_ID */
886 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
887 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
888 + fsl,mdio-mux-val = <0x0>;
889 + phy-mode = "sgmii";
890 + fsl,pfe-phy-if-flags = <0x0>;
891 +
892 + mdio@0 {
893 + reg = <0x1>; /* enabled/disabled */
894 + };
895 + };
896 +
897 + ethernet@1 {
898 + compatible = "fsl,pfe-gemac-port";
899 + #address-cells = <1>;
900 + #size-cells = <0>;
901 + reg = <0x1>; /* GEM_ID */
902 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
903 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
904 + fsl,mdio-mux-val = <0x0>;
905 + phy-mode = "sgmii";
906 + fsl,pfe-phy-if-flags = <0x0>;
907 +
908 + mdio@0 {
909 + reg = <0x0>; /* enabled/disabled */
910 + };
911 + };
912 +};
913 +
914 +&sai2 {
915 + status = "okay";
916 +};
917 +
918 +&sata {
919 + status = "okay";
920 +};
921 --- /dev/null
922 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
923 @@ -0,0 +1,198 @@
924 +/*
925 + * Device Tree file for Freescale LS1012A QDS Board.
926 + *
927 + * Copyright 2016 Freescale Semiconductor, Inc.
928 + *
929 + * This file is dual-licensed: you can use it either under the terms
930 + * of the GPLv2 or the X11 license, at your option. Note that this dual
931 + * licensing only applies to this file, and not this project as a
932 + * whole.
933 + *
934 + * a) This library is free software; you can redistribute it and/or
935 + * modify it under the terms of the GNU General Public License as
936 + * published by the Free Software Foundation; either version 2 of the
937 + * License, or (at your option) any later version.
938 + *
939 + * This library is distributed in the hope that it will be useful,
940 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
941 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
942 + * GNU General Public License for more details.
943 + *
944 + * Or, alternatively,
945 + *
946 + * b) Permission is hereby granted, free of charge, to any person
947 + * obtaining a copy of this software and associated documentation
948 + * files (the "Software"), to deal in the Software without
949 + * restriction, including without limitation the rights to use,
950 + * copy, modify, merge, publish, distribute, sublicense, and/or
951 + * sell copies of the Software, and to permit persons to whom the
952 + * Software is furnished to do so, subject to the following
953 + * conditions:
954 + *
955 + * The above copyright notice and this permission notice shall be
956 + * included in all copies or substantial portions of the Software.
957 + *
958 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
959 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
960 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
961 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
962 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
963 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
964 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
965 + * OTHER DEALINGS IN THE SOFTWARE.
966 + */
967 +/dts-v1/;
968 +
969 +#include "fsl-ls1012a.dtsi"
970 +
971 +/ {
972 + model = "LS1012A QDS Board";
973 + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
974 +
975 + aliases {
976 + ethernet0 = &pfe_mac0;
977 + ethernet1 = &pfe_mac1;
978 + };
979 +
980 + sys_mclk: clock-mclk {
981 + compatible = "fixed-clock";
982 + #clock-cells = <0>;
983 + clock-frequency = <24576000>;
984 + };
985 +
986 + reg_3p3v: regulator-3p3v {
987 + compatible = "regulator-fixed";
988 + regulator-name = "3P3V";
989 + regulator-min-microvolt = <3300000>;
990 + regulator-max-microvolt = <3300000>;
991 + regulator-always-on;
992 + };
993 +
994 + sound {
995 + compatible = "simple-audio-card";
996 + simple-audio-card,format = "i2s";
997 + simple-audio-card,widgets =
998 + "Microphone", "Microphone Jack",
999 + "Headphone", "Headphone Jack",
1000 + "Speaker", "Speaker Ext",
1001 + "Line", "Line In Jack";
1002 + simple-audio-card,routing =
1003 + "MIC_IN", "Microphone Jack",
1004 + "Microphone Jack", "Mic Bias",
1005 + "LINE_IN", "Line In Jack",
1006 + "Headphone Jack", "HP_OUT",
1007 + "Speaker Ext", "LINE_OUT";
1008 +
1009 + simple-audio-card,cpu {
1010 + sound-dai = <&sai2>;
1011 + frame-master;
1012 + bitclock-master;
1013 + };
1014 +
1015 + simple-audio-card,codec {
1016 + sound-dai = <&codec>;
1017 + frame-master;
1018 + bitclock-master;
1019 + system-clock-frequency = <24576000>;
1020 + };
1021 + };
1022 +};
1023 +
1024 +&duart0 {
1025 + status = "okay";
1026 +};
1027 +
1028 +&i2c0 {
1029 + status = "okay";
1030 +
1031 + pca9547@77 {
1032 + compatible = "nxp,pca9547";
1033 + reg = <0x77>;
1034 + #address-cells = <1>;
1035 + #size-cells = <0>;
1036 +
1037 + i2c@4 {
1038 + #address-cells = <1>;
1039 + #size-cells = <0>;
1040 + reg = <0x4>;
1041 +
1042 + codec: sgtl5000@a {
1043 + #sound-dai-cells = <0>;
1044 + compatible = "fsl,sgtl5000";
1045 + reg = <0xa>;
1046 + VDDA-supply = <&reg_3p3v>;
1047 + VDDIO-supply = <&reg_3p3v>;
1048 + clocks = <&sys_mclk>;
1049 + };
1050 + };
1051 + };
1052 +};
1053 +
1054 +&qspi {
1055 + num-cs = <2>;
1056 + bus-num = <0>;
1057 + status = "okay";
1058 +
1059 + qflash0: s25fs512s@0 {
1060 + compatible = "spansion,m25p80";
1061 + #address-cells = <1>;
1062 + #size-cells = <1>;
1063 + spi-max-frequency = <20000000>;
1064 + m25p,fast-read;
1065 + reg = <0>;
1066 + };
1067 +};
1068 +
1069 +&pfe {
1070 + status = "okay";
1071 + #address-cells = <1>;
1072 + #size-cells = <0>;
1073 +
1074 + ethernet@0 {
1075 + compatible = "fsl,pfe-gemac-port";
1076 + #address-cells = <1>;
1077 + #size-cells = <0>;
1078 + reg = <0x0>; /* GEM_ID */
1079 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1080 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1081 + fsl,mdio-mux-val = <0x2>;
1082 + phy-mode = "sgmii-2500";
1083 + fsl,pfe-phy-if-flags = <0x0>;
1084 +
1085 + mdio@0 {
1086 + reg = <0x1>; /* enabled/disabled */
1087 + };
1088 + };
1089 +
1090 + ethernet@1 {
1091 + compatible = "fsl,pfe-gemac-port";
1092 + #address-cells = <1>;
1093 + #size-cells = <0>;
1094 + reg = <0x1>; /* GEM_ID */
1095 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1096 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1097 + fsl,mdio-mux-val = <0x3>;
1098 + phy-mode = "sgmii-2500";
1099 + fsl,pfe-phy-if-flags = <0x0>;
1100 +
1101 + mdio@0 {
1102 + reg = <0x0>; /* enabled/disabled */
1103 + };
1104 + };
1105 +};
1106 +
1107 +&sai2 {
1108 + status = "okay";
1109 +};
1110 +
1111 +&sata {
1112 + status = "okay";
1113 +};
1114 +
1115 +&esdhc0 {
1116 + status = "okay";
1117 +};
1118 +
1119 +&esdhc1 {
1120 + status = "okay";
1121 +};
1122 --- /dev/null
1123 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1124 @@ -0,0 +1,134 @@
1125 +/*
1126 + * Device Tree file for Freescale LS1012A RDB Board.
1127 + *
1128 + * Copyright 2016 Freescale Semiconductor, Inc.
1129 + *
1130 + * This file is dual-licensed: you can use it either under the terms
1131 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1132 + * licensing only applies to this file, and not this project as a
1133 + * whole.
1134 + *
1135 + * a) This library is free software; you can redistribute it and/or
1136 + * modify it under the terms of the GNU General Public License as
1137 + * published by the Free Software Foundation; either version 2 of the
1138 + * License, or (at your option) any later version.
1139 + *
1140 + * This library is distributed in the hope that it will be useful,
1141 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1142 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1143 + * GNU General Public License for more details.
1144 + *
1145 + * Or, alternatively,
1146 + *
1147 + * b) Permission is hereby granted, free of charge, to any person
1148 + * obtaining a copy of this software and associated documentation
1149 + * files (the "Software"), to deal in the Software without
1150 + * restriction, including without limitation the rights to use,
1151 + * copy, modify, merge, publish, distribute, sublicense, and/or
1152 + * sell copies of the Software, and to permit persons to whom the
1153 + * Software is furnished to do so, subject to the following
1154 + * conditions:
1155 + *
1156 + * The above copyright notice and this permission notice shall be
1157 + * included in all copies or substantial portions of the Software.
1158 + *
1159 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1160 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1161 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1162 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1163 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1164 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1165 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1166 + * OTHER DEALINGS IN THE SOFTWARE.
1167 + */
1168 +/dts-v1/;
1169 +
1170 +#include "fsl-ls1012a.dtsi"
1171 +
1172 +/ {
1173 + model = "LS1012A RDB Board";
1174 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
1175 +
1176 + aliases {
1177 + ethernet0 = &pfe_mac0;
1178 + ethernet1 = &pfe_mac1;
1179 + };
1180 +};
1181 +
1182 +&duart0 {
1183 + status = "okay";
1184 +};
1185 +
1186 +&i2c0 {
1187 + status = "okay";
1188 +};
1189 +
1190 +&qspi {
1191 + num-cs = <2>;
1192 + bus-num = <0>;
1193 + status = "okay";
1194 +
1195 + qflash0: s25fs512s@0 {
1196 + compatible = "spansion,m25p80";
1197 + #address-cells = <1>;
1198 + #size-cells = <1>;
1199 + spi-max-frequency = <20000000>;
1200 + m25p,fast-read;
1201 + reg = <0>;
1202 + };
1203 +};
1204 +
1205 +&sata {
1206 + status = "okay";
1207 +};
1208 +
1209 +&esdhc0 {
1210 + sd-uhs-sdr104;
1211 + sd-uhs-sdr50;
1212 + sd-uhs-sdr25;
1213 + sd-uhs-sdr12;
1214 + status = "okay";
1215 +};
1216 +
1217 +&esdhc1 {
1218 + mmc-hs200-1_8v;
1219 + status = "okay";
1220 +};
1221 +
1222 +&pfe {
1223 + status = "okay";
1224 + #address-cells = <1>;
1225 + #size-cells = <0>;
1226 +
1227 + ethernet@0 {
1228 + compatible = "fsl,pfe-gemac-port";
1229 + #address-cells = <1>;
1230 + #size-cells = <0>;
1231 + reg = <0x0>; /* GEM_ID */
1232 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1233 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1234 + fsl,mdio-mux-val = <0x0>;
1235 + phy-mode = "sgmii";
1236 + fsl,pfe-phy-if-flags = <0x0>;
1237 +
1238 + mdio@0 {
1239 + reg = <0x1>; /* enabled/disabled */
1240 + };
1241 + };
1242 +
1243 + ethernet@1 {
1244 + compatible = "fsl,pfe-gemac-port";
1245 + #address-cells = <1>;
1246 + #size-cells = <0>;
1247 + reg = <0x1>; /* GEM_ID */
1248 + fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
1249 + fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
1250 + fsl,mdio-mux-val = <0x0>;
1251 + phy-mode = "rgmii-txid";
1252 + fsl,pfe-phy-if-flags = <0x0>;
1253 +
1254 + mdio@0 {
1255 + reg = <0x0>; /* enabled/disabled */
1256 + };
1257 + };
1258 +};
1259 --- /dev/null
1260 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1261 @@ -0,0 +1,594 @@
1262 +/*
1263 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
1264 + *
1265 + * Copyright 2016 Freescale Semiconductor, Inc.
1266 + *
1267 + * This file is dual-licensed: you can use it either under the terms
1268 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1269 + * licensing only applies to this file, and not this project as a
1270 + * whole.
1271 + *
1272 + * a) This library is free software; you can redistribute it and/or
1273 + * modify it under the terms of the GNU General Public License as
1274 + * published by the Free Software Foundation; either version 2 of the
1275 + * License, or (at your option) any later version.
1276 + *
1277 + * This library is distributed in the hope that it will be useful,
1278 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1279 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1280 + * GNU General Public License for more details.
1281 + *
1282 + * Or, alternatively,
1283 + *
1284 + * b) Permission is hereby granted, free of charge, to any person
1285 + * obtaining a copy of this software and associated documentation
1286 + * files (the "Software"), to deal in the Software without
1287 + * restriction, including without limitation the rights to use,
1288 + * copy, modify, merge, publish, distribute, sublicense, and/or
1289 + * sell copies of the Software, and to permit persons to whom the
1290 + * Software is furnished to do so, subject to the following
1291 + * conditions:
1292 + *
1293 + * The above copyright notice and this permission notice shall be
1294 + * included in all copies or substantial portions of the Software.
1295 + *
1296 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1297 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1298 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1299 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1300 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1301 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1302 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1303 + * OTHER DEALINGS IN THE SOFTWARE.
1304 + */
1305 +
1306 +#include <dt-bindings/interrupt-controller/arm-gic.h>
1307 +#include <dt-bindings/thermal/thermal.h>
1308 +
1309 +/ {
1310 + compatible = "fsl,ls1012a";
1311 + interrupt-parent = <&gic>;
1312 + #address-cells = <2>;
1313 + #size-cells = <2>;
1314 +
1315 + aliases {
1316 + crypto = &crypto;
1317 + rtic_a = &rtic_a;
1318 + rtic_b = &rtic_b;
1319 + rtic_c = &rtic_c;
1320 + rtic_d = &rtic_d;
1321 + sec_mon = &sec_mon;
1322 + };
1323 +
1324 + cpus {
1325 + #address-cells = <1>;
1326 + #size-cells = <0>;
1327 +
1328 + cpu0: cpu@0 {
1329 + device_type = "cpu";
1330 + compatible = "arm,cortex-a53";
1331 + reg = <0x0>;
1332 + clocks = <&clockgen 1 0>;
1333 + #cooling-cells = <2>;
1334 + cpu-idle-states = <&CPU_PH20>;
1335 + };
1336 + };
1337 +
1338 + idle-states {
1339 + /*
1340 + * PSCI node is not added default, U-boot will add missing
1341 + * parts if it determines to use PSCI.
1342 + */
1343 + entry-method = "arm,psci";
1344 +
1345 + CPU_PH20: cpu-ph20 {
1346 + compatible = "arm,idle-state";
1347 + idle-state-name = "PH20";
1348 + arm,psci-suspend-param = <0x0>;
1349 + entry-latency-us = <1000>;
1350 + exit-latency-us = <1000>;
1351 + min-residency-us = <3000>;
1352 + };
1353 + };
1354 +
1355 + sysclk: sysclk {
1356 + compatible = "fixed-clock";
1357 + #clock-cells = <0>;
1358 + clock-frequency = <125000000>;
1359 + clock-output-names = "sysclk";
1360 + };
1361 +
1362 + coreclk: coreclk {
1363 + compatible = "fixed-clock";
1364 + #clock-cells = <0>;
1365 + clock-frequency = <100000000>;
1366 + clock-output-names = "coreclk";
1367 + };
1368 +
1369 + timer {
1370 + compatible = "arm,armv8-timer";
1371 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
1372 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
1373 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
1374 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
1375 + };
1376 +
1377 + pmu {
1378 + compatible = "arm,armv8-pmuv3";
1379 + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1380 + };
1381 +
1382 + gic: interrupt-controller@1400000 {
1383 + compatible = "arm,gic-400";
1384 + #interrupt-cells = <3>;
1385 + interrupt-controller;
1386 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
1387 + <0x0 0x1402000 0 0x2000>, /* GICC */
1388 + <0x0 0x1404000 0 0x2000>, /* GICH */
1389 + <0x0 0x1406000 0 0x2000>; /* GICV */
1390 + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
1391 + };
1392 +
1393 + reboot {
1394 + compatible = "syscon-reboot";
1395 + regmap = <&dcfg>;
1396 + offset = <0xb0>;
1397 + mask = <0x02>;
1398 + };
1399 +
1400 + soc {
1401 + compatible = "simple-bus";
1402 + #address-cells = <2>;
1403 + #size-cells = <2>;
1404 + ranges;
1405 +
1406 + scfg: scfg@1570000 {
1407 + compatible = "fsl,ls1012a-scfg", "syscon";
1408 + reg = <0x0 0x1570000 0x0 0x10000>;
1409 + big-endian;
1410 + };
1411 +
1412 + crypto: crypto@1700000 {
1413 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
1414 + "fsl,sec-v4.0";
1415 + fsl,sec-era = <8>;
1416 + #address-cells = <1>;
1417 + #size-cells = <1>;
1418 + ranges = <0x0 0x00 0x1700000 0x100000>;
1419 + reg = <0x00 0x1700000 0x0 0x100000>;
1420 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1421 +
1422 + sec_jr0: jr@10000 {
1423 + compatible = "fsl,sec-v5.4-job-ring",
1424 + "fsl,sec-v5.0-job-ring",
1425 + "fsl,sec-v4.0-job-ring";
1426 + reg = <0x10000 0x10000>;
1427 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1428 + };
1429 +
1430 + sec_jr1: jr@20000 {
1431 + compatible = "fsl,sec-v5.4-job-ring",
1432 + "fsl,sec-v5.0-job-ring",
1433 + "fsl,sec-v4.0-job-ring";
1434 + reg = <0x20000 0x10000>;
1435 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1436 + };
1437 +
1438 + sec_jr2: jr@30000 {
1439 + compatible = "fsl,sec-v5.4-job-ring",
1440 + "fsl,sec-v5.0-job-ring",
1441 + "fsl,sec-v4.0-job-ring";
1442 + reg = <0x30000 0x10000>;
1443 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1444 + };
1445 +
1446 + sec_jr3: jr@40000 {
1447 + compatible = "fsl,sec-v5.4-job-ring",
1448 + "fsl,sec-v5.0-job-ring",
1449 + "fsl,sec-v4.0-job-ring";
1450 + reg = <0x40000 0x10000>;
1451 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1452 + };
1453 +
1454 + caam-dma {
1455 + compatible = "fsl,sec-v5.4-dma",
1456 + "fsl,sec-v5.0-dma",
1457 + "fsl,sec-v4.0-dma";
1458 + };
1459 +
1460 + rtic@60000 {
1461 + compatible = "fsl,sec-v5.4-rtic",
1462 + "fsl,sec-v5.0-rtic",
1463 + "fsl,sec-v4.0-rtic";
1464 + #address-cells = <1>;
1465 + #size-cells = <1>;
1466 + reg = <0x60000 0x100 0x60e00 0x18>;
1467 + ranges = <0x0 0x60100 0x500>;
1468 +
1469 + rtic_a: rtic-a@0 {
1470 + compatible = "fsl,sec-v5.4-rtic-memory",
1471 + "fsl,sec-v5.0-rtic-memory",
1472 + "fsl,sec-v4.0-rtic-memory";
1473 + reg = <0x00 0x20 0x100 0x100>;
1474 + };
1475 +
1476 + rtic_b: rtic-b@20 {
1477 + compatible = "fsl,sec-v5.4-rtic-memory",
1478 + "fsl,sec-v5.0-rtic-memory",
1479 + "fsl,sec-v4.0-rtic-memory";
1480 + reg = <0x20 0x20 0x200 0x100>;
1481 + };
1482 +
1483 + rtic_c: rtic-c@40 {
1484 + compatible = "fsl,sec-v5.4-rtic-memory",
1485 + "fsl,sec-v5.0-rtic-memory",
1486 + "fsl,sec-v4.0-rtic-memory";
1487 + reg = <0x40 0x20 0x300 0x100>;
1488 + };
1489 +
1490 + rtic_d: rtic-d@60 {
1491 + compatible = "fsl,sec-v5.4-rtic-memory",
1492 + "fsl,sec-v5.0-rtic-memory",
1493 + "fsl,sec-v4.0-rtic-memory";
1494 + reg = <0x60 0x20 0x400 0x100>;
1495 + };
1496 + };
1497 + };
1498 +
1499 + sec_mon: sec_mon@1e90000 {
1500 + compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
1501 + "fsl,sec-v4.0-mon";
1502 + reg = <0x0 0x1e90000 0x0 0x10000>;
1503 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
1504 + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1505 + };
1506 +
1507 + dcfg: dcfg@1ee0000 {
1508 + compatible = "fsl,ls1012a-dcfg",
1509 + "syscon";
1510 + reg = <0x0 0x1ee0000 0x0 0x10000>;
1511 + big-endian;
1512 + };
1513 +
1514 + clockgen: clocking@1ee1000 {
1515 + compatible = "fsl,ls1012a-clockgen";
1516 + reg = <0x0 0x1ee1000 0x0 0x1000>;
1517 + #clock-cells = <2>;
1518 + clocks = <&sysclk &coreclk>;
1519 + clock-names = "sysclk", "coreclk";
1520 + };
1521 +
1522 + tmu: tmu@1f00000 {
1523 + compatible = "fsl,qoriq-tmu";
1524 + reg = <0x0 0x1f00000 0x0 0x10000>;
1525 + interrupts = <0 33 0x4>;
1526 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
1527 + fsl,tmu-calibration = <0x00000000 0x00000026
1528 + 0x00000001 0x0000002d
1529 + 0x00000002 0x00000032
1530 + 0x00000003 0x00000039
1531 + 0x00000004 0x0000003f
1532 + 0x00000005 0x00000046
1533 + 0x00000006 0x0000004d
1534 + 0x00000007 0x00000054
1535 + 0x00000008 0x0000005a
1536 + 0x00000009 0x00000061
1537 + 0x0000000a 0x0000006a
1538 + 0x0000000b 0x00000071
1539 +
1540 + 0x00010000 0x00000025
1541 + 0x00010001 0x0000002c
1542 + 0x00010002 0x00000035
1543 + 0x00010003 0x0000003d
1544 + 0x00010004 0x00000045
1545 + 0x00010005 0x0000004e
1546 + 0x00010006 0x00000057
1547 + 0x00010007 0x00000061
1548 + 0x00010008 0x0000006b
1549 + 0x00010009 0x00000076
1550 +
1551 + 0x00020000 0x00000029
1552 + 0x00020001 0x00000033
1553 + 0x00020002 0x0000003d
1554 + 0x00020003 0x00000049
1555 + 0x00020004 0x00000056
1556 + 0x00020005 0x00000061
1557 + 0x00020006 0x0000006d
1558 +
1559 + 0x00030000 0x00000021
1560 + 0x00030001 0x0000002a
1561 + 0x00030002 0x0000003c
1562 + 0x00030003 0x0000004e>;
1563 + big-endian;
1564 + #thermal-sensor-cells = <1>;
1565 + };
1566 +
1567 + thermal-zones {
1568 + cpu_thermal: cpu-thermal {
1569 + polling-delay-passive = <1000>;
1570 + polling-delay = <5000>;
1571 + thermal-sensors = <&tmu 0>;
1572 +
1573 + trips {
1574 + cpu_alert: cpu-alert {
1575 + temperature = <85000>;
1576 + hysteresis = <2000>;
1577 + type = "passive";
1578 + };
1579 +
1580 + cpu_crit: cpu-crit {
1581 + temperature = <95000>;
1582 + hysteresis = <2000>;
1583 + type = "critical";
1584 + };
1585 + };
1586 +
1587 + cooling-maps {
1588 + map0 {
1589 + trip = <&cpu_alert>;
1590 + cooling-device =
1591 + <&cpu0 THERMAL_NO_LIMIT
1592 + THERMAL_NO_LIMIT>;
1593 + };
1594 + };
1595 + };
1596 + };
1597 +
1598 + esdhc0: esdhc@1560000 {
1599 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1600 + reg = <0x0 0x1560000 0x0 0x10000>;
1601 + interrupts = <0 62 0x4>;
1602 + clocks = <&clockgen 4 0>;
1603 + voltage-ranges = <1800 1800 3300 3300>;
1604 + sdhci,auto-cmd12;
1605 + big-endian;
1606 + bus-width = <4>;
1607 + status = "disabled";
1608 + };
1609 +
1610 + esdhc1: esdhc@1580000 {
1611 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1612 + reg = <0x0 0x1580000 0x0 0x10000>;
1613 + interrupts = <0 65 0x4>;
1614 + clocks = <&clockgen 4 0>;
1615 + voltage-ranges = <1800 1800 3300 3300>;
1616 + sdhci,auto-cmd12;
1617 + big-endian;
1618 + broken-cd;
1619 + bus-width = <4>;
1620 + status = "disabled";
1621 + };
1622 +
1623 + rcpm: rcpm@1ee2000 {
1624 + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
1625 + reg = <0x0 0x1ee2000 0x0 0x1000>;
1626 + fsl,#rcpm-wakeup-cells = <1>;
1627 + };
1628 +
1629 + ftm0: ftm0@29d0000 {
1630 + compatible = "fsl,ls1012a-ftm";
1631 + reg = <0x0 0x29d0000 0x0 0x10000>,
1632 + <0x0 0x1ee2140 0x0 0x4>;
1633 + reg-names = "ftm", "FlexTimer1";
1634 + interrupts = <0 86 0x4>;
1635 + big-endian;
1636 + };
1637 +
1638 + i2c0: i2c@2180000 {
1639 + compatible = "fsl,vf610-i2c";
1640 + #address-cells = <1>;
1641 + #size-cells = <0>;
1642 + reg = <0x0 0x2180000 0x0 0x10000>;
1643 + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
1644 + clocks = <&clockgen 4 0>;
1645 + status = "disabled";
1646 + };
1647 +
1648 + i2c1: i2c@2190000 {
1649 + compatible = "fsl,vf610-i2c";
1650 + #address-cells = <1>;
1651 + #size-cells = <0>;
1652 + reg = <0x0 0x2190000 0x0 0x10000>;
1653 + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
1654 + clocks = <&clockgen 4 0>;
1655 + status = "disabled";
1656 + };
1657 +
1658 + duart0: serial@21c0500 {
1659 + compatible = "fsl,ns16550", "ns16550a";
1660 + reg = <0x00 0x21c0500 0x0 0x100>;
1661 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1662 + clocks = <&clockgen 4 0>;
1663 + status = "disabled";
1664 + };
1665 +
1666 + duart1: serial@21c0600 {
1667 + compatible = "fsl,ns16550", "ns16550a";
1668 + reg = <0x00 0x21c0600 0x0 0x100>;
1669 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1670 + clocks = <&clockgen 4 0>;
1671 + status = "disabled";
1672 + };
1673 +
1674 + gpio0: gpio@2300000 {
1675 + compatible = "fsl,qoriq-gpio";
1676 + reg = <0x0 0x2300000 0x0 0x10000>;
1677 + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
1678 + gpio-controller;
1679 + #gpio-cells = <2>;
1680 + interrupt-controller;
1681 + #interrupt-cells = <2>;
1682 + };
1683 +
1684 + gpio1: gpio@2310000 {
1685 + compatible = "fsl,qoriq-gpio";
1686 + reg = <0x0 0x2310000 0x0 0x10000>;
1687 + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
1688 + gpio-controller;
1689 + #gpio-cells = <2>;
1690 + interrupt-controller;
1691 + #interrupt-cells = <2>;
1692 + };
1693 +
1694 + qspi: quadspi@1550000 {
1695 + compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
1696 + #address-cells = <1>;
1697 + #size-cells = <0>;
1698 + reg = <0x0 0x1550000 0x0 0x10000>,
1699 + <0x0 0x40000000 0x0 0x10000000>;
1700 + reg-names = "QuadSPI", "QuadSPI-memory";
1701 + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1702 + clock-names = "qspi_en", "qspi";
1703 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
1704 + big-endian;
1705 + fsl,qspi-has-second-chip;
1706 + status = "disabled";
1707 + };
1708 +
1709 + wdog0: wdog@2ad0000 {
1710 + compatible = "fsl,ls1012a-wdt",
1711 + "fsl,imx21-wdt";
1712 + reg = <0x0 0x2ad0000 0x0 0x10000>;
1713 + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
1714 + clocks = <&clockgen 4 0>;
1715 + big-endian;
1716 + };
1717 +
1718 + sai1: sai@2b50000 {
1719 + #sound-dai-cells = <0>;
1720 + compatible = "fsl,vf610-sai";
1721 + reg = <0x0 0x2b50000 0x0 0x10000>;
1722 + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
1723 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1724 + <&clockgen 4 3>, <&clockgen 4 3>;
1725 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1726 + dma-names = "tx", "rx";
1727 + dmas = <&edma0 1 47>,
1728 + <&edma0 1 46>;
1729 + status = "disabled";
1730 + };
1731 +
1732 + sai2: sai@2b60000 {
1733 + #sound-dai-cells = <0>;
1734 + compatible = "fsl,vf610-sai";
1735 + reg = <0x0 0x2b60000 0x0 0x10000>;
1736 + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
1737 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1738 + <&clockgen 4 3>, <&clockgen 4 3>;
1739 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1740 + dma-names = "tx", "rx";
1741 + dmas = <&edma0 1 45>,
1742 + <&edma0 1 44>;
1743 + status = "disabled";
1744 + };
1745 +
1746 + edma0: edma@2c00000 {
1747 + #dma-cells = <2>;
1748 + compatible = "fsl,vf610-edma";
1749 + reg = <0x0 0x2c00000 0x0 0x10000>,
1750 + <0x0 0x2c10000 0x0 0x10000>,
1751 + <0x0 0x2c20000 0x0 0x10000>;
1752 + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
1753 + <0 103 IRQ_TYPE_LEVEL_HIGH>;
1754 + interrupt-names = "edma-tx", "edma-err";
1755 + dma-channels = <32>;
1756 + big-endian;
1757 + clock-names = "dmamux0", "dmamux1";
1758 + clocks = <&clockgen 4 3>,
1759 + <&clockgen 4 3>;
1760 + };
1761 +
1762 + usb0: usb3@2f00000 {
1763 + compatible = "snps,dwc3";
1764 + reg = <0x0 0x2f00000 0x0 0x10000>;
1765 + interrupts = <0 60 0x4>;
1766 + dr_mode = "host";
1767 + snps,quirk-frame-length-adjustment = <0x20>;
1768 + snps,dis_rxdet_inp3_quirk;
1769 + };
1770 +
1771 + usb1: usb2@8600000 {
1772 + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
1773 + reg = <0x0 0x8600000 0x0 0x1000>;
1774 + interrupts = <0 139 0x4>;
1775 + dr_mode = "host";
1776 + phy_type = "ulpi";
1777 + };
1778 +
1779 + sata: sata@3200000 {
1780 + compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
1781 + reg = <0x0 0x3200000 0x0 0x10000>,
1782 + <0x0 0x20140520 0x0 0x4>;
1783 + reg-names = "ahci", "sata-ecc";
1784 + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
1785 + clocks = <&clockgen 4 0>;
1786 + dma-coherent;
1787 + status = "disabled";
1788 + };
1789 +
1790 + msi: msi-controller1@1572000 {
1791 + compatible = "fsl,ls1012a-msi";
1792 + reg = <0x0 0x1572000 0x0 0x8>;
1793 + msi-controller;
1794 + interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
1795 + };
1796 +
1797 + pcie@3400000 {
1798 + compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
1799 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
1800 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
1801 + reg-names = "regs", "config";
1802 + interrupts = <0 118 0x4>, /* AER interrupt */
1803 + <0 117 0x4>; /* PME interrupt */
1804 + interrupt-names = "aer", "pme";
1805 + #address-cells = <3>;
1806 + #size-cells = <2>;
1807 + device_type = "pci";
1808 + num-lanes = <4>;
1809 + bus-range = <0x0 0xff>;
1810 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
1811 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1812 + msi-parent = <&msi>;
1813 + #interrupt-cells = <1>;
1814 + interrupt-map-mask = <0 0 0 7>;
1815 + interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
1816 + <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
1817 + <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
1818 + <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1819 + };
1820 + };
1821 +
1822 + reserved-memory {
1823 + #address-cells = <2>;
1824 + #size-cells = <2>;
1825 + ranges;
1826 +
1827 + pfe_reserved: packetbuffer@83400000 {
1828 + reg = <0 0x83400000 0 0xc00000>;
1829 + };
1830 + };
1831 +
1832 + pfe: pfe@04000000 {
1833 + compatible = "fsl,pfe";
1834 + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
1835 + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
1836 + reg-names = "pfe", "pfe-ddr";
1837 + fsl,pfe-num-interfaces = <0x2>;
1838 + interrupts = <0 172 0x4>, /* HIF interrupt */
1839 + <0 173 0x4>, /*HIF_NOCPY interrupt */
1840 + <0 174 0x4>; /* WoL interrupt */
1841 + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
1842 + memory-region = <&pfe_reserved>;
1843 + fsl,pfe-scfg = <&scfg 0>;
1844 + fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
1845 + clocks = <&clockgen 4 0>;
1846 + clock-names = "pfe";
1847 +
1848 + status = "okay";
1849 + pfe_mac0: ethernet@0 {
1850 + };
1851 +
1852 + pfe_mac1: ethernet@1 {
1853 + };
1854 + };
1855 +};
1856 --- /dev/null
1857 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
1858 @@ -0,0 +1,45 @@
1859 +/*
1860 + * QorIQ FMan v3 device tree nodes for ls1043
1861 + *
1862 + * Copyright 2015-2016 Freescale Semiconductor Inc.
1863 + *
1864 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
1865 + */
1866 +
1867 +&soc {
1868 +
1869 +/* include used FMan blocks */
1870 +#include "qoriq-fman3-0.dtsi"
1871 +#include "qoriq-fman3-0-1g-0.dtsi"
1872 +#include "qoriq-fman3-0-1g-1.dtsi"
1873 +#include "qoriq-fman3-0-1g-2.dtsi"
1874 +#include "qoriq-fman3-0-1g-3.dtsi"
1875 +#include "qoriq-fman3-0-1g-4.dtsi"
1876 +#include "qoriq-fman3-0-1g-5.dtsi"
1877 +#include "qoriq-fman3-0-10g-0.dtsi"
1878 +
1879 +};
1880 +
1881 +&fman0 {
1882 + /* these aliases provide the FMan ports mapping */
1883 + enet0: ethernet@e0000 {
1884 + };
1885 +
1886 + enet1: ethernet@e2000 {
1887 + };
1888 +
1889 + enet2: ethernet@e4000 {
1890 + };
1891 +
1892 + enet3: ethernet@e6000 {
1893 + };
1894 +
1895 + enet4: ethernet@e8000 {
1896 + };
1897 +
1898 + enet5: ethernet@ea000 {
1899 + };
1900 +
1901 + enet6: ethernet@f0000 {
1902 + };
1903 +};
1904 --- /dev/null
1905 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
1906 @@ -0,0 +1,69 @@
1907 +/*
1908 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1909 + *
1910 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1911 + *
1912 + * Mingkai Hu <Mingkai.hu@freescale.com>
1913 + *
1914 + * This file is dual-licensed: you can use it either under the terms
1915 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1916 + * licensing only applies to this file, and not this project as a
1917 + * whole.
1918 + *
1919 + * a) This library is free software; you can redistribute it and/or
1920 + * modify it under the terms of the GNU General Public License as
1921 + * published by the Free Software Foundation; either version 2 of the
1922 + * License, or (at your option) any later version.
1923 + *
1924 + * This library is distributed in the hope that it will be useful,
1925 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1926 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1927 + * GNU General Public License for more details.
1928 + *
1929 + * Or, alternatively,
1930 + *
1931 + * b) Permission is hereby granted, free of charge, to any person
1932 + * obtaining a copy of this software and associated documentation
1933 + * files (the "Software"), to deal in the Software without
1934 + * restriction, including without limitation the rights to use,
1935 + * copy, modify, merge, publish, distribute, sublicense, and/or
1936 + * sell copies of the Software, and to permit persons to whom the
1937 + * Software is furnished to do so, subject to the following
1938 + * conditions:
1939 + *
1940 + * The above copyright notice and this permission notice shall be
1941 + * included in all copies or substantial portions of the Software.
1942 + *
1943 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1944 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1945 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1946 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1947 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1948 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1949 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1950 + * OTHER DEALINGS IN THE SOFTWARE.
1951 + */
1952 +
1953 +#include "fsl-ls1043a-qds.dts"
1954 +
1955 +&bman_fbpr {
1956 + compatible = "fsl,bman-fbpr";
1957 + alloc-ranges = <0 0 0x10000 0>;
1958 +};
1959 +&qman_fqd {
1960 + compatible = "fsl,qman-fqd";
1961 + alloc-ranges = <0 0 0x10000 0>;
1962 +};
1963 +&qman_pfdr {
1964 + compatible = "fsl,qman-pfdr";
1965 + alloc-ranges = <0 0 0x10000 0>;
1966 +};
1967 +
1968 +&soc {
1969 +#include "qoriq-dpaa-eth.dtsi"
1970 +#include "qoriq-fman3-0-6oh.dtsi"
1971 +};
1972 +
1973 +&fman0 {
1974 + compatible = "fsl,fman", "simple-bus";
1975 +};
1976 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
1977 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
1978 @@ -1,7 +1,7 @@
1979 /*
1980 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1981 *
1982 - * Copyright 2014-2015, Freescale Semiconductor
1983 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1984 *
1985 * Mingkai Hu <Mingkai.hu@freescale.com>
1986 *
1987 @@ -45,7 +45,7 @@
1988 */
1989
1990 /dts-v1/;
1991 -/include/ "fsl-ls1043a.dtsi"
1992 +#include "fsl-ls1043a.dtsi"
1993
1994 / {
1995 model = "LS1043A QDS Board";
1996 @@ -60,6 +60,22 @@
1997 serial1 = &duart1;
1998 serial2 = &duart2;
1999 serial3 = &duart3;
2000 + sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
2001 + sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
2002 + sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
2003 + sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
2004 + qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
2005 + qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
2006 + qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
2007 + qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
2008 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
2009 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
2010 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
2011 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
2012 + emi1_slot1 = &ls1043mdio_s1;
2013 + emi1_slot2 = &ls1043mdio_s2;
2014 + emi1_slot3 = &ls1043mdio_s3;
2015 + emi1_slot4 = &ls1043mdio_s4;
2016 };
2017
2018 chosen {
2019 @@ -97,8 +113,11 @@
2020 };
2021
2022 fpga: board-control@2,0 {
2023 - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
2024 + #address-cells = <1>;
2025 + #size-cells = <1>;
2026 + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
2027 reg = <0x2 0x0 0x0000100>;
2028 + ranges = <0 2 0 0x100>;
2029 };
2030 };
2031
2032 @@ -181,3 +200,149 @@
2033 reg = <0>;
2034 };
2035 };
2036 +
2037 +#include "fsl-ls1043-post.dtsi"
2038 +
2039 +&fman0 {
2040 + ethernet@e0000 {
2041 + phy-handle = <&qsgmii_phy_s2_p1>;
2042 + phy-connection-type = "sgmii";
2043 + };
2044 +
2045 + ethernet@e2000 {
2046 + phy-handle = <&qsgmii_phy_s2_p2>;
2047 + phy-connection-type = "sgmii";
2048 + };
2049 +
2050 + ethernet@e4000 {
2051 + phy-handle = <&rgmii_phy1>;
2052 + phy-connection-type = "rgmii";
2053 + };
2054 +
2055 + ethernet@e6000 {
2056 + phy-handle = <&rgmii_phy2>;
2057 + phy-connection-type = "rgmii";
2058 + };
2059 +
2060 + ethernet@e8000 {
2061 + phy-handle = <&qsgmii_phy_s2_p3>;
2062 + phy-connection-type = "sgmii";
2063 + };
2064 +
2065 + ethernet@ea000 {
2066 + phy-handle = <&qsgmii_phy_s2_p4>;
2067 + phy-connection-type = "sgmii";
2068 + };
2069 +
2070 + ethernet@f0000 { /* DTSEC9/10GEC1 */
2071 + fixed-link = <1 1 10000 0 0>;
2072 + phy-connection-type = "xgmii";
2073 + };
2074 +};
2075 +
2076 +&fpga {
2077 + mdio-mux-emi1 {
2078 + compatible = "mdio-mux-mmioreg", "mdio-mux";
2079 + mdio-parent-bus = <&mdio0>;
2080 + #address-cells = <1>;
2081 + #size-cells = <0>;
2082 + reg = <0x54 1>; /* BRDCFG4 */
2083 + mux-mask = <0xe0>; /* EMI1 */
2084 +
2085 + /* On-board RGMII1 PHY */
2086 + ls1043mdio0: mdio@0 {
2087 + reg = <0>;
2088 + #address-cells = <1>;
2089 + #size-cells = <0>;
2090 +
2091 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
2092 + reg = <0x1>;
2093 + };
2094 + };
2095 +
2096 + /* On-board RGMII2 PHY */
2097 + ls1043mdio1: mdio@1 {
2098 + reg = <0x20>;
2099 + #address-cells = <1>;
2100 + #size-cells = <0>;
2101 +
2102 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
2103 + reg = <0x2>;
2104 + };
2105 + };
2106 +
2107 + /* Slot 1 */
2108 + ls1043mdio_s1: mdio@2 {
2109 + reg = <0x40>;
2110 + #address-cells = <1>;
2111 + #size-cells = <0>;
2112 + status = "disabled";
2113 +
2114 + qsgmii_phy_s1_p1: ethernet-phy@4 {
2115 + reg = <0x4>;
2116 + };
2117 + qsgmii_phy_s1_p2: ethernet-phy@5 {
2118 + reg = <0x5>;
2119 + };
2120 + qsgmii_phy_s1_p3: ethernet-phy@6 {
2121 + reg = <0x6>;
2122 + };
2123 + qsgmii_phy_s1_p4: ethernet-phy@7 {
2124 + reg = <0x7>;
2125 + };
2126 +
2127 + sgmii_phy_s1_p1: ethernet-phy@1c {
2128 + reg = <0x1c>;
2129 + };
2130 + };
2131 +
2132 + /* Slot 2 */
2133 + ls1043mdio_s2: mdio@3 {
2134 + reg = <0x60>;
2135 + #address-cells = <1>;
2136 + #size-cells = <0>;
2137 + status = "disabled";
2138 +
2139 + qsgmii_phy_s2_p1: ethernet-phy@8 {
2140 + reg = <0x8>;
2141 + };
2142 + qsgmii_phy_s2_p2: ethernet-phy@9 {
2143 + reg = <0x9>;
2144 + };
2145 + qsgmii_phy_s2_p3: ethernet-phy@a {
2146 + reg = <0xa>;
2147 + };
2148 + qsgmii_phy_s2_p4: ethernet-phy@b {
2149 + reg = <0xb>;
2150 + };
2151 +
2152 + sgmii_phy_s2_p1: ethernet-phy@1c {
2153 + reg = <0x1c>;
2154 + };
2155 + };
2156 +
2157 + /* Slot 3 */
2158 + ls1043mdio_s3: mdio@4 {
2159 + reg = <0x80>;
2160 + #address-cells = <1>;
2161 + #size-cells = <0>;
2162 + status = "disabled";
2163 +
2164 + sgmii_phy_s3_p1: ethernet-phy@1c {
2165 + reg = <0x1c>;
2166 + };
2167 + };
2168 +
2169 + /* Slot 4 */
2170 + ls1043mdio_s4: mdio@5 {
2171 + reg = <0xa0>;
2172 + #address-cells = <1>;
2173 + #size-cells = <0>;
2174 + status = "disabled";
2175 +
2176 + sgmii_phy_s4_p1: ethernet-phy@1c {
2177 + reg = <0x1c>;
2178 + };
2179 + };
2180 + };
2181 +};
2182 --- /dev/null
2183 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2184 @@ -0,0 +1,69 @@
2185 +/*
2186 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2187 + *
2188 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2189 + *
2190 + * Mingkai Hu <Mingkai.hu@freescale.com>
2191 + *
2192 + * This file is dual-licensed: you can use it either under the terms
2193 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2194 + * licensing only applies to this file, and not this project as a
2195 + * whole.
2196 + *
2197 + * a) This library is free software; you can redistribute it and/or
2198 + * modify it under the terms of the GNU General Public License as
2199 + * published by the Free Software Foundation; either version 2 of the
2200 + * License, or (at your option) any later version.
2201 + *
2202 + * This library is distributed in the hope that it will be useful,
2203 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2204 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2205 + * GNU General Public License for more details.
2206 + *
2207 + * Or, alternatively,
2208 + *
2209 + * b) Permission is hereby granted, free of charge, to any person
2210 + * obtaining a copy of this software and associated documentation
2211 + * files (the "Software"), to deal in the Software without
2212 + * restriction, including without limitation the rights to use,
2213 + * copy, modify, merge, publish, distribute, sublicense, and/or
2214 + * sell copies of the Software, and to permit persons to whom the
2215 + * Software is furnished to do so, subject to the following
2216 + * conditions:
2217 + *
2218 + * The above copyright notice and this permission notice shall be
2219 + * included in all copies or substantial portions of the Software.
2220 + *
2221 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2222 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2223 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2224 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2225 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2226 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2227 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2228 + * OTHER DEALINGS IN THE SOFTWARE.
2229 + */
2230 +
2231 +#include "fsl-ls1043a-rdb.dts"
2232 +
2233 +&bman_fbpr {
2234 + compatible = "fsl,bman-fbpr";
2235 + alloc-ranges = <0 0 0x10000 0>;
2236 +};
2237 +&qman_fqd {
2238 + compatible = "fsl,qman-fqd";
2239 + alloc-ranges = <0 0 0x10000 0>;
2240 +};
2241 +&qman_pfdr {
2242 + compatible = "fsl,qman-pfdr";
2243 + alloc-ranges = <0 0 0x10000 0>;
2244 +};
2245 +
2246 +&soc {
2247 +#include "qoriq-dpaa-eth.dtsi"
2248 +#include "qoriq-fman3-0-6oh.dtsi"
2249 +};
2250 +
2251 +&fman0 {
2252 + compatible = "fsl,fman", "simple-bus";
2253 +};
2254 --- /dev/null
2255 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2256 @@ -0,0 +1,117 @@
2257 +/*
2258 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2259 + *
2260 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2261 + *
2262 + * This file is licensed under the terms of the GNU General Public
2263 + * License version 2. This program is licensed "as is" without any
2264 + * warranty of any kind, whether express or implied.
2265 + */
2266 +
2267 +#include "fsl-ls1043a-rdb-sdk.dts"
2268 +
2269 +&soc {
2270 + bp7: buffer-pool@7 {
2271 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2272 + fsl,bpid = <7>;
2273 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
2274 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
2275 + };
2276 +
2277 + bp8: buffer-pool@8 {
2278 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2279 + fsl,bpid = <8>;
2280 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
2281 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2282 + };
2283 +
2284 + bp9: buffer-pool@9 {
2285 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2286 + fsl,bpid = <9>;
2287 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
2288 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2289 + };
2290 +
2291 + fsl,dpaa {
2292 + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
2293 +
2294 + ethernet@0 {
2295 + compatible = "fsl,dpa-ethernet-init";
2296 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2297 + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
2298 + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
2299 + };
2300 +
2301 + ethernet@1 {
2302 + compatible = "fsl,dpa-ethernet-init";
2303 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2304 + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
2305 + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
2306 + };
2307 +
2308 + ethernet@2 {
2309 + compatible = "fsl,dpa-ethernet-init";
2310 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2311 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
2312 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
2313 + };
2314 +
2315 + ethernet@3 {
2316 + compatible = "fsl,dpa-ethernet-init";
2317 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2318 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
2319 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
2320 + };
2321 +
2322 + ethernet@4 {
2323 + compatible = "fsl,dpa-ethernet-init";
2324 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2325 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
2326 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
2327 + };
2328 +
2329 + ethernet@5 {
2330 + compatible = "fsl,dpa-ethernet-init";
2331 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2332 + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
2333 + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
2334 + };
2335 +
2336 + ethernet@8 {
2337 + compatible = "fsl,dpa-ethernet-init";
2338 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2339 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
2340 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
2341 +
2342 + };
2343 + dpa-fman0-oh@2 {
2344 + compatible = "fsl,dpa-oh";
2345 + /* Define frame queues for the OH port*/
2346 + /* <OH Rx error, OH Rx default> */
2347 + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
2348 + fsl,fman-oh-port = <&fman0_oh2>;
2349 + };
2350 + };
2351 +};
2352 +/ {
2353 + reserved-memory {
2354 + #address-cells = <2>;
2355 + #size-cells = <2>;
2356 + ranges;
2357 +
2358 + usdpaa_mem: usdpaa_mem {
2359 + compatible = "fsl,usdpaa-mem";
2360 + alloc-ranges = <0 0 0x10000 0>;
2361 + size = <0 0x10000000>;
2362 + alignment = <0 0x10000000>;
2363 + };
2364 + };
2365 +};
2366 +
2367 +&fman0 {
2368 + fman0_oh2: port@83000 {
2369 + cell-index = <1>;
2370 + compatible = "fsl,fman-port-oh";
2371 + reg = <0x83000 0x1000>;
2372 + };
2373 +};
2374 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2375 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2376 @@ -1,7 +1,7 @@
2377 /*
2378 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2379 *
2380 - * Copyright 2014-2015, Freescale Semiconductor
2381 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2382 *
2383 * Mingkai Hu <Mingkai.hu@freescale.com>
2384 *
2385 @@ -45,7 +45,7 @@
2386 */
2387
2388 /dts-v1/;
2389 -/include/ "fsl-ls1043a.dtsi"
2390 +#include "fsl-ls1043a.dtsi"
2391
2392 / {
2393 model = "LS1043A RDB Board";
2394 @@ -86,6 +86,10 @@
2395 compatible = "pericom,pt7c4338";
2396 reg = <0x68>;
2397 };
2398 + rtc@51 {
2399 + compatible = "nxp,pcf85263";
2400 + reg = <0x51>;
2401 + };
2402 };
2403
2404 &ifc {
2405 @@ -130,6 +134,38 @@
2406 reg = <0>;
2407 spi-max-frequency = <1000000>; /* input clock */
2408 };
2409 +
2410 + slic@2 {
2411 + compatible = "maxim,ds26522";
2412 + reg = <2>;
2413 + spi-max-frequency = <2000000>;
2414 + fsl,spi-cs-sck-delay = <100>;
2415 + fsl,spi-sck-cs-delay = <50>;
2416 + };
2417 +
2418 + slic@3 {
2419 + compatible = "maxim,ds26522";
2420 + reg = <3>;
2421 + spi-max-frequency = <2000000>;
2422 + fsl,spi-cs-sck-delay = <100>;
2423 + fsl,spi-sck-cs-delay = <50>;
2424 + };
2425 +};
2426 +
2427 +&uqe {
2428 + ucc_hdlc: ucc@2000 {
2429 + compatible = "fsl,ucc-hdlc";
2430 + rx-clock-name = "clk8";
2431 + tx-clock-name = "clk9";
2432 + fsl,rx-sync-clock = "rsync_pin";
2433 + fsl,tx-sync-clock = "tsync_pin";
2434 + fsl,tx-timeslot-mask = <0xfffffffe>;
2435 + fsl,rx-timeslot-mask = <0xfffffffe>;
2436 + fsl,tdm-framer-type = "e1";
2437 + fsl,tdm-id = <0>;
2438 + fsl,siram-entry-id = <0>;
2439 + fsl,tdm-interface;
2440 + };
2441 };
2442
2443 &duart0 {
2444 @@ -139,3 +175,76 @@
2445 &duart1 {
2446 status = "okay";
2447 };
2448 +
2449 +#include "fsl-ls1043-post.dtsi"
2450 +
2451 +&fman0 {
2452 + ethernet@e0000 {
2453 + phy-handle = <&qsgmii_phy1>;
2454 + phy-connection-type = "qsgmii";
2455 + };
2456 +
2457 + ethernet@e2000 {
2458 + phy-handle = <&qsgmii_phy2>;
2459 + phy-connection-type = "qsgmii";
2460 + };
2461 +
2462 + ethernet@e4000 {
2463 + phy-handle = <&rgmii_phy1>;
2464 + phy-connection-type = "rgmii-txid";
2465 + };
2466 +
2467 + ethernet@e6000 {
2468 + phy-handle = <&rgmii_phy2>;
2469 + phy-connection-type = "rgmii-txid";
2470 + };
2471 +
2472 + ethernet@e8000 {
2473 + phy-handle = <&qsgmii_phy3>;
2474 + phy-connection-type = "qsgmii";
2475 + };
2476 +
2477 + ethernet@ea000 {
2478 + phy-handle = <&qsgmii_phy4>;
2479 + phy-connection-type = "qsgmii";
2480 + };
2481 +
2482 + ethernet@f0000 { /* 10GEC1 */
2483 + phy-handle = <&aqr105_phy>;
2484 + phy-connection-type = "xgmii";
2485 + };
2486 +
2487 + mdio@fc000 {
2488 + rgmii_phy1: ethernet-phy@1 {
2489 + reg = <0x1>;
2490 + };
2491 +
2492 + rgmii_phy2: ethernet-phy@2 {
2493 + reg = <0x2>;
2494 + };
2495 +
2496 + qsgmii_phy1: ethernet-phy@4 {
2497 + reg = <0x4>;
2498 + };
2499 +
2500 + qsgmii_phy2: ethernet-phy@5 {
2501 + reg = <0x5>;
2502 + };
2503 +
2504 + qsgmii_phy3: ethernet-phy@6 {
2505 + reg = <0x6>;
2506 + };
2507 +
2508 + qsgmii_phy4: ethernet-phy@7 {
2509 + reg = <0x7>;
2510 + };
2511 + };
2512 +
2513 + mdio@fd000 {
2514 + aqr105_phy: ethernet-phy@1 {
2515 + compatible = "ethernet-phy-ieee802.3-c45";
2516 + interrupts = <0 132 4>;
2517 + reg = <0x1>;
2518 + };
2519 + };
2520 +};
2521 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2522 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2523 @@ -1,7 +1,7 @@
2524 /*
2525 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2526 *
2527 - * Copyright 2014-2015, Freescale Semiconductor
2528 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2529 *
2530 * Mingkai Hu <Mingkai.hu@freescale.com>
2531 *
2532 @@ -44,12 +44,25 @@
2533 * OTHER DEALINGS IN THE SOFTWARE.
2534 */
2535
2536 +#include <dt-bindings/thermal/thermal.h>
2537 +
2538 / {
2539 compatible = "fsl,ls1043a";
2540 interrupt-parent = <&gic>;
2541 #address-cells = <2>;
2542 #size-cells = <2>;
2543
2544 + aliases {
2545 + fman0 = &fman0;
2546 + ethernet0 = &enet0;
2547 + ethernet1 = &enet1;
2548 + ethernet2 = &enet2;
2549 + ethernet3 = &enet3;
2550 + ethernet4 = &enet4;
2551 + ethernet5 = &enet5;
2552 + ethernet6 = &enet6;
2553 + };
2554 +
2555 cpus {
2556 #address-cells = <1>;
2557 #size-cells = <0>;
2558 @@ -66,6 +79,8 @@
2559 reg = <0x0>;
2560 clocks = <&clockgen 1 0>;
2561 next-level-cache = <&l2>;
2562 + #cooling-cells = <2>;
2563 + cpu-idle-states = <&CPU_PH20>;
2564 };
2565
2566 cpu1: cpu@1 {
2567 @@ -74,6 +89,7 @@
2568 reg = <0x1>;
2569 clocks = <&clockgen 1 0>;
2570 next-level-cache = <&l2>;
2571 + cpu-idle-states = <&CPU_PH20>;
2572 };
2573
2574 cpu2: cpu@2 {
2575 @@ -82,6 +98,7 @@
2576 reg = <0x2>;
2577 clocks = <&clockgen 1 0>;
2578 next-level-cache = <&l2>;
2579 + cpu-idle-states = <&CPU_PH20>;
2580 };
2581
2582 cpu3: cpu@3 {
2583 @@ -90,6 +107,7 @@
2584 reg = <0x3>;
2585 clocks = <&clockgen 1 0>;
2586 next-level-cache = <&l2>;
2587 + cpu-idle-states = <&CPU_PH20>;
2588 };
2589
2590 l2: l2-cache {
2591 @@ -97,12 +115,56 @@
2592 };
2593 };
2594
2595 + idle-states {
2596 + /*
2597 + * PSCI node is not added default, U-boot will add missing
2598 + * parts if it determines to use PSCI.
2599 + */
2600 + entry-method = "arm,psci";
2601 +
2602 + CPU_PH20: cpu-ph20 {
2603 + compatible = "arm,idle-state";
2604 + idle-state-name = "PH20";
2605 + arm,psci-suspend-param = <0x0>;
2606 + entry-latency-us = <1000>;
2607 + exit-latency-us = <1000>;
2608 + min-residency-us = <3000>;
2609 + };
2610 + };
2611 +
2612 memory@80000000 {
2613 device_type = "memory";
2614 reg = <0x0 0x80000000 0 0x80000000>;
2615 /* DRAM space 1, size: 2GiB DRAM */
2616 };
2617
2618 + reserved-memory {
2619 + #address-cells = <2>;
2620 + #size-cells = <2>;
2621 + ranges;
2622 +
2623 + bman_fbpr: bman-fbpr {
2624 + compatible = "shared-dma-pool";
2625 + size = <0 0x1000000>;
2626 + alignment = <0 0x1000000>;
2627 + no-map;
2628 + };
2629 +
2630 + qman_fqd: qman-fqd {
2631 + compatible = "shared-dma-pool";
2632 + size = <0 0x400000>;
2633 + alignment = <0 0x400000>;
2634 + no-map;
2635 + };
2636 +
2637 + qman_pfdr: qman-pfdr {
2638 + compatible = "shared-dma-pool";
2639 + size = <0 0x2000000>;
2640 + alignment = <0 0x2000000>;
2641 + no-map;
2642 + };
2643 + };
2644 +
2645 sysclk: sysclk {
2646 compatible = "fixed-clock";
2647 #clock-cells = <0>;
2648 @@ -149,7 +211,7 @@
2649 interrupts = <1 9 0xf08>;
2650 };
2651
2652 - soc {
2653 + soc: soc {
2654 compatible = "simple-bus";
2655 #address-cells = <2>;
2656 #size-cells = <2>;
2657 @@ -213,13 +275,14 @@
2658
2659 dcfg: dcfg@1ee0000 {
2660 compatible = "fsl,ls1043a-dcfg", "syscon";
2661 - reg = <0x0 0x1ee0000 0x0 0x10000>;
2662 + reg = <0x0 0x1ee0000 0x0 0x1000>;
2663 big-endian;
2664 };
2665
2666 ifc: ifc@1530000 {
2667 compatible = "fsl,ifc", "simple-bus";
2668 reg = <0x0 0x1530000 0x0 0x10000>;
2669 + big-endian;
2670 interrupts = <0 43 0x4>;
2671 };
2672
2673 @@ -255,6 +318,103 @@
2674 big-endian;
2675 };
2676
2677 + tmu: tmu@1f00000 {
2678 + compatible = "fsl,qoriq-tmu";
2679 + reg = <0x0 0x1f00000 0x0 0x10000>;
2680 + interrupts = <0 33 0x4>;
2681 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
2682 + fsl,tmu-calibration = <0x00000000 0x00000026
2683 + 0x00000001 0x0000002d
2684 + 0x00000002 0x00000032
2685 + 0x00000003 0x00000039
2686 + 0x00000004 0x0000003f
2687 + 0x00000005 0x00000046
2688 + 0x00000006 0x0000004d
2689 + 0x00000007 0x00000054
2690 + 0x00000008 0x0000005a
2691 + 0x00000009 0x00000061
2692 + 0x0000000a 0x0000006a
2693 + 0x0000000b 0x00000071
2694 +
2695 + 0x00010000 0x00000025
2696 + 0x00010001 0x0000002c
2697 + 0x00010002 0x00000035
2698 + 0x00010003 0x0000003d
2699 + 0x00010004 0x00000045
2700 + 0x00010005 0x0000004e
2701 + 0x00010006 0x00000057
2702 + 0x00010007 0x00000061
2703 + 0x00010008 0x0000006b
2704 + 0x00010009 0x00000076
2705 +
2706 + 0x00020000 0x00000029
2707 + 0x00020001 0x00000033
2708 + 0x00020002 0x0000003d
2709 + 0x00020003 0x00000049
2710 + 0x00020004 0x00000056
2711 + 0x00020005 0x00000061
2712 + 0x00020006 0x0000006d
2713 +
2714 + 0x00030000 0x00000021
2715 + 0x00030001 0x0000002a
2716 + 0x00030002 0x0000003c
2717 + 0x00030003 0x0000004e>;
2718 + #thermal-sensor-cells = <1>;
2719 + };
2720 +
2721 + thermal-zones {
2722 + cpu_thermal: cpu-thermal {
2723 + polling-delay-passive = <1000>;
2724 + polling-delay = <5000>;
2725 +
2726 + thermal-sensors = <&tmu 3>;
2727 +
2728 + trips {
2729 + cpu_alert: cpu-alert {
2730 + temperature = <85000>;
2731 + hysteresis = <2000>;
2732 + type = "passive";
2733 + };
2734 + cpu_crit: cpu-crit {
2735 + temperature = <95000>;
2736 + hysteresis = <2000>;
2737 + type = "critical";
2738 + };
2739 + };
2740 +
2741 + cooling-maps {
2742 + map0 {
2743 + trip = <&cpu_alert>;
2744 + cooling-device =
2745 + <&cpu0 THERMAL_NO_LIMIT
2746 + THERMAL_NO_LIMIT>;
2747 + };
2748 + };
2749 + };
2750 + };
2751 +
2752 + qman: qman@1880000 {
2753 + compatible = "fsl,qman";
2754 + reg = <0x00 0x1880000 0x0 0x10000>;
2755 + interrupts = <0 45 0x4>;
2756 + memory-region = <&qman_fqd &qman_pfdr>;
2757 + };
2758 +
2759 + bman: bman@1890000 {
2760 + compatible = "fsl,bman";
2761 + reg = <0x00 0x1890000 0x0 0x10000>;
2762 + interrupts = <0 45 0x4>;
2763 + memory-region = <&bman_fbpr>;
2764 + };
2765 +
2766 + bportals: bman-portals@508000000 {
2767 + ranges = <0x0 0x5 0x08000000 0x8000000>;
2768 + };
2769 +
2770 + qportals: qman-portals@500000000 {
2771 + ranges = <0x0 0x5 0x00000000 0x8000000>;
2772 + };
2773 +
2774 dspi0: dspi@2100000 {
2775 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
2776 #address-cells = <1>;
2777 @@ -396,6 +556,72 @@
2778 #interrupt-cells = <2>;
2779 };
2780
2781 + uqe: uqe@2400000 {
2782 + #address-cells = <1>;
2783 + #size-cells = <1>;
2784 + device_type = "qe";
2785 + compatible = "fsl,qe", "simple-bus";
2786 + ranges = <0x0 0x0 0x2400000 0x40000>;
2787 + reg = <0x0 0x2400000 0x0 0x480>;
2788 + brg-frequency = <100000000>;
2789 + bus-frequency = <200000000>;
2790 +
2791 + fsl,qe-num-riscs = <1>;
2792 + fsl,qe-num-snums = <28>;
2793 +
2794 + qeic: qeic@80 {
2795 + compatible = "fsl,qe-ic";
2796 + reg = <0x80 0x80>;
2797 + #address-cells = <0>;
2798 + interrupt-controller;
2799 + #interrupt-cells = <1>;
2800 + interrupts = <0 77 0x04 0 77 0x04>;
2801 + };
2802 +
2803 + si1: si@700 {
2804 + #address-cells = <1>;
2805 + #size-cells = <0>;
2806 + compatible = "fsl,ls1043-qe-si",
2807 + "fsl,t1040-qe-si";
2808 + reg = <0x700 0x80>;
2809 + };
2810 +
2811 + siram1: siram@1000 {
2812 + #address-cells = <1>;
2813 + #size-cells = <1>;
2814 + compatible = "fsl,ls1043-qe-siram",
2815 + "fsl,t1040-qe-siram";
2816 + reg = <0x1000 0x800>;
2817 + };
2818 +
2819 + ucc@2000 {
2820 + cell-index = <1>;
2821 + reg = <0x2000 0x200>;
2822 + interrupts = <32>;
2823 + interrupt-parent = <&qeic>;
2824 + };
2825 +
2826 + ucc@2200 {
2827 + cell-index = <3>;
2828 + reg = <0x2200 0x200>;
2829 + interrupts = <34>;
2830 + interrupt-parent = <&qeic>;
2831 + };
2832 +
2833 + muram@10000 {
2834 + #address-cells = <1>;
2835 + #size-cells = <1>;
2836 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
2837 + ranges = <0x0 0x10000 0x6000>;
2838 +
2839 + data-only@0 {
2840 + compatible = "fsl,qe-muram-data",
2841 + "fsl,cpm-muram-data";
2842 + reg = <0x0 0x6000>;
2843 + };
2844 + };
2845 + };
2846 +
2847 lpuart0: serial@2950000 {
2848 compatible = "fsl,ls1021a-lpuart";
2849 reg = <0x0 0x2950000 0x0 0x1000>;
2850 @@ -450,6 +676,16 @@
2851 status = "disabled";
2852 };
2853
2854 + ftm0: ftm0@29d0000 {
2855 + compatible = "fsl,ls1043a-ftm";
2856 + reg = <0x0 0x29d0000 0x0 0x10000>,
2857 + <0x0 0x1ee2140 0x0 0x4>;
2858 + reg-names = "ftm", "FlexTimer1";
2859 + interrupts = <0 86 0x4>;
2860 + big-endian;
2861 + status = "okay";
2862 + };
2863 +
2864 wdog0: wdog@2ad0000 {
2865 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
2866 reg = <0x0 0x2ad0000 0x0 0x10000>;
2867 @@ -482,6 +718,8 @@
2868 dr_mode = "host";
2869 snps,quirk-frame-length-adjustment = <0x20>;
2870 snps,dis_rxdet_inp3_quirk;
2871 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2872 + snps,dma-snooping;
2873 };
2874
2875 usb1: usb3@3000000 {
2876 @@ -491,6 +729,9 @@
2877 dr_mode = "host";
2878 snps,quirk-frame-length-adjustment = <0x20>;
2879 snps,dis_rxdet_inp3_quirk;
2880 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2881 + snps,dma-snooping;
2882 + configure-gfladj;
2883 };
2884
2885 usb2: usb3@3100000 {
2886 @@ -500,32 +741,52 @@
2887 dr_mode = "host";
2888 snps,quirk-frame-length-adjustment = <0x20>;
2889 snps,dis_rxdet_inp3_quirk;
2890 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2891 + snps,dma-snooping;
2892 + configure-gfladj;
2893 };
2894
2895 sata: sata@3200000 {
2896 compatible = "fsl,ls1043a-ahci";
2897 - reg = <0x0 0x3200000 0x0 0x10000>;
2898 + reg = <0x0 0x3200000 0x0 0x10000>,
2899 + <0x0 0x20140520 0x0 0x4>;
2900 + reg-names = "ahci", "sata-ecc";
2901 interrupts = <0 69 0x4>;
2902 clocks = <&clockgen 4 0>;
2903 dma-coherent;
2904 };
2905
2906 + qdma: qdma@8380000 {
2907 + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
2908 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
2909 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
2910 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
2911 + interrupts = <0 152 0x4>,
2912 + <0 39 0x4>;
2913 + interrupt-names = "qdma-error", "qdma-queue";
2914 + channels = <8>;
2915 + queues = <2>;
2916 + status-sizes = <64>;
2917 + queue-sizes = <64 64>;
2918 + big-endian;
2919 + };
2920 +
2921 msi1: msi-controller1@1571000 {
2922 - compatible = "fsl,1s1043a-msi";
2923 + compatible = "fsl,ls1043a-msi";
2924 reg = <0x0 0x1571000 0x0 0x8>;
2925 msi-controller;
2926 interrupts = <0 116 0x4>;
2927 };
2928
2929 msi2: msi-controller2@1572000 {
2930 - compatible = "fsl,1s1043a-msi";
2931 + compatible = "fsl,ls1043a-msi";
2932 reg = <0x0 0x1572000 0x0 0x8>;
2933 msi-controller;
2934 interrupts = <0 126 0x4>;
2935 };
2936
2937 msi3: msi-controller3@1573000 {
2938 - compatible = "fsl,1s1043a-msi";
2939 + compatible = "fsl,ls1043a-msi";
2940 reg = <0x0 0x1573000 0x0 0x8>;
2941 msi-controller;
2942 interrupts = <0 160 0x4>;
2943 @@ -536,9 +797,9 @@
2944 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
2945 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
2946 reg-names = "regs", "config";
2947 - interrupts = <0 118 0x4>, /* controller interrupt */
2948 - <0 117 0x4>; /* PME interrupt */
2949 - interrupt-names = "intr", "pme";
2950 + interrupts = <0 117 0x4>, /* PME interrupt */
2951 + <0 118 0x4>; /* aer interrupt */
2952 + interrupt-names = "pme", "aer";
2953 #address-cells = <3>;
2954 #size-cells = <2>;
2955 device_type = "pci";
2956 @@ -547,7 +808,7 @@
2957 bus-range = <0x0 0xff>;
2958 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
2959 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2960 - msi-parent = <&msi1>;
2961 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
2962 #interrupt-cells = <1>;
2963 interrupt-map-mask = <0 0 0 7>;
2964 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
2965 @@ -561,9 +822,9 @@
2966 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
2967 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
2968 reg-names = "regs", "config";
2969 - interrupts = <0 128 0x4>,
2970 - <0 127 0x4>;
2971 - interrupt-names = "intr", "pme";
2972 + interrupts = <0 127 0x4>,
2973 + <0 128 0x4>;
2974 + interrupt-names = "pme", "aer";
2975 #address-cells = <3>;
2976 #size-cells = <2>;
2977 device_type = "pci";
2978 @@ -572,7 +833,7 @@
2979 bus-range = <0x0 0xff>;
2980 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
2981 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2982 - msi-parent = <&msi2>;
2983 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
2984 #interrupt-cells = <1>;
2985 interrupt-map-mask = <0 0 0 7>;
2986 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
2987 @@ -586,9 +847,9 @@
2988 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
2989 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
2990 reg-names = "regs", "config";
2991 - interrupts = <0 162 0x4>,
2992 - <0 161 0x4>;
2993 - interrupt-names = "intr", "pme";
2994 + interrupts = <0 161 0x4>,
2995 + <0 162 0x4>;
2996 + interrupt-names = "pme", "aer";
2997 #address-cells = <3>;
2998 #size-cells = <2>;
2999 device_type = "pci";
3000 @@ -597,7 +858,7 @@
3001 bus-range = <0x0 0xff>;
3002 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
3003 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3004 - msi-parent = <&msi3>;
3005 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3006 #interrupt-cells = <1>;
3007 interrupt-map-mask = <0 0 0 7>;
3008 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
3009 @@ -608,3 +869,6 @@
3010 };
3011
3012 };
3013 +
3014 +#include "qoriq-qman1-portals.dtsi"
3015 +#include "qoriq-bman1-portals.dtsi"
3016 --- /dev/null
3017 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
3018 @@ -0,0 +1,48 @@
3019 +/*
3020 + * QorIQ FMan v3 device tree nodes for ls1046
3021 + *
3022 + * Copyright 2015-2016 Freescale Semiconductor Inc.
3023 + *
3024 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3025 + */
3026 +
3027 +&soc {
3028 +
3029 +/* include used FMan blocks */
3030 +#include "qoriq-fman3-0.dtsi"
3031 +#include "qoriq-fman3-0-1g-0.dtsi"
3032 +#include "qoriq-fman3-0-1g-1.dtsi"
3033 +#include "qoriq-fman3-0-1g-2.dtsi"
3034 +#include "qoriq-fman3-0-1g-3.dtsi"
3035 +#include "qoriq-fman3-0-1g-4.dtsi"
3036 +#include "qoriq-fman3-0-1g-5.dtsi"
3037 +#include "qoriq-fman3-0-10g-0.dtsi"
3038 +#include "qoriq-fman3-0-10g-1.dtsi"
3039 +};
3040 +
3041 +&fman0 {
3042 + /* these aliases provide the FMan ports mapping */
3043 + enet0: ethernet@e0000 {
3044 + };
3045 +
3046 + enet1: ethernet@e2000 {
3047 + };
3048 +
3049 + enet2: ethernet@e4000 {
3050 + };
3051 +
3052 + enet3: ethernet@e6000 {
3053 + };
3054 +
3055 + enet4: ethernet@e8000 {
3056 + };
3057 +
3058 + enet5: ethernet@ea000 {
3059 + };
3060 +
3061 + enet6: ethernet@f0000 {
3062 + };
3063 +
3064 + enet7: ethernet@f2000 {
3065 + };
3066 +};
3067 --- /dev/null
3068 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
3069 @@ -0,0 +1,109 @@
3070 +/*
3071 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3072 + *
3073 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3074 + *
3075 + * Mingkai Hu <Mingkai.hu@freescale.com>
3076 + *
3077 + * This file is dual-licensed: you can use it either under the terms
3078 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3079 + * licensing only applies to this file, and not this project as a
3080 + * whole.
3081 + *
3082 + * a) This library is free software; you can redistribute it and/or
3083 + * modify it under the terms of the GNU General Public License as
3084 + * published by the Free Software Foundation; either version 2 of the
3085 + * License, or (at your option) any later version.
3086 + *
3087 + * This library is distributed in the hope that it will be useful,
3088 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3089 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3090 + * GNU General Public License for more details.
3091 + *
3092 + * Or, alternatively,
3093 + *
3094 + * b) Permission is hereby granted, free of charge, to any person
3095 + * obtaining a copy of this software and associated documentation
3096 + * files (the "Software"), to deal in the Software without
3097 + * restriction, including without limitation the rights to use,
3098 + * copy, modify, merge, publish, distribute, sublicense, and/or
3099 + * sell copies of the Software, and to permit persons to whom the
3100 + * Software is furnished to do so, subject to the following
3101 + * conditions:
3102 + *
3103 + * The above copyright notice and this permission notice shall be
3104 + * included in all copies or substantial portions of the Software.
3105 + *
3106 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3107 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3108 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3109 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3110 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3111 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3112 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3113 + * OTHER DEALINGS IN THE SOFTWARE.
3114 + */
3115 +
3116 +#include "fsl-ls1046a-qds.dts"
3117 +
3118 +&bman_fbpr {
3119 + compatible = "fsl,bman-fbpr";
3120 + alloc-ranges = <0 0 0x10000 0>;
3121 +};
3122 +&qman_fqd {
3123 + compatible = "fsl,qman-fqd";
3124 + alloc-ranges = <0 0 0x10000 0>;
3125 +};
3126 +&qman_pfdr {
3127 + compatible = "fsl,qman-pfdr";
3128 + alloc-ranges = <0 0 0x10000 0>;
3129 +};
3130 +
3131 +&soc {
3132 +#include "qoriq-dpaa-eth.dtsi"
3133 +#include "qoriq-fman3-0-6oh.dtsi"
3134 +};
3135 +
3136 +&fsldpaa {
3137 + ethernet@9 {
3138 + compatible = "fsl,dpa-ethernet";
3139 + fsl,fman-mac = <&enet7>;
3140 + };
3141 +};
3142 +
3143 +&fman0 {
3144 + compatible = "fsl,fman", "simple-bus";
3145 +};
3146 +
3147 +&dspi {
3148 + bus-num = <0>;
3149 + status = "okay";
3150 +
3151 + flash@0 {
3152 + #address-cells = <1>;
3153 + #size-cells = <1>;
3154 + compatible = "n25q128a11", "jedec,spi-nor";
3155 + reg = <0>;
3156 + spi-max-frequency = <10000000>;
3157 + };
3158 +
3159 + flash@1 {
3160 + #address-cells = <1>;
3161 + #size-cells = <1>;
3162 + compatible = "sst25wf040b", "jedec,spi-nor";
3163 + spi-cpol;
3164 + spi-cpha;
3165 + reg = <1>;
3166 + spi-max-frequency = <10000000>;
3167 + };
3168 +
3169 + flash@2 {
3170 + #address-cells = <1>;
3171 + #size-cells = <1>;
3172 + compatible = "en25s64", "jedec,spi-nor";
3173 + spi-cpol;
3174 + spi-cpha;
3175 + reg = <2>;
3176 + spi-max-frequency = <10000000>;
3177 + };
3178 +};
3179 --- /dev/null
3180 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3181 @@ -0,0 +1,363 @@
3182 +/*
3183 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3184 + *
3185 + * Copyright 2016 Freescale Semiconductor, Inc.
3186 + *
3187 + * Shaohui Xie <Shaohui.Xie@nxp.com>
3188 + *
3189 + * This file is dual-licensed: you can use it either under the terms
3190 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3191 + * licensing only applies to this file, and not this project as a
3192 + * whole.
3193 + *
3194 + * a) This library is free software; you can redistribute it and/or
3195 + * modify it under the terms of the GNU General Public License as
3196 + * published by the Free Software Foundation; either version 2 of the
3197 + * License, or (at your option) any later version.
3198 + *
3199 + * This library is distributed in the hope that it will be useful,
3200 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3201 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3202 + * GNU General Public License for more details.
3203 + *
3204 + * Or, alternatively,
3205 + *
3206 + * b) Permission is hereby granted, free of charge, to any person
3207 + * obtaining a copy of this software and associated documentation
3208 + * files (the "Software"), to deal in the Software without
3209 + * restriction, including without limitation the rights to use,
3210 + * copy, modify, merge, publish, distribute, sublicense, and/or
3211 + * sell copies of the Software, and to permit persons to whom the
3212 + * Software is furnished to do so, subject to the following
3213 + * conditions:
3214 + *
3215 + * The above copyright notice and this permission notice shall be
3216 + * included in all copies or substantial portions of the Software.
3217 + *
3218 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3219 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3220 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3221 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3222 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3223 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3224 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3225 + * OTHER DEALINGS IN THE SOFTWARE.
3226 + */
3227 +
3228 +/dts-v1/;
3229 +
3230 +#include "fsl-ls1046a.dtsi"
3231 +
3232 +/ {
3233 + model = "LS1046A QDS Board";
3234 + compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
3235 +
3236 + aliases {
3237 + gpio0 = &gpio0;
3238 + gpio1 = &gpio1;
3239 + gpio2 = &gpio2;
3240 + gpio3 = &gpio3;
3241 + serial0 = &duart0;
3242 + serial1 = &duart1;
3243 + serial2 = &duart2;
3244 + serial3 = &duart3;
3245 +
3246 + emi1_slot1 = &ls1046mdio_s1;
3247 + emi1_slot2 = &ls1046mdio_s2;
3248 + emi1_slot4 = &ls1046mdio_s4;
3249 +
3250 + sgmii_s1_p1 = &sgmii_phy_s1_p1;
3251 + sgmii_s1_p2 = &sgmii_phy_s1_p2;
3252 + sgmii_s1_p3 = &sgmii_phy_s1_p3;
3253 + sgmii_s1_p4 = &sgmii_phy_s1_p4;
3254 + sgmii_s4_p1 = &sgmii_phy_s4_p1;
3255 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
3256 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
3257 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
3258 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
3259 + };
3260 +
3261 + chosen {
3262 + stdout-path = "serial0:115200n8";
3263 + };
3264 +};
3265 +
3266 +&dspi {
3267 + bus-num = <0>;
3268 + status = "okay";
3269 +
3270 + flash@0 {
3271 + #address-cells = <1>;
3272 + #size-cells = <1>;
3273 + compatible = "n25q128a11", "jedec,spi-nor";
3274 + reg = <0>;
3275 + spi-max-frequency = <10000000>;
3276 + };
3277 +
3278 + flash@1 {
3279 + #address-cells = <1>;
3280 + #size-cells = <1>;
3281 + compatible = "sst25wf040b", "jedec,spi-nor";
3282 + spi-cpol;
3283 + spi-cpha;
3284 + reg = <1>;
3285 + spi-max-frequency = <10000000>;
3286 + };
3287 +
3288 + flash@2 {
3289 + #address-cells = <1>;
3290 + #size-cells = <1>;
3291 + compatible = "en25s64", "jedec,spi-nor";
3292 + spi-cpol;
3293 + spi-cpha;
3294 + reg = <2>;
3295 + spi-max-frequency = <10000000>;
3296 + };
3297 +};
3298 +
3299 +&duart0 {
3300 + status = "okay";
3301 +};
3302 +
3303 +&duart1 {
3304 + status = "okay";
3305 +};
3306 +
3307 +&i2c0 {
3308 + status = "okay";
3309 +
3310 + pca9547@77 {
3311 + compatible = "nxp,pca9547";
3312 + reg = <0x77>;
3313 + #address-cells = <1>;
3314 + #size-cells = <0>;
3315 +
3316 + i2c@2 {
3317 + #address-cells = <1>;
3318 + #size-cells = <0>;
3319 + reg = <0x2>;
3320 +
3321 + ina220@40 {
3322 + compatible = "ti,ina220";
3323 + reg = <0x40>;
3324 + shunt-resistor = <1000>;
3325 + };
3326 +
3327 + ina220@41 {
3328 + compatible = "ti,ina220";
3329 + reg = <0x41>;
3330 + shunt-resistor = <1000>;
3331 + };
3332 + };
3333 +
3334 + i2c@3 {
3335 + #address-cells = <1>;
3336 + #size-cells = <0>;
3337 + reg = <0x3>;
3338 +
3339 + rtc@51 {
3340 + compatible = "nxp,pcf2129";
3341 + reg = <0x51>;
3342 + /* IRQ10_B */
3343 + interrupts = <0 150 0x4>;
3344 + };
3345 +
3346 + eeprom@56 {
3347 + compatible = "atmel,24c512";
3348 + reg = <0x56>;
3349 + };
3350 +
3351 + eeprom@57 {
3352 + compatible = "atmel,24c512";
3353 + reg = <0x57>;
3354 + };
3355 +
3356 + temp-sensor@4c {
3357 + compatible = "adi,adt7461a";
3358 + reg = <0x4c>;
3359 + };
3360 + };
3361 + };
3362 +};
3363 +
3364 +&ifc {
3365 + #address-cells = <2>;
3366 + #size-cells = <1>;
3367 + /* NOR, NAND Flashes and FPGA on board */
3368 + ranges = <0x0 0x0 0x0 0x60000000 0x08000000
3369 + 0x1 0x0 0x0 0x7e800000 0x00010000
3370 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3371 + status = "okay";
3372 +
3373 + nor@0,0 {
3374 + compatible = "cfi-flash";
3375 + reg = <0x0 0x0 0x8000000>;
3376 + bank-width = <2>;
3377 + device-width = <1>;
3378 + };
3379 +
3380 + nand@1,0 {
3381 + compatible = "fsl,ifc-nand";
3382 + reg = <0x1 0x0 0x10000>;
3383 + };
3384 +
3385 + fpga: board-control@2,0 {
3386 + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
3387 + reg = <0x2 0x0 0x0000100>;
3388 + ranges = <0 2 0 0x100>;
3389 + };
3390 +};
3391 +
3392 +&lpuart0 {
3393 + status = "okay";
3394 +};
3395 +
3396 +&qspi {
3397 + num-cs = <2>;
3398 + bus-num = <0>;
3399 + status = "okay";
3400 +
3401 + qflash0: s25fl128s@0 {
3402 + compatible = "spansion,m25p80";
3403 + #address-cells = <1>;
3404 + #size-cells = <1>;
3405 + spi-max-frequency = <20000000>;
3406 + reg = <0>;
3407 + };
3408 +};
3409 +
3410 +#include "fsl-ls1046-post.dtsi"
3411 +
3412 +&fman0 {
3413 + ethernet@e0000 {
3414 + phy-handle = <&qsgmii_phy_s2_p1>;
3415 + phy-connection-type = "sgmii";
3416 + };
3417 +
3418 + ethernet@e2000 {
3419 + phy-handle = <&sgmii_phy_s4_p1>;
3420 + phy-connection-type = "sgmii";
3421 + };
3422 +
3423 + ethernet@e4000 {
3424 + phy-handle = <&rgmii_phy1>;
3425 + phy-connection-type = "rgmii";
3426 + };
3427 +
3428 + ethernet@e6000 {
3429 + phy-handle = <&rgmii_phy2>;
3430 + phy-connection-type = "rgmii";
3431 + };
3432 +
3433 + ethernet@e8000 {
3434 + phy-handle = <&sgmii_phy_s1_p3>;
3435 + phy-connection-type = "sgmii";
3436 + };
3437 +
3438 + ethernet@ea000 {
3439 + phy-handle = <&sgmii_phy_s1_p4>;
3440 + phy-connection-type = "sgmii";
3441 + };
3442 +
3443 + ethernet@f0000 { /* DTSEC9/10GEC1 */
3444 + phy-handle = <&sgmii_phy_s1_p1>;
3445 + phy-connection-type = "xgmii";
3446 + };
3447 +
3448 + ethernet@f2000 { /* DTSEC10/10GEC2 */
3449 + phy-handle = <&sgmii_phy_s1_p2>;
3450 + phy-connection-type = "xgmii";
3451 + };
3452 +};
3453 +
3454 +&fpga {
3455 + #address-cells = <1>;
3456 + #size-cells = <1>;
3457 + mdio-mux-emi1 {
3458 + compatible = "mdio-mux-mmioreg", "mdio-mux";
3459 + mdio-parent-bus = <&mdio0>;
3460 + #address-cells = <1>;
3461 + #size-cells = <0>;
3462 + reg = <0x54 1>; /* BRDCFG4 */
3463 + mux-mask = <0xe0>; /* EMI1 */
3464 +
3465 + /* On-board RGMII1 PHY */
3466 + ls1046mdio0: mdio@0 {
3467 + reg = <0>;
3468 + #address-cells = <1>;
3469 + #size-cells = <0>;
3470 +
3471 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
3472 + reg = <0x1>;
3473 + };
3474 + };
3475 +
3476 + /* On-board RGMII2 PHY */
3477 + ls1046mdio1: mdio@1 {
3478 + reg = <0x20>;
3479 + #address-cells = <1>;
3480 + #size-cells = <0>;
3481 +
3482 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
3483 + reg = <0x2>;
3484 + };
3485 + };
3486 +
3487 + /* Slot 1 */
3488 + ls1046mdio_s1: mdio@2 {
3489 + reg = <0x40>;
3490 + #address-cells = <1>;
3491 + #size-cells = <0>;
3492 + status = "disabled";
3493 +
3494 + sgmii_phy_s1_p1: ethernet-phy@1c {
3495 + reg = <0x1c>;
3496 + };
3497 +
3498 + sgmii_phy_s1_p2: ethernet-phy@1d {
3499 + reg = <0x1d>;
3500 + };
3501 +
3502 + sgmii_phy_s1_p3: ethernet-phy@1e {
3503 + reg = <0x1e>;
3504 + };
3505 +
3506 + sgmii_phy_s1_p4: ethernet-phy@1f {
3507 + reg = <0x1f>;
3508 + };
3509 + };
3510 +
3511 + /* Slot 2 */
3512 + ls1046mdio_s2: mdio@3 {
3513 + reg = <0x60>;
3514 + #address-cells = <1>;
3515 + #size-cells = <0>;
3516 + status = "disabled";
3517 +
3518 + qsgmii_phy_s2_p1: ethernet-phy@8 {
3519 + reg = <0x8>;
3520 + };
3521 + qsgmii_phy_s2_p2: ethernet-phy@9 {
3522 + reg = <0x9>;
3523 + };
3524 + qsgmii_phy_s2_p3: ethernet-phy@a {
3525 + reg = <0xa>;
3526 + };
3527 + qsgmii_phy_s2_p4: ethernet-phy@b {
3528 + reg = <0xb>;
3529 + };
3530 + };
3531 +
3532 + /* Slot 4 */
3533 + ls1046mdio_s4: mdio@5 {
3534 + reg = <0x80>;
3535 + #address-cells = <1>;
3536 + #size-cells = <0>;
3537 + status = "disabled";
3538 +
3539 + sgmii_phy_s4_p1: ethernet-phy@1c {
3540 + reg = <0x1c>;
3541 + };
3542 + };
3543 + };
3544 +};
3545 --- /dev/null
3546 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
3547 @@ -0,0 +1,76 @@
3548 +/*
3549 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3550 + *
3551 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3552 + *
3553 + * Mingkai Hu <Mingkai.hu@freescale.com>
3554 + *
3555 + * This file is dual-licensed: you can use it either under the terms
3556 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3557 + * licensing only applies to this file, and not this project as a
3558 + * whole.
3559 + *
3560 + * a) This library is free software; you can redistribute it and/or
3561 + * modify it under the terms of the GNU General Public License as
3562 + * published by the Free Software Foundation; either version 2 of the
3563 + * License, or (at your option) any later version.
3564 + *
3565 + * This library is distributed in the hope that it will be useful,
3566 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3567 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3568 + * GNU General Public License for more details.
3569 + *
3570 + * Or, alternatively,
3571 + *
3572 + * b) Permission is hereby granted, free of charge, to any person
3573 + * obtaining a copy of this software and associated documentation
3574 + * files (the "Software"), to deal in the Software without
3575 + * restriction, including without limitation the rights to use,
3576 + * copy, modify, merge, publish, distribute, sublicense, and/or
3577 + * sell copies of the Software, and to permit persons to whom the
3578 + * Software is furnished to do so, subject to the following
3579 + * conditions:
3580 + *
3581 + * The above copyright notice and this permission notice shall be
3582 + * included in all copies or substantial portions of the Software.
3583 + *
3584 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3585 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3586 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3587 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3588 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3589 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3590 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3591 + * OTHER DEALINGS IN THE SOFTWARE.
3592 + */
3593 +
3594 +#include "fsl-ls1046a-rdb.dts"
3595 +
3596 +&bman_fbpr {
3597 + compatible = "fsl,bman-fbpr";
3598 + alloc-ranges = <0 0 0x10000 0>;
3599 +};
3600 +&qman_fqd {
3601 + compatible = "fsl,qman-fqd";
3602 + alloc-ranges = <0 0 0x10000 0>;
3603 +};
3604 +&qman_pfdr {
3605 + compatible = "fsl,qman-pfdr";
3606 + alloc-ranges = <0 0 0x10000 0>;
3607 +};
3608 +
3609 +&soc {
3610 +#include "qoriq-dpaa-eth.dtsi"
3611 +#include "qoriq-fman3-0-6oh.dtsi"
3612 +};
3613 +
3614 +&fsldpaa {
3615 + ethernet@9 {
3616 + compatible = "fsl,dpa-ethernet";
3617 + fsl,fman-mac = <&enet7>;
3618 + };
3619 +};
3620 +
3621 +&fman0 {
3622 + compatible = "fsl,fman", "simple-bus";
3623 +};
3624 --- /dev/null
3625 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
3626 @@ -0,0 +1,110 @@
3627 +/*
3628 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3629 + *
3630 + * Copyright 2016 Freescale Semiconductor, Inc.
3631 + *
3632 + * This file is licensed under the terms of the GNU General Public
3633 + * License version 2. This program is licensed "as is" without any
3634 + * warranty of any kind, whether express or implied.
3635 + */
3636 +
3637 +#include "fsl-ls1046a-rdb-sdk.dts"
3638 +
3639 +&soc {
3640 + bp7: buffer-pool@7 {
3641 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3642 + fsl,bpid = <7>;
3643 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
3644 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
3645 + };
3646 +
3647 + bp8: buffer-pool@8 {
3648 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3649 + fsl,bpid = <8>;
3650 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
3651 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3652 + };
3653 +
3654 + bp9: buffer-pool@9 {
3655 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3656 + fsl,bpid = <9>;
3657 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
3658 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3659 + };
3660 +
3661 + fsl,dpaa {
3662 + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
3663 +
3664 + ethernet@2 {
3665 + compatible = "fsl,dpa-ethernet-init";
3666 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3667 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
3668 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
3669 + };
3670 +
3671 + ethernet@3 {
3672 + compatible = "fsl,dpa-ethernet-init";
3673 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3674 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
3675 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
3676 + };
3677 +
3678 + ethernet@4 {
3679 + compatible = "fsl,dpa-ethernet-init";
3680 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3681 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
3682 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
3683 + };
3684 +
3685 + ethernet@5 {
3686 + compatible = "fsl,dpa-ethernet-init";
3687 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3688 + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
3689 + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
3690 + };
3691 +
3692 + ethernet@8 {
3693 + compatible = "fsl,dpa-ethernet-init";
3694 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3695 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
3696 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
3697 + };
3698 +
3699 + ethernet@9 {
3700 + compatible = "fsl,dpa-ethernet-init";
3701 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3702 + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
3703 + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
3704 + };
3705 +
3706 + dpa-fman0-oh@2 {
3707 + compatible = "fsl,dpa-oh";
3708 + /* Define frame queues for the OH port*/
3709 + /* <OH Rx error, OH Rx default> */
3710 + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
3711 + fsl,fman-oh-port = <&fman0_oh2>;
3712 + };
3713 + };
3714 +};
3715 +/ {
3716 + reserved-memory {
3717 + #address-cells = <2>;
3718 + #size-cells = <2>;
3719 + ranges;
3720 +
3721 + usdpaa_mem: usdpaa_mem {
3722 + compatible = "fsl,usdpaa-mem";
3723 + alloc-ranges = <0 0 0x10000 0>;
3724 + size = <0 0x10000000>;
3725 + alignment = <0 0x10000000>;
3726 + };
3727 + };
3728 +};
3729 +
3730 +&fman0 {
3731 + fman0_oh2: port@83000 {
3732 + cell-index = <1>;
3733 + compatible = "fsl,fman-port-oh";
3734 + reg = <0x83000 0x1000>;
3735 + };
3736 +};
3737 --- /dev/null
3738 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
3739 @@ -0,0 +1,218 @@
3740 +/*
3741 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3742 + *
3743 + * Copyright 2016 Freescale Semiconductor, Inc.
3744 + *
3745 + * Mingkai Hu <mingkai.hu@nxp.com>
3746 + *
3747 + * This file is dual-licensed: you can use it either under the terms
3748 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3749 + * licensing only applies to this file, and not this project as a
3750 + * whole.
3751 + *
3752 + * a) This library is free software; you can redistribute it and/or
3753 + * modify it under the terms of the GNU General Public License as
3754 + * published by the Free Software Foundation; either version 2 of the
3755 + * License, or (at your option) any later version.
3756 + *
3757 + * This library is distributed in the hope that it will be useful,
3758 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3759 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3760 + * GNU General Public License for more details.
3761 + *
3762 + * Or, alternatively,
3763 + *
3764 + * b) Permission is hereby granted, free of charge, to any person
3765 + * obtaining a copy of this software and associated documentation
3766 + * files (the "Software"), to deal in the Software without
3767 + * restriction, including without limitation the rights to use,
3768 + * copy, modify, merge, publish, distribute, sublicense, and/or
3769 + * sell copies of the Software, and to permit persons to whom the
3770 + * Software is furnished to do so, subject to the following
3771 + * conditions:
3772 + *
3773 + * The above copyright notice and this permission notice shall be
3774 + * included in all copies or substantial portions of the Software.
3775 + *
3776 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3777 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3778 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3779 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3780 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3781 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3782 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3783 + * OTHER DEALINGS IN THE SOFTWARE.
3784 + */
3785 +
3786 +/dts-v1/;
3787 +
3788 +#include "fsl-ls1046a.dtsi"
3789 +
3790 +/ {
3791 + model = "LS1046A RDB Board";
3792 + compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
3793 +
3794 + aliases {
3795 + serial0 = &duart0;
3796 + serial1 = &duart1;
3797 + serial2 = &duart2;
3798 + serial3 = &duart3;
3799 + };
3800 +
3801 + chosen {
3802 + stdout-path = "serial0:115200n8";
3803 + };
3804 +};
3805 +
3806 +&esdhc {
3807 + mmc-hs200-1_8v;
3808 + sd-uhs-sdr104;
3809 + sd-uhs-sdr50;
3810 + sd-uhs-sdr25;
3811 + sd-uhs-sdr12;
3812 +};
3813 +
3814 +&duart0 {
3815 + status = "okay";
3816 +};
3817 +
3818 +&duart1 {
3819 + status = "okay";
3820 +};
3821 +
3822 +&i2c0 {
3823 + status = "okay";
3824 +
3825 + ina220@40 {
3826 + compatible = "ti,ina220";
3827 + reg = <0x40>;
3828 + shunt-resistor = <1000>;
3829 + };
3830 +
3831 + temp-sensor@4c {
3832 + compatible = "adi,adt7461";
3833 + reg = <0x4c>;
3834 + };
3835 +
3836 + eeprom@56 {
3837 + compatible = "atmel,24c512";
3838 + reg = <0x52>;
3839 + };
3840 +
3841 + eeprom@57 {
3842 + compatible = "atmel,24c512";
3843 + reg = <0x53>;
3844 + };
3845 +};
3846 +
3847 +&i2c3 {
3848 + status = "okay";
3849 +
3850 + rtc@51 {
3851 + compatible = "nxp,pcf2129";
3852 + reg = <0x51>;
3853 + };
3854 +};
3855 +
3856 +&ifc {
3857 + #address-cells = <2>;
3858 + #size-cells = <1>;
3859 + /* NAND Flashe and CPLD on board */
3860 + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
3861 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3862 + status = "okay";
3863 +
3864 + nand@0,0 {
3865 + compatible = "fsl,ifc-nand";
3866 + #address-cells = <1>;
3867 + #size-cells = <1>;
3868 + reg = <0x0 0x0 0x10000>;
3869 + };
3870 +
3871 + cpld: board-control@2,0 {
3872 + compatible = "fsl,ls1046ardb-cpld";
3873 + reg = <0x2 0x0 0x0000100>;
3874 + };
3875 +};
3876 +
3877 +&qspi {
3878 + num-cs = <2>;
3879 + bus-num = <0>;
3880 + status = "okay";
3881 +
3882 + qflash0: s25fs512s@0 {
3883 + compatible = "spansion,m25p80";
3884 + #address-cells = <1>;
3885 + #size-cells = <1>;
3886 + spi-max-frequency = <20000000>;
3887 + reg = <0>;
3888 + };
3889 +
3890 + qflash1: s25fs512s@1 {
3891 + compatible = "spansion,m25p80";
3892 + #address-cells = <1>;
3893 + #size-cells = <1>;
3894 + spi-max-frequency = <20000000>;
3895 + reg = <1>;
3896 + };
3897 +};
3898 +
3899 +#include "fsl-ls1046-post.dtsi"
3900 +
3901 +&fman0 {
3902 + ethernet@e4000 {
3903 + phy-handle = <&rgmii_phy1>;
3904 + phy-connection-type = "rgmii";
3905 + };
3906 +
3907 + ethernet@e6000 {
3908 + phy-handle = <&rgmii_phy2>;
3909 + phy-connection-type = "rgmii";
3910 + };
3911 +
3912 + ethernet@e8000 {
3913 + phy-handle = <&sgmii_phy1>;
3914 + phy-connection-type = "sgmii";
3915 + };
3916 +
3917 + ethernet@ea000 {
3918 + phy-handle = <&sgmii_phy2>;
3919 + phy-connection-type = "sgmii";
3920 + };
3921 +
3922 + ethernet@f0000 { /* 10GEC1 */
3923 + phy-handle = <&aqr106_phy>;
3924 + phy-connection-type = "xgmii";
3925 + };
3926 +
3927 + ethernet@f2000 { /* 10GEC2 */
3928 + fixed-link = <0 1 1000 0 0>;
3929 + phy-connection-type = "xgmii";
3930 + };
3931 +
3932 + mdio@fc000 {
3933 + rgmii_phy1: ethernet-phy@1 {
3934 + reg = <0x1>;
3935 + };
3936 +
3937 + rgmii_phy2: ethernet-phy@2 {
3938 + reg = <0x2>;
3939 + };
3940 +
3941 + sgmii_phy1: ethernet-phy@3 {
3942 + reg = <0x3>;
3943 + };
3944 +
3945 + sgmii_phy2: ethernet-phy@4 {
3946 + reg = <0x4>;
3947 + };
3948 + };
3949 +
3950 + mdio@fd000 {
3951 + aqr106_phy: ethernet-phy@0 {
3952 + compatible = "ethernet-phy-ieee802.3-c45";
3953 + interrupts = <0 131 4>;
3954 + reg = <0x0>;
3955 + };
3956 + };
3957 +};
3958 --- /dev/null
3959 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
3960 @@ -0,0 +1,793 @@
3961 +/*
3962 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3963 + *
3964 + * Copyright 2016 Freescale Semiconductor, Inc.
3965 + *
3966 + * Mingkai Hu <mingkai.hu@nxp.com>
3967 + *
3968 + * This file is dual-licensed: you can use it either under the terms
3969 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3970 + * licensing only applies to this file, and not this project as a
3971 + * whole.
3972 + *
3973 + * a) This library is free software; you can redistribute it and/or
3974 + * modify it under the terms of the GNU General Public License as
3975 + * published by the Free Software Foundation; either version 2 of the
3976 + * License, or (at your option) any later version.
3977 + *
3978 + * This library is distributed in the hope that it will be useful,
3979 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3980 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3981 + * GNU General Public License for more details.
3982 + *
3983 + * Or, alternatively,
3984 + *
3985 + * b) Permission is hereby granted, free of charge, to any person
3986 + * obtaining a copy of this software and associated documentation
3987 + * files (the "Software"), to deal in the Software without
3988 + * restriction, including without limitation the rights to use,
3989 + * copy, modify, merge, publish, distribute, sublicense, and/or
3990 + * sell copies of the Software, and to permit persons to whom the
3991 + * Software is furnished to do so, subject to the following
3992 + * conditions:
3993 + *
3994 + * The above copyright notice and this permission notice shall be
3995 + * included in all copies or substantial portions of the Software.
3996 + *
3997 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3998 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3999 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4000 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4001 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4002 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4003 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4004 + * OTHER DEALINGS IN THE SOFTWARE.
4005 + */
4006 +
4007 +#include <dt-bindings/interrupt-controller/arm-gic.h>
4008 +#include <dt-bindings/thermal/thermal.h>
4009 +
4010 +/ {
4011 + compatible = "fsl,ls1046a";
4012 + interrupt-parent = <&gic>;
4013 + #address-cells = <2>;
4014 + #size-cells = <2>;
4015 +
4016 + aliases {
4017 + crypto = &crypto;
4018 + fman0 = &fman0;
4019 + ethernet0 = &enet0;
4020 + ethernet1 = &enet1;
4021 + ethernet2 = &enet2;
4022 + ethernet3 = &enet3;
4023 + ethernet4 = &enet4;
4024 + ethernet5 = &enet5;
4025 + ethernet6 = &enet6;
4026 + ethernet7 = &enet7;
4027 + };
4028 +
4029 + cpus {
4030 + #address-cells = <1>;
4031 + #size-cells = <0>;
4032 +
4033 + cpu0: cpu@0 {
4034 + device_type = "cpu";
4035 + compatible = "arm,cortex-a72";
4036 + reg = <0x0>;
4037 + clocks = <&clockgen 1 0>;
4038 + next-level-cache = <&l2>;
4039 + cpu-idle-states = <&CPU_PH20>;
4040 + #cooling-cells = <2>;
4041 + };
4042 +
4043 + cpu1: cpu@1 {
4044 + device_type = "cpu";
4045 + compatible = "arm,cortex-a72";
4046 + reg = <0x1>;
4047 + clocks = <&clockgen 1 0>;
4048 + next-level-cache = <&l2>;
4049 + cpu-idle-states = <&CPU_PH20>;
4050 + };
4051 +
4052 + cpu2: cpu@2 {
4053 + device_type = "cpu";
4054 + compatible = "arm,cortex-a72";
4055 + reg = <0x2>;
4056 + clocks = <&clockgen 1 0>;
4057 + next-level-cache = <&l2>;
4058 + cpu-idle-states = <&CPU_PH20>;
4059 + };
4060 +
4061 + cpu3: cpu@3 {
4062 + device_type = "cpu";
4063 + compatible = "arm,cortex-a72";
4064 + reg = <0x3>;
4065 + clocks = <&clockgen 1 0>;
4066 + next-level-cache = <&l2>;
4067 + cpu-idle-states = <&CPU_PH20>;
4068 + };
4069 +
4070 + l2: l2-cache {
4071 + compatible = "cache";
4072 + };
4073 + };
4074 +
4075 + idle-states {
4076 + /*
4077 + * PSCI node is not added default, U-boot will add missing
4078 + * parts if it determines to use PSCI.
4079 + */
4080 + entry-method = "arm,psci";
4081 +
4082 + CPU_PH20: cpu-ph20 {
4083 + compatible = "arm,idle-state";
4084 + idle-state-name = "PH20";
4085 + arm,psci-suspend-param = <0x0>;
4086 + entry-latency-us = <1000>;
4087 + exit-latency-us = <1000>;
4088 + min-residency-us = <3000>;
4089 + };
4090 + };
4091 +
4092 + memory@80000000 {
4093 + device_type = "memory";
4094 + };
4095 +
4096 + sysclk: sysclk {
4097 + compatible = "fixed-clock";
4098 + #clock-cells = <0>;
4099 + clock-frequency = <100000000>;
4100 + clock-output-names = "sysclk";
4101 + };
4102 +
4103 + reboot {
4104 + compatible ="syscon-reboot";
4105 + regmap = <&dcfg>;
4106 + offset = <0xb0>;
4107 + mask = <0x02>;
4108 + };
4109 +
4110 + timer {
4111 + compatible = "arm,armv8-timer";
4112 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
4113 + IRQ_TYPE_LEVEL_LOW)>,
4114 + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
4115 + IRQ_TYPE_LEVEL_LOW)>,
4116 + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
4117 + IRQ_TYPE_LEVEL_LOW)>,
4118 + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
4119 + IRQ_TYPE_LEVEL_LOW)>;
4120 + };
4121 +
4122 + pmu {
4123 + compatible = "arm,cortex-a72-pmu";
4124 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4125 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4126 + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
4127 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
4128 + interrupt-affinity = <&cpu0>,
4129 + <&cpu1>,
4130 + <&cpu2>,
4131 + <&cpu3>;
4132 + };
4133 +
4134 + gic: interrupt-controller@1400000 {
4135 + compatible = "arm,gic-400";
4136 + #interrupt-cells = <3>;
4137 + interrupt-controller;
4138 + reg = <0x0 0x1410000 0 0x10000>, /* GICD */
4139 + <0x0 0x1420000 0 0x20000>, /* GICC */
4140 + <0x0 0x1440000 0 0x20000>, /* GICH */
4141 + <0x0 0x1460000 0 0x20000>; /* GICV */
4142 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
4143 + IRQ_TYPE_LEVEL_LOW)>;
4144 + };
4145 +
4146 + soc: soc {
4147 + compatible = "simple-bus";
4148 + #address-cells = <2>;
4149 + #size-cells = <2>;
4150 + ranges;
4151 +
4152 + ddr: memory-controller@1080000 {
4153 + compatible = "fsl,qoriq-memory-controller";
4154 + reg = <0x0 0x1080000 0x0 0x1000>;
4155 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
4156 + big-endian;
4157 + };
4158 +
4159 + ifc: ifc@1530000 {
4160 + compatible = "fsl,ifc", "simple-bus";
4161 + reg = <0x0 0x1530000 0x0 0x10000>;
4162 + big-endian;
4163 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
4164 + };
4165 +
4166 + qspi: quadspi@1550000 {
4167 + compatible = "fsl,ls1021a-qspi";
4168 + #address-cells = <1>;
4169 + #size-cells = <0>;
4170 + reg = <0x0 0x1550000 0x0 0x10000>,
4171 + <0x0 0x40000000 0x0 0x10000000>;
4172 + reg-names = "QuadSPI", "QuadSPI-memory";
4173 + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
4174 + clock-names = "qspi_en", "qspi";
4175 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
4176 + big-endian;
4177 + fsl,qspi-has-second-chip;
4178 + status = "disabled";
4179 + };
4180 +
4181 + esdhc: esdhc@1560000 {
4182 + compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
4183 + reg = <0x0 0x1560000 0x0 0x10000>;
4184 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
4185 + clocks = <&clockgen 2 1>;
4186 + voltage-ranges = <1800 1800 3300 3300>;
4187 + sdhci,auto-cmd12;
4188 + big-endian;
4189 + bus-width = <4>;
4190 + };
4191 +
4192 + scfg: scfg@1570000 {
4193 + compatible = "fsl,ls1046a-scfg", "syscon";
4194 + reg = <0x0 0x1570000 0x0 0x10000>;
4195 + big-endian;
4196 + };
4197 +
4198 + crypto: crypto@1700000 {
4199 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
4200 + "fsl,sec-v4.0";
4201 + fsl,sec-era = <8>;
4202 + #address-cells = <1>;
4203 + #size-cells = <1>;
4204 + ranges = <0x0 0x00 0x1700000 0x100000>;
4205 + reg = <0x00 0x1700000 0x0 0x100000>;
4206 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4207 +
4208 + sec_jr0: jr@10000 {
4209 + compatible = "fsl,sec-v5.4-job-ring",
4210 + "fsl,sec-v5.0-job-ring",
4211 + "fsl,sec-v4.0-job-ring";
4212 + reg = <0x10000 0x10000>;
4213 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
4214 + };
4215 +
4216 + sec_jr1: jr@20000 {
4217 + compatible = "fsl,sec-v5.4-job-ring",
4218 + "fsl,sec-v5.0-job-ring",
4219 + "fsl,sec-v4.0-job-ring";
4220 + reg = <0x20000 0x10000>;
4221 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4222 + };
4223 +
4224 + sec_jr2: jr@30000 {
4225 + compatible = "fsl,sec-v5.4-job-ring",
4226 + "fsl,sec-v5.0-job-ring",
4227 + "fsl,sec-v4.0-job-ring";
4228 + reg = <0x30000 0x10000>;
4229 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
4230 + };
4231 +
4232 + sec_jr3: jr@40000 {
4233 + compatible = "fsl,sec-v5.4-job-ring",
4234 + "fsl,sec-v5.0-job-ring",
4235 + "fsl,sec-v4.0-job-ring";
4236 + reg = <0x40000 0x10000>;
4237 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
4238 + };
4239 + };
4240 +
4241 + qman: qman@1880000 {
4242 + compatible = "fsl,qman";
4243 + reg = <0x00 0x1880000 0x0 0x10000>;
4244 + interrupts = <0 45 0x4>;
4245 + memory-region = <&qman_fqd &qman_pfdr>;
4246 +
4247 + };
4248 +
4249 + bman: bman@1890000 {
4250 + compatible = "fsl,bman";
4251 + reg = <0x00 0x1890000 0x0 0x10000>;
4252 + interrupts = <0 45 0x4>;
4253 + memory-region = <&bman_fbpr>;
4254 +
4255 + };
4256 +
4257 + qportals: qman-portals@500000000 {
4258 + ranges = <0x0 0x5 0x00000000 0x8000000>;
4259 + };
4260 +
4261 + bportals: bman-portals@508000000 {
4262 + ranges = <0x0 0x5 0x08000000 0x8000000>;
4263 + };
4264 +
4265 + dcfg: dcfg@1ee0000 {
4266 + compatible = "fsl,ls1046a-dcfg", "syscon";
4267 + reg = <0x0 0x1ee0000 0x0 0x1000>;
4268 + big-endian;
4269 + };
4270 +
4271 + clockgen: clocking@1ee1000 {
4272 + compatible = "fsl,ls1046a-clockgen";
4273 + reg = <0x0 0x1ee1000 0x0 0x1000>;
4274 + #clock-cells = <2>;
4275 + clocks = <&sysclk>;
4276 + };
4277 +
4278 + tmu: tmu@1f00000 {
4279 + compatible = "fsl,qoriq-tmu";
4280 + reg = <0x0 0x1f00000 0x0 0x10000>;
4281 + interrupts = <0 33 0x4>;
4282 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
4283 + fsl,tmu-calibration =
4284 + /* Calibration data group 1 */
4285 + <0x00000000 0x00000026
4286 + 0x00000001 0x0000002d
4287 + 0x00000002 0x00000032
4288 + 0x00000003 0x00000039
4289 + 0x00000004 0x0000003f
4290 + 0x00000005 0x00000046
4291 + 0x00000006 0x0000004d
4292 + 0x00000007 0x00000054
4293 + 0x00000008 0x0000005a
4294 + 0x00000009 0x00000061
4295 + 0x0000000a 0x0000006a
4296 + 0x0000000b 0x00000071
4297 + /* Calibration data group 2 */
4298 + 0x00010000 0x00000025
4299 + 0x00010001 0x0000002c
4300 + 0x00010002 0x00000035
4301 + 0x00010003 0x0000003d
4302 + 0x00010004 0x00000045
4303 + 0x00010005 0x0000004e
4304 + 0x00010006 0x00000057
4305 + 0x00010007 0x00000061
4306 + 0x00010008 0x0000006b
4307 + 0x00010009 0x00000076
4308 + /* Calibration data group 3 */
4309 + 0x00020000 0x00000029
4310 + 0x00020001 0x00000033
4311 + 0x00020002 0x0000003d
4312 + 0x00020003 0x00000049
4313 + 0x00020004 0x00000056
4314 + 0x00020005 0x00000061
4315 + 0x00020006 0x0000006d
4316 + /* Calibration data group 4 */
4317 + 0x00030000 0x00000021
4318 + 0x00030001 0x0000002a
4319 + 0x00030002 0x0000003c
4320 + 0x00030003 0x0000004e>;
4321 + big-endian;
4322 + #thermal-sensor-cells = <1>;
4323 + };
4324 +
4325 + thermal-zones {
4326 + cpu_thermal: cpu-thermal {
4327 + polling-delay-passive = <1000>;
4328 + polling-delay = <5000>;
4329 + thermal-sensors = <&tmu 3>;
4330 +
4331 + trips {
4332 + cpu_alert: cpu-alert {
4333 + temperature = <85000>;
4334 + hysteresis = <2000>;
4335 + type = "passive";
4336 + };
4337 +
4338 + cpu_crit: cpu-crit {
4339 + temperature = <95000>;
4340 + hysteresis = <2000>;
4341 + type = "critical";
4342 + };
4343 + };
4344 +
4345 + cooling-maps {
4346 + map0 {
4347 + trip = <&cpu_alert>;
4348 + cooling-device =
4349 + <&cpu0 THERMAL_NO_LIMIT
4350 + THERMAL_NO_LIMIT>;
4351 + };
4352 + };
4353 + };
4354 + };
4355 +
4356 + dspi: dspi@2100000 {
4357 + compatible = "fsl,ls1021a-v1.0-dspi";
4358 + #address-cells = <1>;
4359 + #size-cells = <0>;
4360 + reg = <0x0 0x2100000 0x0 0x10000>;
4361 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
4362 + clock-names = "dspi";
4363 + clocks = <&clockgen 4 1>;
4364 + spi-num-chipselects = <5>;
4365 + big-endian;
4366 + status = "disabled";
4367 + };
4368 +
4369 + i2c0: i2c@2180000 {
4370 + compatible = "fsl,vf610-i2c";
4371 + #address-cells = <1>;
4372 + #size-cells = <0>;
4373 + reg = <0x0 0x2180000 0x0 0x10000>;
4374 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
4375 + clocks = <&clockgen 4 1>;
4376 + dmas = <&edma0 1 39>,
4377 + <&edma0 1 38>;
4378 + dma-names = "tx", "rx";
4379 + status = "disabled";
4380 + };
4381 +
4382 + i2c1: i2c@2190000 {
4383 + compatible = "fsl,vf610-i2c";
4384 + #address-cells = <1>;
4385 + #size-cells = <0>;
4386 + reg = <0x0 0x2190000 0x0 0x10000>;
4387 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
4388 + clocks = <&clockgen 4 1>;
4389 + status = "disabled";
4390 + };
4391 +
4392 + i2c2: i2c@21a0000 {
4393 + compatible = "fsl,vf610-i2c";
4394 + #address-cells = <1>;
4395 + #size-cells = <0>;
4396 + reg = <0x0 0x21a0000 0x0 0x10000>;
4397 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
4398 + clocks = <&clockgen 4 1>;
4399 + status = "disabled";
4400 + };
4401 +
4402 + i2c3: i2c@21b0000 {
4403 + compatible = "fsl,vf610-i2c";
4404 + #address-cells = <1>;
4405 + #size-cells = <0>;
4406 + reg = <0x0 0x21b0000 0x0 0x10000>;
4407 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
4408 + clocks = <&clockgen 4 1>;
4409 + status = "disabled";
4410 + };
4411 +
4412 + duart0: serial@21c0500 {
4413 + compatible = "fsl,ns16550", "ns16550a";
4414 + reg = <0x00 0x21c0500 0x0 0x100>;
4415 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4416 + clocks = <&clockgen 4 1>;
4417 + };
4418 +
4419 + duart1: serial@21c0600 {
4420 + compatible = "fsl,ns16550", "ns16550a";
4421 + reg = <0x00 0x21c0600 0x0 0x100>;
4422 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4423 + clocks = <&clockgen 4 1>;
4424 + };
4425 +
4426 + duart2: serial@21d0500 {
4427 + compatible = "fsl,ns16550", "ns16550a";
4428 + reg = <0x0 0x21d0500 0x0 0x100>;
4429 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4430 + clocks = <&clockgen 4 1>;
4431 + };
4432 +
4433 + duart3: serial@21d0600 {
4434 + compatible = "fsl,ns16550", "ns16550a";
4435 + reg = <0x0 0x21d0600 0x0 0x100>;
4436 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4437 + clocks = <&clockgen 4 1>;
4438 + };
4439 +
4440 + gpio0: gpio@2300000 {
4441 + compatible = "fsl,qoriq-gpio";
4442 + reg = <0x0 0x2300000 0x0 0x10000>;
4443 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
4444 + gpio-controller;
4445 + #gpio-cells = <2>;
4446 + interrupt-controller;
4447 + #interrupt-cells = <2>;
4448 + };
4449 +
4450 + gpio1: gpio@2310000 {
4451 + compatible = "fsl,qoriq-gpio";
4452 + reg = <0x0 0x2310000 0x0 0x10000>;
4453 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
4454 + gpio-controller;
4455 + #gpio-cells = <2>;
4456 + interrupt-controller;
4457 + #interrupt-cells = <2>;
4458 + };
4459 +
4460 + gpio2: gpio@2320000 {
4461 + compatible = "fsl,qoriq-gpio";
4462 + reg = <0x0 0x2320000 0x0 0x10000>;
4463 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
4464 + gpio-controller;
4465 + #gpio-cells = <2>;
4466 + interrupt-controller;
4467 + #interrupt-cells = <2>;
4468 + };
4469 +
4470 + gpio3: gpio@2330000 {
4471 + compatible = "fsl,qoriq-gpio";
4472 + reg = <0x0 0x2330000 0x0 0x10000>;
4473 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
4474 + gpio-controller;
4475 + #gpio-cells = <2>;
4476 + interrupt-controller;
4477 + #interrupt-cells = <2>;
4478 + };
4479 +
4480 + lpuart0: serial@2950000 {
4481 + compatible = "fsl,ls1021a-lpuart";
4482 + reg = <0x0 0x2950000 0x0 0x1000>;
4483 + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
4484 + clocks = <&clockgen 4 0>;
4485 + clock-names = "ipg";
4486 + status = "disabled";
4487 + };
4488 +
4489 + lpuart1: serial@2960000 {
4490 + compatible = "fsl,ls1021a-lpuart";
4491 + reg = <0x0 0x2960000 0x0 0x1000>;
4492 + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4493 + clocks = <&clockgen 4 1>;
4494 + clock-names = "ipg";
4495 + status = "disabled";
4496 + };
4497 +
4498 + lpuart2: serial@2970000 {
4499 + compatible = "fsl,ls1021a-lpuart";
4500 + reg = <0x0 0x2970000 0x0 0x1000>;
4501 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
4502 + clocks = <&clockgen 4 1>;
4503 + clock-names = "ipg";
4504 + status = "disabled";
4505 + };
4506 +
4507 + lpuart3: serial@2980000 {
4508 + compatible = "fsl,ls1021a-lpuart";
4509 + reg = <0x0 0x2980000 0x0 0x1000>;
4510 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4511 + clocks = <&clockgen 4 1>;
4512 + clock-names = "ipg";
4513 + status = "disabled";
4514 + };
4515 +
4516 + lpuart4: serial@2990000 {
4517 + compatible = "fsl,ls1021a-lpuart";
4518 + reg = <0x0 0x2990000 0x0 0x1000>;
4519 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
4520 + clocks = <&clockgen 4 1>;
4521 + clock-names = "ipg";
4522 + status = "disabled";
4523 + };
4524 +
4525 + lpuart5: serial@29a0000 {
4526 + compatible = "fsl,ls1021a-lpuart";
4527 + reg = <0x0 0x29a0000 0x0 0x1000>;
4528 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4529 + clocks = <&clockgen 4 1>;
4530 + clock-names = "ipg";
4531 + status = "disabled";
4532 + };
4533 +
4534 + ftm0: ftm0@29d0000 {
4535 + compatible = "fsl,ls1046a-ftm";
4536 + reg = <0x0 0x29d0000 0x0 0x10000>,
4537 + <0x0 0x1ee2140 0x0 0x4>;
4538 + reg-names = "ftm", "FlexTimer1";
4539 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
4540 + big-endian;
4541 + };
4542 +
4543 + wdog0: watchdog@2ad0000 {
4544 + compatible = "fsl,imx21-wdt";
4545 + reg = <0x0 0x2ad0000 0x0 0x10000>;
4546 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4547 + clocks = <&clockgen 4 1>;
4548 + big-endian;
4549 + };
4550 +
4551 + edma0: edma@2c00000 {
4552 + #dma-cells = <2>;
4553 + compatible = "fsl,vf610-edma";
4554 + reg = <0x0 0x2c00000 0x0 0x10000>,
4555 + <0x0 0x2c10000 0x0 0x10000>,
4556 + <0x0 0x2c20000 0x0 0x10000>;
4557 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4558 + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
4559 + interrupt-names = "edma-tx", "edma-err";
4560 + dma-channels = <32>;
4561 + big-endian;
4562 + clock-names = "dmamux0", "dmamux1";
4563 + clocks = <&clockgen 4 1>,
4564 + <&clockgen 4 1>;
4565 + };
4566 +
4567 + usb0: usb@2f00000 {
4568 + compatible = "snps,dwc3";
4569 + reg = <0x0 0x2f00000 0x0 0x10000>;
4570 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
4571 + dr_mode = "host";
4572 + snps,quirk-frame-length-adjustment = <0x20>;
4573 + snps,dis_rxdet_inp3_quirk;
4574 + };
4575 +
4576 + usb1: usb@3000000 {
4577 + compatible = "snps,dwc3";
4578 + reg = <0x0 0x3000000 0x0 0x10000>;
4579 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
4580 + dr_mode = "host";
4581 + snps,quirk-frame-length-adjustment = <0x20>;
4582 + snps,dis_rxdet_inp3_quirk;
4583 + };
4584 +
4585 + usb2: usb@3100000 {
4586 + compatible = "snps,dwc3";
4587 + reg = <0x0 0x3100000 0x0 0x10000>;
4588 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
4589 + dr_mode = "host";
4590 + snps,quirk-frame-length-adjustment = <0x20>;
4591 + snps,dis_rxdet_inp3_quirk;
4592 + };
4593 +
4594 + sata: sata@3200000 {
4595 + compatible = "fsl,ls1046a-ahci";
4596 + reg = <0x0 0x3200000 0x0 0x10000>,
4597 + <0x0 0x20140520 0x0 0x4>;
4598 + reg-names = "ahci", "sata-ecc";
4599 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
4600 + clocks = <&clockgen 4 1>;
4601 + dma-coherent;
4602 + };
4603 +
4604 + qdma: qdma@8380000 {
4605 + compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
4606 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
4607 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
4608 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
4609 + interrupts = <0 153 0x4>,
4610 + <0 39 0x4>;
4611 + interrupt-names = "qdma-error", "qdma-queue";
4612 + channels = <8>;
4613 + queues = <2>;
4614 + status-sizes = <64>;
4615 + queue-sizes = <64 64>;
4616 + big-endian;
4617 + };
4618 +
4619 + msi1: msi-controller@1580000 {
4620 + compatible = "fsl,ls1046a-msi";
4621 + msi-controller;
4622 + reg = <0x0 0x1580000 0x0 0x10000>;
4623 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4624 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4625 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4626 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
4627 + };
4628 +
4629 + msi2: msi-controller@1590000 {
4630 + compatible = "fsl,ls1046a-msi";
4631 + msi-controller;
4632 + reg = <0x0 0x1590000 0x0 0x10000>;
4633 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
4634 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
4635 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
4636 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
4637 + };
4638 +
4639 + msi3: msi-controller@15a0000 {
4640 + compatible = "fsl,ls1046a-msi";
4641 + msi-controller;
4642 + reg = <0x0 0x15a0000 0x0 0x10000>;
4643 + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4644 + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
4645 + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
4646 + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
4647 + };
4648 +
4649 + pcie@3400000 {
4650 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4651 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
4652 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
4653 + reg-names = "regs", "config";
4654 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
4655 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
4656 + interrupt-names = "pme", "aer";
4657 + #address-cells = <3>;
4658 + #size-cells = <2>;
4659 + device_type = "pci";
4660 + dma-coherent;
4661 + num-lanes = <4>;
4662 + bus-range = <0x0 0xff>;
4663 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
4664 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4665 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4666 + #interrupt-cells = <1>;
4667 + interrupt-map-mask = <0 0 0 7>;
4668 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4669 + <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4670 + <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4671 + <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
4672 + };
4673 +
4674 + pcie@3500000 {
4675 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4676 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
4677 + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
4678 + reg-names = "regs", "config";
4679 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
4680 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
4681 + interrupt-names = "pme", "aer";
4682 + #address-cells = <3>;
4683 + #size-cells = <2>;
4684 + device_type = "pci";
4685 + dma-coherent;
4686 + num-lanes = <2>;
4687 + bus-range = <0x0 0xff>;
4688 + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
4689 + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4690 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4691 + #interrupt-cells = <1>;
4692 + interrupt-map-mask = <0 0 0 7>;
4693 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4694 + <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4695 + <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4696 + <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
4697 + };
4698 +
4699 + pcie@3600000 {
4700 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4701 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
4702 + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
4703 + reg-names = "regs", "config";
4704 + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
4705 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
4706 + interrupt-names = "pme", "aer";
4707 + #address-cells = <3>;
4708 + #size-cells = <2>;
4709 + device_type = "pci";
4710 + dma-coherent;
4711 + num-lanes = <2>;
4712 + bus-range = <0x0 0xff>;
4713 + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
4714 + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4715 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4716 + #interrupt-cells = <1>;
4717 + interrupt-map-mask = <0 0 0 7>;
4718 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4719 + <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4720 + <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4721 + <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
4722 + };
4723 +
4724 + };
4725 +
4726 + reserved-memory {
4727 + #address-cells = <2>;
4728 + #size-cells = <2>;
4729 + ranges;
4730 +
4731 + bman_fbpr: bman-fbpr {
4732 + compatible = "shared-dma-pool";
4733 + size = <0 0x1000000>;
4734 + alignment = <0 0x1000000>;
4735 + no-map;
4736 + };
4737 + qman_fqd: qman-fqd {
4738 + compatible = "shared-dma-pool";
4739 + size = <0 0x800000>;
4740 + alignment = <0 0x800000>;
4741 + no-map;
4742 + };
4743 + qman_pfdr: qman-pfdr {
4744 + compatible = "shared-dma-pool";
4745 + size = <0 0x2000000>;
4746 + alignment = <0 0x2000000>;
4747 + no-map;
4748 + };
4749 + };
4750 +};
4751 +
4752 +#include "qoriq-qman1-portals.dtsi"
4753 +#include "qoriq-bman1-portals.dtsi"
4754 --- /dev/null
4755 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
4756 @@ -0,0 +1,173 @@
4757 +/*
4758 + * Device Tree file for NXP LS1088A QDS Board.
4759 + *
4760 + * Copyright 2017 NXP
4761 + *
4762 + * Harninder Rai <harninder.rai@nxp.com>
4763 + *
4764 + * This file is dual-licensed: you can use it either under the terms
4765 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4766 + * licensing only applies to this file, and not this project as a
4767 + * whole.
4768 + *
4769 + * a) This library is free software; you can redistribute it and/or
4770 + * modify it under the terms of the GNU General Public License as
4771 + * published by the Free Software Foundation; either version 2 of the
4772 + * License, or (at your option) any later version.
4773 + *
4774 + * This library is distributed in the hope that it will be useful,
4775 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4776 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4777 + * GNU General Public License for more details.
4778 + *
4779 + * Or, alternatively,
4780 + *
4781 + * b) Permission is hereby granted, free of charge, to any person
4782 + * obtaining a copy of this software and associated documentation
4783 + * files (the "Software"), to deal in the Software without
4784 + * restriction, including without limitation the rights to use,
4785 + * copy, modify, merge, publish, distribute, sublicense, and/or
4786 + * sell copies of the Software, and to permit persons to whom the
4787 + * Software is furnished to do so, subject to the following
4788 + * conditions:
4789 + *
4790 + * The above copyright notice and this permission notice shall be
4791 + * included in all copies or substantial portions of the Software.
4792 + *
4793 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4794 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4795 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4796 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4797 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4798 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4799 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4800 + * OTHER DEALINGS IN THE SOFTWARE.
4801 + */
4802 +
4803 +/dts-v1/;
4804 +
4805 +#include "fsl-ls1088a.dtsi"
4806 +
4807 +/ {
4808 + model = "LS1088A QDS Board";
4809 + compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
4810 +};
4811 +
4812 +&i2c0 {
4813 + status = "okay";
4814 +
4815 + i2c-switch@77 {
4816 + compatible = "nxp,pca9547";
4817 + reg = <0x77>;
4818 + #address-cells = <1>;
4819 + #size-cells = <0>;
4820 +
4821 + i2c@2 {
4822 + #address-cells = <1>;
4823 + #size-cells = <0>;
4824 + reg = <0x2>;
4825 +
4826 + ina220@40 {
4827 + compatible = "ti,ina220";
4828 + reg = <0x40>;
4829 + shunt-resistor = <1000>;
4830 + };
4831 +
4832 + ina220@41 {
4833 + compatible = "ti,ina220";
4834 + reg = <0x41>;
4835 + shunt-resistor = <1000>;
4836 + };
4837 + };
4838 +
4839 + i2c@3 {
4840 + #address-cells = <1>;
4841 + #size-cells = <0>;
4842 + reg = <0x3>;
4843 +
4844 + temp-sensor@4c {
4845 + compatible = "adi,adt7461a";
4846 + reg = <0x4c>;
4847 + };
4848 +
4849 + rtc@51 {
4850 + compatible = "nxp,pcf2129";
4851 + reg = <0x51>;
4852 + /* IRQ10_B */
4853 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
4854 + };
4855 +
4856 + eeprom@56 {
4857 + compatible = "atmel,24c512";
4858 + reg = <0x56>;
4859 + };
4860 +
4861 + eeprom@57 {
4862 + compatible = "atmel,24c512";
4863 + reg = <0x57>;
4864 + };
4865 + };
4866 + };
4867 +};
4868 +
4869 +&qspi {
4870 + status = "okay";
4871 + qflash0: s25fs512s@0 {
4872 + compatible = "spansion,m25p80";
4873 + #address-cells = <1>;
4874 + #size-cells = <1>;
4875 + spi-max-frequency = <20000000>;
4876 + m25p,fast-read;
4877 + reg = <0>;
4878 + };
4879 +
4880 + qflash1: s25fs512s@1 {
4881 + compatible = "spansion,m25p80";
4882 + #address-cells = <1>;
4883 + #size-cells = <1>;
4884 + spi-max-frequency = <20000000>;
4885 + m25p,fast-read;
4886 + reg = <1>;
4887 + };
4888 +};
4889 +
4890 +&ifc {
4891 + status = "okay";
4892 +
4893 + ranges = <0 0 0x5 0x80000000 0x08000000
4894 + 2 0 0x5 0x30000000 0x00010000
4895 + 3 0 0x5 0x20000000 0x00010000>;
4896 +
4897 + nor@0,0 {
4898 + compatible = "cfi-flash";
4899 + reg = <0x0 0x0 0x8000000>;
4900 + bank-width = <2>;
4901 + device-width = <1>;
4902 + };
4903 +
4904 + nand@2,0 {
4905 + compatible = "fsl,ifc-nand";
4906 + reg = <0x2 0x0 0x10000>;
4907 + };
4908 +
4909 + fpga: board-control@3,0 {
4910 + compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
4911 + reg = <0x3 0x0 0x0000100>;
4912 + };
4913 +};
4914 +
4915 +&duart0 {
4916 + status = "okay";
4917 +};
4918 +
4919 +&duart1 {
4920 + status = "okay";
4921 +};
4922 +
4923 +&esdhc {
4924 + status = "okay";
4925 +};
4926 +
4927 +&sata {
4928 + status = "okay";
4929 +};
4930 --- /dev/null
4931 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
4932 @@ -0,0 +1,236 @@
4933 +/*
4934 + * Device Tree file for NXP LS1088A RDB Board.
4935 + *
4936 + * Copyright 2017 NXP
4937 + *
4938 + * Harninder Rai <harninder.rai@nxp.com>
4939 + *
4940 + * This file is dual-licensed: you can use it either under the terms
4941 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4942 + * licensing only applies to this file, and not this project as a
4943 + * whole.
4944 + *
4945 + * a) This library is free software; you can redistribute it and/or
4946 + * modify it under the terms of the GNU General Public License as
4947 + * published by the Free Software Foundation; either version 2 of the
4948 + * License, or (at your option) any later version.
4949 + *
4950 + * This library is distributed in the hope that it will be useful,
4951 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4952 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4953 + * GNU General Public License for more details.
4954 + *
4955 + * Or, alternatively,
4956 + *
4957 + * b) Permission is hereby granted, free of charge, to any person
4958 + * obtaining a copy of this software and associated documentation
4959 + * files (the "Software"), to deal in the Software without
4960 + * restriction, including without limitation the rights to use,
4961 + * copy, modify, merge, publish, distribute, sublicense, and/or
4962 + * sell copies of the Software, and to permit persons to whom the
4963 + * Software is furnished to do so, subject to the following
4964 + * conditions:
4965 + *
4966 + * The above copyright notice and this permission notice shall be
4967 + * included in all copies or substantial portions of the Software.
4968 + *
4969 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4970 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4971 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4972 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4973 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4974 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4975 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4976 + * OTHER DEALINGS IN THE SOFTWARE.
4977 + */
4978 +
4979 +/dts-v1/;
4980 +
4981 +#include "fsl-ls1088a.dtsi"
4982 +
4983 +/ {
4984 + model = "L1088A RDB Board";
4985 + compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
4986 +};
4987 +
4988 +&i2c0 {
4989 + status = "okay";
4990 +
4991 + i2c-switch@77 {
4992 + compatible = "nxp,pca9547";
4993 + reg = <0x77>;
4994 + #address-cells = <1>;
4995 + #size-cells = <0>;
4996 +
4997 + i2c@2 {
4998 + #address-cells = <1>;
4999 + #size-cells = <0>;
5000 + reg = <0x2>;
5001 +
5002 + ina220@40 {
5003 + compatible = "ti,ina220";
5004 + reg = <0x40>;
5005 + shunt-resistor = <1000>;
5006 + };
5007 + };
5008 +
5009 + i2c@3 {
5010 + #address-cells = <1>;
5011 + #size-cells = <0>;
5012 + reg = <0x3>;
5013 +
5014 + temp-sensor@4c {
5015 + compatible = "adi,adt7461a";
5016 + reg = <0x4c>;
5017 + };
5018 +
5019 + rtc@51 {
5020 + compatible = "nxp,pcf2129";
5021 + reg = <0x51>;
5022 + /* IRQ10_B */
5023 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
5024 + };
5025 + };
5026 + };
5027 +};
5028 +
5029 +&qspi {
5030 + status = "okay";
5031 + qflash0: s25fs512s@0 {
5032 + compatible = "spansion,m25p80";
5033 + #address-cells = <1>;
5034 + #size-cells = <1>;
5035 + m25p,fast-read;
5036 + spi-max-frequency = <20000000>;
5037 + reg = <0>;
5038 + };
5039 +
5040 + qflash1: s25fs512s@1 {
5041 + compatible = "spansion,m25p80";
5042 + #address-cells = <1>;
5043 + #size-cells = <1>;
5044 + m25p,fast-read;
5045 + spi-max-frequency = <20000000>;
5046 + reg = <1>;
5047 + };
5048 +};
5049 +
5050 +&ifc {
5051 + status = "okay";
5052 +
5053 + ranges = <0 0 0x5 0x30000000 0x00010000
5054 + 2 0 0x5 0x20000000 0x00010000>;
5055 +
5056 + nand@0,0 {
5057 + compatible = "fsl,ifc-nand";
5058 + reg = <0x0 0x0 0x10000>;
5059 + };
5060 +
5061 + fpga: board-control@2,0 {
5062 + compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
5063 + reg = <0x2 0x0 0x0000100>;
5064 + };
5065 +};
5066 +
5067 +&duart0 {
5068 + status = "okay";
5069 +};
5070 +
5071 +&duart1 {
5072 + status = "okay";
5073 +};
5074 +
5075 +&usb0 {
5076 + status = "okay";
5077 +};
5078 +
5079 +&usb1 {
5080 + status = "okay";
5081 +};
5082 +
5083 +&esdhc {
5084 + status = "okay";
5085 +};
5086 +
5087 +&sata {
5088 + status = "okay";
5089 +};
5090 +
5091 +&emdio1 {
5092 + /* Freescale F104 PHY1 */
5093 + mdio1_phy1: emdio1_phy@1 {
5094 + reg = <0x1c>;
5095 + phy-connection-type = "qsgmii";
5096 + };
5097 + mdio1_phy2: emdio1_phy@2 {
5098 + reg = <0x1d>;
5099 + phy-connection-type = "qsgmii";
5100 + };
5101 + mdio1_phy3: emdio1_phy@3 {
5102 + reg = <0x1e>;
5103 + phy-connection-type = "qsgmii";
5104 + };
5105 + mdio1_phy4: emdio1_phy@4 {
5106 + reg = <0x1f>;
5107 + phy-connection-type = "qsgmii";
5108 + };
5109 + /* F104 PHY2 */
5110 + mdio1_phy5: emdio1_phy@5 {
5111 + reg = <0x0c>;
5112 + phy-connection-type = "qsgmii";
5113 + };
5114 + mdio1_phy6: emdio1_phy@6 {
5115 + reg = <0x0d>;
5116 + phy-connection-type = "qsgmii";
5117 + };
5118 + mdio1_phy7: emdio1_phy@7 {
5119 + reg = <0x0e>;
5120 + phy-connection-type = "qsgmii";
5121 + };
5122 + mdio1_phy8: emdio1_phy@8 {
5123 + reg = <0x0f>;
5124 + phy-connection-type = "qsgmii";
5125 + };
5126 +};
5127 +
5128 +&emdio2 {
5129 + /* Aquantia AQR105 10G PHY */
5130 + mdio2_phy1: emdio2_phy@1 {
5131 + compatible = "ethernet-phy-ieee802.3-c45";
5132 + interrupts = <0 2 0x4>;
5133 + reg = <0x0>;
5134 + phy-connection-type = "xfi";
5135 + };
5136 +};
5137 +
5138 +/* DPMAC connections to external PHYs
5139 + * based on LS1088A RM RevC - $24.1.2 SerDes Options
5140 + */
5141 +/* DPMAC1 is 10G SFP+, fixed link */
5142 +&dpmac2 {
5143 + phy-handle = <&mdio2_phy1>;
5144 +};
5145 +&dpmac3 {
5146 + phy-handle = <&mdio1_phy5>;
5147 +};
5148 +&dpmac4 {
5149 + phy-handle = <&mdio1_phy6>;
5150 +};
5151 +&dpmac5 {
5152 + phy-handle = <&mdio1_phy7>;
5153 +};
5154 +&dpmac6 {
5155 + phy-handle = <&mdio1_phy8>;
5156 +};
5157 +&dpmac7 {
5158 + phy-handle = <&mdio1_phy1>;
5159 +};
5160 +&dpmac8 {
5161 + phy-handle = <&mdio1_phy2>;
5162 +};
5163 +&dpmac9 {
5164 + phy-handle = <&mdio1_phy3>;
5165 +};
5166 +&dpmac10 {
5167 + phy-handle = <&mdio1_phy4>;
5168 +};
5169 --- /dev/null
5170 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
5171 @@ -0,0 +1,818 @@
5172 +/*
5173 + * Device Tree Include file for NXP Layerscape-1088A family SoC.
5174 + *
5175 + * Copyright 2017 NXP
5176 + *
5177 + * Harninder Rai <harninder.rai@nxp.com>
5178 + *
5179 + * This file is dual-licensed: you can use it either under the terms
5180 + * of the GPLv2 or the X11 license, at your option. Note that this dual
5181 + * licensing only applies to this file, and not this project as a
5182 + * whole.
5183 + *
5184 + * a) This library is free software; you can redistribute it and/or
5185 + * modify it under the terms of the GNU General Public License as
5186 + * published by the Free Software Foundation; either version 2 of the
5187 + * License, or (at your option) any later version.
5188 + *
5189 + * This library is distributed in the hope that it will be useful,
5190 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5191 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5192 + * GNU General Public License for more details.
5193 + *
5194 + * Or, alternatively,
5195 + *
5196 + * b) Permission is hereby granted, free of charge, to any person
5197 + * obtaining a copy of this software and associated documentation
5198 + * files (the "Software"), to deal in the Software without
5199 + * restriction, including without limitation the rights to use,
5200 + * copy, modify, merge, publish, distribute, sublicense, and/or
5201 + * sell copies of the Software, and to permit persons to whom the
5202 + * Software is furnished to do so, subject to the following
5203 + * conditions:
5204 + *
5205 + * The above copyright notice and this permission notice shall be
5206 + * included in all copies or substantial portions of the Software.
5207 + *
5208 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5209 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5210 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5211 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5212 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5213 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5214 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5215 + * OTHER DEALINGS IN THE SOFTWARE.
5216 + */
5217 +#include <dt-bindings/interrupt-controller/arm-gic.h>
5218 +#include <dt-bindings/thermal/thermal.h>
5219 +
5220 +/ {
5221 + compatible = "fsl,ls1088a";
5222 + interrupt-parent = <&gic>;
5223 + #address-cells = <2>;
5224 + #size-cells = <2>;
5225 +
5226 + aliases {
5227 + crypto = &crypto;
5228 + };
5229 +
5230 + cpus {
5231 + #address-cells = <1>;
5232 + #size-cells = <0>;
5233 +
5234 + /* We have 2 clusters having 4 Cortex-A53 cores each */
5235 + cpu0: cpu@0 {
5236 + device_type = "cpu";
5237 + compatible = "arm,cortex-a53";
5238 + reg = <0x0>;
5239 + clocks = <&clockgen 1 0>;
5240 + #cooling-cells = <2>;
5241 + cpu-idle-states = <&CPU_PH20>;
5242 + };
5243 +
5244 + cpu1: cpu@1 {
5245 + device_type = "cpu";
5246 + compatible = "arm,cortex-a53";
5247 + reg = <0x1>;
5248 + clocks = <&clockgen 1 0>;
5249 + cpu-idle-states = <&CPU_PH20>;
5250 + };
5251 +
5252 + cpu2: cpu@2 {
5253 + device_type = "cpu";
5254 + compatible = "arm,cortex-a53";
5255 + reg = <0x2>;
5256 + clocks = <&clockgen 1 0>;
5257 + cpu-idle-states = <&CPU_PH20>;
5258 + };
5259 +
5260 + cpu3: cpu@3 {
5261 + device_type = "cpu";
5262 + compatible = "arm,cortex-a53";
5263 + reg = <0x3>;
5264 + clocks = <&clockgen 1 0>;
5265 + cpu-idle-states = <&CPU_PH20>;
5266 + };
5267 +
5268 + cpu4: cpu@100 {
5269 + device_type = "cpu";
5270 + compatible = "arm,cortex-a53";
5271 + reg = <0x100>;
5272 + clocks = <&clockgen 1 1>;
5273 + #cooling-cells = <2>;
5274 + cpu-idle-states = <&CPU_PH20>;
5275 + };
5276 +
5277 + cpu5: cpu@101 {
5278 + device_type = "cpu";
5279 + compatible = "arm,cortex-a53";
5280 + reg = <0x101>;
5281 + clocks = <&clockgen 1 1>;
5282 + cpu-idle-states = <&CPU_PH20>;
5283 + };
5284 +
5285 + cpu6: cpu@102 {
5286 + device_type = "cpu";
5287 + compatible = "arm,cortex-a53";
5288 + reg = <0x102>;
5289 + clocks = <&clockgen 1 1>;
5290 + cpu-idle-states = <&CPU_PH20>;
5291 + };
5292 +
5293 + cpu7: cpu@103 {
5294 + device_type = "cpu";
5295 + compatible = "arm,cortex-a53";
5296 + reg = <0x103>;
5297 + clocks = <&clockgen 1 1>;
5298 + cpu-idle-states = <&CPU_PH20>;
5299 + };
5300 + };
5301 +
5302 + idle-states {
5303 + /*
5304 + * PSCI node is not added default, U-boot will add missing
5305 + * parts if it determines to use PSCI.
5306 + */
5307 + entry-method = "arm,psci";
5308 +
5309 + CPU_PH20: cpu-ph20 {
5310 + compatible = "arm,idle-state";
5311 + idle-state-name = "PH20";
5312 + arm,psci-suspend-param = <0x0>;
5313 + entry-latency-us = <1000>;
5314 + exit-latency-us = <1000>;
5315 + min-residency-us = <3000>;
5316 + };
5317 + };
5318 +
5319 + gic: interrupt-controller@6000000 {
5320 + compatible = "arm,gic-v3";
5321 + #interrupt-cells = <3>;
5322 + #address-cells = <2>;
5323 + #size-cells = <2>;
5324 + ranges;
5325 + interrupt-controller;
5326 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
5327 + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
5328 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
5329 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
5330 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
5331 + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
5332 +
5333 + its: gic-its@6020000 {
5334 + compatible = "arm,gic-v3-its";
5335 + msi-controller;
5336 + reg = <0x0 0x6020000 0 0x20000>;
5337 + };
5338 + };
5339 +
5340 + timer {
5341 + compatible = "arm,armv8-timer";
5342 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
5343 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
5344 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
5345 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
5346 + };
5347 +
5348 + fsl_mc: fsl-mc@80c000000 {
5349 + compatible = "fsl,qoriq-mc";
5350 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
5351 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
5352 + msi-parent = <&its>;
5353 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
5354 + #address-cells = <3>;
5355 + #size-cells = <1>;
5356 +
5357 + /*
5358 + * Region type 0x0 - MC portals
5359 + * Region type 0x1 - QBMAN portals
5360 + */
5361 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
5362 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
5363 +
5364 + dpmacs {
5365 + #address-cells = <1>;
5366 + #size-cells = <0>;
5367 +
5368 + dpmac1: dpmac@1 {
5369 + compatible = "fsl,qoriq-mc-dpmac";
5370 + reg = <1>;
5371 + };
5372 + dpmac2: dpmac@2 {
5373 + compatible = "fsl,qoriq-mc-dpmac";
5374 + reg = <2>;
5375 + };
5376 + dpmac3: dpmac@3 {
5377 + compatible = "fsl,qoriq-mc-dpmac";
5378 + reg = <3>;
5379 + };
5380 + dpmac4: dpmac@4 {
5381 + compatible = "fsl,qoriq-mc-dpmac";
5382 + reg = <4>;
5383 + };
5384 + dpmac5: dpmac@5 {
5385 + compatible = "fsl,qoriq-mc-dpmac";
5386 + reg = <5>;
5387 + };
5388 + dpmac6: dpmac@6 {
5389 + compatible = "fsl,qoriq-mc-dpmac";
5390 + reg = <6>;
5391 + };
5392 + dpmac7: dpmac@7 {
5393 + compatible = "fsl,qoriq-mc-dpmac";
5394 + reg = <7>;
5395 + };
5396 + dpmac8: dpmac@8 {
5397 + compatible = "fsl,qoriq-mc-dpmac";
5398 + reg = <8>;
5399 + };
5400 + dpmac9: dpmac@9 {
5401 + compatible = "fsl,qoriq-mc-dpmac";
5402 + reg = <9>;
5403 + };
5404 + dpmac10: dpmac@10 {
5405 + compatible = "fsl,qoriq-mc-dpmac";
5406 + reg = <0xa>;
5407 + };
5408 + };
5409 +
5410 + };
5411 +
5412 + sysclk: sysclk {
5413 + compatible = "fixed-clock";
5414 + #clock-cells = <0>;
5415 + clock-frequency = <100000000>;
5416 + clock-output-names = "sysclk";
5417 + };
5418 +
5419 + dcfg: dcfg@1e00000 {
5420 + compatible = "fsl,ls1088a-dcfg", "syscon";
5421 + reg = <0x0 0x1e00000 0x0 0x10000>;
5422 + little-endian;
5423 + };
5424 +
5425 + rstcr: syscon@1e60000 {
5426 + compatible = "fsl,ls1088a-rstcr", "syscon";
5427 + reg = <0x0 0x1e60000 0x0 0x4>;
5428 + };
5429 +
5430 + reboot {
5431 + compatible = "syscon-reboot";
5432 + regmap = <&rstcr>;
5433 + offset = <0x0>;
5434 + mask = <0x02>;
5435 + };
5436 +
5437 +
5438 + soc {
5439 + compatible = "simple-bus";
5440 + #address-cells = <2>;
5441 + #size-cells = <2>;
5442 + ranges;
5443 +
5444 + clockgen: clocking@1300000 {
5445 + compatible = "fsl,ls1088a-clockgen";
5446 + reg = <0 0x1300000 0 0xa0000>;
5447 + #clock-cells = <2>;
5448 + clocks = <&sysclk>;
5449 + };
5450 +
5451 + tmu: tmu@1f80000 {
5452 + compatible = "fsl,qoriq-tmu";
5453 + reg = <0x0 0x1f80000 0x0 0x10000>;
5454 + interrupts = <0 23 0x4>;
5455 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
5456 + fsl,tmu-calibration =
5457 + /* Calibration data group 1 */
5458 + <0x00000000 0x00000026
5459 + 0x00000001 0x0000002d
5460 + 0x00000002 0x00000032
5461 + 0x00000003 0x00000039
5462 + 0x00000004 0x0000003f
5463 + 0x00000005 0x00000046
5464 + 0x00000006 0x0000004d
5465 + 0x00000007 0x00000054
5466 + 0x00000008 0x0000005a
5467 + 0x00000009 0x00000061
5468 + 0x0000000a 0x0000006a
5469 + 0x0000000b 0x00000071
5470 + /* Calibration data group 2 */
5471 + 0x00010000 0x00000025
5472 + 0x00010001 0x0000002c
5473 + 0x00010002 0x00000035
5474 + 0x00010003 0x0000003d
5475 + 0x00010004 0x00000045
5476 + 0x00010005 0x0000004e
5477 + 0x00010006 0x00000057
5478 + 0x00010007 0x00000061
5479 + 0x00010008 0x0000006b
5480 + 0x00010009 0x00000076
5481 + /* Calibration data group 3 */
5482 + 0x00020000 0x00000029
5483 + 0x00020001 0x00000033
5484 + 0x00020002 0x0000003d
5485 + 0x00020003 0x00000049
5486 + 0x00020004 0x00000056
5487 + 0x00020005 0x00000061
5488 + 0x00020006 0x0000006d
5489 + /* Calibration data group 4 */
5490 + 0x00030000 0x00000021
5491 + 0x00030001 0x0000002a
5492 + 0x00030002 0x0000003c
5493 + 0x00030003 0x0000004e>;
5494 + little-endian;
5495 + #thermal-sensor-cells = <1>;
5496 + };
5497 +
5498 + thermal-zones {
5499 + cpu_thermal: cpu-thermal {
5500 + polling-delay-passive = <1000>;
5501 + polling-delay = <5000>;
5502 + thermal-sensors = <&tmu 0>;
5503 +
5504 + trips {
5505 + cpu_alert: cpu-alert {
5506 + temperature = <85000>;
5507 + hysteresis = <2000>;
5508 + type = "passive";
5509 + };
5510 +
5511 + cpu_crit: cpu-crit {
5512 + temperature = <95000>;
5513 + hysteresis = <2000>;
5514 + type = "critical";
5515 + };
5516 + };
5517 +
5518 + cooling-maps {
5519 + map0 {
5520 + trip = <&cpu_alert>;
5521 + cooling-device =
5522 + <&cpu0 THERMAL_NO_LIMIT
5523 + THERMAL_NO_LIMIT>;
5524 + };
5525 + map1 {
5526 + trip = <&cpu_alert>;
5527 + cooling-device =
5528 + <&cpu4 THERMAL_NO_LIMIT
5529 + THERMAL_NO_LIMIT>;
5530 + };
5531 + };
5532 + };
5533 + };
5534 +
5535 + duart0: serial@21c0500 {
5536 + compatible = "fsl,ns16550", "ns16550a";
5537 + reg = <0x0 0x21c0500 0x0 0x100>;
5538 + clocks = <&clockgen 4 3>;
5539 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5540 + status = "disabled";
5541 + };
5542 +
5543 + duart1: serial@21c0600 {
5544 + compatible = "fsl,ns16550", "ns16550a";
5545 + reg = <0x0 0x21c0600 0x0 0x100>;
5546 + clocks = <&clockgen 4 3>;
5547 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5548 + status = "disabled";
5549 + };
5550 +
5551 + cluster1_core0_watchdog: wdt@c000000 {
5552 + compatible = "arm,sp805-wdt", "arm,primecell";
5553 + reg = <0x0 0xc000000 0x0 0x1000>;
5554 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5555 + clock-names = "apb_pclk", "wdog_clk";
5556 + };
5557 +
5558 + cluster1_core1_watchdog: wdt@c010000 {
5559 + compatible = "arm,sp805-wdt", "arm,primecell";
5560 + reg = <0x0 0xc010000 0x0 0x1000>;
5561 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5562 + clock-names = "apb_pclk", "wdog_clk";
5563 + };
5564 +
5565 + cluster1_core2_watchdog: wdt@c020000 {
5566 + compatible = "arm,sp805-wdt", "arm,primecell";
5567 + reg = <0x0 0xc020000 0x0 0x1000>;
5568 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5569 + clock-names = "apb_pclk", "wdog_clk";
5570 + };
5571 +
5572 + cluster1_core3_watchdog: wdt@c030000 {
5573 + compatible = "arm,sp805-wdt", "arm,primecell";
5574 + reg = <0x0 0xc030000 0x0 0x1000>;
5575 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5576 + clock-names = "apb_pclk", "wdog_clk";
5577 + };
5578 +
5579 + cluster2_core0_watchdog: wdt@c100000 {
5580 + compatible = "arm,sp805-wdt", "arm,primecell";
5581 + reg = <0x0 0xc100000 0x0 0x1000>;
5582 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5583 + clock-names = "apb_pclk", "wdog_clk";
5584 + };
5585 +
5586 + cluster2_core1_watchdog: wdt@c110000 {
5587 + compatible = "arm,sp805-wdt", "arm,primecell";
5588 + reg = <0x0 0xc110000 0x0 0x1000>;
5589 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5590 + clock-names = "apb_pclk", "wdog_clk";
5591 + };
5592 +
5593 + cluster2_core2_watchdog: wdt@c120000 {
5594 + compatible = "arm,sp805-wdt", "arm,primecell";
5595 + reg = <0x0 0xc120000 0x0 0x1000>;
5596 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5597 + clock-names = "apb_pclk", "wdog_clk";
5598 + };
5599 +
5600 + cluster2_core3_watchdog: wdt@c130000 {
5601 + compatible = "arm,sp805-wdt", "arm,primecell";
5602 + reg = <0x0 0xc130000 0x0 0x1000>;
5603 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5604 + clock-names = "apb_pclk", "wdog_clk";
5605 + };
5606 +
5607 + gpio0: gpio@2300000 {
5608 + compatible = "fsl,qoriq-gpio";
5609 + reg = <0x0 0x2300000 0x0 0x10000>;
5610 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5611 + gpio-controller;
5612 + #gpio-cells = <2>;
5613 + interrupt-controller;
5614 + #interrupt-cells = <2>;
5615 + };
5616 +
5617 + gpio1: gpio@2310000 {
5618 + compatible = "fsl,qoriq-gpio";
5619 + reg = <0x0 0x2310000 0x0 0x10000>;
5620 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5621 + gpio-controller;
5622 + #gpio-cells = <2>;
5623 + interrupt-controller;
5624 + #interrupt-cells = <2>;
5625 + };
5626 +
5627 + gpio2: gpio@2320000 {
5628 + compatible = "fsl,qoriq-gpio";
5629 + reg = <0x0 0x2320000 0x0 0x10000>;
5630 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5631 + gpio-controller;
5632 + #gpio-cells = <2>;
5633 + interrupt-controller;
5634 + #interrupt-cells = <2>;
5635 + };
5636 +
5637 + gpio3: gpio@2330000 {
5638 + compatible = "fsl,qoriq-gpio";
5639 + reg = <0x0 0x2330000 0x0 0x10000>;
5640 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5641 + gpio-controller;
5642 + #gpio-cells = <2>;
5643 + interrupt-controller;
5644 + #interrupt-cells = <2>;
5645 + };
5646 +
5647 + /* TODO: WRIOP (CCSR?) */
5648 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
5649 + * E-MDIO1: 0x1_6000
5650 + */
5651 + compatible = "fsl,fman-memac-mdio";
5652 + reg = <0x0 0x8B96000 0x0 0x1000>;
5653 + device_type = "mdio";
5654 + little-endian; /* force the driver in LE mode */
5655 +
5656 + /* Not necessary on the QDS, but needed on the RDB */
5657 + #address-cells = <1>;
5658 + #size-cells = <0>;
5659 + };
5660 +
5661 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
5662 + * E-MDIO2: 0x1_7000
5663 + */
5664 + compatible = "fsl,fman-memac-mdio";
5665 + reg = <0x0 0x8B97000 0x0 0x1000>;
5666 + device_type = "mdio";
5667 + little-endian; /* force the driver in LE mode */
5668 +
5669 + #address-cells = <1>;
5670 + #size-cells = <0>;
5671 + };
5672 +
5673 + ifc: ifc@2240000 {
5674 + compatible = "fsl,ifc", "simple-bus";
5675 + reg = <0x0 0x2240000 0x0 0x20000>;
5676 + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
5677 + little-endian;
5678 + #address-cells = <2>;
5679 + #size-cells = <1>;
5680 +
5681 + };
5682 +
5683 + ftm0: ftm0@2800000 {
5684 + compatible = "fsl,ls1088a-ftm";
5685 + reg = <0x0 0x2800000 0x0 0x10000>,
5686 + <0x0 0x1e34050 0x0 0x4>;
5687 + interrupts = <0 44 4>;
5688 + reg-names = "ftm", "FlexTimer1";
5689 + };
5690 +
5691 + i2c0: i2c@2000000 {
5692 + compatible = "fsl,vf610-i2c";
5693 + #address-cells = <1>;
5694 + #size-cells = <0>;
5695 + reg = <0x0 0x2000000 0x0 0x10000>;
5696 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5697 + clocks = <&clockgen 4 3>;
5698 + status = "disabled";
5699 + };
5700 +
5701 + i2c1: i2c@2010000 {
5702 + compatible = "fsl,vf610-i2c";
5703 + #address-cells = <1>;
5704 + #size-cells = <0>;
5705 + reg = <0x0 0x2010000 0x0 0x10000>;
5706 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5707 + clocks = <&clockgen 4 3>;
5708 + status = "disabled";
5709 + };
5710 +
5711 + i2c2: i2c@2020000 {
5712 + compatible = "fsl,vf610-i2c";
5713 + #address-cells = <1>;
5714 + #size-cells = <0>;
5715 + reg = <0x0 0x2020000 0x0 0x10000>;
5716 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5717 + clocks = <&clockgen 4 3>;
5718 + status = "disabled";
5719 + };
5720 +
5721 + i2c3: i2c@2030000 {
5722 + compatible = "fsl,vf610-i2c";
5723 + #address-cells = <1>;
5724 + #size-cells = <0>;
5725 + reg = <0x0 0x2030000 0x0 0x10000>;
5726 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5727 + clocks = <&clockgen 4 3>;
5728 + status = "disabled";
5729 + };
5730 +
5731 + qspi: quadspi@20c0000 {
5732 + compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
5733 + #address-cells = <1>;
5734 + #size-cells = <0>;
5735 + reg = <0x0 0x20c0000 0x0 0x10000>,
5736 + <0x0 0x20000000 0x0 0x10000000>;
5737 + reg-names = "QuadSPI", "QuadSPI-memory";
5738 + interrupts = <0 25 0x4>; /* Level high type */
5739 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5740 + clock-names = "qspi_en", "qspi";
5741 + fsl,qspi-has-second-chip;
5742 + };
5743 +
5744 + esdhc: esdhc@2140000 {
5745 + compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
5746 + reg = <0x0 0x2140000 0x0 0x10000>;
5747 + interrupts = <0 28 0x4>; /* Level high type */
5748 + clock-frequency = <0>;
5749 + voltage-ranges = <1800 1800 3300 3300>;
5750 + sdhci,auto-cmd12;
5751 + little-endian;
5752 + bus-width = <4>;
5753 + status = "disabled";
5754 + };
5755 +
5756 + usb0: usb3@3100000 {
5757 + compatible = "snps,dwc3";
5758 + reg = <0x0 0x3100000 0x0 0x10000>;
5759 + interrupts = <0 80 0x4>; /* Level high type */
5760 + dr_mode = "host";
5761 + configure-gfladj;
5762 + snps,dis_rxdet_inp3_quirk;
5763 + };
5764 +
5765 + usb1: usb3@3110000 {
5766 + compatible = "snps,dwc3";
5767 + reg = <0x0 0x3110000 0x0 0x10000>;
5768 + interrupts = <0 81 0x4>; /* Level high type */
5769 + dr_mode = "host";
5770 + configure-gfladj;
5771 + snps,dis_rxdet_inp3_quirk;
5772 + };
5773 +
5774 + sata: sata@3200000 {
5775 + compatible = "fsl,ls1088a-ahci";
5776 + reg = <0x0 0x3200000 0x0 0x10000>,
5777 + <0x7 0x100520 0x0 0x4>;
5778 + reg-names = "ahci", "sata-ecc";
5779 + interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
5780 + clocks = <&clockgen 4 3>;
5781 + dma-coherent;
5782 + status = "disabled";
5783 + };
5784 +
5785 + pcie@3400000 {
5786 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5787 + "snps,dw-pcie";
5788 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
5789 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
5790 + reg-names = "regs", "config";
5791 + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5792 + interrupt-names = "aer";
5793 + #address-cells = <3>;
5794 + #size-cells = <2>;
5795 + device_type = "pci";
5796 + dma-coherent;
5797 + num-lanes = <4>;
5798 + bus-range = <0x0 0xff>;
5799 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
5800 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5801 + msi-parent = <&its>;
5802 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5803 + #interrupt-cells = <1>;
5804 + interrupt-map-mask = <0 0 0 7>;
5805 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
5806 + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
5807 + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
5808 + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
5809 + };
5810 +
5811 + pcie@3500000 {
5812 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5813 + "snps,dw-pcie";
5814 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
5815 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
5816 + reg-names = "regs", "config";
5817 + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5818 + interrupt-names = "aer";
5819 + #address-cells = <3>;
5820 + #size-cells = <2>;
5821 + device_type = "pci";
5822 + dma-coherent;
5823 + num-lanes = <4>;
5824 + bus-range = <0x0 0xff>;
5825 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
5826 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5827 + msi-parent = <&its>;
5828 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5829 + #interrupt-cells = <1>;
5830 + interrupt-map-mask = <0 0 0 7>;
5831 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
5832 + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
5833 + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
5834 + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
5835 + };
5836 +
5837 + pcie@3600000 {
5838 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5839 + "snps,dw-pcie";
5840 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
5841 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
5842 + reg-names = "regs", "config";
5843 + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5844 + interrupt-names = "aer";
5845 + #address-cells = <3>;
5846 + #size-cells = <2>;
5847 + device_type = "pci";
5848 + dma-coherent;
5849 + num-lanes = <8>;
5850 + bus-range = <0x0 0xff>;
5851 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
5852 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5853 + msi-parent = <&its>;
5854 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5855 + #interrupt-cells = <1>;
5856 + interrupt-map-mask = <0 0 0 7>;
5857 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
5858 + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
5859 + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
5860 + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
5861 + };
5862 +
5863 + smmu: iommu@5000000 {
5864 + compatible = "arm,mmu-500";
5865 + reg = <0 0x5000000 0 0x800000>;
5866 + #global-interrupts = <12>;
5867 + #iommu-cells = <1>;
5868 + stream-match-mask = <0x7C00>;
5869 + interrupts = <0 13 4>, /* global secure fault */
5870 + <0 14 4>, /* combined secure interrupt */
5871 + <0 15 4>, /* global non-secure fault */
5872 + <0 16 4>, /* combined non-secure interrupt */
5873 + /* performance counter interrupts 0-7 */
5874 + <0 211 4>,
5875 + <0 212 4>,
5876 + <0 213 4>,
5877 + <0 214 4>,
5878 + <0 215 4>,
5879 + <0 216 4>,
5880 + <0 217 4>,
5881 + <0 218 4>,
5882 + /* per context interrupt, 64 interrupts */
5883 + <0 146 4>,
5884 + <0 147 4>,
5885 + <0 148 4>,
5886 + <0 149 4>,
5887 + <0 150 4>,
5888 + <0 151 4>,
5889 + <0 152 4>,
5890 + <0 153 4>,
5891 + <0 154 4>,
5892 + <0 155 4>,
5893 + <0 156 4>,
5894 + <0 157 4>,
5895 + <0 158 4>,
5896 + <0 159 4>,
5897 + <0 160 4>,
5898 + <0 161 4>,
5899 + <0 162 4>,
5900 + <0 163 4>,
5901 + <0 164 4>,
5902 + <0 165 4>,
5903 + <0 166 4>,
5904 + <0 167 4>,
5905 + <0 168 4>,
5906 + <0 169 4>,
5907 + <0 170 4>,
5908 + <0 171 4>,
5909 + <0 172 4>,
5910 + <0 173 4>,
5911 + <0 174 4>,
5912 + <0 175 4>,
5913 + <0 176 4>,
5914 + <0 177 4>,
5915 + <0 178 4>,
5916 + <0 179 4>,
5917 + <0 180 4>,
5918 + <0 181 4>,
5919 + <0 182 4>,
5920 + <0 183 4>,
5921 + <0 184 4>,
5922 + <0 185 4>,
5923 + <0 186 4>,
5924 + <0 187 4>,
5925 + <0 188 4>,
5926 + <0 189 4>,
5927 + <0 190 4>,
5928 + <0 191 4>,
5929 + <0 192 4>,
5930 + <0 193 4>,
5931 + <0 194 4>,
5932 + <0 195 4>,
5933 + <0 196 4>,
5934 + <0 197 4>,
5935 + <0 198 4>,
5936 + <0 199 4>,
5937 + <0 200 4>,
5938 + <0 201 4>,
5939 + <0 202 4>,
5940 + <0 203 4>,
5941 + <0 204 4>,
5942 + <0 205 4>,
5943 + <0 206 4>,
5944 + <0 207 4>,
5945 + <0 208 4>,
5946 + <0 209 4>;
5947 + };
5948 +
5949 + crypto: crypto@8000000 {
5950 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
5951 + fsl,sec-era = <8>;
5952 + #address-cells = <1>;
5953 + #size-cells = <1>;
5954 + ranges = <0x0 0x00 0x8000000 0x100000>;
5955 + reg = <0x00 0x8000000 0x0 0x100000>;
5956 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
5957 + dma-coherent;
5958 +
5959 + sec_jr0: jr@10000 {
5960 + compatible = "fsl,sec-v5.0-job-ring",
5961 + "fsl,sec-v4.0-job-ring";
5962 + reg = <0x10000 0x10000>;
5963 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
5964 + };
5965 +
5966 + sec_jr1: jr@20000 {
5967 + compatible = "fsl,sec-v5.0-job-ring",
5968 + "fsl,sec-v4.0-job-ring";
5969 + reg = <0x20000 0x10000>;
5970 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
5971 + };
5972 +
5973 + sec_jr2: jr@30000 {
5974 + compatible = "fsl,sec-v5.0-job-ring",
5975 + "fsl,sec-v4.0-job-ring";
5976 + reg = <0x30000 0x10000>;
5977 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
5978 + };
5979 +
5980 + sec_jr3: jr@40000 {
5981 + compatible = "fsl,sec-v5.0-job-ring",
5982 + "fsl,sec-v4.0-job-ring";
5983 + reg = <0x40000 0x10000>;
5984 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
5985 + };
5986 + };
5987 + };
5988 +
5989 +};
5990 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
5991 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
5992 @@ -1,8 +1,10 @@
5993 /*
5994 * Device Tree file for Freescale LS2080a QDS Board.
5995 *
5996 - * Copyright (C) 2015, Freescale Semiconductor
5997 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
5998 + * Copyright 2017 NXP
5999 *
6000 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6001 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6002 *
6003 * This file is dual-licensed: you can use it either under the terms
6004 @@ -46,169 +48,76 @@
6005
6006 /dts-v1/;
6007
6008 -/include/ "fsl-ls2080a.dtsi"
6009 +#include "fsl-ls2080a.dtsi"
6010 +#include "fsl-ls208xa-qds.dtsi"
6011
6012 / {
6013 model = "Freescale Layerscape 2080a QDS Board";
6014 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
6015
6016 - aliases {
6017 - serial0 = &serial0;
6018 - serial1 = &serial1;
6019 - };
6020 -
6021 chosen {
6022 stdout-path = "serial0:115200n8";
6023 };
6024 };
6025
6026 -&esdhc {
6027 - status = "okay";
6028 -};
6029 -
6030 &ifc {
6031 - status = "okay";
6032 - #address-cells = <2>;
6033 - #size-cells = <1>;
6034 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6035 - 0x2 0x0 0x5 0x30000000 0x00010000
6036 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6037 -
6038 - nor@0,0 {
6039 + boardctrl: board-control@3,0 {
6040 #address-cells = <1>;
6041 #size-cells = <1>;
6042 - compatible = "cfi-flash";
6043 - reg = <0x0 0x0 0x8000000>;
6044 - bank-width = <2>;
6045 - device-width = <1>;
6046 - };
6047 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
6048 + reg = <3 0 0x300>; /* TODO check address */
6049 + ranges = <0 3 0 0x300>;
6050
6051 - nand@2,0 {
6052 - compatible = "fsl,ifc-nand";
6053 - reg = <0x2 0x0 0x10000>;
6054 - };
6055 + mdio_mux_emi1 {
6056 + compatible = "mdio-mux-mmioreg", "mdio-mux";
6057 + mdio-parent-bus = <&emdio1>;
6058 + reg = <0x54 1>; /* BRDCFG4 */
6059 + mux-mask = <0xe0>; /* EMI1_MDIO */
6060
6061 - cpld@3,0 {
6062 - reg = <0x3 0x0 0x10000>;
6063 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6064 - };
6065 -};
6066 -
6067 -&i2c0 {
6068 - status = "okay";
6069 - pca9547@77 {
6070 - compatible = "nxp,pca9547";
6071 - reg = <0x77>;
6072 - #address-cells = <1>;
6073 - #size-cells = <0>;
6074 - i2c@0 {
6075 - #address-cells = <1>;
6076 + #address-cells=<1>;
6077 #size-cells = <0>;
6078 - reg = <0x00>;
6079 - rtc@68 {
6080 - compatible = "dallas,ds3232";
6081 - reg = <0x68>;
6082 - };
6083 - };
6084
6085 - i2c@2 {
6086 - #address-cells = <1>;
6087 - #size-cells = <0>;
6088 - reg = <0x02>;
6089 -
6090 - ina220@40 {
6091 - compatible = "ti,ina220";
6092 - reg = <0x40>;
6093 - shunt-resistor = <500>;
6094 - };
6095 -
6096 - ina220@41 {
6097 - compatible = "ti,ina220";
6098 - reg = <0x41>;
6099 - shunt-resistor = <1000>;
6100 - };
6101 - };
6102 -
6103 - i2c@3 {
6104 - #address-cells = <1>;
6105 - #size-cells = <0>;
6106 - reg = <0x3>;
6107 -
6108 - adt7481@4c {
6109 - compatible = "adi,adt7461";
6110 - reg = <0x4c>;
6111 + /* Child MDIO buses, one for each riser card:
6112 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
6113 + * VSC8234 PHYs on the riser cards.
6114 + */
6115 +
6116 + mdio_mux3: mdio@60 {
6117 + reg = <0x60>;
6118 + #address-cells = <1>;
6119 + #size-cells = <0>;
6120 +
6121 + mdio0_phy12: mdio_phy0@1c {
6122 + reg = <0x1c>;
6123 + phy-connection-type = "sgmii";
6124 + };
6125 + mdio0_phy13: mdio_phy1@1d {
6126 + reg = <0x1d>;
6127 + phy-connection-type = "sgmii";
6128 + };
6129 + mdio0_phy14: mdio_phy2@1e {
6130 + reg = <0x1e>;
6131 + phy-connection-type = "sgmii";
6132 + };
6133 + mdio0_phy15: mdio_phy3@1f {
6134 + reg = <0x1f>;
6135 + phy-connection-type = "sgmii";
6136 + };
6137 };
6138 };
6139 };
6140 };
6141
6142 -&i2c1 {
6143 - status = "disabled";
6144 -};
6145 -
6146 -&i2c2 {
6147 - status = "disabled";
6148 -};
6149 -
6150 -&i2c3 {
6151 - status = "disabled";
6152 -};
6153 -
6154 -&dspi {
6155 - status = "okay";
6156 - dflash0: n25q128a {
6157 - #address-cells = <1>;
6158 - #size-cells = <1>;
6159 - compatible = "st,m25p80";
6160 - spi-max-frequency = <3000000>;
6161 - reg = <0>;
6162 - };
6163 - dflash1: sst25wf040b {
6164 - #address-cells = <1>;
6165 - #size-cells = <1>;
6166 - compatible = "st,m25p80";
6167 - spi-max-frequency = <3000000>;
6168 - reg = <1>;
6169 - };
6170 - dflash2: en25s64 {
6171 - #address-cells = <1>;
6172 - #size-cells = <1>;
6173 - compatible = "st,m25p80";
6174 - spi-max-frequency = <3000000>;
6175 - reg = <2>;
6176 - };
6177 -};
6178 -
6179 -&qspi {
6180 - status = "okay";
6181 - flash0: s25fl256s1@0 {
6182 - #address-cells = <1>;
6183 - #size-cells = <1>;
6184 - compatible = "st,m25p80";
6185 - spi-max-frequency = <20000000>;
6186 - reg = <0>;
6187 - };
6188 - flash2: s25fl256s1@2 {
6189 - #address-cells = <1>;
6190 - #size-cells = <1>;
6191 - compatible = "st,m25p80";
6192 - spi-max-frequency = <20000000>;
6193 - reg = <0>;
6194 - };
6195 -};
6196 -
6197 -&sata0 {
6198 - status = "okay";
6199 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
6200 +&dpmac9 {
6201 + phy-handle = <&mdio0_phy12>;
6202 };
6203 -
6204 -&sata1 {
6205 - status = "okay";
6206 +&dpmac10 {
6207 + phy-handle = <&mdio0_phy13>;
6208 };
6209 -
6210 -&usb0 {
6211 - status = "okay";
6212 +&dpmac11 {
6213 + phy-handle = <&mdio0_phy14>;
6214 };
6215 -
6216 -&usb1 {
6217 - status = "okay";
6218 +&dpmac12 {
6219 + phy-handle = <&mdio0_phy15>;
6220 };
6221 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6222 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6223 @@ -1,8 +1,10 @@
6224 /*
6225 * Device Tree file for Freescale LS2080a RDB Board.
6226 *
6227 - * Copyright (C) 2015, Freescale Semiconductor
6228 + * Copyright 2016 Freescale Semiconductor, Inc.
6229 + * Copyright 2017 NXP
6230 *
6231 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6232 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6233 *
6234 * This file is dual-licensed: you can use it either under the terms
6235 @@ -46,125 +48,94 @@
6236
6237 /dts-v1/;
6238
6239 -/include/ "fsl-ls2080a.dtsi"
6240 +#include "fsl-ls2080a.dtsi"
6241 +#include "fsl-ls208xa-rdb.dtsi"
6242
6243 / {
6244 model = "Freescale Layerscape 2080a RDB Board";
6245 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
6246
6247 - aliases {
6248 - serial0 = &serial0;
6249 - serial1 = &serial1;
6250 - };
6251 -
6252 chosen {
6253 stdout-path = "serial1:115200n8";
6254 };
6255 };
6256
6257 -&esdhc {
6258 - status = "okay";
6259 -};
6260 -
6261 -&ifc {
6262 - status = "okay";
6263 - #address-cells = <2>;
6264 - #size-cells = <1>;
6265 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6266 - 0x2 0x0 0x5 0x30000000 0x00010000
6267 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6268 -
6269 - nor@0,0 {
6270 - #address-cells = <1>;
6271 - #size-cells = <1>;
6272 - compatible = "cfi-flash";
6273 - reg = <0x0 0x0 0x8000000>;
6274 - bank-width = <2>;
6275 - device-width = <1>;
6276 - };
6277 -
6278 - nand@2,0 {
6279 - compatible = "fsl,ifc-nand";
6280 - reg = <0x2 0x0 0x10000>;
6281 - };
6282 -
6283 - cpld@3,0 {
6284 - reg = <0x3 0x0 0x10000>;
6285 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6286 - };
6287 -
6288 -};
6289 -
6290 -&i2c0 {
6291 - status = "okay";
6292 - pca9547@75 {
6293 - compatible = "nxp,pca9547";
6294 - reg = <0x75>;
6295 - #address-cells = <1>;
6296 - #size-cells = <0>;
6297 - status = "disabled";
6298 - i2c@1 {
6299 - #address-cells = <1>;
6300 - #size-cells = <0>;
6301 - reg = <0x01>;
6302 - rtc@68 {
6303 - compatible = "dallas,ds3232";
6304 - reg = <0x68>;
6305 - };
6306 - };
6307 -
6308 - i2c@3 {
6309 - #address-cells = <1>;
6310 - #size-cells = <0>;
6311 - reg = <0x3>;
6312 -
6313 - adt7481@4c {
6314 - compatible = "adi,adt7461";
6315 - reg = <0x4c>;
6316 - };
6317 - };
6318 - };
6319 -};
6320 -
6321 -&i2c1 {
6322 - status = "disabled";
6323 -};
6324 -
6325 -&i2c2 {
6326 - status = "disabled";
6327 -};
6328 -
6329 -&i2c3 {
6330 +&emdio1 {
6331 status = "disabled";
6332 + /* CS4340 PHYs */
6333 + mdio1_phy1: emdio1_phy@1 {
6334 + reg = <0x10>;
6335 + phy-connection-type = "xfi";
6336 + };
6337 + mdio1_phy2: emdio1_phy@2 {
6338 + reg = <0x11>;
6339 + phy-connection-type = "xfi";
6340 + };
6341 + mdio1_phy3: emdio1_phy@3 {
6342 + reg = <0x12>;
6343 + phy-connection-type = "xfi";
6344 + };
6345 + mdio1_phy4: emdio1_phy@4 {
6346 + reg = <0x13>;
6347 + phy-connection-type = "xfi";
6348 + };
6349 };
6350
6351 -&dspi {
6352 - status = "okay";
6353 - dflash0: n25q512a {
6354 - #address-cells = <1>;
6355 - #size-cells = <1>;
6356 - compatible = "st,m25p80";
6357 - spi-max-frequency = <3000000>;
6358 - reg = <0>;
6359 +&emdio2 {
6360 + /* AQR405 PHYs */
6361 + mdio2_phy1: emdio2_phy@1 {
6362 + compatible = "ethernet-phy-ieee802.3-c45";
6363 + interrupts = <0 1 0x4>; /* Level high type */
6364 + reg = <0x0>;
6365 + phy-connection-type = "xfi";
6366 + };
6367 + mdio2_phy2: emdio2_phy@2 {
6368 + compatible = "ethernet-phy-ieee802.3-c45";
6369 + interrupts = <0 2 0x4>; /* Level high type */
6370 + reg = <0x1>;
6371 + phy-connection-type = "xfi";
6372 + };
6373 + mdio2_phy3: emdio2_phy@3 {
6374 + compatible = "ethernet-phy-ieee802.3-c45";
6375 + interrupts = <0 4 0x4>; /* Level high type */
6376 + reg = <0x2>;
6377 + phy-connection-type = "xfi";
6378 + };
6379 + mdio2_phy4: emdio2_phy@4 {
6380 + compatible = "ethernet-phy-ieee802.3-c45";
6381 + interrupts = <0 5 0x4>; /* Level high type */
6382 + reg = <0x3>;
6383 + phy-connection-type = "xfi";
6384 };
6385 };
6386
6387 -&qspi {
6388 - status = "disabled";
6389 -};
6390 +/* Update DPMAC connections to external PHYs, under the assumption of
6391 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
6392 + */
6393 +/* Leave Cortina nodes commented out until driver is integrated
6394 + *&dpmac1 {
6395 + * phy-handle = <&mdio1_phy1>;
6396 + *};
6397 + *&dpmac2 {
6398 + * phy-handle = <&mdio1_phy2>;
6399 + *};
6400 + *&dpmac3 {
6401 + * phy-handle = <&mdio1_phy3>;
6402 + *};
6403 + *&dpmac4 {
6404 + * phy-handle = <&mdio1_phy4>;
6405 + *};
6406 + */
6407
6408 -&sata0 {
6409 - status = "okay";
6410 +&dpmac5 {
6411 + phy-handle = <&mdio2_phy1>;
6412 };
6413 -
6414 -&sata1 {
6415 - status = "okay";
6416 +&dpmac6 {
6417 + phy-handle = <&mdio2_phy2>;
6418 };
6419 -
6420 -&usb0 {
6421 - status = "okay";
6422 +&dpmac7 {
6423 + phy-handle = <&mdio2_phy3>;
6424 };
6425 -
6426 -&usb1 {
6427 - status = "okay";
6428 +&dpmac8 {
6429 + phy-handle = <&mdio2_phy4>;
6430 };
6431 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6432 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6433 @@ -1,7 +1,7 @@
6434 /*
6435 * Device Tree file for Freescale LS2080a software Simulator model
6436 *
6437 - * Copyright (C) 2014-2015, Freescale Semiconductor
6438 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
6439 *
6440 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6441 *
6442 @@ -46,17 +46,12 @@
6443
6444 /dts-v1/;
6445
6446 -/include/ "fsl-ls2080a.dtsi"
6447 +#include "fsl-ls2080a.dtsi"
6448
6449 / {
6450 model = "Freescale Layerscape 2080a software Simulator model";
6451 compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
6452
6453 - aliases {
6454 - serial0 = &serial0;
6455 - serial1 = &serial1;
6456 - };
6457 -
6458 ethernet@2210000 {
6459 compatible = "smsc,lan91c111";
6460 reg = <0x0 0x2210000 0x0 0x100>;
6461 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6462 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6463 @@ -1,8 +1,9 @@
6464 /*
6465 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6466 *
6467 - * Copyright (C) 2014-2015, Freescale Semiconductor
6468 + * Copyright 2014-2016 Freescale Semiconductor, Inc.
6469 *
6470 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6471 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6472 *
6473 * This file is dual-licensed: you can use it either under the terms
6474 @@ -44,696 +45,132 @@
6475 * OTHER DEALINGS IN THE SOFTWARE.
6476 */
6477
6478 -/ {
6479 - compatible = "fsl,ls2080a";
6480 - interrupt-parent = <&gic>;
6481 - #address-cells = <2>;
6482 - #size-cells = <2>;
6483 -
6484 - cpus {
6485 - #address-cells = <1>;
6486 - #size-cells = <0>;
6487 -
6488 - /*
6489 - * We expect the enable-method for cpu's to be "psci", but this
6490 - * is dependent on the SoC FW, which will fill this in.
6491 - *
6492 - * Currently supported enable-method is psci v0.2
6493 - */
6494 -
6495 - /* We have 4 clusters having 2 Cortex-A57 cores each */
6496 - cpu@0 {
6497 - device_type = "cpu";
6498 - compatible = "arm,cortex-a57";
6499 - reg = <0x0>;
6500 - clocks = <&clockgen 1 0>;
6501 - next-level-cache = <&cluster0_l2>;
6502 - };
6503 -
6504 - cpu@1 {
6505 - device_type = "cpu";
6506 - compatible = "arm,cortex-a57";
6507 - reg = <0x1>;
6508 - clocks = <&clockgen 1 0>;
6509 - next-level-cache = <&cluster0_l2>;
6510 - };
6511 -
6512 - cpu@100 {
6513 - device_type = "cpu";
6514 - compatible = "arm,cortex-a57";
6515 - reg = <0x100>;
6516 - clocks = <&clockgen 1 1>;
6517 - next-level-cache = <&cluster1_l2>;
6518 - };
6519 -
6520 - cpu@101 {
6521 - device_type = "cpu";
6522 - compatible = "arm,cortex-a57";
6523 - reg = <0x101>;
6524 - clocks = <&clockgen 1 1>;
6525 - next-level-cache = <&cluster1_l2>;
6526 - };
6527 -
6528 - cpu@200 {
6529 - device_type = "cpu";
6530 - compatible = "arm,cortex-a57";
6531 - reg = <0x200>;
6532 - clocks = <&clockgen 1 2>;
6533 - next-level-cache = <&cluster2_l2>;
6534 - };
6535 -
6536 - cpu@201 {
6537 - device_type = "cpu";
6538 - compatible = "arm,cortex-a57";
6539 - reg = <0x201>;
6540 - clocks = <&clockgen 1 2>;
6541 - next-level-cache = <&cluster2_l2>;
6542 - };
6543 -
6544 - cpu@300 {
6545 - device_type = "cpu";
6546 - compatible = "arm,cortex-a57";
6547 - reg = <0x300>;
6548 - clocks = <&clockgen 1 3>;
6549 - next-level-cache = <&cluster3_l2>;
6550 - };
6551 -
6552 - cpu@301 {
6553 - device_type = "cpu";
6554 - compatible = "arm,cortex-a57";
6555 - reg = <0x301>;
6556 - clocks = <&clockgen 1 3>;
6557 - next-level-cache = <&cluster3_l2>;
6558 - };
6559 -
6560 - cluster0_l2: l2-cache0 {
6561 - compatible = "cache";
6562 - };
6563 -
6564 - cluster1_l2: l2-cache1 {
6565 - compatible = "cache";
6566 - };
6567 -
6568 - cluster2_l2: l2-cache2 {
6569 - compatible = "cache";
6570 - };
6571 -
6572 - cluster3_l2: l2-cache3 {
6573 - compatible = "cache";
6574 - };
6575 - };
6576 -
6577 - memory@80000000 {
6578 - device_type = "memory";
6579 - reg = <0x00000000 0x80000000 0 0x80000000>;
6580 - /* DRAM space - 1, size : 2 GB DRAM */
6581 - };
6582 -
6583 - sysclk: sysclk {
6584 - compatible = "fixed-clock";
6585 - #clock-cells = <0>;
6586 - clock-frequency = <100000000>;
6587 - clock-output-names = "sysclk";
6588 - };
6589 -
6590 - gic: interrupt-controller@6000000 {
6591 - compatible = "arm,gic-v3";
6592 - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
6593 - <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
6594 - <0x0 0x0c0c0000 0 0x2000>, /* GICC */
6595 - <0x0 0x0c0d0000 0 0x1000>, /* GICH */
6596 - <0x0 0x0c0e0000 0 0x20000>; /* GICV */
6597 - #interrupt-cells = <3>;
6598 - #address-cells = <2>;
6599 - #size-cells = <2>;
6600 - ranges;
6601 - interrupt-controller;
6602 - interrupts = <1 9 0x4>;
6603 -
6604 - its: gic-its@6020000 {
6605 - compatible = "arm,gic-v3-its";
6606 - msi-controller;
6607 - reg = <0x0 0x6020000 0 0x20000>;
6608 - };
6609 - };
6610 -
6611 - rstcr: syscon@1e60000 {
6612 - compatible = "fsl,ls2080a-rstcr", "syscon";
6613 - reg = <0x0 0x1e60000 0x0 0x4>;
6614 - };
6615 -
6616 - reboot {
6617 - compatible ="syscon-reboot";
6618 - regmap = <&rstcr>;
6619 - offset = <0x0>;
6620 - mask = <0x2>;
6621 - };
6622 -
6623 - timer {
6624 - compatible = "arm,armv8-timer";
6625 - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
6626 - <1 14 4>, /* Physical Non-Secure PPI, active-low */
6627 - <1 11 4>, /* Virtual PPI, active-low */
6628 - <1 10 4>; /* Hypervisor PPI, active-low */
6629 - fsl,erratum-a008585;
6630 - };
6631 -
6632 - pmu {
6633 - compatible = "arm,armv8-pmuv3";
6634 - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
6635 - };
6636 -
6637 - soc {
6638 - compatible = "simple-bus";
6639 - #address-cells = <2>;
6640 - #size-cells = <2>;
6641 - ranges;
6642 -
6643 - clockgen: clocking@1300000 {
6644 - compatible = "fsl,ls2080a-clockgen";
6645 - reg = <0 0x1300000 0 0xa0000>;
6646 - #clock-cells = <2>;
6647 - clocks = <&sysclk>;
6648 - };
6649 -
6650 - serial0: serial@21c0500 {
6651 - compatible = "fsl,ns16550", "ns16550a";
6652 - reg = <0x0 0x21c0500 0x0 0x100>;
6653 - clocks = <&clockgen 4 3>;
6654 - interrupts = <0 32 0x4>; /* Level high type */
6655 - };
6656 -
6657 - serial1: serial@21c0600 {
6658 - compatible = "fsl,ns16550", "ns16550a";
6659 - reg = <0x0 0x21c0600 0x0 0x100>;
6660 - clocks = <&clockgen 4 3>;
6661 - interrupts = <0 32 0x4>; /* Level high type */
6662 - };
6663 -
6664 - cluster1_core0_watchdog: wdt@c000000 {
6665 - compatible = "arm,sp805-wdt", "arm,primecell";
6666 - reg = <0x0 0xc000000 0x0 0x1000>;
6667 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6668 - clock-names = "apb_pclk", "wdog_clk";
6669 - };
6670 -
6671 - cluster1_core1_watchdog: wdt@c010000 {
6672 - compatible = "arm,sp805-wdt", "arm,primecell";
6673 - reg = <0x0 0xc010000 0x0 0x1000>;
6674 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6675 - clock-names = "apb_pclk", "wdog_clk";
6676 - };
6677 -
6678 - cluster2_core0_watchdog: wdt@c100000 {
6679 - compatible = "arm,sp805-wdt", "arm,primecell";
6680 - reg = <0x0 0xc100000 0x0 0x1000>;
6681 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6682 - clock-names = "apb_pclk", "wdog_clk";
6683 - };
6684 -
6685 - cluster2_core1_watchdog: wdt@c110000 {
6686 - compatible = "arm,sp805-wdt", "arm,primecell";
6687 - reg = <0x0 0xc110000 0x0 0x1000>;
6688 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6689 - clock-names = "apb_pclk", "wdog_clk";
6690 - };
6691 -
6692 - cluster3_core0_watchdog: wdt@c200000 {
6693 - compatible = "arm,sp805-wdt", "arm,primecell";
6694 - reg = <0x0 0xc200000 0x0 0x1000>;
6695 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6696 - clock-names = "apb_pclk", "wdog_clk";
6697 - };
6698 -
6699 - cluster3_core1_watchdog: wdt@c210000 {
6700 - compatible = "arm,sp805-wdt", "arm,primecell";
6701 - reg = <0x0 0xc210000 0x0 0x1000>;
6702 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6703 - clock-names = "apb_pclk", "wdog_clk";
6704 - };
6705 -
6706 - cluster4_core0_watchdog: wdt@c300000 {
6707 - compatible = "arm,sp805-wdt", "arm,primecell";
6708 - reg = <0x0 0xc300000 0x0 0x1000>;
6709 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6710 - clock-names = "apb_pclk", "wdog_clk";
6711 - };
6712 -
6713 - cluster4_core1_watchdog: wdt@c310000 {
6714 - compatible = "arm,sp805-wdt", "arm,primecell";
6715 - reg = <0x0 0xc310000 0x0 0x1000>;
6716 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6717 - clock-names = "apb_pclk", "wdog_clk";
6718 - };
6719 -
6720 - fsl_mc: fsl-mc@80c000000 {
6721 - compatible = "fsl,qoriq-mc";
6722 - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
6723 - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
6724 - msi-parent = <&its>;
6725 - #address-cells = <3>;
6726 - #size-cells = <1>;
6727 -
6728 - /*
6729 - * Region type 0x0 - MC portals
6730 - * Region type 0x1 - QBMAN portals
6731 - */
6732 - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
6733 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
6734 -
6735 - /*
6736 - * Define the maximum number of MACs present on the SoC.
6737 - */
6738 - dpmacs {
6739 - #address-cells = <1>;
6740 - #size-cells = <0>;
6741 -
6742 - dpmac1: dpmac@1 {
6743 - compatible = "fsl,qoriq-mc-dpmac";
6744 - reg = <0x1>;
6745 - };
6746 -
6747 - dpmac2: dpmac@2 {
6748 - compatible = "fsl,qoriq-mc-dpmac";
6749 - reg = <0x2>;
6750 - };
6751 -
6752 - dpmac3: dpmac@3 {
6753 - compatible = "fsl,qoriq-mc-dpmac";
6754 - reg = <0x3>;
6755 - };
6756 -
6757 - dpmac4: dpmac@4 {
6758 - compatible = "fsl,qoriq-mc-dpmac";
6759 - reg = <0x4>;
6760 - };
6761 -
6762 - dpmac5: dpmac@5 {
6763 - compatible = "fsl,qoriq-mc-dpmac";
6764 - reg = <0x5>;
6765 - };
6766 -
6767 - dpmac6: dpmac@6 {
6768 - compatible = "fsl,qoriq-mc-dpmac";
6769 - reg = <0x6>;
6770 - };
6771 -
6772 - dpmac7: dpmac@7 {
6773 - compatible = "fsl,qoriq-mc-dpmac";
6774 - reg = <0x7>;
6775 - };
6776 -
6777 - dpmac8: dpmac@8 {
6778 - compatible = "fsl,qoriq-mc-dpmac";
6779 - reg = <0x8>;
6780 - };
6781 -
6782 - dpmac9: dpmac@9 {
6783 - compatible = "fsl,qoriq-mc-dpmac";
6784 - reg = <0x9>;
6785 - };
6786 -
6787 - dpmac10: dpmac@a {
6788 - compatible = "fsl,qoriq-mc-dpmac";
6789 - reg = <0xa>;
6790 - };
6791 -
6792 - dpmac11: dpmac@b {
6793 - compatible = "fsl,qoriq-mc-dpmac";
6794 - reg = <0xb>;
6795 - };
6796 -
6797 - dpmac12: dpmac@c {
6798 - compatible = "fsl,qoriq-mc-dpmac";
6799 - reg = <0xc>;
6800 - };
6801 -
6802 - dpmac13: dpmac@d {
6803 - compatible = "fsl,qoriq-mc-dpmac";
6804 - reg = <0xd>;
6805 - };
6806 -
6807 - dpmac14: dpmac@e {
6808 - compatible = "fsl,qoriq-mc-dpmac";
6809 - reg = <0xe>;
6810 - };
6811 -
6812 - dpmac15: dpmac@f {
6813 - compatible = "fsl,qoriq-mc-dpmac";
6814 - reg = <0xf>;
6815 - };
6816 -
6817 - dpmac16: dpmac@10 {
6818 - compatible = "fsl,qoriq-mc-dpmac";
6819 - reg = <0x10>;
6820 - };
6821 - };
6822 - };
6823 -
6824 - smmu: iommu@5000000 {
6825 - compatible = "arm,mmu-500";
6826 - reg = <0 0x5000000 0 0x800000>;
6827 - #global-interrupts = <12>;
6828 - interrupts = <0 13 4>, /* global secure fault */
6829 - <0 14 4>, /* combined secure interrupt */
6830 - <0 15 4>, /* global non-secure fault */
6831 - <0 16 4>, /* combined non-secure interrupt */
6832 - /* performance counter interrupts 0-7 */
6833 - <0 211 4>, <0 212 4>,
6834 - <0 213 4>, <0 214 4>,
6835 - <0 215 4>, <0 216 4>,
6836 - <0 217 4>, <0 218 4>,
6837 - /* per context interrupt, 64 interrupts */
6838 - <0 146 4>, <0 147 4>,
6839 - <0 148 4>, <0 149 4>,
6840 - <0 150 4>, <0 151 4>,
6841 - <0 152 4>, <0 153 4>,
6842 - <0 154 4>, <0 155 4>,
6843 - <0 156 4>, <0 157 4>,
6844 - <0 158 4>, <0 159 4>,
6845 - <0 160 4>, <0 161 4>,
6846 - <0 162 4>, <0 163 4>,
6847 - <0 164 4>, <0 165 4>,
6848 - <0 166 4>, <0 167 4>,
6849 - <0 168 4>, <0 169 4>,
6850 - <0 170 4>, <0 171 4>,
6851 - <0 172 4>, <0 173 4>,
6852 - <0 174 4>, <0 175 4>,
6853 - <0 176 4>, <0 177 4>,
6854 - <0 178 4>, <0 179 4>,
6855 - <0 180 4>, <0 181 4>,
6856 - <0 182 4>, <0 183 4>,
6857 - <0 184 4>, <0 185 4>,
6858 - <0 186 4>, <0 187 4>,
6859 - <0 188 4>, <0 189 4>,
6860 - <0 190 4>, <0 191 4>,
6861 - <0 192 4>, <0 193 4>,
6862 - <0 194 4>, <0 195 4>,
6863 - <0 196 4>, <0 197 4>,
6864 - <0 198 4>, <0 199 4>,
6865 - <0 200 4>, <0 201 4>,
6866 - <0 202 4>, <0 203 4>,
6867 - <0 204 4>, <0 205 4>,
6868 - <0 206 4>, <0 207 4>,
6869 - <0 208 4>, <0 209 4>;
6870 - mmu-masters = <&fsl_mc 0x300 0>;
6871 - };
6872 -
6873 - dspi: dspi@2100000 {
6874 - status = "disabled";
6875 - compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
6876 - #address-cells = <1>;
6877 - #size-cells = <0>;
6878 - reg = <0x0 0x2100000 0x0 0x10000>;
6879 - interrupts = <0 26 0x4>; /* Level high type */
6880 - clocks = <&clockgen 4 3>;
6881 - clock-names = "dspi";
6882 - spi-num-chipselects = <5>;
6883 - bus-num = <0>;
6884 - };
6885 -
6886 - esdhc: esdhc@2140000 {
6887 - status = "disabled";
6888 - compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
6889 - reg = <0x0 0x2140000 0x0 0x10000>;
6890 - interrupts = <0 28 0x4>; /* Level high type */
6891 - clock-frequency = <0>; /* Updated by bootloader */
6892 - voltage-ranges = <1800 1800 3300 3300>;
6893 - sdhci,auto-cmd12;
6894 - little-endian;
6895 - bus-width = <4>;
6896 - };
6897 -
6898 - gpio0: gpio@2300000 {
6899 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6900 - reg = <0x0 0x2300000 0x0 0x10000>;
6901 - interrupts = <0 36 0x4>; /* Level high type */
6902 - gpio-controller;
6903 - little-endian;
6904 - #gpio-cells = <2>;
6905 - interrupt-controller;
6906 - #interrupt-cells = <2>;
6907 - };
6908 -
6909 - gpio1: gpio@2310000 {
6910 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6911 - reg = <0x0 0x2310000 0x0 0x10000>;
6912 - interrupts = <0 36 0x4>; /* Level high type */
6913 - gpio-controller;
6914 - little-endian;
6915 - #gpio-cells = <2>;
6916 - interrupt-controller;
6917 - #interrupt-cells = <2>;
6918 - };
6919 -
6920 - gpio2: gpio@2320000 {
6921 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6922 - reg = <0x0 0x2320000 0x0 0x10000>;
6923 - interrupts = <0 37 0x4>; /* Level high type */
6924 - gpio-controller;
6925 - little-endian;
6926 - #gpio-cells = <2>;
6927 - interrupt-controller;
6928 - #interrupt-cells = <2>;
6929 - };
6930 -
6931 - gpio3: gpio@2330000 {
6932 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6933 - reg = <0x0 0x2330000 0x0 0x10000>;
6934 - interrupts = <0 37 0x4>; /* Level high type */
6935 - gpio-controller;
6936 - little-endian;
6937 - #gpio-cells = <2>;
6938 - interrupt-controller;
6939 - #interrupt-cells = <2>;
6940 - };
6941 -
6942 - i2c0: i2c@2000000 {
6943 - status = "disabled";
6944 - compatible = "fsl,vf610-i2c";
6945 - #address-cells = <1>;
6946 - #size-cells = <0>;
6947 - reg = <0x0 0x2000000 0x0 0x10000>;
6948 - interrupts = <0 34 0x4>; /* Level high type */
6949 - clock-names = "i2c";
6950 - clocks = <&clockgen 4 3>;
6951 - };
6952 -
6953 - i2c1: i2c@2010000 {
6954 - status = "disabled";
6955 - compatible = "fsl,vf610-i2c";
6956 - #address-cells = <1>;
6957 - #size-cells = <0>;
6958 - reg = <0x0 0x2010000 0x0 0x10000>;
6959 - interrupts = <0 34 0x4>; /* Level high type */
6960 - clock-names = "i2c";
6961 - clocks = <&clockgen 4 3>;
6962 - };
6963 -
6964 - i2c2: i2c@2020000 {
6965 - status = "disabled";
6966 - compatible = "fsl,vf610-i2c";
6967 - #address-cells = <1>;
6968 - #size-cells = <0>;
6969 - reg = <0x0 0x2020000 0x0 0x10000>;
6970 - interrupts = <0 35 0x4>; /* Level high type */
6971 - clock-names = "i2c";
6972 - clocks = <&clockgen 4 3>;
6973 - };
6974 -
6975 - i2c3: i2c@2030000 {
6976 - status = "disabled";
6977 - compatible = "fsl,vf610-i2c";
6978 - #address-cells = <1>;
6979 - #size-cells = <0>;
6980 - reg = <0x0 0x2030000 0x0 0x10000>;
6981 - interrupts = <0 35 0x4>; /* Level high type */
6982 - clock-names = "i2c";
6983 - clocks = <&clockgen 4 3>;
6984 - };
6985 -
6986 - ifc: ifc@2240000 {
6987 - compatible = "fsl,ifc", "simple-bus";
6988 - reg = <0x0 0x2240000 0x0 0x20000>;
6989 - interrupts = <0 21 0x4>; /* Level high type */
6990 - little-endian;
6991 - #address-cells = <2>;
6992 - #size-cells = <1>;
6993 -
6994 - ranges = <0 0 0x5 0x80000000 0x08000000
6995 - 2 0 0x5 0x30000000 0x00010000
6996 - 3 0 0x5 0x20000000 0x00010000>;
6997 - };
6998 -
6999 - qspi: quadspi@20c0000 {
7000 - status = "disabled";
7001 - compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
7002 - #address-cells = <1>;
7003 - #size-cells = <0>;
7004 - reg = <0x0 0x20c0000 0x0 0x10000>,
7005 - <0x0 0x20000000 0x0 0x10000000>;
7006 - reg-names = "QuadSPI", "QuadSPI-memory";
7007 - interrupts = <0 25 0x4>; /* Level high type */
7008 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7009 - clock-names = "qspi_en", "qspi";
7010 - };
7011 -
7012 - pcie@3400000 {
7013 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7014 - "snps,dw-pcie";
7015 - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7016 - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7017 - reg-names = "regs", "config";
7018 - interrupts = <0 108 0x4>; /* Level high type */
7019 - interrupt-names = "intr";
7020 - #address-cells = <3>;
7021 - #size-cells = <2>;
7022 - device_type = "pci";
7023 - dma-coherent;
7024 - num-lanes = <4>;
7025 - bus-range = <0x0 0xff>;
7026 - ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7027 - 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7028 - msi-parent = <&its>;
7029 - #interrupt-cells = <1>;
7030 - interrupt-map-mask = <0 0 0 7>;
7031 - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
7032 - <0000 0 0 2 &gic 0 0 0 110 4>,
7033 - <0000 0 0 3 &gic 0 0 0 111 4>,
7034 - <0000 0 0 4 &gic 0 0 0 112 4>;
7035 - };
7036 -
7037 - pcie@3500000 {
7038 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7039 - "snps,dw-pcie";
7040 - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7041 - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7042 - reg-names = "regs", "config";
7043 - interrupts = <0 113 0x4>; /* Level high type */
7044 - interrupt-names = "intr";
7045 - #address-cells = <3>;
7046 - #size-cells = <2>;
7047 - device_type = "pci";
7048 - dma-coherent;
7049 - num-lanes = <4>;
7050 - bus-range = <0x0 0xff>;
7051 - ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7052 - 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7053 - msi-parent = <&its>;
7054 - #interrupt-cells = <1>;
7055 - interrupt-map-mask = <0 0 0 7>;
7056 - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
7057 - <0000 0 0 2 &gic 0 0 0 115 4>,
7058 - <0000 0 0 3 &gic 0 0 0 116 4>,
7059 - <0000 0 0 4 &gic 0 0 0 117 4>;
7060 - };
7061 -
7062 - pcie@3600000 {
7063 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7064 - "snps,dw-pcie";
7065 - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7066 - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7067 - reg-names = "regs", "config";
7068 - interrupts = <0 118 0x4>; /* Level high type */
7069 - interrupt-names = "intr";
7070 - #address-cells = <3>;
7071 - #size-cells = <2>;
7072 - device_type = "pci";
7073 - dma-coherent;
7074 - num-lanes = <8>;
7075 - bus-range = <0x0 0xff>;
7076 - ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7077 - 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7078 - msi-parent = <&its>;
7079 - #interrupt-cells = <1>;
7080 - interrupt-map-mask = <0 0 0 7>;
7081 - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
7082 - <0000 0 0 2 &gic 0 0 0 120 4>,
7083 - <0000 0 0 3 &gic 0 0 0 121 4>,
7084 - <0000 0 0 4 &gic 0 0 0 122 4>;
7085 - };
7086 -
7087 - pcie@3700000 {
7088 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7089 - "snps,dw-pcie";
7090 - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7091 - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7092 - reg-names = "regs", "config";
7093 - interrupts = <0 123 0x4>; /* Level high type */
7094 - interrupt-names = "intr";
7095 - #address-cells = <3>;
7096 - #size-cells = <2>;
7097 - device_type = "pci";
7098 - dma-coherent;
7099 - num-lanes = <4>;
7100 - bus-range = <0x0 0xff>;
7101 - ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7102 - 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7103 - msi-parent = <&its>;
7104 - #interrupt-cells = <1>;
7105 - interrupt-map-mask = <0 0 0 7>;
7106 - interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
7107 - <0000 0 0 2 &gic 0 0 0 125 4>,
7108 - <0000 0 0 3 &gic 0 0 0 126 4>,
7109 - <0000 0 0 4 &gic 0 0 0 127 4>;
7110 - };
7111 -
7112 - sata0: sata@3200000 {
7113 - status = "disabled";
7114 - compatible = "fsl,ls2080a-ahci";
7115 - reg = <0x0 0x3200000 0x0 0x10000>;
7116 - interrupts = <0 133 0x4>; /* Level high type */
7117 - clocks = <&clockgen 4 3>;
7118 - dma-coherent;
7119 - };
7120 -
7121 - sata1: sata@3210000 {
7122 - status = "disabled";
7123 - compatible = "fsl,ls2080a-ahci";
7124 - reg = <0x0 0x3210000 0x0 0x10000>;
7125 - interrupts = <0 136 0x4>; /* Level high type */
7126 - clocks = <&clockgen 4 3>;
7127 - dma-coherent;
7128 - };
7129 -
7130 - usb0: usb3@3100000 {
7131 - status = "disabled";
7132 - compatible = "snps,dwc3";
7133 - reg = <0x0 0x3100000 0x0 0x10000>;
7134 - interrupts = <0 80 0x4>; /* Level high type */
7135 - dr_mode = "host";
7136 - snps,quirk-frame-length-adjustment = <0x20>;
7137 - snps,dis_rxdet_inp3_quirk;
7138 - };
7139 -
7140 - usb1: usb3@3110000 {
7141 - status = "disabled";
7142 - compatible = "snps,dwc3";
7143 - reg = <0x0 0x3110000 0x0 0x10000>;
7144 - interrupts = <0 81 0x4>; /* Level high type */
7145 - dr_mode = "host";
7146 - snps,quirk-frame-length-adjustment = <0x20>;
7147 - snps,dis_rxdet_inp3_quirk;
7148 - };
7149 -
7150 - ccn@4000000 {
7151 - compatible = "arm,ccn-504";
7152 - reg = <0x0 0x04000000 0x0 0x01000000>;
7153 - interrupts = <0 12 4>;
7154 - };
7155 - };
7156 -
7157 - ddr1: memory-controller@1080000 {
7158 - compatible = "fsl,qoriq-memory-controller";
7159 - reg = <0x0 0x1080000 0x0 0x1000>;
7160 - interrupts = <0 17 0x4>;
7161 - little-endian;
7162 - };
7163 -
7164 - ddr2: memory-controller@1090000 {
7165 - compatible = "fsl,qoriq-memory-controller";
7166 - reg = <0x0 0x1090000 0x0 0x1000>;
7167 - interrupts = <0 18 0x4>;
7168 - little-endian;
7169 +#include "fsl-ls208xa.dtsi"
7170 +
7171 +&cpu {
7172 + cpu0: cpu@0 {
7173 + device_type = "cpu";
7174 + compatible = "arm,cortex-a57";
7175 + reg = <0x0>;
7176 + clocks = <&clockgen 1 0>;
7177 + next-level-cache = <&cluster0_l2>;
7178 + #cooling-cells = <2>;
7179 + };
7180 +
7181 + cpu1: cpu@1 {
7182 + device_type = "cpu";
7183 + compatible = "arm,cortex-a57";
7184 + reg = <0x1>;
7185 + clocks = <&clockgen 1 0>;
7186 + next-level-cache = <&cluster0_l2>;
7187 + };
7188 +
7189 + cpu2: cpu@100 {
7190 + device_type = "cpu";
7191 + compatible = "arm,cortex-a57";
7192 + reg = <0x100>;
7193 + clocks = <&clockgen 1 1>;
7194 + next-level-cache = <&cluster1_l2>;
7195 + #cooling-cells = <2>;
7196 + };
7197 +
7198 + cpu3: cpu@101 {
7199 + device_type = "cpu";
7200 + compatible = "arm,cortex-a57";
7201 + reg = <0x101>;
7202 + clocks = <&clockgen 1 1>;
7203 + next-level-cache = <&cluster1_l2>;
7204 + };
7205 +
7206 + cpu4: cpu@200 {
7207 + device_type = "cpu";
7208 + compatible = "arm,cortex-a57";
7209 + reg = <0x200>;
7210 + clocks = <&clockgen 1 2>;
7211 + next-level-cache = <&cluster2_l2>;
7212 + #cooling-cells = <2>;
7213 + };
7214 +
7215 + cpu5: cpu@201 {
7216 + device_type = "cpu";
7217 + compatible = "arm,cortex-a57";
7218 + reg = <0x201>;
7219 + clocks = <&clockgen 1 2>;
7220 + next-level-cache = <&cluster2_l2>;
7221 + };
7222 +
7223 + cpu6: cpu@300 {
7224 + device_type = "cpu";
7225 + compatible = "arm,cortex-a57";
7226 + reg = <0x300>;
7227 + clocks = <&clockgen 1 3>;
7228 + next-level-cache = <&cluster3_l2>;
7229 + #cooling-cells = <2>;
7230 + };
7231 +
7232 + cpu7: cpu@301 {
7233 + device_type = "cpu";
7234 + compatible = "arm,cortex-a57";
7235 + reg = <0x301>;
7236 + clocks = <&clockgen 1 3>;
7237 + next-level-cache = <&cluster3_l2>;
7238 };
7239 +
7240 + cluster0_l2: l2-cache0 {
7241 + compatible = "cache";
7242 + };
7243 +
7244 + cluster1_l2: l2-cache1 {
7245 + compatible = "cache";
7246 + };
7247 +
7248 + cluster2_l2: l2-cache2 {
7249 + compatible = "cache";
7250 + };
7251 +
7252 + cluster3_l2: l2-cache3 {
7253 + compatible = "cache";
7254 + };
7255 +};
7256 +
7257 +&usb0 {
7258 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7259 + snps,dma-snooping;
7260 +};
7261 +
7262 +&usb1 {
7263 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7264 + snps,dma-snooping;
7265 +};
7266 +
7267 +&pcie1 {
7268 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7269 + 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7270 +
7271 + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7272 + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7273 +};
7274 +
7275 +&pcie2 {
7276 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7277 + 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7278 +
7279 + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7280 + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7281 +};
7282 +
7283 +&pcie3 {
7284 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7285 + 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7286 +
7287 + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7288 + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7289 +};
7290 +
7291 +&pcie4 {
7292 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7293 + 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7294 +
7295 + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7296 + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7297 };
7298 --- /dev/null
7299 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
7300 @@ -0,0 +1,161 @@
7301 +/*
7302 + * Device Tree file for NXP LS2081A RDB Board.
7303 + *
7304 + * Copyright 2017 NXP
7305 + *
7306 + * Priyanka Jain <priyanka.jain@nxp.com>
7307 + *
7308 + * This file is dual-licensed: you can use it either under the terms
7309 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7310 + * licensing only applies to this file, and not this project as a
7311 + * whole.
7312 + *
7313 + * a) This library is free software; you can redistribute it and/or
7314 + * modify it under the terms of the GNU General Public License as
7315 + * published by the Free Software Foundation; either version 2 of the
7316 + * License, or (at your option) any later version.
7317 + *
7318 + * This library is distributed in the hope that it will be useful,
7319 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7320 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7321 + * GNU General Public License for more details.
7322 + *
7323 + * Or, alternatively,
7324 + *
7325 + * b) Permission is hereby granted, free of charge, to any person
7326 + * obtaining a copy of this software and associated documentation
7327 + * files (the "Software"), to deal in the Software without
7328 + * restriction, including without limitation the rights to use,
7329 + * copy, modify, merge, publish, distribute, sublicense, and/or
7330 + * sell copies of the Software, and to permit persons to whom the
7331 + * Software is furnished to do so, subject to the following
7332 + * conditions:
7333 + *
7334 + * The above copyright notice and this permission notice shall be
7335 + * included in all copies or substantial portions of the Software.
7336 + *
7337 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7338 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7339 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7340 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7341 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7342 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7343 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7344 + * OTHER DEALINGS IN THE SOFTWARE.
7345 + */
7346 +
7347 +/dts-v1/;
7348 +
7349 +#include "fsl-ls2088a.dtsi"
7350 +
7351 +/ {
7352 + model = "NXP Layerscape 2081A RDB Board";
7353 + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
7354 +
7355 + aliases {
7356 + serial0 = &serial0;
7357 + serial1 = &serial1;
7358 + };
7359 +
7360 + chosen {
7361 + stdout-path = "serial1:115200n8";
7362 + };
7363 +};
7364 +
7365 +&esdhc {
7366 + status = "okay";
7367 +};
7368 +
7369 +&ifc {
7370 + status = "disabled";
7371 +};
7372 +
7373 +&i2c0 {
7374 + status = "okay";
7375 + pca9547@75 {
7376 + compatible = "nxp,pca9547";
7377 + reg = <0x75>;
7378 + #address-cells = <1>;
7379 + #size-cells = <0>;
7380 + i2c@1 {
7381 + #address-cells = <1>;
7382 + #size-cells = <0>;
7383 + reg = <0x01>;
7384 + rtc@51 {
7385 + compatible = "nxp,pcf2129";
7386 + reg = <0x51>;
7387 + };
7388 + };
7389 +
7390 + i2c@2 {
7391 + #address-cells = <1>;
7392 + #size-cells = <0>;
7393 + reg = <0x02>;
7394 +
7395 + ina220@40 {
7396 + compatible = "ti,ina220";
7397 + reg = <0x40>;
7398 + shunt-resistor = <500>;
7399 + };
7400 + };
7401 +
7402 + i2c@3 {
7403 + #address-cells = <1>;
7404 + #size-cells = <0>;
7405 + reg = <0x3>;
7406 +
7407 + adt7481@4c {
7408 + compatible = "adi,adt7461";
7409 + reg = <0x4c>;
7410 + };
7411 + };
7412 + };
7413 +};
7414 +
7415 +&dspi {
7416 + status = "okay";
7417 + dflash0: n25q512a {
7418 + #address-cells = <1>;
7419 + #size-cells = <1>;
7420 + compatible = "st,m25p80";
7421 + spi-max-frequency = <3000000>;
7422 + reg = <0>;
7423 + };
7424 +};
7425 +
7426 +&qspi {
7427 + status = "okay";
7428 + fsl,qspi-has-second-chip;
7429 + flash0: s25fs512s@0 {
7430 + #address-cells = <1>;
7431 + #size-cells = <1>;
7432 + compatible = "spansion,m25p80";
7433 + m25p,fast-read;
7434 + spi-max-frequency = <20000000>;
7435 + reg = <0>;
7436 + };
7437 + flash1: s25fs512s@1 {
7438 + #address-cells = <1>;
7439 + #size-cells = <1>;
7440 + compatible = "spansion,m25p80";
7441 + m25p,fast-read;
7442 + spi-max-frequency = <20000000>;
7443 + reg = <1>;
7444 + };
7445 +};
7446 +
7447 +&sata0 {
7448 + status = "okay";
7449 +};
7450 +
7451 +&sata1 {
7452 + status = "okay";
7453 +};
7454 +
7455 +&usb0 {
7456 + status = "okay";
7457 +};
7458 +
7459 +&usb1 {
7460 + status = "okay";
7461 +};
7462 --- /dev/null
7463 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
7464 @@ -0,0 +1,162 @@
7465 +/*
7466 + * Device Tree file for Freescale LS2088A QDS Board.
7467 + *
7468 + * Copyright 2016 Freescale Semiconductor, Inc.
7469 + * Copyright 2017 NXP
7470 + *
7471 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7472 + *
7473 + * This file is dual-licensed: you can use it either under the terms
7474 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7475 + * licensing only applies to this file, and not this project as a
7476 + * whole.
7477 + *
7478 + * a) This library is free software; you can redistribute it and/or
7479 + * modify it under the terms of the GNU General Public License as
7480 + * published by the Free Software Foundation; either version 2 of the
7481 + * License, or (at your option) any later version.
7482 + *
7483 + * This library is distributed in the hope that it will be useful,
7484 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7485 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7486 + * GNU General Public License for more details.
7487 + *
7488 + * Or, alternatively,
7489 + *
7490 + * b) Permission is hereby granted, free of charge, to any person
7491 + * obtaining a copy of this software and associated documentation
7492 + * files (the "Software"), to deal in the Software without
7493 + * restriction, including without limitation the rights to use,
7494 + * copy, modify, merge, publish, distribute, sublicense, and/or
7495 + * sell copies of the Software, and to permit persons to whom the
7496 + * Software is furnished to do so, subject to the following
7497 + * conditions:
7498 + *
7499 + * The above copyright notice and this permission notice shall be
7500 + * included in all copies or substantial portions of the Software.
7501 + *
7502 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7503 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7504 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7505 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7506 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7507 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7508 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7509 + * OTHER DEALINGS IN THE SOFTWARE.
7510 + */
7511 +
7512 +/dts-v1/;
7513 +
7514 +#include "fsl-ls2088a.dtsi"
7515 +#include "fsl-ls208xa-qds.dtsi"
7516 +
7517 +/ {
7518 + model = "Freescale Layerscape 2088A QDS Board";
7519 + compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
7520 +
7521 + chosen {
7522 + stdout-path = "serial0:115200n8";
7523 + };
7524 +};
7525 +
7526 +&ifc {
7527 + boardctrl: board-control@3,0 {
7528 + #address-cells = <1>;
7529 + #size-cells = <1>;
7530 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
7531 + reg = <3 0 0x300>; /* TODO check address */
7532 + ranges = <0 3 0 0x300>;
7533 +
7534 + mdio_mux_emi1 {
7535 + compatible = "mdio-mux-mmioreg", "mdio-mux";
7536 + mdio-parent-bus = <&emdio1>;
7537 + reg = <0x54 1>; /* BRDCFG4 */
7538 + mux-mask = <0xe0>; /* EMI1_MDIO */
7539 +
7540 + #address-cells=<1>;
7541 + #size-cells = <0>;
7542 +
7543 + /* Child MDIO buses, one for each riser card:
7544 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
7545 + * VSC8234 PHYs on the riser cards.
7546 + */
7547 +
7548 + mdio_mux3: mdio@60 {
7549 + reg = <0x60>;
7550 + #address-cells = <1>;
7551 + #size-cells = <0>;
7552 +
7553 + mdio0_phy12: mdio_phy0@1c {
7554 + reg = <0x1c>;
7555 + phy-connection-type = "sgmii";
7556 + };
7557 + mdio0_phy13: mdio_phy1@1d {
7558 + reg = <0x1d>;
7559 + phy-connection-type = "sgmii";
7560 + };
7561 + mdio0_phy14: mdio_phy2@1e {
7562 + reg = <0x1e>;
7563 + phy-connection-type = "sgmii";
7564 + };
7565 + mdio0_phy15: mdio_phy3@1f {
7566 + reg = <0x1f>;
7567 + phy-connection-type = "sgmii";
7568 + };
7569 + };
7570 + };
7571 + };
7572 +};
7573 +
7574 +&pcs_mdio1 {
7575 + pcs_phy1: ethernet-phy@0 {
7576 + backplane-mode = "10gbase-kr";
7577 + compatible = "ethernet-phy-ieee802.3-c45";
7578 + reg = <0x0>;
7579 + fsl,lane-handle = <&serdes1>;
7580 + fsl,lane-reg = <0x9C0 0x40>;/* lane H */
7581 + };
7582 +};
7583 +
7584 +&pcs_mdio2 {
7585 + pcs_phy2: ethernet-phy@0 {
7586 + backplane-mode = "10gbase-kr";
7587 + compatible = "ethernet-phy-ieee802.3-c45";
7588 + reg = <0x0>;
7589 + fsl,lane-handle = <&serdes1>;
7590 + fsl,lane-reg = <0x980 0x40>;/* lane G */
7591 + };
7592 +};
7593 +
7594 +&pcs_mdio3 {
7595 + pcs_phy3: ethernet-phy@0 {
7596 + backplane-mode = "10gbase-kr";
7597 + compatible = "ethernet-phy-ieee802.3-c45";
7598 + reg = <0x0>;
7599 + fsl,lane-handle = <&serdes1>;
7600 + fsl,lane-reg = <0x940 0x40>;/* lane F */
7601 + };
7602 +};
7603 +
7604 +&pcs_mdio4 {
7605 + pcs_phy4: ethernet-phy@0 {
7606 + backplane-mode = "10gbase-kr";
7607 + compatible = "ethernet-phy-ieee802.3-c45";
7608 + reg = <0x0>;
7609 + fsl,lane-handle = <&serdes1>;
7610 + fsl,lane-reg = <0x900 0x40>;/* lane E */
7611 + };
7612 +};
7613 +
7614 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
7615 +&dpmac9 {
7616 + phy-handle = <&mdio0_phy12>;
7617 +};
7618 +&dpmac10 {
7619 + phy-handle = <&mdio0_phy13>;
7620 +};
7621 +&dpmac11 {
7622 + phy-handle = <&mdio0_phy14>;
7623 +};
7624 +&dpmac12 {
7625 + phy-handle = <&mdio0_phy15>;
7626 +};
7627 --- /dev/null
7628 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
7629 @@ -0,0 +1,140 @@
7630 +/*
7631 + * Device Tree file for Freescale LS2088A RDB Board.
7632 + *
7633 + * Copyright 2016 Freescale Semiconductor, Inc.
7634 + * Copyright 2017 NXP
7635 + *
7636 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7637 + *
7638 + * This file is dual-licensed: you can use it either under the terms
7639 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7640 + * licensing only applies to this file, and not this project as a
7641 + * whole.
7642 + *
7643 + * a) This library is free software; you can redistribute it and/or
7644 + * modify it under the terms of the GNU General Public License as
7645 + * published by the Free Software Foundation; either version 2 of the
7646 + * License, or (at your option) any later version.
7647 + *
7648 + * This library is distributed in the hope that it will be useful,
7649 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7650 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7651 + * GNU General Public License for more details.
7652 + *
7653 + * Or, alternatively,
7654 + *
7655 + * b) Permission is hereby granted, free of charge, to any person
7656 + * obtaining a copy of this software and associated documentation
7657 + * files (the "Software"), to deal in the Software without
7658 + * restriction, including without limitation the rights to use,
7659 + * copy, modify, merge, publish, distribute, sublicense, and/or
7660 + * sell copies of the Software, and to permit persons to whom the
7661 + * Software is furnished to do so, subject to the following
7662 + * conditions:
7663 + *
7664 + * The above copyright notice and this permission notice shall be
7665 + * included in all copies or substantial portions of the Software.
7666 + *
7667 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7668 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7669 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7670 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7671 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7672 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7673 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7674 + * OTHER DEALINGS IN THE SOFTWARE.
7675 + */
7676 +
7677 +/dts-v1/;
7678 +
7679 +#include "fsl-ls2088a.dtsi"
7680 +#include "fsl-ls208xa-rdb.dtsi"
7681 +
7682 +/ {
7683 + model = "Freescale Layerscape 2088A RDB Board";
7684 + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
7685 +
7686 + chosen {
7687 + stdout-path = "serial1:115200n8";
7688 + };
7689 +};
7690 +
7691 +&emdio1 {
7692 + status = "disabled";
7693 + /* CS4340 PHYs */
7694 + mdio1_phy1: emdio1_phy@1 {
7695 + reg = <0x10>;
7696 + phy-connection-type = "xfi";
7697 + };
7698 + mdio1_phy2: emdio1_phy@2 {
7699 + reg = <0x11>;
7700 + phy-connection-type = "xfi";
7701 + };
7702 + mdio1_phy3: emdio1_phy@3 {
7703 + reg = <0x12>;
7704 + phy-connection-type = "xfi";
7705 + };
7706 + mdio1_phy4: emdio1_phy@4 {
7707 + reg = <0x13>;
7708 + phy-connection-type = "xfi";
7709 + };
7710 +};
7711 +
7712 +&emdio2 {
7713 + /* AQR405 PHYs */
7714 + mdio2_phy1: emdio2_phy@1 {
7715 + compatible = "ethernet-phy-ieee802.3-c45";
7716 + interrupts = <0 1 0x4>; /* Level high type */
7717 + reg = <0x0>;
7718 + phy-connection-type = "xfi";
7719 + };
7720 + mdio2_phy2: emdio2_phy@2 {
7721 + compatible = "ethernet-phy-ieee802.3-c45";
7722 + interrupts = <0 2 0x4>; /* Level high type */
7723 + reg = <0x1>;
7724 + phy-connection-type = "xfi";
7725 + };
7726 + mdio2_phy3: emdio2_phy@3 {
7727 + compatible = "ethernet-phy-ieee802.3-c45";
7728 + interrupts = <0 4 0x4>; /* Level high type */
7729 + reg = <0x2>;
7730 + phy-connection-type = "xfi";
7731 + };
7732 + mdio2_phy4: emdio2_phy@4 {
7733 + compatible = "ethernet-phy-ieee802.3-c45";
7734 + interrupts = <0 5 0x4>; /* Level high type */
7735 + reg = <0x3>;
7736 + phy-connection-type = "xfi";
7737 + };
7738 +};
7739 +
7740 +/* Update DPMAC connections to external PHYs, under the assumption of
7741 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
7742 + */
7743 +/* Leave Cortina PHYs commented out until proper driver is integrated
7744 + *&dpmac1 {
7745 + * phy-handle = <&mdio1_phy1>;
7746 + *};
7747 + *&dpmac2 {
7748 + * phy-handle = <&mdio1_phy2>;
7749 + *};
7750 + *&dpmac3 {
7751 + * phy-handle = <&mdio1_phy3>;
7752 + *};
7753 + *&dpmac4 {
7754 + * phy-handle = <&mdio1_phy4>;
7755 + *};
7756 + */
7757 +
7758 +&dpmac5 {
7759 + phy-handle = <&mdio2_phy1>;
7760 +};
7761 +&dpmac6 {
7762 + phy-handle = <&mdio2_phy2>;
7763 +};
7764 +&dpmac7 {
7765 + phy-handle = <&mdio2_phy3>;
7766 +};
7767 +&dpmac8 {
7768 + phy-handle = <&mdio2_phy4>;
7769 +};
7770 --- /dev/null
7771 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
7772 @@ -0,0 +1,195 @@
7773 +/*
7774 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
7775 + *
7776 + * Copyright 2016 Freescale Semiconductor, Inc.
7777 + * Copyright 2017 NXP
7778 + *
7779 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7780 + *
7781 + * This file is dual-licensed: you can use it either under the terms
7782 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7783 + * licensing only applies to this file, and not this project as a
7784 + * whole.
7785 + *
7786 + * a) This library is free software; you can redistribute it and/or
7787 + * modify it under the terms of the GNU General Public License as
7788 + * published by the Free Software Foundation; either version 2 of the
7789 + * License, or (at your option) any later version.
7790 + *
7791 + * This library is distributed in the hope that it will be useful,
7792 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7793 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7794 + * GNU General Public License for more details.
7795 + *
7796 + * Or, alternatively,
7797 + *
7798 + * b) Permission is hereby granted, free of charge, to any person
7799 + * obtaining a copy of this software and associated documentation
7800 + * files (the "Software"), to deal in the Software without
7801 + * restriction, including without limitation the rights to use,
7802 + * copy, modify, merge, publish, distribute, sublicense, and/or
7803 + * sell copies of the Software, and to permit persons to whom the
7804 + * Software is furnished to do so, subject to the following
7805 + * conditions:
7806 + *
7807 + * The above copyright notice and this permission notice shall be
7808 + * included in all copies or substantial portions of the Software.
7809 + *
7810 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7811 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7812 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7813 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7814 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7815 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7816 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7817 + * OTHER DEALINGS IN THE SOFTWARE.
7818 + */
7819 +
7820 +#include "fsl-ls208xa.dtsi"
7821 +
7822 +&cpu {
7823 + cpu0: cpu@0 {
7824 + device_type = "cpu";
7825 + compatible = "arm,cortex-a72";
7826 + reg = <0x0>;
7827 + clocks = <&clockgen 1 0>;
7828 + next-level-cache = <&cluster0_l2>;
7829 + #cooling-cells = <2>;
7830 + cpu-idle-states = <&CPU_PH20>;
7831 + };
7832 +
7833 + cpu1: cpu@1 {
7834 + device_type = "cpu";
7835 + compatible = "arm,cortex-a72";
7836 + reg = <0x1>;
7837 + clocks = <&clockgen 1 0>;
7838 + next-level-cache = <&cluster0_l2>;
7839 + cpu-idle-states = <&CPU_PH20>;
7840 + };
7841 +
7842 + cpu2: cpu@100 {
7843 + device_type = "cpu";
7844 + compatible = "arm,cortex-a72";
7845 + reg = <0x100>;
7846 + clocks = <&clockgen 1 1>;
7847 + next-level-cache = <&cluster1_l2>;
7848 + #cooling-cells = <2>;
7849 + cpu-idle-states = <&CPU_PH20>;
7850 + };
7851 +
7852 + cpu3: cpu@101 {
7853 + device_type = "cpu";
7854 + compatible = "arm,cortex-a72";
7855 + reg = <0x101>;
7856 + clocks = <&clockgen 1 1>;
7857 + next-level-cache = <&cluster1_l2>;
7858 + cpu-idle-states = <&CPU_PH20>;
7859 + };
7860 +
7861 + cpu4: cpu@200 {
7862 + device_type = "cpu";
7863 + compatible = "arm,cortex-a72";
7864 + reg = <0x200>;
7865 + clocks = <&clockgen 1 2>;
7866 + next-level-cache = <&cluster2_l2>;
7867 + #cooling-cells = <2>;
7868 + cpu-idle-states = <&CPU_PH20>;
7869 + };
7870 +
7871 + cpu5: cpu@201 {
7872 + device_type = "cpu";
7873 + compatible = "arm,cortex-a72";
7874 + reg = <0x201>;
7875 + clocks = <&clockgen 1 2>;
7876 + next-level-cache = <&cluster2_l2>;
7877 + cpu-idle-states = <&CPU_PH20>;
7878 + };
7879 +
7880 + cpu6: cpu@300 {
7881 + device_type = "cpu";
7882 + compatible = "arm,cortex-a72";
7883 + reg = <0x300>;
7884 + clocks = <&clockgen 1 3>;
7885 + next-level-cache = <&cluster3_l2>;
7886 + #cooling-cells = <2>;
7887 + cpu-idle-states = <&CPU_PH20>;
7888 + };
7889 +
7890 + cpu7: cpu@301 {
7891 + device_type = "cpu";
7892 + compatible = "arm,cortex-a72";
7893 + reg = <0x301>;
7894 + clocks = <&clockgen 1 3>;
7895 + next-level-cache = <&cluster3_l2>;
7896 + cpu-idle-states = <&CPU_PH20>;
7897 + };
7898 +
7899 + idle-states {
7900 + /*
7901 + * PSCI node is not added default, U-boot will add missing
7902 + * parts if it determines to use PSCI.
7903 + */
7904 + entry-method = "arm,psci";
7905 +
7906 + CPU_PH20: cpu-ph20 {
7907 + compatible = "arm,idle-state";
7908 + idle-state-name = "PH20";
7909 + arm,psci-suspend-param = <0x0>;
7910 + entry-latency-us = <1000>;
7911 + exit-latency-us = <1000>;
7912 + min-residency-us = <3000>;
7913 + };
7914 + };
7915 +
7916 + cluster0_l2: l2-cache0 {
7917 + compatible = "cache";
7918 + };
7919 +
7920 + cluster1_l2: l2-cache1 {
7921 + compatible = "cache";
7922 + };
7923 +
7924 + cluster2_l2: l2-cache2 {
7925 + compatible = "cache";
7926 + };
7927 +
7928 + cluster3_l2: l2-cache3 {
7929 + compatible = "cache";
7930 + };
7931 +};
7932 +
7933 +&pcie1 {
7934 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7935 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7936 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
7937 +
7938 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
7939 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
7940 +};
7941 +
7942 +&pcie2 {
7943 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7944 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7945 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
7946 +
7947 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
7948 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
7949 +};
7950 +
7951 +&pcie3 {
7952 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7953 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7954 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
7955 +
7956 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
7957 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
7958 +};
7959 +
7960 +&pcie4 {
7961 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7962 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7963 + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
7964 +
7965 + ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
7966 + 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
7967 +};
7968 --- /dev/null
7969 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
7970 @@ -0,0 +1,198 @@
7971 +/*
7972 + * Device Tree file for Freescale LS2080A QDS Board.
7973 + *
7974 + * Copyright 2016 Freescale Semiconductor, Inc.
7975 + * Copyright 2017 NXP
7976 + *
7977 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7978 + *
7979 + * This file is dual-licensed: you can use it either under the terms
7980 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7981 + * licensing only applies to this file, and not this project as a
7982 + * whole.
7983 + *
7984 + * a) This library is free software; you can redistribute it and/or
7985 + * modify it under the terms of the GNU General Public License as
7986 + * published by the Free Software Foundation; either version 2 of the
7987 + * License, or (at your option) any later version.
7988 + *
7989 + * This library is distributed in the hope that it will be useful,
7990 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7991 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7992 + * GNU General Public License for more details.
7993 + *
7994 + * Or, alternatively,
7995 + *
7996 + * b) Permission is hereby granted, free of charge, to any person
7997 + * obtaining a copy of this software and associated documentation
7998 + * files (the "Software"), to deal in the Software without
7999 + * restriction, including without limitation the rights to use,
8000 + * copy, modify, merge, publish, distribute, sublicense, and/or
8001 + * sell copies of the Software, and to permit persons to whom the
8002 + * Software is furnished to do so, subject to the following
8003 + * conditions:
8004 + *
8005 + * The above copyright notice and this permission notice shall be
8006 + * included in all copies or substantial portions of the Software.
8007 + *
8008 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8009 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8010 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8011 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8012 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8013 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8014 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8015 + * OTHER DEALINGS IN THE SOFTWARE.
8016 + */
8017 +
8018 +&esdhc {
8019 + mmc-hs200-1_8v;
8020 + status = "okay";
8021 +};
8022 +
8023 +&ifc {
8024 + status = "okay";
8025 + #address-cells = <2>;
8026 + #size-cells = <1>;
8027 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8028 + 0x2 0x0 0x5 0x30000000 0x00010000
8029 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8030 +
8031 + nor@0,0 {
8032 + #address-cells = <1>;
8033 + #size-cells = <1>;
8034 + compatible = "cfi-flash";
8035 + reg = <0x0 0x0 0x8000000>;
8036 + bank-width = <2>;
8037 + device-width = <1>;
8038 + };
8039 +
8040 + nand@2,0 {
8041 + compatible = "fsl,ifc-nand";
8042 + reg = <0x2 0x0 0x10000>;
8043 + };
8044 +
8045 + cpld@3,0 {
8046 + reg = <0x3 0x0 0x10000>;
8047 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8048 + };
8049 +};
8050 +
8051 +&i2c0 {
8052 + status = "okay";
8053 + pca9547@77 {
8054 + compatible = "nxp,pca9547";
8055 + reg = <0x77>;
8056 + #address-cells = <1>;
8057 + #size-cells = <0>;
8058 + i2c@0 {
8059 + #address-cells = <1>;
8060 + #size-cells = <0>;
8061 + reg = <0x00>;
8062 + rtc@68 {
8063 + compatible = "dallas,ds3232";
8064 + reg = <0x68>;
8065 + };
8066 + };
8067 +
8068 + i2c@2 {
8069 + #address-cells = <1>;
8070 + #size-cells = <0>;
8071 + reg = <0x02>;
8072 +
8073 + ina220@40 {
8074 + compatible = "ti,ina220";
8075 + reg = <0x40>;
8076 + shunt-resistor = <500>;
8077 + };
8078 +
8079 + ina220@41 {
8080 + compatible = "ti,ina220";
8081 + reg = <0x41>;
8082 + shunt-resistor = <1000>;
8083 + };
8084 + };
8085 +
8086 + i2c@3 {
8087 + #address-cells = <1>;
8088 + #size-cells = <0>;
8089 + reg = <0x3>;
8090 +
8091 + adt7481@4c {
8092 + compatible = "adi,adt7461";
8093 + reg = <0x4c>;
8094 + };
8095 + };
8096 + };
8097 +};
8098 +
8099 +&i2c1 {
8100 + status = "disabled";
8101 +};
8102 +
8103 +&i2c2 {
8104 + status = "disabled";
8105 +};
8106 +
8107 +&i2c3 {
8108 + status = "disabled";
8109 +};
8110 +
8111 +&dspi {
8112 + status = "okay";
8113 + dflash0: n25q128a {
8114 + #address-cells = <1>;
8115 + #size-cells = <1>;
8116 + compatible = "st,m25p80";
8117 + spi-max-frequency = <3000000>;
8118 + reg = <0>;
8119 + };
8120 + dflash1: sst25wf040b {
8121 + #address-cells = <1>;
8122 + #size-cells = <1>;
8123 + compatible = "st,m25p80";
8124 + spi-max-frequency = <3000000>;
8125 + reg = <1>;
8126 + };
8127 + dflash2: en25s64 {
8128 + #address-cells = <1>;
8129 + #size-cells = <1>;
8130 + compatible = "st,m25p80";
8131 + spi-max-frequency = <3000000>;
8132 + reg = <2>;
8133 + };
8134 +};
8135 +
8136 +&qspi {
8137 + status = "okay";
8138 + flash0: s25fl256s1@0 {
8139 + #address-cells = <1>;
8140 + #size-cells = <1>;
8141 + compatible = "st,m25p80";
8142 + spi-max-frequency = <20000000>;
8143 + reg = <0>;
8144 + };
8145 + flash2: s25fl256s1@2 {
8146 + #address-cells = <1>;
8147 + #size-cells = <1>;
8148 + compatible = "st,m25p80";
8149 + spi-max-frequency = <20000000>;
8150 + reg = <0>;
8151 + };
8152 +};
8153 +
8154 +&sata0 {
8155 + status = "okay";
8156 +};
8157 +
8158 +&sata1 {
8159 + status = "okay";
8160 +};
8161 +
8162 +&usb0 {
8163 + status = "okay";
8164 +};
8165 +
8166 +&usb1 {
8167 + status = "okay";
8168 +};
8169 --- /dev/null
8170 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
8171 @@ -0,0 +1,161 @@
8172 +/*
8173 + * Device Tree file for Freescale LS2080A RDB Board.
8174 + *
8175 + * Copyright 2016 Freescale Semiconductor, Inc.
8176 + * Copyright 2017 NXP
8177 + *
8178 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8179 + *
8180 + * This file is dual-licensed: you can use it either under the terms
8181 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8182 + * licensing only applies to this file, and not this project as a
8183 + * whole.
8184 + *
8185 + * a) This library is free software; you can redistribute it and/or
8186 + * modify it under the terms of the GNU General Public License as
8187 + * published by the Free Software Foundation; either version 2 of the
8188 + * License, or (at your option) any later version.
8189 + *
8190 + * This library is distributed in the hope that it will be useful,
8191 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8192 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8193 + * GNU General Public License for more details.
8194 + *
8195 + * Or, alternatively,
8196 + *
8197 + * b) Permission is hereby granted, free of charge, to any person
8198 + * obtaining a copy of this software and associated documentation
8199 + * files (the "Software"), to deal in the Software without
8200 + * restriction, including without limitation the rights to use,
8201 + * copy, modify, merge, publish, distribute, sublicense, and/or
8202 + * sell copies of the Software, and to permit persons to whom the
8203 + * Software is furnished to do so, subject to the following
8204 + * conditions:
8205 + *
8206 + * The above copyright notice and this permission notice shall be
8207 + * included in all copies or substantial portions of the Software.
8208 + *
8209 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8210 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8211 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8212 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8213 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8214 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8215 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8216 + * OTHER DEALINGS IN THE SOFTWARE.
8217 + */
8218 +
8219 +&esdhc {
8220 + status = "okay";
8221 +};
8222 +
8223 +&ifc {
8224 + status = "okay";
8225 + #address-cells = <2>;
8226 + #size-cells = <1>;
8227 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8228 + 0x2 0x0 0x5 0x30000000 0x00010000
8229 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8230 +
8231 + nor@0,0 {
8232 + #address-cells = <1>;
8233 + #size-cells = <1>;
8234 + compatible = "cfi-flash";
8235 + reg = <0x0 0x0 0x8000000>;
8236 + bank-width = <2>;
8237 + device-width = <1>;
8238 + };
8239 +
8240 + nand@2,0 {
8241 + compatible = "fsl,ifc-nand";
8242 + reg = <0x2 0x0 0x10000>;
8243 + };
8244 +
8245 + cpld@3,0 {
8246 + reg = <0x3 0x0 0x10000>;
8247 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8248 + };
8249 +
8250 +};
8251 +
8252 +&i2c0 {
8253 + status = "okay";
8254 + pca9547@75 {
8255 + compatible = "nxp,pca9547";
8256 + reg = <0x75>;
8257 + #address-cells = <1>;
8258 + #size-cells = <0>;
8259 + i2c-mux-never-disable;
8260 + i2c@1 {
8261 + #address-cells = <1>;
8262 + #size-cells = <0>;
8263 + reg = <0x01>;
8264 + rtc@68 {
8265 + compatible = "dallas,ds3232";
8266 + reg = <0x68>;
8267 + };
8268 + };
8269 +
8270 + i2c@3 {
8271 + #address-cells = <1>;
8272 + #size-cells = <0>;
8273 + reg = <0x3>;
8274 +
8275 + adt7481@4c {
8276 + compatible = "adi,adt7461";
8277 + reg = <0x4c>;
8278 + };
8279 + };
8280 + };
8281 +};
8282 +
8283 +&i2c1 {
8284 + status = "disabled";
8285 +};
8286 +
8287 +&i2c2 {
8288 + status = "disabled";
8289 +};
8290 +
8291 +&i2c3 {
8292 + status = "disabled";
8293 +};
8294 +
8295 +&dspi {
8296 + status = "okay";
8297 + dflash0: n25q512a {
8298 + #address-cells = <1>;
8299 + #size-cells = <1>;
8300 + compatible = "st,m25p80";
8301 + spi-max-frequency = <3000000>;
8302 + reg = <0>;
8303 + };
8304 +};
8305 +
8306 +&qspi {
8307 + status = "okay";
8308 + flash0: s25fs512s@0 {
8309 + #address-cells = <1>;
8310 + #size-cells = <1>;
8311 + compatible = "spansion,m25p80";
8312 + m25p,fast-read;
8313 + spi-max-frequency = <20000000>;
8314 + reg = <0>;
8315 + };
8316 +};
8317 +
8318 +&sata0 {
8319 + status = "okay";
8320 +};
8321 +
8322 +&sata1 {
8323 + status = "okay";
8324 +};
8325 +
8326 +&usb0 {
8327 + status = "okay";
8328 +};
8329 +
8330 +&usb1 {
8331 + status = "okay";
8332 +};
8333 --- /dev/null
8334 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
8335 @@ -0,0 +1,912 @@
8336 +/*
8337 + * Device Tree Include file for Freescale Layerscape-2080A family SoC.
8338 + *
8339 + * Copyright 2016 Freescale Semiconductor, Inc.
8340 + * Copyright 2017 NXP
8341 + *
8342 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8343 + *
8344 + * This file is dual-licensed: you can use it either under the terms
8345 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8346 + * licensing only applies to this file, and not this project as a
8347 + * whole.
8348 + *
8349 + * a) This library is free software; you can redistribute it and/or
8350 + * modify it under the terms of the GNU General Public License as
8351 + * published by the Free Software Foundation; either version 2 of the
8352 + * License, or (at your option) any later version.
8353 + *
8354 + * This library is distributed in the hope that it will be useful,
8355 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8356 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8357 + * GNU General Public License for more details.
8358 + *
8359 + * Or, alternatively,
8360 + *
8361 + * b) Permission is hereby granted, free of charge, to any person
8362 + * obtaining a copy of this software and associated documentation
8363 + * files (the "Software"), to deal in the Software without
8364 + * restriction, including without limitation the rights to use,
8365 + * copy, modify, merge, publish, distribute, sublicense, and/or
8366 + * sell copies of the Software, and to permit persons to whom the
8367 + * Software is furnished to do so, subject to the following
8368 + * conditions:
8369 + *
8370 + * The above copyright notice and this permission notice shall be
8371 + * included in all copies or substantial portions of the Software.
8372 + *
8373 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8374 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8375 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8376 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8377 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8378 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8379 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8380 + * OTHER DEALINGS IN THE SOFTWARE.
8381 + */
8382 +
8383 +#include <dt-bindings/thermal/thermal.h>
8384 +#include <dt-bindings/interrupt-controller/arm-gic.h>
8385 +
8386 +/ {
8387 + compatible = "fsl,ls2080a";
8388 + interrupt-parent = <&gic>;
8389 + #address-cells = <2>;
8390 + #size-cells = <2>;
8391 +
8392 + aliases {
8393 + crypto = &crypto;
8394 + serial0 = &serial0;
8395 + serial1 = &serial1;
8396 + };
8397 +
8398 + cpu: cpus {
8399 + #address-cells = <1>;
8400 + #size-cells = <0>;
8401 + };
8402 +
8403 + memory@80000000 {
8404 + device_type = "memory";
8405 + reg = <0x00000000 0x80000000 0 0x80000000>;
8406 + /* DRAM space - 1, size : 2 GB DRAM */
8407 + };
8408 +
8409 + sysclk: sysclk {
8410 + compatible = "fixed-clock";
8411 + #clock-cells = <0>;
8412 + clock-frequency = <100000000>;
8413 + clock-output-names = "sysclk";
8414 + };
8415 +
8416 + gic: interrupt-controller@6000000 {
8417 + compatible = "arm,gic-v3";
8418 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
8419 + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
8420 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
8421 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
8422 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
8423 + #interrupt-cells = <3>;
8424 + #address-cells = <2>;
8425 + #size-cells = <2>;
8426 + ranges;
8427 + interrupt-controller;
8428 + interrupts = <1 9 0x4>;
8429 +
8430 + its: gic-its@6020000 {
8431 + compatible = "arm,gic-v3-its";
8432 + msi-controller;
8433 + reg = <0x0 0x6020000 0 0x20000>;
8434 + };
8435 + };
8436 +
8437 + rstcr: syscon@1e60000 {
8438 + compatible = "fsl,ls2080a-rstcr", "syscon";
8439 + reg = <0x0 0x1e60000 0x0 0x4>;
8440 + };
8441 +
8442 + reboot {
8443 + compatible ="syscon-reboot";
8444 + regmap = <&rstcr>;
8445 + offset = <0x0>;
8446 + mask = <0x2>;
8447 + };
8448 +
8449 + timer {
8450 + compatible = "arm,armv8-timer";
8451 + interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
8452 + <1 14 4>, /* Physical Non-Secure PPI, active-low */
8453 + <1 11 4>, /* Virtual PPI, active-low */
8454 + <1 10 4>; /* Hypervisor PPI, active-low */
8455 + fsl,erratum-a008585;
8456 + };
8457 +
8458 + pmu {
8459 + compatible = "arm,armv8-pmuv3";
8460 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
8461 + };
8462 +
8463 + soc {
8464 + compatible = "simple-bus";
8465 + #address-cells = <2>;
8466 + #size-cells = <2>;
8467 + ranges;
8468 +
8469 + clockgen: clocking@1300000 {
8470 + compatible = "fsl,ls2080a-clockgen";
8471 + reg = <0 0x1300000 0 0xa0000>;
8472 + #clock-cells = <2>;
8473 + clocks = <&sysclk>;
8474 + };
8475 +
8476 + dcfg: dcfg@1e00000 {
8477 + compatible = "fsl,ls2080a-dcfg", "syscon";
8478 + reg = <0x0 0x1e00000 0x0 0x10000>;
8479 + little-endian;
8480 + };
8481 +
8482 + tmu: tmu@1f80000 {
8483 + compatible = "fsl,qoriq-tmu";
8484 + reg = <0x0 0x1f80000 0x0 0x10000>;
8485 + interrupts = <0 23 0x4>;
8486 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
8487 + fsl,tmu-calibration = <0x00000000 0x00000026
8488 + 0x00000001 0x0000002d
8489 + 0x00000002 0x00000032
8490 + 0x00000003 0x00000039
8491 + 0x00000004 0x0000003f
8492 + 0x00000005 0x00000046
8493 + 0x00000006 0x0000004d
8494 + 0x00000007 0x00000054
8495 + 0x00000008 0x0000005a
8496 + 0x00000009 0x00000061
8497 + 0x0000000a 0x0000006a
8498 + 0x0000000b 0x00000071
8499 +
8500 + 0x00010000 0x00000025
8501 + 0x00010001 0x0000002c
8502 + 0x00010002 0x00000035
8503 + 0x00010003 0x0000003d
8504 + 0x00010004 0x00000045
8505 + 0x00010005 0x0000004e
8506 + 0x00010006 0x00000057
8507 + 0x00010007 0x00000061
8508 + 0x00010008 0x0000006b
8509 + 0x00010009 0x00000076
8510 +
8511 + 0x00020000 0x00000029
8512 + 0x00020001 0x00000033
8513 + 0x00020002 0x0000003d
8514 + 0x00020003 0x00000049
8515 + 0x00020004 0x00000056
8516 + 0x00020005 0x00000061
8517 + 0x00020006 0x0000006d
8518 +
8519 + 0x00030000 0x00000021
8520 + 0x00030001 0x0000002a
8521 + 0x00030002 0x0000003c
8522 + 0x00030003 0x0000004e>;
8523 + little-endian;
8524 + #thermal-sensor-cells = <1>;
8525 + };
8526 +
8527 + thermal-zones {
8528 + cpu_thermal: cpu-thermal {
8529 + polling-delay-passive = <1000>;
8530 + polling-delay = <5000>;
8531 +
8532 + thermal-sensors = <&tmu 4>;
8533 +
8534 + trips {
8535 + cpu_alert: cpu-alert {
8536 + temperature = <75000>;
8537 + hysteresis = <2000>;
8538 + type = "passive";
8539 + };
8540 + cpu_crit: cpu-crit {
8541 + temperature = <85000>;
8542 + hysteresis = <2000>;
8543 + type = "critical";
8544 + };
8545 + };
8546 +
8547 + cooling-maps {
8548 + map0 {
8549 + trip = <&cpu_alert>;
8550 + cooling-device =
8551 + <&cpu0 THERMAL_NO_LIMIT
8552 + THERMAL_NO_LIMIT>;
8553 + };
8554 + map1 {
8555 + trip = <&cpu_alert>;
8556 + cooling-device =
8557 + <&cpu2 THERMAL_NO_LIMIT
8558 + THERMAL_NO_LIMIT>;
8559 + };
8560 + map2 {
8561 + trip = <&cpu_alert>;
8562 + cooling-device =
8563 + <&cpu4 THERMAL_NO_LIMIT
8564 + THERMAL_NO_LIMIT>;
8565 + };
8566 + map3 {
8567 + trip = <&cpu_alert>;
8568 + cooling-device =
8569 + <&cpu6 THERMAL_NO_LIMIT
8570 + THERMAL_NO_LIMIT>;
8571 + };
8572 + };
8573 + };
8574 + };
8575 +
8576 + serial0: serial@21c0500 {
8577 + compatible = "fsl,ns16550", "ns16550a";
8578 + reg = <0x0 0x21c0500 0x0 0x100>;
8579 + clocks = <&clockgen 4 3>;
8580 + interrupts = <0 32 0x4>; /* Level high type */
8581 + };
8582 +
8583 + serial1: serial@21c0600 {
8584 + compatible = "fsl,ns16550", "ns16550a";
8585 + reg = <0x0 0x21c0600 0x0 0x100>;
8586 + clocks = <&clockgen 4 3>;
8587 + interrupts = <0 32 0x4>; /* Level high type */
8588 + };
8589 +
8590 + cluster1_core0_watchdog: wdt@c000000 {
8591 + compatible = "arm,sp805-wdt", "arm,primecell";
8592 + reg = <0x0 0xc000000 0x0 0x1000>;
8593 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8594 + clock-names = "apb_pclk", "wdog_clk";
8595 + };
8596 +
8597 + cluster1_core1_watchdog: wdt@c010000 {
8598 + compatible = "arm,sp805-wdt", "arm,primecell";
8599 + reg = <0x0 0xc010000 0x0 0x1000>;
8600 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8601 + clock-names = "apb_pclk", "wdog_clk";
8602 + };
8603 +
8604 + cluster2_core0_watchdog: wdt@c100000 {
8605 + compatible = "arm,sp805-wdt", "arm,primecell";
8606 + reg = <0x0 0xc100000 0x0 0x1000>;
8607 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8608 + clock-names = "apb_pclk", "wdog_clk";
8609 + };
8610 +
8611 + cluster2_core1_watchdog: wdt@c110000 {
8612 + compatible = "arm,sp805-wdt", "arm,primecell";
8613 + reg = <0x0 0xc110000 0x0 0x1000>;
8614 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8615 + clock-names = "apb_pclk", "wdog_clk";
8616 + };
8617 +
8618 + cluster3_core0_watchdog: wdt@c200000 {
8619 + compatible = "arm,sp805-wdt", "arm,primecell";
8620 + reg = <0x0 0xc200000 0x0 0x1000>;
8621 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8622 + clock-names = "apb_pclk", "wdog_clk";
8623 + };
8624 +
8625 + cluster3_core1_watchdog: wdt@c210000 {
8626 + compatible = "arm,sp805-wdt", "arm,primecell";
8627 + reg = <0x0 0xc210000 0x0 0x1000>;
8628 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8629 + clock-names = "apb_pclk", "wdog_clk";
8630 + };
8631 +
8632 + cluster4_core0_watchdog: wdt@c300000 {
8633 + compatible = "arm,sp805-wdt", "arm,primecell";
8634 + reg = <0x0 0xc300000 0x0 0x1000>;
8635 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8636 + clock-names = "apb_pclk", "wdog_clk";
8637 + };
8638 +
8639 + cluster4_core1_watchdog: wdt@c310000 {
8640 + compatible = "arm,sp805-wdt", "arm,primecell";
8641 + reg = <0x0 0xc310000 0x0 0x1000>;
8642 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8643 + clock-names = "apb_pclk", "wdog_clk";
8644 + };
8645 +
8646 + crypto: crypto@8000000 {
8647 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
8648 + fsl,sec-era = <8>;
8649 + #address-cells = <1>;
8650 + #size-cells = <1>;
8651 + ranges = <0x0 0x00 0x8000000 0x100000>;
8652 + reg = <0x00 0x8000000 0x0 0x100000>;
8653 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
8654 + dma-coherent;
8655 +
8656 + sec_jr0: jr@10000 {
8657 + compatible = "fsl,sec-v5.0-job-ring",
8658 + "fsl,sec-v4.0-job-ring";
8659 + reg = <0x10000 0x10000>;
8660 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
8661 + };
8662 +
8663 + sec_jr1: jr@20000 {
8664 + compatible = "fsl,sec-v5.0-job-ring",
8665 + "fsl,sec-v4.0-job-ring";
8666 + reg = <0x20000 0x10000>;
8667 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
8668 + };
8669 +
8670 + sec_jr2: jr@30000 {
8671 + compatible = "fsl,sec-v5.0-job-ring",
8672 + "fsl,sec-v4.0-job-ring";
8673 + reg = <0x30000 0x10000>;
8674 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
8675 + };
8676 +
8677 + sec_jr3: jr@40000 {
8678 + compatible = "fsl,sec-v5.0-job-ring",
8679 + "fsl,sec-v4.0-job-ring";
8680 + reg = <0x40000 0x10000>;
8681 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
8682 + };
8683 + };
8684 +
8685 + fsl_mc: fsl-mc@80c000000 {
8686 + compatible = "fsl,qoriq-mc";
8687 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
8688 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
8689 + msi-parent = <&its>;
8690 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
8691 + #address-cells = <3>;
8692 + #size-cells = <1>;
8693 +
8694 + /*
8695 + * Region type 0x0 - MC portals
8696 + * Region type 0x1 - QBMAN portals
8697 + */
8698 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
8699 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
8700 +
8701 + /*
8702 + * Define the maximum number of MACs present on the SoC.
8703 + */
8704 + dpmacs {
8705 + #address-cells = <1>;
8706 + #size-cells = <0>;
8707 +
8708 + dpmac1: dpmac@1 {
8709 + compatible = "fsl,qoriq-mc-dpmac";
8710 + reg = <0x1>;
8711 + };
8712 +
8713 + dpmac2: dpmac@2 {
8714 + compatible = "fsl,qoriq-mc-dpmac";
8715 + reg = <0x2>;
8716 + };
8717 +
8718 + dpmac3: dpmac@3 {
8719 + compatible = "fsl,qoriq-mc-dpmac";
8720 + reg = <0x3>;
8721 + };
8722 +
8723 + dpmac4: dpmac@4 {
8724 + compatible = "fsl,qoriq-mc-dpmac";
8725 + reg = <0x4>;
8726 + };
8727 +
8728 + dpmac5: dpmac@5 {
8729 + compatible = "fsl,qoriq-mc-dpmac";
8730 + reg = <0x5>;
8731 + };
8732 +
8733 + dpmac6: dpmac@6 {
8734 + compatible = "fsl,qoriq-mc-dpmac";
8735 + reg = <0x6>;
8736 + };
8737 +
8738 + dpmac7: dpmac@7 {
8739 + compatible = "fsl,qoriq-mc-dpmac";
8740 + reg = <0x7>;
8741 + };
8742 +
8743 + dpmac8: dpmac@8 {
8744 + compatible = "fsl,qoriq-mc-dpmac";
8745 + reg = <0x8>;
8746 + };
8747 +
8748 + dpmac9: dpmac@9 {
8749 + compatible = "fsl,qoriq-mc-dpmac";
8750 + reg = <0x9>;
8751 + };
8752 +
8753 + dpmac10: dpmac@a {
8754 + compatible = "fsl,qoriq-mc-dpmac";
8755 + reg = <0xa>;
8756 + };
8757 +
8758 + dpmac11: dpmac@b {
8759 + compatible = "fsl,qoriq-mc-dpmac";
8760 + reg = <0xb>;
8761 + };
8762 +
8763 + dpmac12: dpmac@c {
8764 + compatible = "fsl,qoriq-mc-dpmac";
8765 + reg = <0xc>;
8766 + };
8767 +
8768 + dpmac13: dpmac@d {
8769 + compatible = "fsl,qoriq-mc-dpmac";
8770 + reg = <0xd>;
8771 + };
8772 +
8773 + dpmac14: dpmac@e {
8774 + compatible = "fsl,qoriq-mc-dpmac";
8775 + reg = <0xe>;
8776 + };
8777 +
8778 + dpmac15: dpmac@f {
8779 + compatible = "fsl,qoriq-mc-dpmac";
8780 + reg = <0xf>;
8781 + };
8782 +
8783 + dpmac16: dpmac@10 {
8784 + compatible = "fsl,qoriq-mc-dpmac";
8785 + reg = <0x10>;
8786 + };
8787 + };
8788 + };
8789 +
8790 + smmu: iommu@5000000 {
8791 + compatible = "arm,mmu-500";
8792 + reg = <0 0x5000000 0 0x800000>;
8793 + #global-interrupts = <12>;
8794 + #iommu-cells = <1>;
8795 + stream-match-mask = <0x7C00>;
8796 + interrupts = <0 13 4>, /* global secure fault */
8797 + <0 14 4>, /* combined secure interrupt */
8798 + <0 15 4>, /* global non-secure fault */
8799 + <0 16 4>, /* combined non-secure interrupt */
8800 + /* performance counter interrupts 0-7 */
8801 + <0 211 4>, <0 212 4>,
8802 + <0 213 4>, <0 214 4>,
8803 + <0 215 4>, <0 216 4>,
8804 + <0 217 4>, <0 218 4>,
8805 + /* per context interrupt, 64 interrupts */
8806 + <0 146 4>, <0 147 4>,
8807 + <0 148 4>, <0 149 4>,
8808 + <0 150 4>, <0 151 4>,
8809 + <0 152 4>, <0 153 4>,
8810 + <0 154 4>, <0 155 4>,
8811 + <0 156 4>, <0 157 4>,
8812 + <0 158 4>, <0 159 4>,
8813 + <0 160 4>, <0 161 4>,
8814 + <0 162 4>, <0 163 4>,
8815 + <0 164 4>, <0 165 4>,
8816 + <0 166 4>, <0 167 4>,
8817 + <0 168 4>, <0 169 4>,
8818 + <0 170 4>, <0 171 4>,
8819 + <0 172 4>, <0 173 4>,
8820 + <0 174 4>, <0 175 4>,
8821 + <0 176 4>, <0 177 4>,
8822 + <0 178 4>, <0 179 4>,
8823 + <0 180 4>, <0 181 4>,
8824 + <0 182 4>, <0 183 4>,
8825 + <0 184 4>, <0 185 4>,
8826 + <0 186 4>, <0 187 4>,
8827 + <0 188 4>, <0 189 4>,
8828 + <0 190 4>, <0 191 4>,
8829 + <0 192 4>, <0 193 4>,
8830 + <0 194 4>, <0 195 4>,
8831 + <0 196 4>, <0 197 4>,
8832 + <0 198 4>, <0 199 4>,
8833 + <0 200 4>, <0 201 4>,
8834 + <0 202 4>, <0 203 4>,
8835 + <0 204 4>, <0 205 4>,
8836 + <0 206 4>, <0 207 4>,
8837 + <0 208 4>, <0 209 4>;
8838 + };
8839 +
8840 + dspi: dspi@2100000 {
8841 + status = "disabled";
8842 + compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
8843 + #address-cells = <1>;
8844 + #size-cells = <0>;
8845 + reg = <0x0 0x2100000 0x0 0x10000>;
8846 + interrupts = <0 26 0x4>; /* Level high type */
8847 + clocks = <&clockgen 4 3>;
8848 + clock-names = "dspi";
8849 + spi-num-chipselects = <5>;
8850 + bus-num = <0>;
8851 + };
8852 +
8853 + esdhc: esdhc@2140000 {
8854 + status = "disabled";
8855 + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
8856 + reg = <0x0 0x2140000 0x0 0x10000>;
8857 + interrupts = <0 28 0x4>; /* Level high type */
8858 + clocks = <&clockgen 4 1>;
8859 + voltage-ranges = <1800 1800 3300 3300>;
8860 + sdhci,auto-cmd12;
8861 + little-endian;
8862 + bus-width = <4>;
8863 + };
8864 +
8865 + gpio0: gpio@2300000 {
8866 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8867 + reg = <0x0 0x2300000 0x0 0x10000>;
8868 + interrupts = <0 36 0x4>; /* Level high type */
8869 + gpio-controller;
8870 + little-endian;
8871 + #gpio-cells = <2>;
8872 + interrupt-controller;
8873 + #interrupt-cells = <2>;
8874 + };
8875 +
8876 + gpio1: gpio@2310000 {
8877 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8878 + reg = <0x0 0x2310000 0x0 0x10000>;
8879 + interrupts = <0 36 0x4>; /* Level high type */
8880 + gpio-controller;
8881 + little-endian;
8882 + #gpio-cells = <2>;
8883 + interrupt-controller;
8884 + #interrupt-cells = <2>;
8885 + };
8886 +
8887 + gpio2: gpio@2320000 {
8888 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8889 + reg = <0x0 0x2320000 0x0 0x10000>;
8890 + interrupts = <0 37 0x4>; /* Level high type */
8891 + gpio-controller;
8892 + little-endian;
8893 + #gpio-cells = <2>;
8894 + interrupt-controller;
8895 + #interrupt-cells = <2>;
8896 + };
8897 +
8898 + gpio3: gpio@2330000 {
8899 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8900 + reg = <0x0 0x2330000 0x0 0x10000>;
8901 + interrupts = <0 37 0x4>; /* Level high type */
8902 + gpio-controller;
8903 + little-endian;
8904 + #gpio-cells = <2>;
8905 + interrupt-controller;
8906 + #interrupt-cells = <2>;
8907 + };
8908 +
8909 + /* TODO: WRIOP (CCSR?) */
8910 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
8911 + * E-MDIO1: 0x1_6000
8912 + */
8913 + compatible = "fsl,fman-memac-mdio";
8914 + reg = <0x0 0x8B96000 0x0 0x1000>;
8915 + device_type = "mdio"; /* TODO: is this necessary? */
8916 + little-endian; /* force the driver in LE mode */
8917 +
8918 + /* Not necessary on the QDS, but needed on the RDB */
8919 + #address-cells = <1>;
8920 + #size-cells = <0>;
8921 + };
8922 +
8923 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
8924 + * E-MDIO2: 0x1_7000
8925 + */
8926 + compatible = "fsl,fman-memac-mdio";
8927 + reg = <0x0 0x8B97000 0x0 0x1000>;
8928 + device_type = "mdio"; /* TODO: is this necessary? */
8929 + little-endian; /* force the driver in LE mode */
8930 +
8931 + #address-cells = <1>;
8932 + #size-cells = <0>;
8933 + };
8934 +
8935 + pcs_mdio1: mdio@0x8c07000 {
8936 + compatible = "fsl,fman-memac-mdio";
8937 + reg = <0x0 0x8c07000 0x0 0x1000>;
8938 + device_type = "mdio";
8939 + little-endian;
8940 +
8941 + #address-cells = <1>;
8942 + #size-cells = <0>;
8943 + };
8944 +
8945 + pcs_mdio2: mdio@0x8c0b000 {
8946 + compatible = "fsl,fman-memac-mdio";
8947 + reg = <0x0 0x8c0b000 0x0 0x1000>;
8948 + device_type = "mdio";
8949 + little-endian;
8950 +
8951 + #address-cells = <1>;
8952 + #size-cells = <0>;
8953 + };
8954 +
8955 + pcs_mdio3: mdio@0x8c0f000 {
8956 + compatible = "fsl,fman-memac-mdio";
8957 + reg = <0x0 0x8c0f000 0x0 0x1000>;
8958 + device_type = "mdio";
8959 + little-endian;
8960 +
8961 + #address-cells = <1>;
8962 + #size-cells = <0>;
8963 + };
8964 +
8965 + pcs_mdio4: mdio@0x8c13000 {
8966 + compatible = "fsl,fman-memac-mdio";
8967 + reg = <0x0 0x8c13000 0x0 0x1000>;
8968 + device_type = "mdio";
8969 + little-endian;
8970 +
8971 + #address-cells = <1>;
8972 + #size-cells = <0>;
8973 + };
8974 +
8975 + pcs_mdio5: mdio@0x8c17000 {
8976 + status = "disabled";
8977 + compatible = "fsl,fman-memac-mdio";
8978 + reg = <0x0 0x8c17000 0x0 0x1000>;
8979 + device_type = "mdio";
8980 + little-endian;
8981 +
8982 + #address-cells = <1>;
8983 + #size-cells = <0>;
8984 + };
8985 +
8986 + pcs_mdio6: mdio@0x8c1b000 {
8987 + status = "disabled";
8988 + compatible = "fsl,fman-memac-mdio";
8989 + reg = <0x0 0x8c1b000 0x0 0x1000>;
8990 + device_type = "mdio";
8991 + little-endian;
8992 +
8993 + #address-cells = <1>;
8994 + #size-cells = <0>;
8995 + };
8996 +
8997 + pcs_mdio7: mdio@0x8c1f000 {
8998 + status = "disabled";
8999 + compatible = "fsl,fman-memac-mdio";
9000 + reg = <0x0 0x8c1f000 0x0 0x1000>;
9001 + device_type = "mdio";
9002 + little-endian;
9003 +
9004 + #address-cells = <1>;
9005 + #size-cells = <0>;
9006 + };
9007 +
9008 + pcs_mdio8: mdio@0x8c23000 {
9009 + status = "disabled";
9010 + compatible = "fsl,fman-memac-mdio";
9011 + reg = <0x0 0x8c23000 0x0 0x1000>;
9012 + device_type = "mdio";
9013 + little-endian;
9014 +
9015 + #address-cells = <1>;
9016 + #size-cells = <0>;
9017 + };
9018 +
9019 + i2c0: i2c@2000000 {
9020 + status = "disabled";
9021 + compatible = "fsl,vf610-i2c";
9022 + #address-cells = <1>;
9023 + #size-cells = <0>;
9024 + reg = <0x0 0x2000000 0x0 0x10000>;
9025 + interrupts = <0 34 0x4>; /* Level high type */
9026 + clock-names = "i2c";
9027 + clocks = <&clockgen 4 3>;
9028 + };
9029 +
9030 + i2c1: i2c@2010000 {
9031 + status = "disabled";
9032 + compatible = "fsl,vf610-i2c";
9033 + #address-cells = <1>;
9034 + #size-cells = <0>;
9035 + reg = <0x0 0x2010000 0x0 0x10000>;
9036 + interrupts = <0 34 0x4>; /* Level high type */
9037 + clock-names = "i2c";
9038 + clocks = <&clockgen 4 3>;
9039 + };
9040 +
9041 + i2c2: i2c@2020000 {
9042 + status = "disabled";
9043 + compatible = "fsl,vf610-i2c";
9044 + #address-cells = <1>;
9045 + #size-cells = <0>;
9046 + reg = <0x0 0x2020000 0x0 0x10000>;
9047 + interrupts = <0 35 0x4>; /* Level high type */
9048 + clock-names = "i2c";
9049 + clocks = <&clockgen 4 3>;
9050 + };
9051 +
9052 + i2c3: i2c@2030000 {
9053 + status = "disabled";
9054 + compatible = "fsl,vf610-i2c";
9055 + #address-cells = <1>;
9056 + #size-cells = <0>;
9057 + reg = <0x0 0x2030000 0x0 0x10000>;
9058 + interrupts = <0 35 0x4>; /* Level high type */
9059 + clock-names = "i2c";
9060 + clocks = <&clockgen 4 3>;
9061 + };
9062 +
9063 + ifc: ifc@2240000 {
9064 + compatible = "fsl,ifc", "simple-bus";
9065 + reg = <0x0 0x2240000 0x0 0x20000>;
9066 + interrupts = <0 21 0x4>; /* Level high type */
9067 + little-endian;
9068 + #address-cells = <2>;
9069 + #size-cells = <1>;
9070 +
9071 + ranges = <0 0 0x5 0x80000000 0x08000000
9072 + 2 0 0x5 0x30000000 0x00010000
9073 + 3 0 0x5 0x20000000 0x00010000>;
9074 + };
9075 +
9076 + qspi: quadspi@20c0000 {
9077 + status = "disabled";
9078 + compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
9079 + #address-cells = <1>;
9080 + #size-cells = <0>;
9081 + reg = <0x0 0x20c0000 0x0 0x10000>,
9082 + <0x0 0x20000000 0x0 0x10000000>;
9083 + reg-names = "QuadSPI", "QuadSPI-memory";
9084 + interrupts = <0 25 0x4>; /* Level high type */
9085 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
9086 + clock-names = "qspi_en", "qspi";
9087 + };
9088 +
9089 + pcie1: pcie@3400000 {
9090 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9091 + "snps,dw-pcie";
9092 + reg-names = "regs", "config";
9093 + interrupts = <0 108 0x4>; /* aer interrupt */
9094 + interrupt-names = "aer";
9095 + #address-cells = <3>;
9096 + #size-cells = <2>;
9097 + device_type = "pci";
9098 + dma-coherent;
9099 + num-lanes = <4>;
9100 + bus-range = <0x0 0xff>;
9101 + msi-parent = <&its>;
9102 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9103 + #interrupt-cells = <1>;
9104 + interrupt-map-mask = <0 0 0 7>;
9105 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
9106 + <0000 0 0 2 &gic 0 0 0 110 4>,
9107 + <0000 0 0 3 &gic 0 0 0 111 4>,
9108 + <0000 0 0 4 &gic 0 0 0 112 4>;
9109 + };
9110 +
9111 + pcie2: pcie@3500000 {
9112 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9113 + "snps,dw-pcie";
9114 + reg-names = "regs", "config";
9115 + interrupts = <0 113 0x4>; /* aer interrupt */
9116 + interrupt-names = "aer";
9117 + #address-cells = <3>;
9118 + #size-cells = <2>;
9119 + device_type = "pci";
9120 + dma-coherent;
9121 + num-lanes = <4>;
9122 + bus-range = <0x0 0xff>;
9123 + msi-parent = <&its>;
9124 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9125 + #interrupt-cells = <1>;
9126 + interrupt-map-mask = <0 0 0 7>;
9127 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
9128 + <0000 0 0 2 &gic 0 0 0 115 4>,
9129 + <0000 0 0 3 &gic 0 0 0 116 4>,
9130 + <0000 0 0 4 &gic 0 0 0 117 4>;
9131 + };
9132 +
9133 + pcie3: pcie@3600000 {
9134 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9135 + "snps,dw-pcie";
9136 + reg-names = "regs", "config";
9137 + interrupts = <0 118 0x4>; /* aer interrupt */
9138 + interrupt-names = "aer";
9139 + #address-cells = <3>;
9140 + #size-cells = <2>;
9141 + device_type = "pci";
9142 + dma-coherent;
9143 + num-lanes = <8>;
9144 + bus-range = <0x0 0xff>;
9145 + msi-parent = <&its>;
9146 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9147 + #interrupt-cells = <1>;
9148 + interrupt-map-mask = <0 0 0 7>;
9149 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
9150 + <0000 0 0 2 &gic 0 0 0 120 4>,
9151 + <0000 0 0 3 &gic 0 0 0 121 4>,
9152 + <0000 0 0 4 &gic 0 0 0 122 4>;
9153 + };
9154 +
9155 + pcie4: pcie@3700000 {
9156 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9157 + "snps,dw-pcie";
9158 + reg-names = "regs", "config";
9159 + interrupts = <0 123 0x4>; /* aer interrupt */
9160 + interrupt-names = "aer";
9161 + #address-cells = <3>;
9162 + #size-cells = <2>;
9163 + device_type = "pci";
9164 + dma-coherent;
9165 + num-lanes = <4>;
9166 + bus-range = <0x0 0xff>;
9167 + msi-parent = <&its>;
9168 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9169 + #interrupt-cells = <1>;
9170 + interrupt-map-mask = <0 0 0 7>;
9171 + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
9172 + <0000 0 0 2 &gic 0 0 0 125 4>,
9173 + <0000 0 0 3 &gic 0 0 0 126 4>,
9174 + <0000 0 0 4 &gic 0 0 0 127 4>;
9175 + };
9176 +
9177 + sata0: sata@3200000 {
9178 + status = "disabled";
9179 + compatible = "fsl,ls2080a-ahci";
9180 + reg = <0x0 0x3200000 0x0 0x10000>;
9181 + interrupts = <0 133 0x4>; /* Level high type */
9182 + clocks = <&clockgen 4 3>;
9183 + dma-coherent;
9184 + };
9185 +
9186 + sata1: sata@3210000 {
9187 + status = "disabled";
9188 + compatible = "fsl,ls2080a-ahci";
9189 + reg = <0x0 0x3210000 0x0 0x10000>;
9190 + interrupts = <0 136 0x4>; /* Level high type */
9191 + clocks = <&clockgen 4 3>;
9192 + dma-coherent;
9193 + };
9194 +
9195 + usb0: usb3@3100000 {
9196 + status = "disabled";
9197 + compatible = "snps,dwc3";
9198 + reg = <0x0 0x3100000 0x0 0x10000>;
9199 + interrupts = <0 80 0x4>; /* Level high type */
9200 + dr_mode = "host";
9201 + snps,quirk-frame-length-adjustment = <0x20>;
9202 + snps,dis_rxdet_inp3_quirk;
9203 + };
9204 +
9205 + usb1: usb3@3110000 {
9206 + status = "disabled";
9207 + compatible = "snps,dwc3";
9208 + reg = <0x0 0x3110000 0x0 0x10000>;
9209 + interrupts = <0 81 0x4>; /* Level high type */
9210 + dr_mode = "host";
9211 + snps,quirk-frame-length-adjustment = <0x20>;
9212 + snps,dis_rxdet_inp3_quirk;
9213 + };
9214 +
9215 + serdes1: serdes@1ea0000 {
9216 + reg = <0x0 0x1ea0000 0 0x00002000>;
9217 + };
9218 +
9219 + ccn@4000000 {
9220 + compatible = "arm,ccn-504";
9221 + reg = <0x0 0x04000000 0x0 0x01000000>;
9222 + interrupts = <0 12 4>;
9223 + };
9224 +
9225 + ftm0: ftm0@2800000 {
9226 + compatible = "fsl,ls208xa-ftm";
9227 + reg = <0x0 0x2800000 0x0 0x10000>,
9228 + <0x0 0x1e34050 0x0 0x4>;
9229 + interrupts = <0 44 4>;
9230 + reg-names = "ftm", "FlexTimer1";
9231 + };
9232 + };
9233 +
9234 + ddr1: memory-controller@1080000 {
9235 + compatible = "fsl,qoriq-memory-controller";
9236 + reg = <0x0 0x1080000 0x0 0x1000>;
9237 + interrupts = <0 17 0x4>;
9238 + little-endian;
9239 + };
9240 +
9241 + ddr2: memory-controller@1090000 {
9242 + compatible = "fsl,qoriq-memory-controller";
9243 + reg = <0x0 0x1090000 0x0 0x1000>;
9244 + interrupts = <0 18 0x4>;
9245 + little-endian;
9246 + };
9247 +};
9248 --- /dev/null
9249 +++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
9250 @@ -0,0 +1,81 @@
9251 +/*
9252 + * QorIQ BMan Portals device tree
9253 + *
9254 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9255 + *
9256 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9257 + */
9258 +
9259 +&bportals {
9260 + #address-cells = <1>;
9261 + #size-cells = <1>;
9262 + compatible = "simple-bus";
9263 +
9264 + bman-portal@0 {
9265 + cell-index = <0>;
9266 + compatible = "fsl,bman-portal";
9267 + reg = <0x0 0x4000 0x4000000 0x4000>;
9268 + interrupts = <0 173 0x4>;
9269 + };
9270 +
9271 + bman-portal@10000 {
9272 + cell-index = <1>;
9273 + compatible = "fsl,bman-portal";
9274 + reg = <0x10000 0x4000 0x4010000 0x4000>;
9275 + interrupts = <0 175 0x4>;
9276 + };
9277 +
9278 + bman-portal@20000 {
9279 + cell-index = <2>;
9280 + compatible = "fsl,bman-portal";
9281 + reg = <0x20000 0x4000 0x4020000 0x4000>;
9282 + interrupts = <0 177 0x4>;
9283 + };
9284 +
9285 + bman-portal@30000 {
9286 + cell-index = <3>;
9287 + compatible = "fsl,bman-portal";
9288 + reg = <0x30000 0x4000 0x4030000 0x4000>;
9289 + interrupts = <0 179 0x4>;
9290 + };
9291 +
9292 + bman-portal@40000 {
9293 + cell-index = <4>;
9294 + compatible = "fsl,bman-portal";
9295 + reg = <0x40000 0x4000 0x4040000 0x4000>;
9296 + interrupts = <0 181 0x4>;
9297 + };
9298 +
9299 + bman-portal@50000 {
9300 + cell-index = <5>;
9301 + compatible = "fsl,bman-portal";
9302 + reg = <0x50000 0x4000 0x4050000 0x4000>;
9303 + interrupts = <0 183 0x4>;
9304 + };
9305 +
9306 + bman-portal@60000 {
9307 + cell-index = <6>;
9308 + compatible = "fsl,bman-portal";
9309 + reg = <0x60000 0x4000 0x4060000 0x4000>;
9310 + interrupts = <0 185 0x4>;
9311 + };
9312 +
9313 + bman-portal@70000 {
9314 + cell-index = <7>;
9315 + compatible = "fsl,bman-portal";
9316 + reg = <0x70000 0x4000 0x4070000 0x4000>;
9317 + interrupts = <0 187 0x4>;
9318 + };
9319 +
9320 + bman-portal@80000 {
9321 + cell-index = <8>;
9322 + compatible = "fsl,bman-portal";
9323 + reg = <0x80000 0x4000 0x4080000 0x4000>;
9324 + interrupts = <0 189 0x4>;
9325 + };
9326 +
9327 + bman-bpids@0 {
9328 + compatible = "fsl,bpid-range";
9329 + fsl,bpid-range = <32 32>;
9330 + };
9331 +};
9332 --- /dev/null
9333 +++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
9334 @@ -0,0 +1,66 @@
9335 +/*
9336 + * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
9337 + *
9338 + * Copyright 2012 - 2015 Freescale Semiconductor Inc.
9339 + *
9340 + * Redistribution and use in source and binary forms, with or without
9341 + * modification, are permitted provided that the following conditions are met:
9342 + * * Redistributions of source code must retain the above copyright
9343 + * notice, this list of conditions and the following disclaimer.
9344 + * * Redistributions in binary form must reproduce the above copyright
9345 + * notice, this list of conditions and the following disclaimer in the
9346 + * documentation and/or other materials provided with the distribution.
9347 + * * Neither the name of Freescale Semiconductor nor the
9348 + * names of its contributors may be used to endorse or promote products
9349 + * derived from this software without specific prior written permission.
9350 + *
9351 + *
9352 + * ALTERNATIVELY, this software may be distributed under the terms of the
9353 + * GNU General Public License ("GPL") as published by the Free Software
9354 + * Foundation, either version 2 of that License or (at your option) any
9355 + * later version.
9356 + *
9357 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9358 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9359 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9360 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9361 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9362 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9363 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9364 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9365 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9366 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9367 + */
9368 +
9369 +fsldpaa: fsl,dpaa {
9370 + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
9371 + ethernet@0 {
9372 + compatible = "fsl,dpa-ethernet";
9373 + fsl,fman-mac = <&enet0>;
9374 + };
9375 + ethernet@1 {
9376 + compatible = "fsl,dpa-ethernet";
9377 + fsl,fman-mac = <&enet1>;
9378 + };
9379 + ethernet@2 {
9380 + compatible = "fsl,dpa-ethernet";
9381 + fsl,fman-mac = <&enet2>;
9382 + };
9383 + ethernet@3 {
9384 + compatible = "fsl,dpa-ethernet";
9385 + fsl,fman-mac = <&enet3>;
9386 + };
9387 + ethernet@4 {
9388 + compatible = "fsl,dpa-ethernet";
9389 + fsl,fman-mac = <&enet4>;
9390 + };
9391 + ethernet@5 {
9392 + compatible = "fsl,dpa-ethernet";
9393 + fsl,fman-mac = <&enet5>;
9394 + };
9395 + ethernet@8 {
9396 + compatible = "fsl,dpa-ethernet";
9397 + fsl,fman-mac = <&enet6>;
9398 + };
9399 +};
9400 +
9401 --- /dev/null
9402 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
9403 @@ -0,0 +1,43 @@
9404 +/*
9405 + * QorIQ FMan v3 10g port #0 device tree
9406 + *
9407 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9408 + *
9409 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9410 + */
9411 +
9412 +fman@1a00000 {
9413 + fman0_rx_0x10: port@90000 {
9414 + cell-index = <0x10>;
9415 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9416 + reg = <0x90000 0x1000>;
9417 + fsl,fman-10g-port;
9418 + };
9419 +
9420 + fman0_tx_0x30: port@b0000 {
9421 + cell-index = <0x30>;
9422 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9423 + reg = <0xb0000 0x1000>;
9424 + fsl,fman-10g-port;
9425 + fsl,qman-channel-id = <0x800>;
9426 + };
9427 +
9428 + ethernet@f0000 {
9429 + cell-index = <0x8>;
9430 + compatible = "fsl,fman-memac";
9431 + reg = <0xf0000 0x1000>;
9432 + fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
9433 + pcsphy-handle = <&pcsphy6>;
9434 + };
9435 +
9436 + mdio@f1000 {
9437 + #address-cells = <1>;
9438 + #size-cells = <0>;
9439 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9440 + reg = <0xf1000 0x1000>;
9441 +
9442 + pcsphy6: ethernet-phy@0 {
9443 + reg = <0x0>;
9444 + };
9445 + };
9446 +};
9447 --- /dev/null
9448 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
9449 @@ -0,0 +1,43 @@
9450 +/*
9451 + * QorIQ FMan v3 10g port #1 device tree
9452 + *
9453 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9454 + *
9455 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9456 + */
9457 +
9458 +fman@1a00000 {
9459 + fman0_rx_0x11: port@91000 {
9460 + cell-index = <0x11>;
9461 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9462 + reg = <0x91000 0x1000>;
9463 + fsl,fman-10g-port;
9464 + };
9465 +
9466 + fman0_tx_0x31: port@b1000 {
9467 + cell-index = <0x31>;
9468 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9469 + reg = <0xb1000 0x1000>;
9470 + fsl,fman-10g-port;
9471 + fsl,qman-channel-id = <0x801>;
9472 + };
9473 +
9474 + ethernet@f2000 {
9475 + cell-index = <0x9>;
9476 + compatible = "fsl,fman-memac";
9477 + reg = <0xf2000 0x1000>;
9478 + fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
9479 + pcsphy-handle = <&pcsphy7>;
9480 + };
9481 +
9482 + mdio@f3000 {
9483 + #address-cells = <1>;
9484 + #size-cells = <0>;
9485 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9486 + reg = <0xf3000 0x1000>;
9487 +
9488 + pcsphy7: ethernet-phy@0 {
9489 + reg = <0x0>;
9490 + };
9491 + };
9492 +};
9493 --- /dev/null
9494 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
9495 @@ -0,0 +1,42 @@
9496 +/*
9497 + * QorIQ FMan v3 1g port #0 device tree
9498 + *
9499 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9500 + *
9501 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9502 + */
9503 +
9504 +fman@1a00000 {
9505 + fman0_rx_0x08: port@88000 {
9506 + cell-index = <0x8>;
9507 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9508 + reg = <0x88000 0x1000>;
9509 + };
9510 +
9511 + fman0_tx_0x28: port@a8000 {
9512 + cell-index = <0x28>;
9513 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9514 + reg = <0xa8000 0x1000>;
9515 + fsl,qman-channel-id = <0x802>;
9516 + };
9517 +
9518 + ethernet@e0000 {
9519 + cell-index = <0>;
9520 + compatible = "fsl,fman-memac";
9521 + reg = <0xe0000 0x1000>;
9522 + fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
9523 + ptp-timer = <&ptp_timer0>;
9524 + pcsphy-handle = <&pcsphy0>;
9525 + };
9526 +
9527 + mdio@e1000 {
9528 + #address-cells = <1>;
9529 + #size-cells = <0>;
9530 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9531 + reg = <0xe1000 0x1000>;
9532 +
9533 + pcsphy0: ethernet-phy@0 {
9534 + reg = <0x0>;
9535 + };
9536 + };
9537 +};
9538 --- /dev/null
9539 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
9540 @@ -0,0 +1,42 @@
9541 +/*
9542 + * QorIQ FMan v3 1g port #1 device tree
9543 + *
9544 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9545 + *
9546 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9547 + */
9548 +
9549 +fman@1a00000 {
9550 + fman0_rx_0x09: port@89000 {
9551 + cell-index = <0x9>;
9552 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9553 + reg = <0x89000 0x1000>;
9554 + };
9555 +
9556 + fman0_tx_0x29: port@a9000 {
9557 + cell-index = <0x29>;
9558 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9559 + reg = <0xa9000 0x1000>;
9560 + fsl,qman-channel-id = <0x803>;
9561 + };
9562 +
9563 + ethernet@e2000 {
9564 + cell-index = <1>;
9565 + compatible = "fsl,fman-memac";
9566 + reg = <0xe2000 0x1000>;
9567 + fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
9568 + ptp-timer = <&ptp_timer0>;
9569 + pcsphy-handle = <&pcsphy1>;
9570 + };
9571 +
9572 + mdio@e3000 {
9573 + #address-cells = <1>;
9574 + #size-cells = <0>;
9575 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9576 + reg = <0xe3000 0x1000>;
9577 +
9578 + pcsphy1: ethernet-phy@0 {
9579 + reg = <0x0>;
9580 + };
9581 + };
9582 +};
9583 --- /dev/null
9584 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
9585 @@ -0,0 +1,42 @@
9586 +/*
9587 + * QorIQ FMan v3 1g port #2 device tree
9588 + *
9589 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9590 + *
9591 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9592 + */
9593 +
9594 +fman@1a00000 {
9595 + fman0_rx_0x0a: port@8a000 {
9596 + cell-index = <0xa>;
9597 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9598 + reg = <0x8a000 0x1000>;
9599 + };
9600 +
9601 + fman0_tx_0x2a: port@aa000 {
9602 + cell-index = <0x2a>;
9603 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9604 + reg = <0xaa000 0x1000>;
9605 + fsl,qman-channel-id = <0x804>;
9606 + };
9607 +
9608 + ethernet@e4000 {
9609 + cell-index = <2>;
9610 + compatible = "fsl,fman-memac";
9611 + reg = <0xe4000 0x1000>;
9612 + fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
9613 + ptp-timer = <&ptp_timer0>;
9614 + pcsphy-handle = <&pcsphy2>;
9615 + };
9616 +
9617 + mdio@e5000 {
9618 + #address-cells = <1>;
9619 + #size-cells = <0>;
9620 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9621 + reg = <0xe5000 0x1000>;
9622 +
9623 + pcsphy2: ethernet-phy@0 {
9624 + reg = <0x0>;
9625 + };
9626 + };
9627 +};
9628 --- /dev/null
9629 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
9630 @@ -0,0 +1,42 @@
9631 +/*
9632 + * QorIQ FMan v3 1g port #3 device tree
9633 + *
9634 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9635 + *
9636 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9637 + */
9638 +
9639 +fman@1a00000 {
9640 + fman0_rx_0x0b: port@8b000 {
9641 + cell-index = <0xb>;
9642 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9643 + reg = <0x8b000 0x1000>;
9644 + };
9645 +
9646 + fman0_tx_0x2b: port@ab000 {
9647 + cell-index = <0x2b>;
9648 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9649 + reg = <0xab000 0x1000>;
9650 + fsl,qman-channel-id = <0x805>;
9651 + };
9652 +
9653 + ethernet@e6000 {
9654 + cell-index = <3>;
9655 + compatible = "fsl,fman-memac";
9656 + reg = <0xe6000 0x1000>;
9657 + fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
9658 + ptp-timer = <&ptp_timer0>;
9659 + pcsphy-handle = <&pcsphy3>;
9660 + };
9661 +
9662 + mdio@e7000 {
9663 + #address-cells = <1>;
9664 + #size-cells = <0>;
9665 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9666 + reg = <0xe7000 0x1000>;
9667 +
9668 + pcsphy3: ethernet-phy@0 {
9669 + reg = <0x0>;
9670 + };
9671 + };
9672 +};
9673 --- /dev/null
9674 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
9675 @@ -0,0 +1,42 @@
9676 +/*
9677 + * QorIQ FMan v3 1g port #4 device tree
9678 + *
9679 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9680 + *
9681 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9682 + */
9683 +
9684 +fman@1a00000 {
9685 + fman0_rx_0x0c: port@8c000 {
9686 + cell-index = <0xc>;
9687 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9688 + reg = <0x8c000 0x1000>;
9689 + };
9690 +
9691 + fman0_tx_0x2c: port@ac000 {
9692 + cell-index = <0x2c>;
9693 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9694 + reg = <0xac000 0x1000>;
9695 + fsl,qman-channel-id = <0x806>;
9696 + };
9697 +
9698 + ethernet@e8000 {
9699 + cell-index = <4>;
9700 + compatible = "fsl,fman-memac";
9701 + reg = <0xe8000 0x1000>;
9702 + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
9703 + ptp-timer = <&ptp_timer0>;
9704 + pcsphy-handle = <&pcsphy4>;
9705 + };
9706 +
9707 + mdio@e9000 {
9708 + #address-cells = <1>;
9709 + #size-cells = <0>;
9710 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9711 + reg = <0xe9000 0x1000>;
9712 +
9713 + pcsphy4: ethernet-phy@0 {
9714 + reg = <0x0>;
9715 + };
9716 + };
9717 +};
9718 --- /dev/null
9719 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
9720 @@ -0,0 +1,42 @@
9721 +/*
9722 + * QorIQ FMan v3 1g port #5 device tree
9723 + *
9724 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9725 + *
9726 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9727 + */
9728 +
9729 +fman@1a00000 {
9730 + fman0_rx_0x0d: port@8d000 {
9731 + cell-index = <0xd>;
9732 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9733 + reg = <0x8d000 0x1000>;
9734 + };
9735 +
9736 + fman0_tx_0x2d: port@ad000 {
9737 + cell-index = <0x2d>;
9738 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9739 + reg = <0xad000 0x1000>;
9740 + fsl,qman-channel-id = <0x807>;
9741 + };
9742 +
9743 + ethernet@ea000 {
9744 + cell-index = <5>;
9745 + compatible = "fsl,fman-memac";
9746 + reg = <0xea000 0x1000>;
9747 + fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
9748 + ptp-timer = <&ptp_timer0>;
9749 + pcsphy-handle = <&pcsphy5>;
9750 + };
9751 +
9752 + mdio@eb000 {
9753 + #address-cells = <1>;
9754 + #size-cells = <0>;
9755 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9756 + reg = <0xeb000 0x1000>;
9757 +
9758 + pcsphy5: ethernet-phy@0 {
9759 + reg = <0x0>;
9760 + };
9761 + };
9762 +};
9763 --- /dev/null
9764 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
9765 @@ -0,0 +1,47 @@
9766 +/*
9767 + * QorIQ FMan v3 OH ports device tree
9768 + *
9769 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9770 + *
9771 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9772 + */
9773 +
9774 +fman@1a00000 {
9775 +
9776 + fman0_oh1: port@82000 {
9777 + cell-index = <0>;
9778 + compatible = "fsl,fman-port-oh";
9779 + reg = <0x82000 0x1000>;
9780 + };
9781 +
9782 + fman0_oh2: port@83000 {
9783 + cell-index = <1>;
9784 + compatible = "fsl,fman-port-oh";
9785 + reg = <0x83000 0x1000>;
9786 + };
9787 +
9788 + fman0_oh3: port@84000 {
9789 + cell-index = <2>;
9790 + compatible = "fsl,fman-port-oh";
9791 + reg = <0x84000 0x1000>;
9792 + };
9793 +
9794 + fman0_oh4: port@85000 {
9795 + cell-index = <3>;
9796 + compatible = "fsl,fman-port-oh";
9797 + reg = <0x85000 0x1000>;
9798 + };
9799 +
9800 + fman0_oh5: port@86000 {
9801 + cell-index = <4>;
9802 + compatible = "fsl,fman-port-oh";
9803 + reg = <0x86000 0x1000>;
9804 + };
9805 +
9806 + fman0_oh6: port@87000 {
9807 + cell-index = <5>;
9808 + compatible = "fsl,fman-port-oh";
9809 + reg = <0x87000 0x1000>;
9810 + };
9811 +
9812 +};
9813 --- /dev/null
9814 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
9815 @@ -0,0 +1,130 @@
9816 +/*
9817 + * QorIQ FMan v3 device tree
9818 + *
9819 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9820 + *
9821 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9822 + */
9823 +
9824 +fman0: fman@1a00000 {
9825 + #address-cells = <1>;
9826 + #size-cells = <1>;
9827 + cell-index = <0>;
9828 + compatible = "fsl,fman";
9829 + ranges = <0x0 0x00 0x1a00000 0x100000>;
9830 + reg = <0x0 0x1a00000 0x0 0x100000>;
9831 + interrupts = <0 44 0x4>, <0 45 0x4>;
9832 + clocks = <&clockgen 3 0>;
9833 + clock-names = "fmanclk";
9834 + fsl,qman-channel-range = <0x800 0x10>;
9835 +
9836 + cc {
9837 + compatible = "fsl,fman-cc";
9838 + };
9839 +
9840 + muram@0 {
9841 + compatible = "fsl,fman-muram";
9842 + reg = <0x0 0x60000>;
9843 + };
9844 +
9845 + bmi@80000 {
9846 + compatible = "fsl,fman-bmi";
9847 + reg = <0x80000 0x400>;
9848 + };
9849 +
9850 + qmi@80400 {
9851 + compatible = "fsl,fman-qmi";
9852 + reg = <0x80400 0x400>;
9853 + };
9854 +
9855 + fman0_oh_0x2: port@82000 {
9856 + cell-index = <0x2>;
9857 + compatible = "fsl,fman-v3-port-oh";
9858 + reg = <0x82000 0x1000>;
9859 + fsl,qman-channel-id = <0x809>;
9860 + };
9861 +
9862 + fman0_oh_0x3: port@83000 {
9863 + cell-index = <0x3>;
9864 + compatible = "fsl,fman-v3-port-oh";
9865 + reg = <0x83000 0x1000>;
9866 + fsl,qman-channel-id = <0x80a>;
9867 + };
9868 +
9869 + fman0_oh_0x4: port@84000 {
9870 + cell-index = <0x4>;
9871 + compatible = "fsl,fman-v3-port-oh";
9872 + reg = <0x84000 0x1000>;
9873 + fsl,qman-channel-id = <0x80b>;
9874 + };
9875 +
9876 + fman0_oh_0x5: port@85000 {
9877 + cell-index = <0x5>;
9878 + compatible = "fsl,fman-v3-port-oh";
9879 + reg = <0x85000 0x1000>;
9880 + fsl,qman-channel-id = <0x80c>;
9881 + };
9882 +
9883 + fman0_oh_0x6: port@86000 {
9884 + cell-index = <0x6>;
9885 + compatible = "fsl,fman-v3-port-oh";
9886 + reg = <0x86000 0x1000>;
9887 + fsl,qman-channel-id = <0x80d>;
9888 + };
9889 +
9890 + fman0_oh_0x7: port@87000 {
9891 + cell-index = <0x7>;
9892 + compatible = "fsl,fman-v3-port-oh";
9893 + reg = <0x87000 0x1000>;
9894 + fsl,qman-channel-id = <0x80e>;
9895 + };
9896 +
9897 + policer@c0000 {
9898 + compatible = "fsl,fman-policer";
9899 + reg = <0xc0000 0x1000>;
9900 + };
9901 +
9902 + keygen@c1000 {
9903 + compatible = "fsl,fman-keygen";
9904 + reg = <0xc1000 0x1000>;
9905 + };
9906 +
9907 + dma@c2000 {
9908 + compatible = "fsl,fman-dma";
9909 + reg = <0xc2000 0x1000>;
9910 + };
9911 +
9912 + fpm@c3000 {
9913 + compatible = "fsl,fman-fpm";
9914 + reg = <0xc3000 0x1000>;
9915 + };
9916 +
9917 + parser@c7000 {
9918 + compatible = "fsl,fman-parser";
9919 + reg = <0xc7000 0x1000>;
9920 + };
9921 +
9922 + vsps@dc000 {
9923 + compatible = "fsl,fman-vsps";
9924 + reg = <0xdc000 0x1000>;
9925 + };
9926 +
9927 + mdio0: mdio@fc000 {
9928 + #address-cells = <1>;
9929 + #size-cells = <0>;
9930 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9931 + reg = <0xfc000 0x1000>;
9932 + };
9933 +
9934 + xmdio0: mdio@fd000 {
9935 + #address-cells = <1>;
9936 + #size-cells = <0>;
9937 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9938 + reg = <0xfd000 0x1000>;
9939 + };
9940 +
9941 + ptp_timer0: ptp-timer@fe000 {
9942 + compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
9943 + reg = <0xfe000 0x1000>;
9944 + };
9945 +};
9946 --- /dev/null
9947 +++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
9948 @@ -0,0 +1,104 @@
9949 +/*
9950 + * QorIQ QMan Portals device tree
9951 + *
9952 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9953 + *
9954 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9955 + */
9956 +
9957 +&qportals {
9958 + #address-cells = <1>;
9959 + #size-cells = <1>;
9960 + compatible = "simple-bus";
9961 +
9962 + qportal0: qman-portal@0 {
9963 + compatible = "fsl,qman-portal";
9964 + reg = <0x0 0x4000 0x4000000 0x4000>;
9965 + interrupts = <0 172 0x4>;
9966 + cell-index = <0>;
9967 + };
9968 +
9969 + qportal1: qman-portal@10000 {
9970 + compatible = "fsl,qman-portal";
9971 + reg = <0x10000 0x4000 0x4010000 0x4000>;
9972 + interrupts = <0 174 0x4>;
9973 + cell-index = <1>;
9974 + };
9975 +
9976 + qportal2: qman-portal@20000 {
9977 + compatible = "fsl,qman-portal";
9978 + reg = <0x20000 0x4000 0x4020000 0x4000>;
9979 + interrupts = <0 176 0x4>;
9980 + cell-index = <2>;
9981 + };
9982 +
9983 + qportal3: qman-portal@30000 {
9984 + compatible = "fsl,qman-portal";
9985 + reg = <0x30000 0x4000 0x4030000 0x4000>;
9986 + interrupts = <0 178 0x4>;
9987 + cell-index = <3>;
9988 + };
9989 +
9990 + qportal4: qman-portal@40000 {
9991 + compatible = "fsl,qman-portal";
9992 + reg = <0x40000 0x4000 0x4040000 0x4000>;
9993 + interrupts = <0 180 0x4>;
9994 + cell-index = <4>;
9995 + };
9996 +
9997 + qportal5: qman-portal@50000 {
9998 + compatible = "fsl,qman-portal";
9999 + reg = <0x50000 0x4000 0x4050000 0x4000>;
10000 + interrupts = <0 182 0x4>;
10001 + cell-index = <5>;
10002 + };
10003 +
10004 + qportal6: qman-portal@60000 {
10005 + compatible = "fsl,qman-portal";
10006 + reg = <0x60000 0x4000 0x4060000 0x4000>;
10007 + interrupts = <0 184 0x4>;
10008 + cell-index = <6>;
10009 + };
10010 +
10011 + qportal7: qman-portal@70000 {
10012 + compatible = "fsl,qman-portal";
10013 + reg = <0x70000 0x4000 0x4070000 0x4000>;
10014 + interrupts = <0 186 0x4>;
10015 + cell-index = <7>;
10016 + };
10017 +
10018 + qportal8: qman-portal@80000 {
10019 + compatible = "fsl,qman-portal";
10020 + reg = <0x80000 0x4000 0x4080000 0x4000>;
10021 + interrupts = <0 188 0x4>;
10022 + cell-index = <8>;
10023 + };
10024 +
10025 + qman-fqids@0 {
10026 + compatible = "fsl,fqid-range";
10027 + fsl,fqid-range = <256 256>;
10028 + };
10029 +
10030 + qman-fqids@1 {
10031 + compatible = "fsl,fqid-range";
10032 + fsl,fqid-range = <32768 32768>;
10033 + };
10034 +
10035 + qman-pools@0 {
10036 + compatible = "fsl,pool-channel-range";
10037 + fsl,pool-channel-range = <0x401 0xf>;
10038 + };
10039 +
10040 + qman-cgrids@0 {
10041 + compatible = "fsl,cgrid-range";
10042 + fsl,cgrid-range = <0 256>;
10043 + };
10044 +
10045 + qman-ceetm@0 {
10046 + compatible = "fsl,qman-ceetm";
10047 + fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
10048 + fsl,ceetm-sp-range = <0 12>;
10049 + fsl,ceetm-lni-range = <0 8>;
10050 + fsl,ceetm-channel-range = <0 32>;
10051 + };
10052 +};
10053 --- a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10054 +++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10055 @@ -38,51 +38,61 @@
10056 compatible = "simple-bus";
10057
10058 bman-portal@0 {
10059 + cell-index = <0>;
10060 compatible = "fsl,bman-portal";
10061 reg = <0x0 0x4000>, <0x100000 0x1000>;
10062 interrupts = <105 2 0 0>;
10063 };
10064 bman-portal@4000 {
10065 + cell-index = <1>;
10066 compatible = "fsl,bman-portal";
10067 reg = <0x4000 0x4000>, <0x101000 0x1000>;
10068 interrupts = <107 2 0 0>;
10069 };
10070 bman-portal@8000 {
10071 + cell-index = <2>;
10072 compatible = "fsl,bman-portal";
10073 reg = <0x8000 0x4000>, <0x102000 0x1000>;
10074 interrupts = <109 2 0 0>;
10075 };
10076 bman-portal@c000 {
10077 + cell-index = <3>;
10078 compatible = "fsl,bman-portal";
10079 reg = <0xc000 0x4000>, <0x103000 0x1000>;
10080 interrupts = <111 2 0 0>;
10081 };
10082 bman-portal@10000 {
10083 + cell-index = <4>;
10084 compatible = "fsl,bman-portal";
10085 reg = <0x10000 0x4000>, <0x104000 0x1000>;
10086 interrupts = <113 2 0 0>;
10087 };
10088 bman-portal@14000 {
10089 + cell-index = <5>;
10090 compatible = "fsl,bman-portal";
10091 reg = <0x14000 0x4000>, <0x105000 0x1000>;
10092 interrupts = <115 2 0 0>;
10093 };
10094 bman-portal@18000 {
10095 + cell-index = <6>;
10096 compatible = "fsl,bman-portal";
10097 reg = <0x18000 0x4000>, <0x106000 0x1000>;
10098 interrupts = <117 2 0 0>;
10099 };
10100 bman-portal@1c000 {
10101 + cell-index = <7>;
10102 compatible = "fsl,bman-portal";
10103 reg = <0x1c000 0x4000>, <0x107000 0x1000>;
10104 interrupts = <119 2 0 0>;
10105 };
10106 bman-portal@20000 {
10107 + cell-index = <8>;
10108 compatible = "fsl,bman-portal";
10109 reg = <0x20000 0x4000>, <0x108000 0x1000>;
10110 interrupts = <121 2 0 0>;
10111 };
10112 bman-portal@24000 {
10113 + cell-index = <9>;
10114 compatible = "fsl,bman-portal";
10115 reg = <0x24000 0x4000>, <0x109000 0x1000>;
10116 interrupts = <123 2 0 0>;
10117 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10118 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10119 @@ -35,14 +35,14 @@
10120 fman@400000 {
10121 fman0_rx_0x10: port@90000 {
10122 cell-index = <0x10>;
10123 - compatible = "fsl,fman-v3-port-rx";
10124 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10125 reg = <0x90000 0x1000>;
10126 fsl,fman-10g-port;
10127 };
10128
10129 fman0_tx_0x30: port@b0000 {
10130 cell-index = <0x30>;
10131 - compatible = "fsl,fman-v3-port-tx";
10132 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10133 reg = <0xb0000 0x1000>;
10134 fsl,fman-10g-port;
10135 };
10136 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10137 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10138 @@ -35,14 +35,14 @@
10139 fman@400000 {
10140 fman0_rx_0x11: port@91000 {
10141 cell-index = <0x11>;
10142 - compatible = "fsl,fman-v3-port-rx";
10143 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10144 reg = <0x91000 0x1000>;
10145 fsl,fman-10g-port;
10146 };
10147
10148 fman0_tx_0x31: port@b1000 {
10149 cell-index = <0x31>;
10150 - compatible = "fsl,fman-v3-port-tx";
10151 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10152 reg = <0xb1000 0x1000>;
10153 fsl,fman-10g-port;
10154 };
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