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layerscape: update kernel patches
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 302-dts-support-layercape.patch
1 From bfa4a794f91162cfeccfa4d59121cde9a84e32a3 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 10:02:10 +0800
4 Subject: [PATCH] dts: support layercape
5
6 This is a integrated patch for layerscape dts support.
7
8 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
9 Signed-off-by: Alison Wang <b18965@freescale.com>
10 Signed-off-by: Li Yang <leoyang.li@nxp.com>
11 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
12 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
15 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
16 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
17 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
18 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
19 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
20 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
21 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
22 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
23 Signed-off-by: Meng Yi <meng.yi@nxp.com>
24 Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
25 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
26 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
27 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
28 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
29 ---
30 arch/arm/boot/dts/alpine.dtsi | 2 +-
31 arch/arm/boot/dts/axm55xx.dtsi | 2 +-
32 arch/arm/boot/dts/ecx-2000.dts | 2 +-
33 arch/arm/boot/dts/imx6ul.dtsi | 4 +-
34 arch/arm/boot/dts/keystone.dtsi | 4 +-
35 arch/arm/boot/dts/ls1021a-qds.dts | 13 +
36 arch/arm/boot/dts/ls1021a-twr.dts | 13 +
37 arch/arm/boot/dts/ls1021a.dtsi | 155 ++--
38 arch/arm/boot/dts/mt6580.dtsi | 2 +-
39 arch/arm/boot/dts/mt6589.dtsi | 2 +-
40 arch/arm/boot/dts/mt8127.dtsi | 2 +-
41 arch/arm/boot/dts/mt8135.dtsi | 2 +-
42 arch/arm/boot/dts/rk3288.dtsi | 2 +-
43 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
44 arch/arm/boot/dts/sun7i-a20.dtsi | 4 +-
45 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
46 arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
47 arch/arm64/boot/dts/freescale/Makefile | 16 +
48 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 177 ++++
49 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 198 +++++
50 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 134 +++
51 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 594 ++++++++++++++
52 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi | 45 +
53 .../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 69 ++
54 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 171 +++-
55 .../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 69 ++
56 .../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++
57 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 113 ++-
58 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 302 ++++++-
59 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi | 48 ++
60 .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 109 +++
61 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 363 ++++++++
62 .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 76 ++
63 .../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++
64 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 218 +++++
65 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 793 ++++++++++++++++++
66 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 173 ++++
67 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 236 ++++++
68 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 818 ++++++++++++++++++
69 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 191 ++---
70 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 169 ++--
71 arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 9 +-
72 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 763 +++--------------
73 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 161 ++++
74 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 162 ++++
75 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 140 ++++
76 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 195 +++++
77 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 198 +++++
78 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 161 ++++
79 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 912 +++++++++++++++++++++
80 .../boot/dts/freescale/qoriq-bman1-portals.dtsi | 81 ++
81 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 66 ++
82 .../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 +
83 .../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 +
84 .../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 +
85 .../boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi | 42 +
86 .../boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi | 42 +
87 .../boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi | 42 +
88 .../boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi | 42 +
89 .../boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi | 42 +
90 .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 ++
91 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi | 130 +++
92 .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 104 +++
93 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 +
94 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
95 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
96 66 files changed, 7988 insertions(+), 1021 deletions(-)
97 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
98 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
99 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
100 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
101 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
102 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
103 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
104 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
105 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
106 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
107 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
108 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
109 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
110 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
111 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
112 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
113 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
114 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
115 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
116 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
117 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
118 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
119 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
120 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
121 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
122 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
123 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
124 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
125 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
126 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
127 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
128 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
129 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
130 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
131 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
132 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
133 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
134 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
135
136 diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
137 index db8752fc..d0eefc3b 100644
138 --- a/arch/arm/boot/dts/alpine.dtsi
139 +++ b/arch/arm/boot/dts/alpine.dtsi
140 @@ -93,7 +93,7 @@
141 interrupt-controller;
142 reg = <0x0 0xfb001000 0x0 0x1000>,
143 <0x0 0xfb002000 0x0 0x2000>,
144 - <0x0 0xfb004000 0x0 0x1000>,
145 + <0x0 0xfb004000 0x0 0x2000>,
146 <0x0 0xfb006000 0x0 0x2000>;
147 interrupts =
148 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
150 index a9d6d593..47799f59 100644
151 --- a/arch/arm/boot/dts/axm55xx.dtsi
152 +++ b/arch/arm/boot/dts/axm55xx.dtsi
153 @@ -62,7 +62,7 @@
154 #address-cells = <0>;
155 interrupt-controller;
156 reg = <0x20 0x01001000 0 0x1000>,
157 - <0x20 0x01002000 0 0x1000>,
158 + <0x20 0x01002000 0 0x2000>,
159 <0x20 0x01004000 0 0x2000>,
160 <0x20 0x01006000 0 0x2000>;
161 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
162 diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
163 index 2ccbb57f..c15e7e0c 100644
164 --- a/arch/arm/boot/dts/ecx-2000.dts
165 +++ b/arch/arm/boot/dts/ecx-2000.dts
166 @@ -99,7 +99,7 @@
167 interrupt-controller;
168 interrupts = <1 9 0xf04>;
169 reg = <0xfff11000 0x1000>,
170 - <0xfff12000 0x1000>,
171 + <0xfff12000 0x2000>,
172 <0xfff14000 0x2000>,
173 <0xfff16000 0x2000>;
174 };
175 diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
176 index c5c05fdc..c1396873 100644
177 --- a/arch/arm/boot/dts/imx6ul.dtsi
178 +++ b/arch/arm/boot/dts/imx6ul.dtsi
179 @@ -89,11 +89,11 @@
180 };
181
182 intc: interrupt-controller@00a01000 {
183 - compatible = "arm,cortex-a7-gic";
184 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
185 #interrupt-cells = <3>;
186 interrupt-controller;
187 reg = <0x00a01000 0x1000>,
188 - <0x00a02000 0x1000>,
189 + <0x00a02000 0x2000>,
190 <0x00a04000 0x2000>,
191 <0x00a06000 0x2000>;
192 };
193 diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
194 index 02708ba2..e30c83fc 100644
195 --- a/arch/arm/boot/dts/keystone.dtsi
196 +++ b/arch/arm/boot/dts/keystone.dtsi
197 @@ -30,12 +30,12 @@
198 };
199
200 gic: interrupt-controller {
201 - compatible = "arm,cortex-a15-gic";
202 + compatible = "arm,gic-400", "arm,cortex-a15-gic";
203 #interrupt-cells = <3>;
204 interrupt-controller;
205 reg = <0x0 0x02561000 0x0 0x1000>,
206 <0x0 0x02562000 0x0 0x2000>,
207 - <0x0 0x02564000 0x0 0x1000>,
208 + <0x0 0x02564000 0x0 0x2000>,
209 <0x0 0x02566000 0x0 0x2000>;
210 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
211 IRQ_TYPE_LEVEL_HIGH)>;
212 diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
213 index 94087531..5611a9c9 100644
214 --- a/arch/arm/boot/dts/ls1021a-qds.dts
215 +++ b/arch/arm/boot/dts/ls1021a-qds.dts
216 @@ -124,6 +124,19 @@
217 };
218 };
219
220 +&qspi {
221 + num-cs = <2>;
222 + status = "okay";
223 +
224 + qflash0: s25fl128s@0 {
225 + compatible = "spansion,m25p80";
226 + #address-cells = <1>;
227 + #size-cells = <1>;
228 + spi-max-frequency = <20000000>;
229 + reg = <0>;
230 + };
231 +};
232 +
233 &enet0 {
234 tbi-handle = <&tbi0>;
235 phy-handle = <&sgmii_phy1c>;
236 diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
237 index a8b148ad..907e5392 100644
238 --- a/arch/arm/boot/dts/ls1021a-twr.dts
239 +++ b/arch/arm/boot/dts/ls1021a-twr.dts
240 @@ -142,6 +142,19 @@
241 };
242 };
243
244 +&qspi {
245 + num-cs = <2>;
246 + status = "okay";
247 +
248 + qflash0: n25q128a13@0 {
249 + compatible = "n25q128a13", "jedec,spi-nor";
250 + #address-cells = <1>;
251 + #size-cells = <1>;
252 + spi-max-frequency = <20000000>;
253 + reg = <0>;
254 + };
255 +};
256 +
257 &enet0 {
258 tbi-handle = <&tbi1>;
259 phy-handle = <&sgmii_phy2>;
260 diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
261 index 368e2193..9d8d1fee 100644
262 --- a/arch/arm/boot/dts/ls1021a.dtsi
263 +++ b/arch/arm/boot/dts/ls1021a.dtsi
264 @@ -74,17 +74,24 @@
265 compatible = "arm,cortex-a7";
266 device_type = "cpu";
267 reg = <0xf00>;
268 - clocks = <&cluster1_clk>;
269 + clocks = <&clockgen 1 0>;
270 };
271
272 cpu@f01 {
273 compatible = "arm,cortex-a7";
274 device_type = "cpu";
275 reg = <0xf01>;
276 - clocks = <&cluster1_clk>;
277 + clocks = <&clockgen 1 0>;
278 };
279 };
280
281 + sysclk: sysclk {
282 + compatible = "fixed-clock";
283 + #clock-cells = <0>;
284 + clock-frequency = <100000000>;
285 + clock-output-names = "sysclk";
286 + };
287 +
288 timer {
289 compatible = "arm,armv7-timer";
290 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
291 @@ -108,11 +115,11 @@
292 ranges;
293
294 gic: interrupt-controller@1400000 {
295 - compatible = "arm,cortex-a7-gic";
296 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
297 #interrupt-cells = <3>;
298 interrupt-controller;
299 reg = <0x0 0x1401000 0x0 0x1000>,
300 - <0x0 0x1402000 0x0 0x1000>,
301 + <0x0 0x1402000 0x0 0x2000>,
302 <0x0 0x1404000 0x0 0x2000>,
303 <0x0 0x1406000 0x0 0x2000>;
304 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
305 @@ -120,14 +127,14 @@
306 };
307
308 msi1: msi-controller@1570e00 {
309 - compatible = "fsl,1s1021a-msi";
310 + compatible = "fsl,ls1021a-msi";
311 reg = <0x0 0x1570e00 0x0 0x8>;
312 msi-controller;
313 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
314 };
315
316 msi2: msi-controller@1570e08 {
317 - compatible = "fsl,1s1021a-msi";
318 + compatible = "fsl,ls1021a-msi";
319 reg = <0x0 0x1570e08 0x0 0x8>;
320 msi-controller;
321 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
322 @@ -137,11 +144,12 @@
323 compatible = "fsl,ifc", "simple-bus";
324 reg = <0x0 0x1530000 0x0 0x10000>;
325 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
326 + big-endian;
327 };
328
329 dcfg: dcfg@1ee0000 {
330 compatible = "fsl,ls1021a-dcfg", "syscon";
331 - reg = <0x0 0x1ee0000 0x0 0x10000>;
332 + reg = <0x0 0x1ee0000 0x0 0x1000>;
333 big-endian;
334 };
335
336 @@ -163,7 +171,7 @@
337 <0x0 0x20220520 0x0 0x4>;
338 reg-names = "ahci", "sata-ecc";
339 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
340 - clocks = <&platform_clk 1>;
341 + clocks = <&clockgen 4 1>;
342 dma-coherent;
343 status = "disabled";
344 };
345 @@ -214,41 +222,10 @@
346 };
347
348 clockgen: clocking@1ee1000 {
349 - #address-cells = <1>;
350 - #size-cells = <1>;
351 - ranges = <0x0 0x0 0x1ee1000 0x10000>;
352 -
353 - sysclk: sysclk {
354 - compatible = "fixed-clock";
355 - #clock-cells = <0>;
356 - clock-output-names = "sysclk";
357 - };
358 -
359 - cga_pll1: pll@800 {
360 - compatible = "fsl,qoriq-core-pll-2.0";
361 - #clock-cells = <1>;
362 - reg = <0x800 0x10>;
363 - clocks = <&sysclk>;
364 - clock-output-names = "cga-pll1", "cga-pll1-div2",
365 - "cga-pll1-div4";
366 - };
367 -
368 - platform_clk: pll@c00 {
369 - compatible = "fsl,qoriq-core-pll-2.0";
370 - #clock-cells = <1>;
371 - reg = <0xc00 0x10>;
372 - clocks = <&sysclk>;
373 - clock-output-names = "platform-clk", "platform-clk-div2";
374 - };
375 -
376 - cluster1_clk: clk0c0@0 {
377 - compatible = "fsl,qoriq-core-mux-2.0";
378 - #clock-cells = <0>;
379 - reg = <0x0 0x10>;
380 - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
381 - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
382 - clock-output-names = "cluster1-clk";
383 - };
384 + compatible = "fsl,ls1021a-clockgen";
385 + reg = <0x0 0x1ee1000 0x0 0x1000>;
386 + #clock-cells = <2>;
387 + clocks = <&sysclk>;
388 };
389
390 dspi0: dspi@2100000 {
391 @@ -258,7 +235,7 @@
392 reg = <0x0 0x2100000 0x0 0x10000>;
393 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
394 clock-names = "dspi";
395 - clocks = <&platform_clk 1>;
396 + clocks = <&clockgen 4 1>;
397 spi-num-chipselects = <6>;
398 big-endian;
399 status = "disabled";
400 @@ -271,12 +248,27 @@
401 reg = <0x0 0x2110000 0x0 0x10000>;
402 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
403 clock-names = "dspi";
404 - clocks = <&platform_clk 1>;
405 + clocks = <&clockgen 4 1>;
406 spi-num-chipselects = <6>;
407 big-endian;
408 status = "disabled";
409 };
410
411 + qspi: quadspi@1550000 {
412 + compatible = "fsl,ls1021a-qspi";
413 + #address-cells = <1>;
414 + #size-cells = <0>;
415 + reg = <0x0 0x1550000 0x0 0x10000>,
416 + <0x0 0x40000000 0x0 0x4000000>;
417 + reg-names = "QuadSPI", "QuadSPI-memory";
418 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
419 + clock-names = "qspi_en", "qspi";
420 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
421 + big-endian;
422 + amba-base = <0x40000000>;
423 + status = "disabled";
424 + };
425 +
426 i2c0: i2c@2180000 {
427 compatible = "fsl,vf610-i2c";
428 #address-cells = <1>;
429 @@ -284,7 +276,7 @@
430 reg = <0x0 0x2180000 0x0 0x10000>;
431 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
432 clock-names = "i2c";
433 - clocks = <&platform_clk 1>;
434 + clocks = <&clockgen 4 1>;
435 status = "disabled";
436 };
437
438 @@ -295,7 +287,7 @@
439 reg = <0x0 0x2190000 0x0 0x10000>;
440 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
441 clock-names = "i2c";
442 - clocks = <&platform_clk 1>;
443 + clocks = <&clockgen 4 1>;
444 status = "disabled";
445 };
446
447 @@ -306,7 +298,7 @@
448 reg = <0x0 0x21a0000 0x0 0x10000>;
449 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
450 clock-names = "i2c";
451 - clocks = <&platform_clk 1>;
452 + clocks = <&clockgen 4 1>;
453 status = "disabled";
454 };
455
456 @@ -399,7 +391,7 @@
457 compatible = "fsl,ls1021a-lpuart";
458 reg = <0x0 0x2960000 0x0 0x1000>;
459 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
460 - clocks = <&platform_clk 1>;
461 + clocks = <&clockgen 4 1>;
462 clock-names = "ipg";
463 status = "disabled";
464 };
465 @@ -408,7 +400,7 @@
466 compatible = "fsl,ls1021a-lpuart";
467 reg = <0x0 0x2970000 0x0 0x1000>;
468 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
469 - clocks = <&platform_clk 1>;
470 + clocks = <&clockgen 4 1>;
471 clock-names = "ipg";
472 status = "disabled";
473 };
474 @@ -417,7 +409,7 @@
475 compatible = "fsl,ls1021a-lpuart";
476 reg = <0x0 0x2980000 0x0 0x1000>;
477 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
478 - clocks = <&platform_clk 1>;
479 + clocks = <&clockgen 4 1>;
480 clock-names = "ipg";
481 status = "disabled";
482 };
483 @@ -426,7 +418,7 @@
484 compatible = "fsl,ls1021a-lpuart";
485 reg = <0x0 0x2990000 0x0 0x1000>;
486 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
487 - clocks = <&platform_clk 1>;
488 + clocks = <&clockgen 4 1>;
489 clock-names = "ipg";
490 status = "disabled";
491 };
492 @@ -435,16 +427,26 @@
493 compatible = "fsl,ls1021a-lpuart";
494 reg = <0x0 0x29a0000 0x0 0x1000>;
495 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
496 - clocks = <&platform_clk 1>;
497 + clocks = <&clockgen 4 1>;
498 clock-names = "ipg";
499 status = "disabled";
500 };
501
502 + ftm0: ftm0@29d0000 {
503 + compatible = "fsl,ls1021a-ftm";
504 + reg = <0x0 0x29d0000 0x0 0x10000>,
505 + <0x0 0x1ee2140 0x0 0x4>;
506 + reg-names = "ftm", "FlexTimer1";
507 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
508 + big-endian;
509 + status = "okay";
510 + };
511 +
512 wdog0: watchdog@2ad0000 {
513 compatible = "fsl,imx21-wdt";
514 reg = <0x0 0x2ad0000 0x0 0x10000>;
515 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
516 - clocks = <&platform_clk 1>;
517 + clocks = <&clockgen 4 1>;
518 clock-names = "wdog-en";
519 big-endian;
520 };
521 @@ -454,8 +456,8 @@
522 compatible = "fsl,vf610-sai";
523 reg = <0x0 0x2b50000 0x0 0x10000>;
524 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
525 - clocks = <&platform_clk 1>, <&platform_clk 1>,
526 - <&platform_clk 1>, <&platform_clk 1>;
527 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
528 + <&clockgen 4 1>, <&clockgen 4 1>;
529 clock-names = "bus", "mclk1", "mclk2", "mclk3";
530 dma-names = "tx", "rx";
531 dmas = <&edma0 1 47>,
532 @@ -468,8 +470,8 @@
533 compatible = "fsl,vf610-sai";
534 reg = <0x0 0x2b60000 0x0 0x10000>;
535 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
536 - clocks = <&platform_clk 1>, <&platform_clk 1>,
537 - <&platform_clk 1>, <&platform_clk 1>;
538 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
539 + <&clockgen 4 1>, <&clockgen 4 1>;
540 clock-names = "bus", "mclk1", "mclk2", "mclk3";
541 dma-names = "tx", "rx";
542 dmas = <&edma0 1 45>,
543 @@ -489,16 +491,31 @@
544 dma-channels = <32>;
545 big-endian;
546 clock-names = "dmamux0", "dmamux1";
547 - clocks = <&platform_clk 1>,
548 - <&platform_clk 1>;
549 + clocks = <&clockgen 4 1>,
550 + <&clockgen 4 1>;
551 + };
552 +
553 + qdma: qdma@8390000 {
554 + compatible = "fsl,ls1021a-qdma";
555 + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
556 + <0x0 0x8389000 0x0 0x1000>, /* Status regs */
557 + <0x0 0x838a000 0x0 0x2000>; /* Block regs */
558 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
559 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
560 + interrupt-names = "qdma-error", "qdma-queue";
561 + channels = <8>;
562 + queues = <2>;
563 + status-sizes = <64>;
564 + queue-sizes = <64 64>;
565 + big-endian;
566 };
567
568 dcu: dcu@2ce0000 {
569 compatible = "fsl,ls1021a-dcu";
570 reg = <0x0 0x2ce0000 0x0 0x10000>;
571 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
572 - clocks = <&platform_clk 0>,
573 - <&platform_clk 0>;
574 + clocks = <&clockgen 4 0>,
575 + <&clockgen 4 0>;
576 clock-names = "dcu", "pix";
577 big-endian;
578 status = "disabled";
579 @@ -626,6 +643,8 @@
580 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
581 dr_mode = "host";
582 snps,quirk-frame-length-adjustment = <0x20>;
583 + configure-gfladj;
584 + dma-coherent;
585 snps,dis_rxdet_inp3_quirk;
586 };
587
588 @@ -634,7 +653,9 @@
589 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
590 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
591 reg-names = "regs", "config";
592 - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
593 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
594 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
595 + interrupt-names = "pme", "aer";
596 fsl,pcie-scfg = <&scfg 0>;
597 #address-cells = <3>;
598 #size-cells = <2>;
599 @@ -643,7 +664,7 @@
600 bus-range = <0x0 0xff>;
601 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
602 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
603 - msi-parent = <&msi1>;
604 + msi-parent = <&msi1>, <&msi2>;
605 #interrupt-cells = <1>;
606 interrupt-map-mask = <0 0 0 7>;
607 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
608 @@ -657,7 +678,9 @@
609 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
610 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
611 reg-names = "regs", "config";
612 - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
613 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
614 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
615 + interrupt-names = "pme", "aer";
616 fsl,pcie-scfg = <&scfg 1>;
617 #address-cells = <3>;
618 #size-cells = <2>;
619 @@ -666,7 +689,7 @@
620 bus-range = <0x0 0xff>;
621 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
622 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
623 - msi-parent = <&msi2>;
624 + msi-parent = <&msi1>, <&msi2>;
625 #interrupt-cells = <1>;
626 interrupt-map-mask = <0 0 0 7>;
627 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
628 diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
629 index 06fdf6c2..a349dba5 100644
630 --- a/arch/arm/boot/dts/mt6580.dtsi
631 +++ b/arch/arm/boot/dts/mt6580.dtsi
632 @@ -91,7 +91,7 @@
633 #interrupt-cells = <3>;
634 interrupt-parent = <&gic>;
635 reg = <0x10211000 0x1000>,
636 - <0x10212000 0x1000>,
637 + <0x10212000 0x2000>,
638 <0x10214000 0x2000>,
639 <0x10216000 0x2000>;
640 };
641 diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
642 index 88b3cb12..0d6f60af 100644
643 --- a/arch/arm/boot/dts/mt6589.dtsi
644 +++ b/arch/arm/boot/dts/mt6589.dtsi
645 @@ -102,7 +102,7 @@
646 #interrupt-cells = <3>;
647 interrupt-parent = <&gic>;
648 reg = <0x10211000 0x1000>,
649 - <0x10212000 0x1000>,
650 + <0x10212000 0x2000>,
651 <0x10214000 0x2000>,
652 <0x10216000 0x2000>;
653 };
654 diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
655 index 52086c80..916c095d 100644
656 --- a/arch/arm/boot/dts/mt8127.dtsi
657 +++ b/arch/arm/boot/dts/mt8127.dtsi
658 @@ -129,7 +129,7 @@
659 #interrupt-cells = <3>;
660 interrupt-parent = <&gic>;
661 reg = <0 0x10211000 0 0x1000>,
662 - <0 0x10212000 0 0x1000>,
663 + <0 0x10212000 0 0x2000>,
664 <0 0x10214000 0 0x2000>,
665 <0 0x10216000 0 0x2000>;
666 };
667 diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
668 index 1d7f92bd..a97b4ee4 100644
669 --- a/arch/arm/boot/dts/mt8135.dtsi
670 +++ b/arch/arm/boot/dts/mt8135.dtsi
671 @@ -221,7 +221,7 @@
672 #interrupt-cells = <3>;
673 interrupt-parent = <&gic>;
674 reg = <0 0x10211000 0 0x1000>,
675 - <0 0x10212000 0 0x1000>,
676 + <0 0x10212000 0 0x2000>,
677 <0 0x10214000 0 0x2000>,
678 <0 0x10216000 0 0x2000>;
679 };
680 diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
681 index 17ec2e2d..559fc549 100644
682 --- a/arch/arm/boot/dts/rk3288.dtsi
683 +++ b/arch/arm/boot/dts/rk3288.dtsi
684 @@ -1109,7 +1109,7 @@
685 #address-cells = <0>;
686
687 reg = <0xffc01000 0x1000>,
688 - <0xffc02000 0x1000>,
689 + <0xffc02000 0x2000>,
690 <0xffc04000 0x2000>,
691 <0xffc06000 0x2000>;
692 interrupts = <GIC_PPI 9 0xf04>;
693 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
694 index ce196045..97f28399 100644
695 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
696 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
697 @@ -791,7 +791,7 @@
698 gic: interrupt-controller@01c81000 {
699 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
700 reg = <0x01c81000 0x1000>,
701 - <0x01c82000 0x1000>,
702 + <0x01c82000 0x2000>,
703 <0x01c84000 0x2000>,
704 <0x01c86000 0x2000>;
705 interrupt-controller;
706 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
707 index 94cf5a1c..81e5a44c 100644
708 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
709 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
710 @@ -1685,9 +1685,9 @@
711 };
712
713 gic: interrupt-controller@01c81000 {
714 - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
715 + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
716 reg = <0x01c81000 0x1000>,
717 - <0x01c82000 0x1000>,
718 + <0x01c82000 0x2000>,
719 <0x01c84000 0x2000>,
720 <0x01c86000 0x2000>;
721 interrupt-controller;
722 diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
723 index 300a1bd5..cdff5888 100644
724 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
725 +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
726 @@ -488,7 +488,7 @@
727 gic: interrupt-controller@01c81000 {
728 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
729 reg = <0x01c81000 0x1000>,
730 - <0x01c82000 0x1000>,
731 + <0x01c82000 0x2000>,
732 <0x01c84000 0x2000>,
733 <0x01c86000 0x2000>;
734 interrupt-controller;
735 diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
736 index 3c5214cb..ba7e7c71 100644
737 --- a/arch/arm/boot/dts/sun9i-a80.dtsi
738 +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
739 @@ -613,7 +613,7 @@
740 gic: interrupt-controller@01c41000 {
741 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
742 reg = <0x01c41000 0x1000>,
743 - <0x01c42000 0x1000>,
744 + <0x01c42000 0x2000>,
745 <0x01c44000 0x2000>,
746 <0x01c46000 0x2000>;
747 interrupt-controller;
748 diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
749 index 1b7783db..2d7986a1 100644
750 --- a/arch/arm64/boot/dts/freescale/Makefile
751 +++ b/arch/arm64/boot/dts/freescale/Makefile
752 @@ -1,8 +1,24 @@
753 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
754 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
755 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
756 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
757 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
758 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
759 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
760 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
761 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
762 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
763 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
764 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
765 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
766 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
767 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
768 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
769 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
770 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
771 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
772 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
773 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
774
775 always := $(dtb-y)
776 subdir-y := $(dts-dirs)
777 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
778 new file mode 100644
779 index 00000000..de8ee499
780 --- /dev/null
781 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
782 @@ -0,0 +1,177 @@
783 +/*
784 + * Device Tree file for Freescale LS1012A Freedom Board.
785 + *
786 + * Copyright 2016 Freescale Semiconductor, Inc.
787 + *
788 + * This file is dual-licensed: you can use it either under the terms
789 + * of the GPLv2 or the X11 license, at your option. Note that this dual
790 + * licensing only applies to this file, and not this project as a
791 + * whole.
792 + *
793 + * a) This library is free software; you can redistribute it and/or
794 + * modify it under the terms of the GNU General Public License as
795 + * published by the Free Software Foundation; either version 2 of the
796 + * License, or (at your option) any later version.
797 + *
798 + * This library is distributed in the hope that it will be useful,
799 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
800 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
801 + * GNU General Public License for more details.
802 + *
803 + * Or, alternatively,
804 + *
805 + * b) Permission is hereby granted, free of charge, to any person
806 + * obtaining a copy of this software and associated documentation
807 + * files (the "Software"), to deal in the Software without
808 + * restriction, including without limitation the rights to use,
809 + * copy, modify, merge, publish, distribute, sublicense, and/or
810 + * sell copies of the Software, and to permit persons to whom the
811 + * Software is furnished to do so, subject to the following
812 + * conditions:
813 + *
814 + * The above copyright notice and this permission notice shall be
815 + * included in all copies or substantial portions of the Software.
816 + *
817 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
818 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
819 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
820 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
821 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
822 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
823 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
824 + * OTHER DEALINGS IN THE SOFTWARE.
825 + */
826 +/dts-v1/;
827 +
828 +#include "fsl-ls1012a.dtsi"
829 +
830 +/ {
831 + model = "LS1012A Freedom Board";
832 + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
833 +
834 + aliases {
835 + ethernet0 = &pfe_mac0;
836 + ethernet1 = &pfe_mac1;
837 + };
838 +
839 + sys_mclk: clock-mclk {
840 + compatible = "fixed-clock";
841 + #clock-cells = <0>;
842 + clock-frequency = <25000000>;
843 + };
844 +
845 + reg_1p8v: regulator-1p8v {
846 + compatible = "regulator-fixed";
847 + regulator-name = "1P8V";
848 + regulator-min-microvolt = <1800000>;
849 + regulator-max-microvolt = <1800000>;
850 + regulator-always-on;
851 + };
852 +
853 + sound {
854 + compatible = "simple-audio-card";
855 + simple-audio-card,format = "i2s";
856 + simple-audio-card,widgets =
857 + "Microphone", "Microphone Jack",
858 + "Headphone", "Headphone Jack",
859 + "Speaker", "Speaker Ext",
860 + "Line", "Line In Jack";
861 + simple-audio-card,routing =
862 + "MIC_IN", "Microphone Jack",
863 + "Microphone Jack", "Mic Bias",
864 + "LINE_IN", "Line In Jack",
865 + "Headphone Jack", "HP_OUT",
866 + "Speaker Ext", "LINE_OUT";
867 +
868 + simple-audio-card,cpu {
869 + sound-dai = <&sai2>;
870 + frame-master;
871 + bitclock-master;
872 + };
873 +
874 + simple-audio-card,codec {
875 + sound-dai = <&codec>;
876 + frame-master;
877 + bitclock-master;
878 + system-clock-frequency = <25000000>;
879 + };
880 + };
881 +};
882 +
883 +&duart0 {
884 + status = "okay";
885 +};
886 +
887 +&i2c0 {
888 + status = "okay";
889 +
890 + codec: sgtl5000@a {
891 + #sound-dai-cells = <0>;
892 + compatible = "fsl,sgtl5000";
893 + reg = <0xa>;
894 + VDDA-supply = <&reg_1p8v>;
895 + VDDIO-supply = <&reg_1p8v>;
896 + clocks = <&sys_mclk>;
897 + };
898 +};
899 +
900 +&qspi {
901 + num-cs = <1>;
902 + bus-num = <0>;
903 + status = "okay";
904 +
905 + qflash0: s25fs512s@0 {
906 + compatible = "spansion,m25p80";
907 + #address-cells = <1>;
908 + #size-cells = <1>;
909 + m25p,fast-read;
910 + spi-max-frequency = <20000000>;
911 + reg = <0>;
912 + };
913 +};
914 +
915 +&pfe {
916 + status = "okay";
917 + #address-cells = <1>;
918 + #size-cells = <0>;
919 +
920 + ethernet@0 {
921 + compatible = "fsl,pfe-gemac-port";
922 + #address-cells = <1>;
923 + #size-cells = <0>;
924 + reg = <0x0>; /* GEM_ID */
925 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
926 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
927 + fsl,mdio-mux-val = <0x0>;
928 + phy-mode = "sgmii";
929 + fsl,pfe-phy-if-flags = <0x0>;
930 +
931 + mdio@0 {
932 + reg = <0x1>; /* enabled/disabled */
933 + };
934 + };
935 +
936 + ethernet@1 {
937 + compatible = "fsl,pfe-gemac-port";
938 + #address-cells = <1>;
939 + #size-cells = <0>;
940 + reg = <0x1>; /* GEM_ID */
941 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
942 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
943 + fsl,mdio-mux-val = <0x0>;
944 + phy-mode = "sgmii";
945 + fsl,pfe-phy-if-flags = <0x0>;
946 +
947 + mdio@0 {
948 + reg = <0x0>; /* enabled/disabled */
949 + };
950 + };
951 +};
952 +
953 +&sai2 {
954 + status = "okay";
955 +};
956 +
957 +&sata {
958 + status = "okay";
959 +};
960 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
961 new file mode 100644
962 index 00000000..edd87676
963 --- /dev/null
964 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
965 @@ -0,0 +1,198 @@
966 +/*
967 + * Device Tree file for Freescale LS1012A QDS Board.
968 + *
969 + * Copyright 2016 Freescale Semiconductor, Inc.
970 + *
971 + * This file is dual-licensed: you can use it either under the terms
972 + * of the GPLv2 or the X11 license, at your option. Note that this dual
973 + * licensing only applies to this file, and not this project as a
974 + * whole.
975 + *
976 + * a) This library is free software; you can redistribute it and/or
977 + * modify it under the terms of the GNU General Public License as
978 + * published by the Free Software Foundation; either version 2 of the
979 + * License, or (at your option) any later version.
980 + *
981 + * This library is distributed in the hope that it will be useful,
982 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
983 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
984 + * GNU General Public License for more details.
985 + *
986 + * Or, alternatively,
987 + *
988 + * b) Permission is hereby granted, free of charge, to any person
989 + * obtaining a copy of this software and associated documentation
990 + * files (the "Software"), to deal in the Software without
991 + * restriction, including without limitation the rights to use,
992 + * copy, modify, merge, publish, distribute, sublicense, and/or
993 + * sell copies of the Software, and to permit persons to whom the
994 + * Software is furnished to do so, subject to the following
995 + * conditions:
996 + *
997 + * The above copyright notice and this permission notice shall be
998 + * included in all copies or substantial portions of the Software.
999 + *
1000 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1001 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1002 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1003 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1004 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1005 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1006 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1007 + * OTHER DEALINGS IN THE SOFTWARE.
1008 + */
1009 +/dts-v1/;
1010 +
1011 +#include "fsl-ls1012a.dtsi"
1012 +
1013 +/ {
1014 + model = "LS1012A QDS Board";
1015 + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
1016 +
1017 + aliases {
1018 + ethernet0 = &pfe_mac0;
1019 + ethernet1 = &pfe_mac1;
1020 + };
1021 +
1022 + sys_mclk: clock-mclk {
1023 + compatible = "fixed-clock";
1024 + #clock-cells = <0>;
1025 + clock-frequency = <24576000>;
1026 + };
1027 +
1028 + reg_3p3v: regulator-3p3v {
1029 + compatible = "regulator-fixed";
1030 + regulator-name = "3P3V";
1031 + regulator-min-microvolt = <3300000>;
1032 + regulator-max-microvolt = <3300000>;
1033 + regulator-always-on;
1034 + };
1035 +
1036 + sound {
1037 + compatible = "simple-audio-card";
1038 + simple-audio-card,format = "i2s";
1039 + simple-audio-card,widgets =
1040 + "Microphone", "Microphone Jack",
1041 + "Headphone", "Headphone Jack",
1042 + "Speaker", "Speaker Ext",
1043 + "Line", "Line In Jack";
1044 + simple-audio-card,routing =
1045 + "MIC_IN", "Microphone Jack",
1046 + "Microphone Jack", "Mic Bias",
1047 + "LINE_IN", "Line In Jack",
1048 + "Headphone Jack", "HP_OUT",
1049 + "Speaker Ext", "LINE_OUT";
1050 +
1051 + simple-audio-card,cpu {
1052 + sound-dai = <&sai2>;
1053 + frame-master;
1054 + bitclock-master;
1055 + };
1056 +
1057 + simple-audio-card,codec {
1058 + sound-dai = <&codec>;
1059 + frame-master;
1060 + bitclock-master;
1061 + system-clock-frequency = <24576000>;
1062 + };
1063 + };
1064 +};
1065 +
1066 +&duart0 {
1067 + status = "okay";
1068 +};
1069 +
1070 +&i2c0 {
1071 + status = "okay";
1072 +
1073 + pca9547@77 {
1074 + compatible = "nxp,pca9547";
1075 + reg = <0x77>;
1076 + #address-cells = <1>;
1077 + #size-cells = <0>;
1078 +
1079 + i2c@4 {
1080 + #address-cells = <1>;
1081 + #size-cells = <0>;
1082 + reg = <0x4>;
1083 +
1084 + codec: sgtl5000@a {
1085 + #sound-dai-cells = <0>;
1086 + compatible = "fsl,sgtl5000";
1087 + reg = <0xa>;
1088 + VDDA-supply = <&reg_3p3v>;
1089 + VDDIO-supply = <&reg_3p3v>;
1090 + clocks = <&sys_mclk>;
1091 + };
1092 + };
1093 + };
1094 +};
1095 +
1096 +&qspi {
1097 + num-cs = <2>;
1098 + bus-num = <0>;
1099 + status = "okay";
1100 +
1101 + qflash0: s25fs512s@0 {
1102 + compatible = "spansion,m25p80";
1103 + #address-cells = <1>;
1104 + #size-cells = <1>;
1105 + spi-max-frequency = <20000000>;
1106 + m25p,fast-read;
1107 + reg = <0>;
1108 + };
1109 +};
1110 +
1111 +&pfe {
1112 + status = "okay";
1113 + #address-cells = <1>;
1114 + #size-cells = <0>;
1115 +
1116 + ethernet@0 {
1117 + compatible = "fsl,pfe-gemac-port";
1118 + #address-cells = <1>;
1119 + #size-cells = <0>;
1120 + reg = <0x0>; /* GEM_ID */
1121 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1122 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
1123 + fsl,mdio-mux-val = <0x2>;
1124 + phy-mode = "sgmii-2500";
1125 + fsl,pfe-phy-if-flags = <0x0>;
1126 +
1127 + mdio@0 {
1128 + reg = <0x1>; /* enabled/disabled */
1129 + };
1130 + };
1131 +
1132 + ethernet@1 {
1133 + compatible = "fsl,pfe-gemac-port";
1134 + #address-cells = <1>;
1135 + #size-cells = <0>;
1136 + reg = <0x1>; /* GEM_ID */
1137 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
1138 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1139 + fsl,mdio-mux-val = <0x3>;
1140 + phy-mode = "sgmii-2500";
1141 + fsl,pfe-phy-if-flags = <0x0>;
1142 +
1143 + mdio@0 {
1144 + reg = <0x0>; /* enabled/disabled */
1145 + };
1146 + };
1147 +};
1148 +
1149 +&sai2 {
1150 + status = "okay";
1151 +};
1152 +
1153 +&sata {
1154 + status = "okay";
1155 +};
1156 +
1157 +&esdhc0 {
1158 + status = "okay";
1159 +};
1160 +
1161 +&esdhc1 {
1162 + status = "okay";
1163 +};
1164 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1165 new file mode 100644
1166 index 00000000..88684eac
1167 --- /dev/null
1168 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1169 @@ -0,0 +1,134 @@
1170 +/*
1171 + * Device Tree file for Freescale LS1012A RDB Board.
1172 + *
1173 + * Copyright 2016 Freescale Semiconductor, Inc.
1174 + *
1175 + * This file is dual-licensed: you can use it either under the terms
1176 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1177 + * licensing only applies to this file, and not this project as a
1178 + * whole.
1179 + *
1180 + * a) This library is free software; you can redistribute it and/or
1181 + * modify it under the terms of the GNU General Public License as
1182 + * published by the Free Software Foundation; either version 2 of the
1183 + * License, or (at your option) any later version.
1184 + *
1185 + * This library is distributed in the hope that it will be useful,
1186 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1187 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1188 + * GNU General Public License for more details.
1189 + *
1190 + * Or, alternatively,
1191 + *
1192 + * b) Permission is hereby granted, free of charge, to any person
1193 + * obtaining a copy of this software and associated documentation
1194 + * files (the "Software"), to deal in the Software without
1195 + * restriction, including without limitation the rights to use,
1196 + * copy, modify, merge, publish, distribute, sublicense, and/or
1197 + * sell copies of the Software, and to permit persons to whom the
1198 + * Software is furnished to do so, subject to the following
1199 + * conditions:
1200 + *
1201 + * The above copyright notice and this permission notice shall be
1202 + * included in all copies or substantial portions of the Software.
1203 + *
1204 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1205 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1206 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1207 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1208 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1209 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1210 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1211 + * OTHER DEALINGS IN THE SOFTWARE.
1212 + */
1213 +/dts-v1/;
1214 +
1215 +#include "fsl-ls1012a.dtsi"
1216 +
1217 +/ {
1218 + model = "LS1012A RDB Board";
1219 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
1220 +
1221 + aliases {
1222 + ethernet0 = &pfe_mac0;
1223 + ethernet1 = &pfe_mac1;
1224 + };
1225 +};
1226 +
1227 +&duart0 {
1228 + status = "okay";
1229 +};
1230 +
1231 +&i2c0 {
1232 + status = "okay";
1233 +};
1234 +
1235 +&qspi {
1236 + num-cs = <2>;
1237 + bus-num = <0>;
1238 + status = "okay";
1239 +
1240 + qflash0: s25fs512s@0 {
1241 + compatible = "spansion,m25p80";
1242 + #address-cells = <1>;
1243 + #size-cells = <1>;
1244 + spi-max-frequency = <20000000>;
1245 + m25p,fast-read;
1246 + reg = <0>;
1247 + };
1248 +};
1249 +
1250 +&sata {
1251 + status = "okay";
1252 +};
1253 +
1254 +&esdhc0 {
1255 + sd-uhs-sdr104;
1256 + sd-uhs-sdr50;
1257 + sd-uhs-sdr25;
1258 + sd-uhs-sdr12;
1259 + status = "okay";
1260 +};
1261 +
1262 +&esdhc1 {
1263 + mmc-hs200-1_8v;
1264 + status = "okay";
1265 +};
1266 +
1267 +&pfe {
1268 + status = "okay";
1269 + #address-cells = <1>;
1270 + #size-cells = <0>;
1271 +
1272 + ethernet@0 {
1273 + compatible = "fsl,pfe-gemac-port";
1274 + #address-cells = <1>;
1275 + #size-cells = <0>;
1276 + reg = <0x0>; /* GEM_ID */
1277 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
1278 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
1279 + fsl,mdio-mux-val = <0x0>;
1280 + phy-mode = "sgmii";
1281 + fsl,pfe-phy-if-flags = <0x0>;
1282 +
1283 + mdio@0 {
1284 + reg = <0x1>; /* enabled/disabled */
1285 + };
1286 + };
1287 +
1288 + ethernet@1 {
1289 + compatible = "fsl,pfe-gemac-port";
1290 + #address-cells = <1>;
1291 + #size-cells = <0>;
1292 + reg = <0x1>; /* GEM_ID */
1293 + fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
1294 + fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
1295 + fsl,mdio-mux-val = <0x0>;
1296 + phy-mode = "rgmii-txid";
1297 + fsl,pfe-phy-if-flags = <0x0>;
1298 +
1299 + mdio@0 {
1300 + reg = <0x0>; /* enabled/disabled */
1301 + };
1302 + };
1303 +};
1304 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1305 new file mode 100644
1306 index 00000000..0b11ece1
1307 --- /dev/null
1308 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1309 @@ -0,0 +1,594 @@
1310 +/*
1311 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
1312 + *
1313 + * Copyright 2016 Freescale Semiconductor, Inc.
1314 + *
1315 + * This file is dual-licensed: you can use it either under the terms
1316 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1317 + * licensing only applies to this file, and not this project as a
1318 + * whole.
1319 + *
1320 + * a) This library is free software; you can redistribute it and/or
1321 + * modify it under the terms of the GNU General Public License as
1322 + * published by the Free Software Foundation; either version 2 of the
1323 + * License, or (at your option) any later version.
1324 + *
1325 + * This library is distributed in the hope that it will be useful,
1326 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1327 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1328 + * GNU General Public License for more details.
1329 + *
1330 + * Or, alternatively,
1331 + *
1332 + * b) Permission is hereby granted, free of charge, to any person
1333 + * obtaining a copy of this software and associated documentation
1334 + * files (the "Software"), to deal in the Software without
1335 + * restriction, including without limitation the rights to use,
1336 + * copy, modify, merge, publish, distribute, sublicense, and/or
1337 + * sell copies of the Software, and to permit persons to whom the
1338 + * Software is furnished to do so, subject to the following
1339 + * conditions:
1340 + *
1341 + * The above copyright notice and this permission notice shall be
1342 + * included in all copies or substantial portions of the Software.
1343 + *
1344 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1345 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1346 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1347 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1348 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1349 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1350 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1351 + * OTHER DEALINGS IN THE SOFTWARE.
1352 + */
1353 +
1354 +#include <dt-bindings/interrupt-controller/arm-gic.h>
1355 +#include <dt-bindings/thermal/thermal.h>
1356 +
1357 +/ {
1358 + compatible = "fsl,ls1012a";
1359 + interrupt-parent = <&gic>;
1360 + #address-cells = <2>;
1361 + #size-cells = <2>;
1362 +
1363 + aliases {
1364 + crypto = &crypto;
1365 + rtic_a = &rtic_a;
1366 + rtic_b = &rtic_b;
1367 + rtic_c = &rtic_c;
1368 + rtic_d = &rtic_d;
1369 + sec_mon = &sec_mon;
1370 + };
1371 +
1372 + cpus {
1373 + #address-cells = <1>;
1374 + #size-cells = <0>;
1375 +
1376 + cpu0: cpu@0 {
1377 + device_type = "cpu";
1378 + compatible = "arm,cortex-a53";
1379 + reg = <0x0>;
1380 + clocks = <&clockgen 1 0>;
1381 + #cooling-cells = <2>;
1382 + cpu-idle-states = <&CPU_PH20>;
1383 + };
1384 + };
1385 +
1386 + idle-states {
1387 + /*
1388 + * PSCI node is not added default, U-boot will add missing
1389 + * parts if it determines to use PSCI.
1390 + */
1391 + entry-method = "arm,psci";
1392 +
1393 + CPU_PH20: cpu-ph20 {
1394 + compatible = "arm,idle-state";
1395 + idle-state-name = "PH20";
1396 + arm,psci-suspend-param = <0x0>;
1397 + entry-latency-us = <1000>;
1398 + exit-latency-us = <1000>;
1399 + min-residency-us = <3000>;
1400 + };
1401 + };
1402 +
1403 + sysclk: sysclk {
1404 + compatible = "fixed-clock";
1405 + #clock-cells = <0>;
1406 + clock-frequency = <125000000>;
1407 + clock-output-names = "sysclk";
1408 + };
1409 +
1410 + coreclk: coreclk {
1411 + compatible = "fixed-clock";
1412 + #clock-cells = <0>;
1413 + clock-frequency = <100000000>;
1414 + clock-output-names = "coreclk";
1415 + };
1416 +
1417 + timer {
1418 + compatible = "arm,armv8-timer";
1419 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
1420 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
1421 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
1422 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
1423 + };
1424 +
1425 + pmu {
1426 + compatible = "arm,armv8-pmuv3";
1427 + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1428 + };
1429 +
1430 + gic: interrupt-controller@1400000 {
1431 + compatible = "arm,gic-400";
1432 + #interrupt-cells = <3>;
1433 + interrupt-controller;
1434 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
1435 + <0x0 0x1402000 0 0x2000>, /* GICC */
1436 + <0x0 0x1404000 0 0x2000>, /* GICH */
1437 + <0x0 0x1406000 0 0x2000>; /* GICV */
1438 + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
1439 + };
1440 +
1441 + reboot {
1442 + compatible = "syscon-reboot";
1443 + regmap = <&dcfg>;
1444 + offset = <0xb0>;
1445 + mask = <0x02>;
1446 + };
1447 +
1448 + soc {
1449 + compatible = "simple-bus";
1450 + #address-cells = <2>;
1451 + #size-cells = <2>;
1452 + ranges;
1453 +
1454 + scfg: scfg@1570000 {
1455 + compatible = "fsl,ls1012a-scfg", "syscon";
1456 + reg = <0x0 0x1570000 0x0 0x10000>;
1457 + big-endian;
1458 + };
1459 +
1460 + crypto: crypto@1700000 {
1461 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
1462 + "fsl,sec-v4.0";
1463 + fsl,sec-era = <8>;
1464 + #address-cells = <1>;
1465 + #size-cells = <1>;
1466 + ranges = <0x0 0x00 0x1700000 0x100000>;
1467 + reg = <0x00 0x1700000 0x0 0x100000>;
1468 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1469 +
1470 + sec_jr0: jr@10000 {
1471 + compatible = "fsl,sec-v5.4-job-ring",
1472 + "fsl,sec-v5.0-job-ring",
1473 + "fsl,sec-v4.0-job-ring";
1474 + reg = <0x10000 0x10000>;
1475 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1476 + };
1477 +
1478 + sec_jr1: jr@20000 {
1479 + compatible = "fsl,sec-v5.4-job-ring",
1480 + "fsl,sec-v5.0-job-ring",
1481 + "fsl,sec-v4.0-job-ring";
1482 + reg = <0x20000 0x10000>;
1483 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1484 + };
1485 +
1486 + sec_jr2: jr@30000 {
1487 + compatible = "fsl,sec-v5.4-job-ring",
1488 + "fsl,sec-v5.0-job-ring",
1489 + "fsl,sec-v4.0-job-ring";
1490 + reg = <0x30000 0x10000>;
1491 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1492 + };
1493 +
1494 + sec_jr3: jr@40000 {
1495 + compatible = "fsl,sec-v5.4-job-ring",
1496 + "fsl,sec-v5.0-job-ring",
1497 + "fsl,sec-v4.0-job-ring";
1498 + reg = <0x40000 0x10000>;
1499 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1500 + };
1501 +
1502 + caam-dma {
1503 + compatible = "fsl,sec-v5.4-dma",
1504 + "fsl,sec-v5.0-dma",
1505 + "fsl,sec-v4.0-dma";
1506 + };
1507 +
1508 + rtic@60000 {
1509 + compatible = "fsl,sec-v5.4-rtic",
1510 + "fsl,sec-v5.0-rtic",
1511 + "fsl,sec-v4.0-rtic";
1512 + #address-cells = <1>;
1513 + #size-cells = <1>;
1514 + reg = <0x60000 0x100 0x60e00 0x18>;
1515 + ranges = <0x0 0x60100 0x500>;
1516 +
1517 + rtic_a: rtic-a@0 {
1518 + compatible = "fsl,sec-v5.4-rtic-memory",
1519 + "fsl,sec-v5.0-rtic-memory",
1520 + "fsl,sec-v4.0-rtic-memory";
1521 + reg = <0x00 0x20 0x100 0x100>;
1522 + };
1523 +
1524 + rtic_b: rtic-b@20 {
1525 + compatible = "fsl,sec-v5.4-rtic-memory",
1526 + "fsl,sec-v5.0-rtic-memory",
1527 + "fsl,sec-v4.0-rtic-memory";
1528 + reg = <0x20 0x20 0x200 0x100>;
1529 + };
1530 +
1531 + rtic_c: rtic-c@40 {
1532 + compatible = "fsl,sec-v5.4-rtic-memory",
1533 + "fsl,sec-v5.0-rtic-memory",
1534 + "fsl,sec-v4.0-rtic-memory";
1535 + reg = <0x40 0x20 0x300 0x100>;
1536 + };
1537 +
1538 + rtic_d: rtic-d@60 {
1539 + compatible = "fsl,sec-v5.4-rtic-memory",
1540 + "fsl,sec-v5.0-rtic-memory",
1541 + "fsl,sec-v4.0-rtic-memory";
1542 + reg = <0x60 0x20 0x400 0x100>;
1543 + };
1544 + };
1545 + };
1546 +
1547 + sec_mon: sec_mon@1e90000 {
1548 + compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
1549 + "fsl,sec-v4.0-mon";
1550 + reg = <0x0 0x1e90000 0x0 0x10000>;
1551 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
1552 + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1553 + };
1554 +
1555 + dcfg: dcfg@1ee0000 {
1556 + compatible = "fsl,ls1012a-dcfg",
1557 + "syscon";
1558 + reg = <0x0 0x1ee0000 0x0 0x10000>;
1559 + big-endian;
1560 + };
1561 +
1562 + clockgen: clocking@1ee1000 {
1563 + compatible = "fsl,ls1012a-clockgen";
1564 + reg = <0x0 0x1ee1000 0x0 0x1000>;
1565 + #clock-cells = <2>;
1566 + clocks = <&sysclk &coreclk>;
1567 + clock-names = "sysclk", "coreclk";
1568 + };
1569 +
1570 + tmu: tmu@1f00000 {
1571 + compatible = "fsl,qoriq-tmu";
1572 + reg = <0x0 0x1f00000 0x0 0x10000>;
1573 + interrupts = <0 33 0x4>;
1574 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
1575 + fsl,tmu-calibration = <0x00000000 0x00000026
1576 + 0x00000001 0x0000002d
1577 + 0x00000002 0x00000032
1578 + 0x00000003 0x00000039
1579 + 0x00000004 0x0000003f
1580 + 0x00000005 0x00000046
1581 + 0x00000006 0x0000004d
1582 + 0x00000007 0x00000054
1583 + 0x00000008 0x0000005a
1584 + 0x00000009 0x00000061
1585 + 0x0000000a 0x0000006a
1586 + 0x0000000b 0x00000071
1587 +
1588 + 0x00010000 0x00000025
1589 + 0x00010001 0x0000002c
1590 + 0x00010002 0x00000035
1591 + 0x00010003 0x0000003d
1592 + 0x00010004 0x00000045
1593 + 0x00010005 0x0000004e
1594 + 0x00010006 0x00000057
1595 + 0x00010007 0x00000061
1596 + 0x00010008 0x0000006b
1597 + 0x00010009 0x00000076
1598 +
1599 + 0x00020000 0x00000029
1600 + 0x00020001 0x00000033
1601 + 0x00020002 0x0000003d
1602 + 0x00020003 0x00000049
1603 + 0x00020004 0x00000056
1604 + 0x00020005 0x00000061
1605 + 0x00020006 0x0000006d
1606 +
1607 + 0x00030000 0x00000021
1608 + 0x00030001 0x0000002a
1609 + 0x00030002 0x0000003c
1610 + 0x00030003 0x0000004e>;
1611 + big-endian;
1612 + #thermal-sensor-cells = <1>;
1613 + };
1614 +
1615 + thermal-zones {
1616 + cpu_thermal: cpu-thermal {
1617 + polling-delay-passive = <1000>;
1618 + polling-delay = <5000>;
1619 + thermal-sensors = <&tmu 0>;
1620 +
1621 + trips {
1622 + cpu_alert: cpu-alert {
1623 + temperature = <85000>;
1624 + hysteresis = <2000>;
1625 + type = "passive";
1626 + };
1627 +
1628 + cpu_crit: cpu-crit {
1629 + temperature = <95000>;
1630 + hysteresis = <2000>;
1631 + type = "critical";
1632 + };
1633 + };
1634 +
1635 + cooling-maps {
1636 + map0 {
1637 + trip = <&cpu_alert>;
1638 + cooling-device =
1639 + <&cpu0 THERMAL_NO_LIMIT
1640 + THERMAL_NO_LIMIT>;
1641 + };
1642 + };
1643 + };
1644 + };
1645 +
1646 + esdhc0: esdhc@1560000 {
1647 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1648 + reg = <0x0 0x1560000 0x0 0x10000>;
1649 + interrupts = <0 62 0x4>;
1650 + clocks = <&clockgen 4 0>;
1651 + voltage-ranges = <1800 1800 3300 3300>;
1652 + sdhci,auto-cmd12;
1653 + big-endian;
1654 + bus-width = <4>;
1655 + status = "disabled";
1656 + };
1657 +
1658 + esdhc1: esdhc@1580000 {
1659 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1660 + reg = <0x0 0x1580000 0x0 0x10000>;
1661 + interrupts = <0 65 0x4>;
1662 + clocks = <&clockgen 4 0>;
1663 + voltage-ranges = <1800 1800 3300 3300>;
1664 + sdhci,auto-cmd12;
1665 + big-endian;
1666 + broken-cd;
1667 + bus-width = <4>;
1668 + status = "disabled";
1669 + };
1670 +
1671 + rcpm: rcpm@1ee2000 {
1672 + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
1673 + reg = <0x0 0x1ee2000 0x0 0x1000>;
1674 + fsl,#rcpm-wakeup-cells = <1>;
1675 + };
1676 +
1677 + ftm0: ftm0@29d0000 {
1678 + compatible = "fsl,ls1012a-ftm";
1679 + reg = <0x0 0x29d0000 0x0 0x10000>,
1680 + <0x0 0x1ee2140 0x0 0x4>;
1681 + reg-names = "ftm", "FlexTimer1";
1682 + interrupts = <0 86 0x4>;
1683 + big-endian;
1684 + };
1685 +
1686 + i2c0: i2c@2180000 {
1687 + compatible = "fsl,vf610-i2c";
1688 + #address-cells = <1>;
1689 + #size-cells = <0>;
1690 + reg = <0x0 0x2180000 0x0 0x10000>;
1691 + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
1692 + clocks = <&clockgen 4 0>;
1693 + status = "disabled";
1694 + };
1695 +
1696 + i2c1: i2c@2190000 {
1697 + compatible = "fsl,vf610-i2c";
1698 + #address-cells = <1>;
1699 + #size-cells = <0>;
1700 + reg = <0x0 0x2190000 0x0 0x10000>;
1701 + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
1702 + clocks = <&clockgen 4 0>;
1703 + status = "disabled";
1704 + };
1705 +
1706 + duart0: serial@21c0500 {
1707 + compatible = "fsl,ns16550", "ns16550a";
1708 + reg = <0x00 0x21c0500 0x0 0x100>;
1709 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1710 + clocks = <&clockgen 4 0>;
1711 + status = "disabled";
1712 + };
1713 +
1714 + duart1: serial@21c0600 {
1715 + compatible = "fsl,ns16550", "ns16550a";
1716 + reg = <0x00 0x21c0600 0x0 0x100>;
1717 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1718 + clocks = <&clockgen 4 0>;
1719 + status = "disabled";
1720 + };
1721 +
1722 + gpio0: gpio@2300000 {
1723 + compatible = "fsl,qoriq-gpio";
1724 + reg = <0x0 0x2300000 0x0 0x10000>;
1725 + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
1726 + gpio-controller;
1727 + #gpio-cells = <2>;
1728 + interrupt-controller;
1729 + #interrupt-cells = <2>;
1730 + };
1731 +
1732 + gpio1: gpio@2310000 {
1733 + compatible = "fsl,qoriq-gpio";
1734 + reg = <0x0 0x2310000 0x0 0x10000>;
1735 + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
1736 + gpio-controller;
1737 + #gpio-cells = <2>;
1738 + interrupt-controller;
1739 + #interrupt-cells = <2>;
1740 + };
1741 +
1742 + qspi: quadspi@1550000 {
1743 + compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
1744 + #address-cells = <1>;
1745 + #size-cells = <0>;
1746 + reg = <0x0 0x1550000 0x0 0x10000>,
1747 + <0x0 0x40000000 0x0 0x10000000>;
1748 + reg-names = "QuadSPI", "QuadSPI-memory";
1749 + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1750 + clock-names = "qspi_en", "qspi";
1751 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
1752 + big-endian;
1753 + fsl,qspi-has-second-chip;
1754 + status = "disabled";
1755 + };
1756 +
1757 + wdog0: wdog@2ad0000 {
1758 + compatible = "fsl,ls1012a-wdt",
1759 + "fsl,imx21-wdt";
1760 + reg = <0x0 0x2ad0000 0x0 0x10000>;
1761 + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
1762 + clocks = <&clockgen 4 0>;
1763 + big-endian;
1764 + };
1765 +
1766 + sai1: sai@2b50000 {
1767 + #sound-dai-cells = <0>;
1768 + compatible = "fsl,vf610-sai";
1769 + reg = <0x0 0x2b50000 0x0 0x10000>;
1770 + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
1771 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1772 + <&clockgen 4 3>, <&clockgen 4 3>;
1773 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1774 + dma-names = "tx", "rx";
1775 + dmas = <&edma0 1 47>,
1776 + <&edma0 1 46>;
1777 + status = "disabled";
1778 + };
1779 +
1780 + sai2: sai@2b60000 {
1781 + #sound-dai-cells = <0>;
1782 + compatible = "fsl,vf610-sai";
1783 + reg = <0x0 0x2b60000 0x0 0x10000>;
1784 + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
1785 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1786 + <&clockgen 4 3>, <&clockgen 4 3>;
1787 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1788 + dma-names = "tx", "rx";
1789 + dmas = <&edma0 1 45>,
1790 + <&edma0 1 44>;
1791 + status = "disabled";
1792 + };
1793 +
1794 + edma0: edma@2c00000 {
1795 + #dma-cells = <2>;
1796 + compatible = "fsl,vf610-edma";
1797 + reg = <0x0 0x2c00000 0x0 0x10000>,
1798 + <0x0 0x2c10000 0x0 0x10000>,
1799 + <0x0 0x2c20000 0x0 0x10000>;
1800 + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
1801 + <0 103 IRQ_TYPE_LEVEL_HIGH>;
1802 + interrupt-names = "edma-tx", "edma-err";
1803 + dma-channels = <32>;
1804 + big-endian;
1805 + clock-names = "dmamux0", "dmamux1";
1806 + clocks = <&clockgen 4 3>,
1807 + <&clockgen 4 3>;
1808 + };
1809 +
1810 + usb0: usb3@2f00000 {
1811 + compatible = "snps,dwc3";
1812 + reg = <0x0 0x2f00000 0x0 0x10000>;
1813 + interrupts = <0 60 0x4>;
1814 + dr_mode = "host";
1815 + snps,quirk-frame-length-adjustment = <0x20>;
1816 + snps,dis_rxdet_inp3_quirk;
1817 + };
1818 +
1819 + usb1: usb2@8600000 {
1820 + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
1821 + reg = <0x0 0x8600000 0x0 0x1000>;
1822 + interrupts = <0 139 0x4>;
1823 + dr_mode = "host";
1824 + phy_type = "ulpi";
1825 + };
1826 +
1827 + sata: sata@3200000 {
1828 + compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
1829 + reg = <0x0 0x3200000 0x0 0x10000>,
1830 + <0x0 0x20140520 0x0 0x4>;
1831 + reg-names = "ahci", "sata-ecc";
1832 + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
1833 + clocks = <&clockgen 4 0>;
1834 + dma-coherent;
1835 + status = "disabled";
1836 + };
1837 +
1838 + msi: msi-controller1@1572000 {
1839 + compatible = "fsl,ls1012a-msi";
1840 + reg = <0x0 0x1572000 0x0 0x8>;
1841 + msi-controller;
1842 + interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
1843 + };
1844 +
1845 + pcie@3400000 {
1846 + compatible = "fsl,ls1012a-pcie", "snps,dw-pcie";
1847 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
1848 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
1849 + reg-names = "regs", "config";
1850 + interrupts = <0 118 0x4>, /* AER interrupt */
1851 + <0 117 0x4>; /* PME interrupt */
1852 + interrupt-names = "aer", "pme";
1853 + #address-cells = <3>;
1854 + #size-cells = <2>;
1855 + device_type = "pci";
1856 + num-lanes = <4>;
1857 + bus-range = <0x0 0xff>;
1858 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
1859 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1860 + msi-parent = <&msi>;
1861 + #interrupt-cells = <1>;
1862 + interrupt-map-mask = <0 0 0 7>;
1863 + interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
1864 + <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
1865 + <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
1866 + <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1867 + };
1868 + };
1869 +
1870 + reserved-memory {
1871 + #address-cells = <2>;
1872 + #size-cells = <2>;
1873 + ranges;
1874 +
1875 + pfe_reserved: packetbuffer@83400000 {
1876 + reg = <0 0x83400000 0 0xc00000>;
1877 + };
1878 + };
1879 +
1880 + pfe: pfe@04000000 {
1881 + compatible = "fsl,pfe";
1882 + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
1883 + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
1884 + reg-names = "pfe", "pfe-ddr";
1885 + fsl,pfe-num-interfaces = <0x2>;
1886 + interrupts = <0 172 0x4>, /* HIF interrupt */
1887 + <0 173 0x4>, /*HIF_NOCPY interrupt */
1888 + <0 174 0x4>; /* WoL interrupt */
1889 + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
1890 + memory-region = <&pfe_reserved>;
1891 + fsl,pfe-scfg = <&scfg 0>;
1892 + fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
1893 + clocks = <&clockgen 4 0>;
1894 + clock-names = "pfe";
1895 +
1896 + status = "okay";
1897 + pfe_mac0: ethernet@0 {
1898 + };
1899 +
1900 + pfe_mac1: ethernet@1 {
1901 + };
1902 + };
1903 +};
1904 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
1905 new file mode 100644
1906 index 00000000..169e1714
1907 --- /dev/null
1908 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
1909 @@ -0,0 +1,45 @@
1910 +/*
1911 + * QorIQ FMan v3 device tree nodes for ls1043
1912 + *
1913 + * Copyright 2015-2016 Freescale Semiconductor Inc.
1914 + *
1915 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
1916 + */
1917 +
1918 +&soc {
1919 +
1920 +/* include used FMan blocks */
1921 +#include "qoriq-fman3-0.dtsi"
1922 +#include "qoriq-fman3-0-1g-0.dtsi"
1923 +#include "qoriq-fman3-0-1g-1.dtsi"
1924 +#include "qoriq-fman3-0-1g-2.dtsi"
1925 +#include "qoriq-fman3-0-1g-3.dtsi"
1926 +#include "qoriq-fman3-0-1g-4.dtsi"
1927 +#include "qoriq-fman3-0-1g-5.dtsi"
1928 +#include "qoriq-fman3-0-10g-0.dtsi"
1929 +
1930 +};
1931 +
1932 +&fman0 {
1933 + /* these aliases provide the FMan ports mapping */
1934 + enet0: ethernet@e0000 {
1935 + };
1936 +
1937 + enet1: ethernet@e2000 {
1938 + };
1939 +
1940 + enet2: ethernet@e4000 {
1941 + };
1942 +
1943 + enet3: ethernet@e6000 {
1944 + };
1945 +
1946 + enet4: ethernet@e8000 {
1947 + };
1948 +
1949 + enet5: ethernet@ea000 {
1950 + };
1951 +
1952 + enet6: ethernet@f0000 {
1953 + };
1954 +};
1955 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
1956 new file mode 100644
1957 index 00000000..6c13b416
1958 --- /dev/null
1959 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
1960 @@ -0,0 +1,69 @@
1961 +/*
1962 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1963 + *
1964 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1965 + *
1966 + * Mingkai Hu <Mingkai.hu@freescale.com>
1967 + *
1968 + * This file is dual-licensed: you can use it either under the terms
1969 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1970 + * licensing only applies to this file, and not this project as a
1971 + * whole.
1972 + *
1973 + * a) This library is free software; you can redistribute it and/or
1974 + * modify it under the terms of the GNU General Public License as
1975 + * published by the Free Software Foundation; either version 2 of the
1976 + * License, or (at your option) any later version.
1977 + *
1978 + * This library is distributed in the hope that it will be useful,
1979 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1980 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1981 + * GNU General Public License for more details.
1982 + *
1983 + * Or, alternatively,
1984 + *
1985 + * b) Permission is hereby granted, free of charge, to any person
1986 + * obtaining a copy of this software and associated documentation
1987 + * files (the "Software"), to deal in the Software without
1988 + * restriction, including without limitation the rights to use,
1989 + * copy, modify, merge, publish, distribute, sublicense, and/or
1990 + * sell copies of the Software, and to permit persons to whom the
1991 + * Software is furnished to do so, subject to the following
1992 + * conditions:
1993 + *
1994 + * The above copyright notice and this permission notice shall be
1995 + * included in all copies or substantial portions of the Software.
1996 + *
1997 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1998 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1999 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2000 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2001 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2002 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2003 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2004 + * OTHER DEALINGS IN THE SOFTWARE.
2005 + */
2006 +
2007 +#include "fsl-ls1043a-qds.dts"
2008 +
2009 +&bman_fbpr {
2010 + compatible = "fsl,bman-fbpr";
2011 + alloc-ranges = <0 0 0x10000 0>;
2012 +};
2013 +&qman_fqd {
2014 + compatible = "fsl,qman-fqd";
2015 + alloc-ranges = <0 0 0x10000 0>;
2016 +};
2017 +&qman_pfdr {
2018 + compatible = "fsl,qman-pfdr";
2019 + alloc-ranges = <0 0 0x10000 0>;
2020 +};
2021 +
2022 +&soc {
2023 +#include "qoriq-dpaa-eth.dtsi"
2024 +#include "qoriq-fman3-0-6oh.dtsi"
2025 +};
2026 +
2027 +&fman0 {
2028 + compatible = "fsl,fman", "simple-bus";
2029 +};
2030 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2031 index dd9e9194..08abff73 100644
2032 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2033 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
2034 @@ -1,7 +1,7 @@
2035 /*
2036 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2037 *
2038 - * Copyright 2014-2015, Freescale Semiconductor
2039 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2040 *
2041 * Mingkai Hu <Mingkai.hu@freescale.com>
2042 *
2043 @@ -45,7 +45,7 @@
2044 */
2045
2046 /dts-v1/;
2047 -/include/ "fsl-ls1043a.dtsi"
2048 +#include "fsl-ls1043a.dtsi"
2049
2050 / {
2051 model = "LS1043A QDS Board";
2052 @@ -60,6 +60,22 @@
2053 serial1 = &duart1;
2054 serial2 = &duart2;
2055 serial3 = &duart3;
2056 + sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
2057 + sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
2058 + sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
2059 + sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
2060 + qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
2061 + qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
2062 + qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
2063 + qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
2064 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
2065 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
2066 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
2067 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
2068 + emi1_slot1 = &ls1043mdio_s1;
2069 + emi1_slot2 = &ls1043mdio_s2;
2070 + emi1_slot3 = &ls1043mdio_s3;
2071 + emi1_slot4 = &ls1043mdio_s4;
2072 };
2073
2074 chosen {
2075 @@ -97,8 +113,11 @@
2076 };
2077
2078 fpga: board-control@2,0 {
2079 - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
2080 + #address-cells = <1>;
2081 + #size-cells = <1>;
2082 + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
2083 reg = <0x2 0x0 0x0000100>;
2084 + ranges = <0 2 0 0x100>;
2085 };
2086 };
2087
2088 @@ -181,3 +200,149 @@
2089 reg = <0>;
2090 };
2091 };
2092 +
2093 +#include "fsl-ls1043-post.dtsi"
2094 +
2095 +&fman0 {
2096 + ethernet@e0000 {
2097 + phy-handle = <&qsgmii_phy_s2_p1>;
2098 + phy-connection-type = "sgmii";
2099 + };
2100 +
2101 + ethernet@e2000 {
2102 + phy-handle = <&qsgmii_phy_s2_p2>;
2103 + phy-connection-type = "sgmii";
2104 + };
2105 +
2106 + ethernet@e4000 {
2107 + phy-handle = <&rgmii_phy1>;
2108 + phy-connection-type = "rgmii";
2109 + };
2110 +
2111 + ethernet@e6000 {
2112 + phy-handle = <&rgmii_phy2>;
2113 + phy-connection-type = "rgmii";
2114 + };
2115 +
2116 + ethernet@e8000 {
2117 + phy-handle = <&qsgmii_phy_s2_p3>;
2118 + phy-connection-type = "sgmii";
2119 + };
2120 +
2121 + ethernet@ea000 {
2122 + phy-handle = <&qsgmii_phy_s2_p4>;
2123 + phy-connection-type = "sgmii";
2124 + };
2125 +
2126 + ethernet@f0000 { /* DTSEC9/10GEC1 */
2127 + fixed-link = <1 1 10000 0 0>;
2128 + phy-connection-type = "xgmii";
2129 + };
2130 +};
2131 +
2132 +&fpga {
2133 + mdio-mux-emi1 {
2134 + compatible = "mdio-mux-mmioreg", "mdio-mux";
2135 + mdio-parent-bus = <&mdio0>;
2136 + #address-cells = <1>;
2137 + #size-cells = <0>;
2138 + reg = <0x54 1>; /* BRDCFG4 */
2139 + mux-mask = <0xe0>; /* EMI1 */
2140 +
2141 + /* On-board RGMII1 PHY */
2142 + ls1043mdio0: mdio@0 {
2143 + reg = <0>;
2144 + #address-cells = <1>;
2145 + #size-cells = <0>;
2146 +
2147 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
2148 + reg = <0x1>;
2149 + };
2150 + };
2151 +
2152 + /* On-board RGMII2 PHY */
2153 + ls1043mdio1: mdio@1 {
2154 + reg = <0x20>;
2155 + #address-cells = <1>;
2156 + #size-cells = <0>;
2157 +
2158 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
2159 + reg = <0x2>;
2160 + };
2161 + };
2162 +
2163 + /* Slot 1 */
2164 + ls1043mdio_s1: mdio@2 {
2165 + reg = <0x40>;
2166 + #address-cells = <1>;
2167 + #size-cells = <0>;
2168 + status = "disabled";
2169 +
2170 + qsgmii_phy_s1_p1: ethernet-phy@4 {
2171 + reg = <0x4>;
2172 + };
2173 + qsgmii_phy_s1_p2: ethernet-phy@5 {
2174 + reg = <0x5>;
2175 + };
2176 + qsgmii_phy_s1_p3: ethernet-phy@6 {
2177 + reg = <0x6>;
2178 + };
2179 + qsgmii_phy_s1_p4: ethernet-phy@7 {
2180 + reg = <0x7>;
2181 + };
2182 +
2183 + sgmii_phy_s1_p1: ethernet-phy@1c {
2184 + reg = <0x1c>;
2185 + };
2186 + };
2187 +
2188 + /* Slot 2 */
2189 + ls1043mdio_s2: mdio@3 {
2190 + reg = <0x60>;
2191 + #address-cells = <1>;
2192 + #size-cells = <0>;
2193 + status = "disabled";
2194 +
2195 + qsgmii_phy_s2_p1: ethernet-phy@8 {
2196 + reg = <0x8>;
2197 + };
2198 + qsgmii_phy_s2_p2: ethernet-phy@9 {
2199 + reg = <0x9>;
2200 + };
2201 + qsgmii_phy_s2_p3: ethernet-phy@a {
2202 + reg = <0xa>;
2203 + };
2204 + qsgmii_phy_s2_p4: ethernet-phy@b {
2205 + reg = <0xb>;
2206 + };
2207 +
2208 + sgmii_phy_s2_p1: ethernet-phy@1c {
2209 + reg = <0x1c>;
2210 + };
2211 + };
2212 +
2213 + /* Slot 3 */
2214 + ls1043mdio_s3: mdio@4 {
2215 + reg = <0x80>;
2216 + #address-cells = <1>;
2217 + #size-cells = <0>;
2218 + status = "disabled";
2219 +
2220 + sgmii_phy_s3_p1: ethernet-phy@1c {
2221 + reg = <0x1c>;
2222 + };
2223 + };
2224 +
2225 + /* Slot 4 */
2226 + ls1043mdio_s4: mdio@5 {
2227 + reg = <0xa0>;
2228 + #address-cells = <1>;
2229 + #size-cells = <0>;
2230 + status = "disabled";
2231 +
2232 + sgmii_phy_s4_p1: ethernet-phy@1c {
2233 + reg = <0x1c>;
2234 + };
2235 + };
2236 + };
2237 +};
2238 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2239 new file mode 100644
2240 index 00000000..ac4b9a41
2241 --- /dev/null
2242 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2243 @@ -0,0 +1,69 @@
2244 +/*
2245 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2246 + *
2247 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2248 + *
2249 + * Mingkai Hu <Mingkai.hu@freescale.com>
2250 + *
2251 + * This file is dual-licensed: you can use it either under the terms
2252 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2253 + * licensing only applies to this file, and not this project as a
2254 + * whole.
2255 + *
2256 + * a) This library is free software; you can redistribute it and/or
2257 + * modify it under the terms of the GNU General Public License as
2258 + * published by the Free Software Foundation; either version 2 of the
2259 + * License, or (at your option) any later version.
2260 + *
2261 + * This library is distributed in the hope that it will be useful,
2262 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2263 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2264 + * GNU General Public License for more details.
2265 + *
2266 + * Or, alternatively,
2267 + *
2268 + * b) Permission is hereby granted, free of charge, to any person
2269 + * obtaining a copy of this software and associated documentation
2270 + * files (the "Software"), to deal in the Software without
2271 + * restriction, including without limitation the rights to use,
2272 + * copy, modify, merge, publish, distribute, sublicense, and/or
2273 + * sell copies of the Software, and to permit persons to whom the
2274 + * Software is furnished to do so, subject to the following
2275 + * conditions:
2276 + *
2277 + * The above copyright notice and this permission notice shall be
2278 + * included in all copies or substantial portions of the Software.
2279 + *
2280 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2281 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2282 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2283 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2284 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2285 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2286 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2287 + * OTHER DEALINGS IN THE SOFTWARE.
2288 + */
2289 +
2290 +#include "fsl-ls1043a-rdb.dts"
2291 +
2292 +&bman_fbpr {
2293 + compatible = "fsl,bman-fbpr";
2294 + alloc-ranges = <0 0 0x10000 0>;
2295 +};
2296 +&qman_fqd {
2297 + compatible = "fsl,qman-fqd";
2298 + alloc-ranges = <0 0 0x10000 0>;
2299 +};
2300 +&qman_pfdr {
2301 + compatible = "fsl,qman-pfdr";
2302 + alloc-ranges = <0 0 0x10000 0>;
2303 +};
2304 +
2305 +&soc {
2306 +#include "qoriq-dpaa-eth.dtsi"
2307 +#include "qoriq-fman3-0-6oh.dtsi"
2308 +};
2309 +
2310 +&fman0 {
2311 + compatible = "fsl,fman", "simple-bus";
2312 +};
2313 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2314 new file mode 100644
2315 index 00000000..4e46a0a5
2316 --- /dev/null
2317 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2318 @@ -0,0 +1,117 @@
2319 +/*
2320 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2321 + *
2322 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2323 + *
2324 + * This file is licensed under the terms of the GNU General Public
2325 + * License version 2. This program is licensed "as is" without any
2326 + * warranty of any kind, whether express or implied.
2327 + */
2328 +
2329 +#include "fsl-ls1043a-rdb-sdk.dts"
2330 +
2331 +&soc {
2332 + bp7: buffer-pool@7 {
2333 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2334 + fsl,bpid = <7>;
2335 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
2336 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
2337 + };
2338 +
2339 + bp8: buffer-pool@8 {
2340 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2341 + fsl,bpid = <8>;
2342 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
2343 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2344 + };
2345 +
2346 + bp9: buffer-pool@9 {
2347 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2348 + fsl,bpid = <9>;
2349 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
2350 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2351 + };
2352 +
2353 + fsl,dpaa {
2354 + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
2355 +
2356 + ethernet@0 {
2357 + compatible = "fsl,dpa-ethernet-init";
2358 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2359 + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
2360 + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
2361 + };
2362 +
2363 + ethernet@1 {
2364 + compatible = "fsl,dpa-ethernet-init";
2365 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2366 + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
2367 + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
2368 + };
2369 +
2370 + ethernet@2 {
2371 + compatible = "fsl,dpa-ethernet-init";
2372 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2373 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
2374 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
2375 + };
2376 +
2377 + ethernet@3 {
2378 + compatible = "fsl,dpa-ethernet-init";
2379 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2380 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
2381 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
2382 + };
2383 +
2384 + ethernet@4 {
2385 + compatible = "fsl,dpa-ethernet-init";
2386 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2387 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
2388 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
2389 + };
2390 +
2391 + ethernet@5 {
2392 + compatible = "fsl,dpa-ethernet-init";
2393 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2394 + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
2395 + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
2396 + };
2397 +
2398 + ethernet@8 {
2399 + compatible = "fsl,dpa-ethernet-init";
2400 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2401 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
2402 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
2403 +
2404 + };
2405 + dpa-fman0-oh@2 {
2406 + compatible = "fsl,dpa-oh";
2407 + /* Define frame queues for the OH port*/
2408 + /* <OH Rx error, OH Rx default> */
2409 + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
2410 + fsl,fman-oh-port = <&fman0_oh2>;
2411 + };
2412 + };
2413 +};
2414 +/ {
2415 + reserved-memory {
2416 + #address-cells = <2>;
2417 + #size-cells = <2>;
2418 + ranges;
2419 +
2420 + usdpaa_mem: usdpaa_mem {
2421 + compatible = "fsl,usdpaa-mem";
2422 + alloc-ranges = <0 0 0x10000 0>;
2423 + size = <0 0x10000000>;
2424 + alignment = <0 0x10000000>;
2425 + };
2426 + };
2427 +};
2428 +
2429 +&fman0 {
2430 + fman0_oh2: port@83000 {
2431 + cell-index = <1>;
2432 + compatible = "fsl,fman-port-oh";
2433 + reg = <0x83000 0x1000>;
2434 + };
2435 +};
2436 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2437 index d2313e05..f92ae325 100644
2438 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2439 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2440 @@ -1,7 +1,7 @@
2441 /*
2442 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2443 *
2444 - * Copyright 2014-2015, Freescale Semiconductor
2445 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2446 *
2447 * Mingkai Hu <Mingkai.hu@freescale.com>
2448 *
2449 @@ -45,7 +45,7 @@
2450 */
2451
2452 /dts-v1/;
2453 -/include/ "fsl-ls1043a.dtsi"
2454 +#include "fsl-ls1043a.dtsi"
2455
2456 / {
2457 model = "LS1043A RDB Board";
2458 @@ -86,6 +86,10 @@
2459 compatible = "pericom,pt7c4338";
2460 reg = <0x68>;
2461 };
2462 + rtc@51 {
2463 + compatible = "nxp,pcf85263";
2464 + reg = <0x51>;
2465 + };
2466 };
2467
2468 &ifc {
2469 @@ -130,6 +134,38 @@
2470 reg = <0>;
2471 spi-max-frequency = <1000000>; /* input clock */
2472 };
2473 +
2474 + slic@2 {
2475 + compatible = "maxim,ds26522";
2476 + reg = <2>;
2477 + spi-max-frequency = <2000000>;
2478 + fsl,spi-cs-sck-delay = <100>;
2479 + fsl,spi-sck-cs-delay = <50>;
2480 + };
2481 +
2482 + slic@3 {
2483 + compatible = "maxim,ds26522";
2484 + reg = <3>;
2485 + spi-max-frequency = <2000000>;
2486 + fsl,spi-cs-sck-delay = <100>;
2487 + fsl,spi-sck-cs-delay = <50>;
2488 + };
2489 +};
2490 +
2491 +&uqe {
2492 + ucc_hdlc: ucc@2000 {
2493 + compatible = "fsl,ucc-hdlc";
2494 + rx-clock-name = "clk8";
2495 + tx-clock-name = "clk9";
2496 + fsl,rx-sync-clock = "rsync_pin";
2497 + fsl,tx-sync-clock = "tsync_pin";
2498 + fsl,tx-timeslot-mask = <0xfffffffe>;
2499 + fsl,rx-timeslot-mask = <0xfffffffe>;
2500 + fsl,tdm-framer-type = "e1";
2501 + fsl,tdm-id = <0>;
2502 + fsl,siram-entry-id = <0>;
2503 + fsl,tdm-interface;
2504 + };
2505 };
2506
2507 &duart0 {
2508 @@ -139,3 +175,76 @@
2509 &duart1 {
2510 status = "okay";
2511 };
2512 +
2513 +#include "fsl-ls1043-post.dtsi"
2514 +
2515 +&fman0 {
2516 + ethernet@e0000 {
2517 + phy-handle = <&qsgmii_phy1>;
2518 + phy-connection-type = "qsgmii";
2519 + };
2520 +
2521 + ethernet@e2000 {
2522 + phy-handle = <&qsgmii_phy2>;
2523 + phy-connection-type = "qsgmii";
2524 + };
2525 +
2526 + ethernet@e4000 {
2527 + phy-handle = <&rgmii_phy1>;
2528 + phy-connection-type = "rgmii-txid";
2529 + };
2530 +
2531 + ethernet@e6000 {
2532 + phy-handle = <&rgmii_phy2>;
2533 + phy-connection-type = "rgmii-txid";
2534 + };
2535 +
2536 + ethernet@e8000 {
2537 + phy-handle = <&qsgmii_phy3>;
2538 + phy-connection-type = "qsgmii";
2539 + };
2540 +
2541 + ethernet@ea000 {
2542 + phy-handle = <&qsgmii_phy4>;
2543 + phy-connection-type = "qsgmii";
2544 + };
2545 +
2546 + ethernet@f0000 { /* 10GEC1 */
2547 + phy-handle = <&aqr105_phy>;
2548 + phy-connection-type = "xgmii";
2549 + };
2550 +
2551 + mdio@fc000 {
2552 + rgmii_phy1: ethernet-phy@1 {
2553 + reg = <0x1>;
2554 + };
2555 +
2556 + rgmii_phy2: ethernet-phy@2 {
2557 + reg = <0x2>;
2558 + };
2559 +
2560 + qsgmii_phy1: ethernet-phy@4 {
2561 + reg = <0x4>;
2562 + };
2563 +
2564 + qsgmii_phy2: ethernet-phy@5 {
2565 + reg = <0x5>;
2566 + };
2567 +
2568 + qsgmii_phy3: ethernet-phy@6 {
2569 + reg = <0x6>;
2570 + };
2571 +
2572 + qsgmii_phy4: ethernet-phy@7 {
2573 + reg = <0x7>;
2574 + };
2575 + };
2576 +
2577 + mdio@fd000 {
2578 + aqr105_phy: ethernet-phy@1 {
2579 + compatible = "ethernet-phy-ieee802.3-c45";
2580 + interrupts = <0 132 4>;
2581 + reg = <0x1>;
2582 + };
2583 + };
2584 +};
2585 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2586 index 97d331ec..ef7c0a24 100644
2587 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2588 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2589 @@ -1,7 +1,7 @@
2590 /*
2591 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2592 *
2593 - * Copyright 2014-2015, Freescale Semiconductor
2594 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2595 *
2596 * Mingkai Hu <Mingkai.hu@freescale.com>
2597 *
2598 @@ -44,12 +44,25 @@
2599 * OTHER DEALINGS IN THE SOFTWARE.
2600 */
2601
2602 +#include <dt-bindings/thermal/thermal.h>
2603 +
2604 / {
2605 compatible = "fsl,ls1043a";
2606 interrupt-parent = <&gic>;
2607 #address-cells = <2>;
2608 #size-cells = <2>;
2609
2610 + aliases {
2611 + fman0 = &fman0;
2612 + ethernet0 = &enet0;
2613 + ethernet1 = &enet1;
2614 + ethernet2 = &enet2;
2615 + ethernet3 = &enet3;
2616 + ethernet4 = &enet4;
2617 + ethernet5 = &enet5;
2618 + ethernet6 = &enet6;
2619 + };
2620 +
2621 cpus {
2622 #address-cells = <1>;
2623 #size-cells = <0>;
2624 @@ -66,6 +79,8 @@
2625 reg = <0x0>;
2626 clocks = <&clockgen 1 0>;
2627 next-level-cache = <&l2>;
2628 + #cooling-cells = <2>;
2629 + cpu-idle-states = <&CPU_PH20>;
2630 };
2631
2632 cpu1: cpu@1 {
2633 @@ -74,6 +89,7 @@
2634 reg = <0x1>;
2635 clocks = <&clockgen 1 0>;
2636 next-level-cache = <&l2>;
2637 + cpu-idle-states = <&CPU_PH20>;
2638 };
2639
2640 cpu2: cpu@2 {
2641 @@ -82,6 +98,7 @@
2642 reg = <0x2>;
2643 clocks = <&clockgen 1 0>;
2644 next-level-cache = <&l2>;
2645 + cpu-idle-states = <&CPU_PH20>;
2646 };
2647
2648 cpu3: cpu@3 {
2649 @@ -90,6 +107,7 @@
2650 reg = <0x3>;
2651 clocks = <&clockgen 1 0>;
2652 next-level-cache = <&l2>;
2653 + cpu-idle-states = <&CPU_PH20>;
2654 };
2655
2656 l2: l2-cache {
2657 @@ -97,12 +115,56 @@
2658 };
2659 };
2660
2661 + idle-states {
2662 + /*
2663 + * PSCI node is not added default, U-boot will add missing
2664 + * parts if it determines to use PSCI.
2665 + */
2666 + entry-method = "arm,psci";
2667 +
2668 + CPU_PH20: cpu-ph20 {
2669 + compatible = "arm,idle-state";
2670 + idle-state-name = "PH20";
2671 + arm,psci-suspend-param = <0x0>;
2672 + entry-latency-us = <1000>;
2673 + exit-latency-us = <1000>;
2674 + min-residency-us = <3000>;
2675 + };
2676 + };
2677 +
2678 memory@80000000 {
2679 device_type = "memory";
2680 reg = <0x0 0x80000000 0 0x80000000>;
2681 /* DRAM space 1, size: 2GiB DRAM */
2682 };
2683
2684 + reserved-memory {
2685 + #address-cells = <2>;
2686 + #size-cells = <2>;
2687 + ranges;
2688 +
2689 + bman_fbpr: bman-fbpr {
2690 + compatible = "shared-dma-pool";
2691 + size = <0 0x1000000>;
2692 + alignment = <0 0x1000000>;
2693 + no-map;
2694 + };
2695 +
2696 + qman_fqd: qman-fqd {
2697 + compatible = "shared-dma-pool";
2698 + size = <0 0x400000>;
2699 + alignment = <0 0x400000>;
2700 + no-map;
2701 + };
2702 +
2703 + qman_pfdr: qman-pfdr {
2704 + compatible = "shared-dma-pool";
2705 + size = <0 0x2000000>;
2706 + alignment = <0 0x2000000>;
2707 + no-map;
2708 + };
2709 + };
2710 +
2711 sysclk: sysclk {
2712 compatible = "fixed-clock";
2713 #clock-cells = <0>;
2714 @@ -149,7 +211,7 @@
2715 interrupts = <1 9 0xf08>;
2716 };
2717
2718 - soc {
2719 + soc: soc {
2720 compatible = "simple-bus";
2721 #address-cells = <2>;
2722 #size-cells = <2>;
2723 @@ -213,13 +275,14 @@
2724
2725 dcfg: dcfg@1ee0000 {
2726 compatible = "fsl,ls1043a-dcfg", "syscon";
2727 - reg = <0x0 0x1ee0000 0x0 0x10000>;
2728 + reg = <0x0 0x1ee0000 0x0 0x1000>;
2729 big-endian;
2730 };
2731
2732 ifc: ifc@1530000 {
2733 compatible = "fsl,ifc", "simple-bus";
2734 reg = <0x0 0x1530000 0x0 0x10000>;
2735 + big-endian;
2736 interrupts = <0 43 0x4>;
2737 };
2738
2739 @@ -255,6 +318,103 @@
2740 big-endian;
2741 };
2742
2743 + tmu: tmu@1f00000 {
2744 + compatible = "fsl,qoriq-tmu";
2745 + reg = <0x0 0x1f00000 0x0 0x10000>;
2746 + interrupts = <0 33 0x4>;
2747 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
2748 + fsl,tmu-calibration = <0x00000000 0x00000026
2749 + 0x00000001 0x0000002d
2750 + 0x00000002 0x00000032
2751 + 0x00000003 0x00000039
2752 + 0x00000004 0x0000003f
2753 + 0x00000005 0x00000046
2754 + 0x00000006 0x0000004d
2755 + 0x00000007 0x00000054
2756 + 0x00000008 0x0000005a
2757 + 0x00000009 0x00000061
2758 + 0x0000000a 0x0000006a
2759 + 0x0000000b 0x00000071
2760 +
2761 + 0x00010000 0x00000025
2762 + 0x00010001 0x0000002c
2763 + 0x00010002 0x00000035
2764 + 0x00010003 0x0000003d
2765 + 0x00010004 0x00000045
2766 + 0x00010005 0x0000004e
2767 + 0x00010006 0x00000057
2768 + 0x00010007 0x00000061
2769 + 0x00010008 0x0000006b
2770 + 0x00010009 0x00000076
2771 +
2772 + 0x00020000 0x00000029
2773 + 0x00020001 0x00000033
2774 + 0x00020002 0x0000003d
2775 + 0x00020003 0x00000049
2776 + 0x00020004 0x00000056
2777 + 0x00020005 0x00000061
2778 + 0x00020006 0x0000006d
2779 +
2780 + 0x00030000 0x00000021
2781 + 0x00030001 0x0000002a
2782 + 0x00030002 0x0000003c
2783 + 0x00030003 0x0000004e>;
2784 + #thermal-sensor-cells = <1>;
2785 + };
2786 +
2787 + thermal-zones {
2788 + cpu_thermal: cpu-thermal {
2789 + polling-delay-passive = <1000>;
2790 + polling-delay = <5000>;
2791 +
2792 + thermal-sensors = <&tmu 3>;
2793 +
2794 + trips {
2795 + cpu_alert: cpu-alert {
2796 + temperature = <85000>;
2797 + hysteresis = <2000>;
2798 + type = "passive";
2799 + };
2800 + cpu_crit: cpu-crit {
2801 + temperature = <95000>;
2802 + hysteresis = <2000>;
2803 + type = "critical";
2804 + };
2805 + };
2806 +
2807 + cooling-maps {
2808 + map0 {
2809 + trip = <&cpu_alert>;
2810 + cooling-device =
2811 + <&cpu0 THERMAL_NO_LIMIT
2812 + THERMAL_NO_LIMIT>;
2813 + };
2814 + };
2815 + };
2816 + };
2817 +
2818 + qman: qman@1880000 {
2819 + compatible = "fsl,qman";
2820 + reg = <0x00 0x1880000 0x0 0x10000>;
2821 + interrupts = <0 45 0x4>;
2822 + memory-region = <&qman_fqd &qman_pfdr>;
2823 + };
2824 +
2825 + bman: bman@1890000 {
2826 + compatible = "fsl,bman";
2827 + reg = <0x00 0x1890000 0x0 0x10000>;
2828 + interrupts = <0 45 0x4>;
2829 + memory-region = <&bman_fbpr>;
2830 + };
2831 +
2832 + bportals: bman-portals@508000000 {
2833 + ranges = <0x0 0x5 0x08000000 0x8000000>;
2834 + };
2835 +
2836 + qportals: qman-portals@500000000 {
2837 + ranges = <0x0 0x5 0x00000000 0x8000000>;
2838 + };
2839 +
2840 dspi0: dspi@2100000 {
2841 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
2842 #address-cells = <1>;
2843 @@ -396,6 +556,72 @@
2844 #interrupt-cells = <2>;
2845 };
2846
2847 + uqe: uqe@2400000 {
2848 + #address-cells = <1>;
2849 + #size-cells = <1>;
2850 + device_type = "qe";
2851 + compatible = "fsl,qe", "simple-bus";
2852 + ranges = <0x0 0x0 0x2400000 0x40000>;
2853 + reg = <0x0 0x2400000 0x0 0x480>;
2854 + brg-frequency = <100000000>;
2855 + bus-frequency = <200000000>;
2856 +
2857 + fsl,qe-num-riscs = <1>;
2858 + fsl,qe-num-snums = <28>;
2859 +
2860 + qeic: qeic@80 {
2861 + compatible = "fsl,qe-ic";
2862 + reg = <0x80 0x80>;
2863 + #address-cells = <0>;
2864 + interrupt-controller;
2865 + #interrupt-cells = <1>;
2866 + interrupts = <0 77 0x04 0 77 0x04>;
2867 + };
2868 +
2869 + si1: si@700 {
2870 + #address-cells = <1>;
2871 + #size-cells = <0>;
2872 + compatible = "fsl,ls1043-qe-si",
2873 + "fsl,t1040-qe-si";
2874 + reg = <0x700 0x80>;
2875 + };
2876 +
2877 + siram1: siram@1000 {
2878 + #address-cells = <1>;
2879 + #size-cells = <1>;
2880 + compatible = "fsl,ls1043-qe-siram",
2881 + "fsl,t1040-qe-siram";
2882 + reg = <0x1000 0x800>;
2883 + };
2884 +
2885 + ucc@2000 {
2886 + cell-index = <1>;
2887 + reg = <0x2000 0x200>;
2888 + interrupts = <32>;
2889 + interrupt-parent = <&qeic>;
2890 + };
2891 +
2892 + ucc@2200 {
2893 + cell-index = <3>;
2894 + reg = <0x2200 0x200>;
2895 + interrupts = <34>;
2896 + interrupt-parent = <&qeic>;
2897 + };
2898 +
2899 + muram@10000 {
2900 + #address-cells = <1>;
2901 + #size-cells = <1>;
2902 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
2903 + ranges = <0x0 0x10000 0x6000>;
2904 +
2905 + data-only@0 {
2906 + compatible = "fsl,qe-muram-data",
2907 + "fsl,cpm-muram-data";
2908 + reg = <0x0 0x6000>;
2909 + };
2910 + };
2911 + };
2912 +
2913 lpuart0: serial@2950000 {
2914 compatible = "fsl,ls1021a-lpuart";
2915 reg = <0x0 0x2950000 0x0 0x1000>;
2916 @@ -450,6 +676,16 @@
2917 status = "disabled";
2918 };
2919
2920 + ftm0: ftm0@29d0000 {
2921 + compatible = "fsl,ls1043a-ftm";
2922 + reg = <0x0 0x29d0000 0x0 0x10000>,
2923 + <0x0 0x1ee2140 0x0 0x4>;
2924 + reg-names = "ftm", "FlexTimer1";
2925 + interrupts = <0 86 0x4>;
2926 + big-endian;
2927 + status = "okay";
2928 + };
2929 +
2930 wdog0: wdog@2ad0000 {
2931 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
2932 reg = <0x0 0x2ad0000 0x0 0x10000>;
2933 @@ -482,6 +718,8 @@
2934 dr_mode = "host";
2935 snps,quirk-frame-length-adjustment = <0x20>;
2936 snps,dis_rxdet_inp3_quirk;
2937 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2938 + snps,dma-snooping;
2939 };
2940
2941 usb1: usb3@3000000 {
2942 @@ -491,6 +729,9 @@
2943 dr_mode = "host";
2944 snps,quirk-frame-length-adjustment = <0x20>;
2945 snps,dis_rxdet_inp3_quirk;
2946 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2947 + snps,dma-snooping;
2948 + configure-gfladj;
2949 };
2950
2951 usb2: usb3@3100000 {
2952 @@ -500,32 +741,52 @@
2953 dr_mode = "host";
2954 snps,quirk-frame-length-adjustment = <0x20>;
2955 snps,dis_rxdet_inp3_quirk;
2956 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2957 + snps,dma-snooping;
2958 + configure-gfladj;
2959 };
2960
2961 sata: sata@3200000 {
2962 compatible = "fsl,ls1043a-ahci";
2963 - reg = <0x0 0x3200000 0x0 0x10000>;
2964 + reg = <0x0 0x3200000 0x0 0x10000>,
2965 + <0x0 0x20140520 0x0 0x4>;
2966 + reg-names = "ahci", "sata-ecc";
2967 interrupts = <0 69 0x4>;
2968 clocks = <&clockgen 4 0>;
2969 dma-coherent;
2970 };
2971
2972 + qdma: qdma@8380000 {
2973 + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
2974 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
2975 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
2976 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
2977 + interrupts = <0 152 0x4>,
2978 + <0 39 0x4>;
2979 + interrupt-names = "qdma-error", "qdma-queue";
2980 + channels = <8>;
2981 + queues = <2>;
2982 + status-sizes = <64>;
2983 + queue-sizes = <64 64>;
2984 + big-endian;
2985 + };
2986 +
2987 msi1: msi-controller1@1571000 {
2988 - compatible = "fsl,1s1043a-msi";
2989 + compatible = "fsl,ls1043a-msi";
2990 reg = <0x0 0x1571000 0x0 0x8>;
2991 msi-controller;
2992 interrupts = <0 116 0x4>;
2993 };
2994
2995 msi2: msi-controller2@1572000 {
2996 - compatible = "fsl,1s1043a-msi";
2997 + compatible = "fsl,ls1043a-msi";
2998 reg = <0x0 0x1572000 0x0 0x8>;
2999 msi-controller;
3000 interrupts = <0 126 0x4>;
3001 };
3002
3003 msi3: msi-controller3@1573000 {
3004 - compatible = "fsl,1s1043a-msi";
3005 + compatible = "fsl,ls1043a-msi";
3006 reg = <0x0 0x1573000 0x0 0x8>;
3007 msi-controller;
3008 interrupts = <0 160 0x4>;
3009 @@ -536,9 +797,9 @@
3010 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
3011 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
3012 reg-names = "regs", "config";
3013 - interrupts = <0 118 0x4>, /* controller interrupt */
3014 - <0 117 0x4>; /* PME interrupt */
3015 - interrupt-names = "intr", "pme";
3016 + interrupts = <0 117 0x4>, /* PME interrupt */
3017 + <0 118 0x4>; /* aer interrupt */
3018 + interrupt-names = "pme", "aer";
3019 #address-cells = <3>;
3020 #size-cells = <2>;
3021 device_type = "pci";
3022 @@ -547,7 +808,7 @@
3023 bus-range = <0x0 0xff>;
3024 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
3025 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3026 - msi-parent = <&msi1>;
3027 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3028 #interrupt-cells = <1>;
3029 interrupt-map-mask = <0 0 0 7>;
3030 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
3031 @@ -561,9 +822,9 @@
3032 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
3033 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
3034 reg-names = "regs", "config";
3035 - interrupts = <0 128 0x4>,
3036 - <0 127 0x4>;
3037 - interrupt-names = "intr", "pme";
3038 + interrupts = <0 127 0x4>,
3039 + <0 128 0x4>;
3040 + interrupt-names = "pme", "aer";
3041 #address-cells = <3>;
3042 #size-cells = <2>;
3043 device_type = "pci";
3044 @@ -572,7 +833,7 @@
3045 bus-range = <0x0 0xff>;
3046 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
3047 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3048 - msi-parent = <&msi2>;
3049 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3050 #interrupt-cells = <1>;
3051 interrupt-map-mask = <0 0 0 7>;
3052 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
3053 @@ -586,9 +847,9 @@
3054 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
3055 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
3056 reg-names = "regs", "config";
3057 - interrupts = <0 162 0x4>,
3058 - <0 161 0x4>;
3059 - interrupt-names = "intr", "pme";
3060 + interrupts = <0 161 0x4>,
3061 + <0 162 0x4>;
3062 + interrupt-names = "pme", "aer";
3063 #address-cells = <3>;
3064 #size-cells = <2>;
3065 device_type = "pci";
3066 @@ -597,7 +858,7 @@
3067 bus-range = <0x0 0xff>;
3068 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
3069 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
3070 - msi-parent = <&msi3>;
3071 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
3072 #interrupt-cells = <1>;
3073 interrupt-map-mask = <0 0 0 7>;
3074 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
3075 @@ -608,3 +869,6 @@
3076 };
3077
3078 };
3079 +
3080 +#include "qoriq-qman1-portals.dtsi"
3081 +#include "qoriq-bman1-portals.dtsi"
3082 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
3083 new file mode 100644
3084 index 00000000..f5017dba
3085 --- /dev/null
3086 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
3087 @@ -0,0 +1,48 @@
3088 +/*
3089 + * QorIQ FMan v3 device tree nodes for ls1046
3090 + *
3091 + * Copyright 2015-2016 Freescale Semiconductor Inc.
3092 + *
3093 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3094 + */
3095 +
3096 +&soc {
3097 +
3098 +/* include used FMan blocks */
3099 +#include "qoriq-fman3-0.dtsi"
3100 +#include "qoriq-fman3-0-1g-0.dtsi"
3101 +#include "qoriq-fman3-0-1g-1.dtsi"
3102 +#include "qoriq-fman3-0-1g-2.dtsi"
3103 +#include "qoriq-fman3-0-1g-3.dtsi"
3104 +#include "qoriq-fman3-0-1g-4.dtsi"
3105 +#include "qoriq-fman3-0-1g-5.dtsi"
3106 +#include "qoriq-fman3-0-10g-0.dtsi"
3107 +#include "qoriq-fman3-0-10g-1.dtsi"
3108 +};
3109 +
3110 +&fman0 {
3111 + /* these aliases provide the FMan ports mapping */
3112 + enet0: ethernet@e0000 {
3113 + };
3114 +
3115 + enet1: ethernet@e2000 {
3116 + };
3117 +
3118 + enet2: ethernet@e4000 {
3119 + };
3120 +
3121 + enet3: ethernet@e6000 {
3122 + };
3123 +
3124 + enet4: ethernet@e8000 {
3125 + };
3126 +
3127 + enet5: ethernet@ea000 {
3128 + };
3129 +
3130 + enet6: ethernet@f0000 {
3131 + };
3132 +
3133 + enet7: ethernet@f2000 {
3134 + };
3135 +};
3136 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
3137 new file mode 100644
3138 index 00000000..c375af47
3139 --- /dev/null
3140 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
3141 @@ -0,0 +1,109 @@
3142 +/*
3143 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3144 + *
3145 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3146 + *
3147 + * Mingkai Hu <Mingkai.hu@freescale.com>
3148 + *
3149 + * This file is dual-licensed: you can use it either under the terms
3150 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3151 + * licensing only applies to this file, and not this project as a
3152 + * whole.
3153 + *
3154 + * a) This library is free software; you can redistribute it and/or
3155 + * modify it under the terms of the GNU General Public License as
3156 + * published by the Free Software Foundation; either version 2 of the
3157 + * License, or (at your option) any later version.
3158 + *
3159 + * This library is distributed in the hope that it will be useful,
3160 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3161 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3162 + * GNU General Public License for more details.
3163 + *
3164 + * Or, alternatively,
3165 + *
3166 + * b) Permission is hereby granted, free of charge, to any person
3167 + * obtaining a copy of this software and associated documentation
3168 + * files (the "Software"), to deal in the Software without
3169 + * restriction, including without limitation the rights to use,
3170 + * copy, modify, merge, publish, distribute, sublicense, and/or
3171 + * sell copies of the Software, and to permit persons to whom the
3172 + * Software is furnished to do so, subject to the following
3173 + * conditions:
3174 + *
3175 + * The above copyright notice and this permission notice shall be
3176 + * included in all copies or substantial portions of the Software.
3177 + *
3178 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3179 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3180 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3181 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3182 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3183 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3184 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3185 + * OTHER DEALINGS IN THE SOFTWARE.
3186 + */
3187 +
3188 +#include "fsl-ls1046a-qds.dts"
3189 +
3190 +&bman_fbpr {
3191 + compatible = "fsl,bman-fbpr";
3192 + alloc-ranges = <0 0 0x10000 0>;
3193 +};
3194 +&qman_fqd {
3195 + compatible = "fsl,qman-fqd";
3196 + alloc-ranges = <0 0 0x10000 0>;
3197 +};
3198 +&qman_pfdr {
3199 + compatible = "fsl,qman-pfdr";
3200 + alloc-ranges = <0 0 0x10000 0>;
3201 +};
3202 +
3203 +&soc {
3204 +#include "qoriq-dpaa-eth.dtsi"
3205 +#include "qoriq-fman3-0-6oh.dtsi"
3206 +};
3207 +
3208 +&fsldpaa {
3209 + ethernet@9 {
3210 + compatible = "fsl,dpa-ethernet";
3211 + fsl,fman-mac = <&enet7>;
3212 + };
3213 +};
3214 +
3215 +&fman0 {
3216 + compatible = "fsl,fman", "simple-bus";
3217 +};
3218 +
3219 +&dspi {
3220 + bus-num = <0>;
3221 + status = "okay";
3222 +
3223 + flash@0 {
3224 + #address-cells = <1>;
3225 + #size-cells = <1>;
3226 + compatible = "n25q128a11", "jedec,spi-nor";
3227 + reg = <0>;
3228 + spi-max-frequency = <10000000>;
3229 + };
3230 +
3231 + flash@1 {
3232 + #address-cells = <1>;
3233 + #size-cells = <1>;
3234 + compatible = "sst25wf040b", "jedec,spi-nor";
3235 + spi-cpol;
3236 + spi-cpha;
3237 + reg = <1>;
3238 + spi-max-frequency = <10000000>;
3239 + };
3240 +
3241 + flash@2 {
3242 + #address-cells = <1>;
3243 + #size-cells = <1>;
3244 + compatible = "en25s64", "jedec,spi-nor";
3245 + spi-cpol;
3246 + spi-cpha;
3247 + reg = <2>;
3248 + spi-max-frequency = <10000000>;
3249 + };
3250 +};
3251 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3252 new file mode 100644
3253 index 00000000..3b8e9b7e
3254 --- /dev/null
3255 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3256 @@ -0,0 +1,363 @@
3257 +/*
3258 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3259 + *
3260 + * Copyright 2016 Freescale Semiconductor, Inc.
3261 + *
3262 + * Shaohui Xie <Shaohui.Xie@nxp.com>
3263 + *
3264 + * This file is dual-licensed: you can use it either under the terms
3265 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3266 + * licensing only applies to this file, and not this project as a
3267 + * whole.
3268 + *
3269 + * a) This library is free software; you can redistribute it and/or
3270 + * modify it under the terms of the GNU General Public License as
3271 + * published by the Free Software Foundation; either version 2 of the
3272 + * License, or (at your option) any later version.
3273 + *
3274 + * This library is distributed in the hope that it will be useful,
3275 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3276 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3277 + * GNU General Public License for more details.
3278 + *
3279 + * Or, alternatively,
3280 + *
3281 + * b) Permission is hereby granted, free of charge, to any person
3282 + * obtaining a copy of this software and associated documentation
3283 + * files (the "Software"), to deal in the Software without
3284 + * restriction, including without limitation the rights to use,
3285 + * copy, modify, merge, publish, distribute, sublicense, and/or
3286 + * sell copies of the Software, and to permit persons to whom the
3287 + * Software is furnished to do so, subject to the following
3288 + * conditions:
3289 + *
3290 + * The above copyright notice and this permission notice shall be
3291 + * included in all copies or substantial portions of the Software.
3292 + *
3293 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3294 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3295 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3296 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3297 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3298 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3299 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3300 + * OTHER DEALINGS IN THE SOFTWARE.
3301 + */
3302 +
3303 +/dts-v1/;
3304 +
3305 +#include "fsl-ls1046a.dtsi"
3306 +
3307 +/ {
3308 + model = "LS1046A QDS Board";
3309 + compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
3310 +
3311 + aliases {
3312 + gpio0 = &gpio0;
3313 + gpio1 = &gpio1;
3314 + gpio2 = &gpio2;
3315 + gpio3 = &gpio3;
3316 + serial0 = &duart0;
3317 + serial1 = &duart1;
3318 + serial2 = &duart2;
3319 + serial3 = &duart3;
3320 +
3321 + emi1_slot1 = &ls1046mdio_s1;
3322 + emi1_slot2 = &ls1046mdio_s2;
3323 + emi1_slot4 = &ls1046mdio_s4;
3324 +
3325 + sgmii_s1_p1 = &sgmii_phy_s1_p1;
3326 + sgmii_s1_p2 = &sgmii_phy_s1_p2;
3327 + sgmii_s1_p3 = &sgmii_phy_s1_p3;
3328 + sgmii_s1_p4 = &sgmii_phy_s1_p4;
3329 + sgmii_s4_p1 = &sgmii_phy_s4_p1;
3330 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
3331 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
3332 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
3333 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
3334 + };
3335 +
3336 + chosen {
3337 + stdout-path = "serial0:115200n8";
3338 + };
3339 +};
3340 +
3341 +&dspi {
3342 + bus-num = <0>;
3343 + status = "okay";
3344 +
3345 + flash@0 {
3346 + #address-cells = <1>;
3347 + #size-cells = <1>;
3348 + compatible = "n25q128a11", "jedec,spi-nor";
3349 + reg = <0>;
3350 + spi-max-frequency = <10000000>;
3351 + };
3352 +
3353 + flash@1 {
3354 + #address-cells = <1>;
3355 + #size-cells = <1>;
3356 + compatible = "sst25wf040b", "jedec,spi-nor";
3357 + spi-cpol;
3358 + spi-cpha;
3359 + reg = <1>;
3360 + spi-max-frequency = <10000000>;
3361 + };
3362 +
3363 + flash@2 {
3364 + #address-cells = <1>;
3365 + #size-cells = <1>;
3366 + compatible = "en25s64", "jedec,spi-nor";
3367 + spi-cpol;
3368 + spi-cpha;
3369 + reg = <2>;
3370 + spi-max-frequency = <10000000>;
3371 + };
3372 +};
3373 +
3374 +&duart0 {
3375 + status = "okay";
3376 +};
3377 +
3378 +&duart1 {
3379 + status = "okay";
3380 +};
3381 +
3382 +&i2c0 {
3383 + status = "okay";
3384 +
3385 + pca9547@77 {
3386 + compatible = "nxp,pca9547";
3387 + reg = <0x77>;
3388 + #address-cells = <1>;
3389 + #size-cells = <0>;
3390 +
3391 + i2c@2 {
3392 + #address-cells = <1>;
3393 + #size-cells = <0>;
3394 + reg = <0x2>;
3395 +
3396 + ina220@40 {
3397 + compatible = "ti,ina220";
3398 + reg = <0x40>;
3399 + shunt-resistor = <1000>;
3400 + };
3401 +
3402 + ina220@41 {
3403 + compatible = "ti,ina220";
3404 + reg = <0x41>;
3405 + shunt-resistor = <1000>;
3406 + };
3407 + };
3408 +
3409 + i2c@3 {
3410 + #address-cells = <1>;
3411 + #size-cells = <0>;
3412 + reg = <0x3>;
3413 +
3414 + rtc@51 {
3415 + compatible = "nxp,pcf2129";
3416 + reg = <0x51>;
3417 + /* IRQ10_B */
3418 + interrupts = <0 150 0x4>;
3419 + };
3420 +
3421 + eeprom@56 {
3422 + compatible = "atmel,24c512";
3423 + reg = <0x56>;
3424 + };
3425 +
3426 + eeprom@57 {
3427 + compatible = "atmel,24c512";
3428 + reg = <0x57>;
3429 + };
3430 +
3431 + temp-sensor@4c {
3432 + compatible = "adi,adt7461a";
3433 + reg = <0x4c>;
3434 + };
3435 + };
3436 + };
3437 +};
3438 +
3439 +&ifc {
3440 + #address-cells = <2>;
3441 + #size-cells = <1>;
3442 + /* NOR, NAND Flashes and FPGA on board */
3443 + ranges = <0x0 0x0 0x0 0x60000000 0x08000000
3444 + 0x1 0x0 0x0 0x7e800000 0x00010000
3445 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3446 + status = "okay";
3447 +
3448 + nor@0,0 {
3449 + compatible = "cfi-flash";
3450 + reg = <0x0 0x0 0x8000000>;
3451 + bank-width = <2>;
3452 + device-width = <1>;
3453 + };
3454 +
3455 + nand@1,0 {
3456 + compatible = "fsl,ifc-nand";
3457 + reg = <0x1 0x0 0x10000>;
3458 + };
3459 +
3460 + fpga: board-control@2,0 {
3461 + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
3462 + reg = <0x2 0x0 0x0000100>;
3463 + ranges = <0 2 0 0x100>;
3464 + };
3465 +};
3466 +
3467 +&lpuart0 {
3468 + status = "okay";
3469 +};
3470 +
3471 +&qspi {
3472 + num-cs = <2>;
3473 + bus-num = <0>;
3474 + status = "okay";
3475 +
3476 + qflash0: s25fl128s@0 {
3477 + compatible = "spansion,m25p80";
3478 + #address-cells = <1>;
3479 + #size-cells = <1>;
3480 + spi-max-frequency = <20000000>;
3481 + reg = <0>;
3482 + };
3483 +};
3484 +
3485 +#include "fsl-ls1046-post.dtsi"
3486 +
3487 +&fman0 {
3488 + ethernet@e0000 {
3489 + phy-handle = <&qsgmii_phy_s2_p1>;
3490 + phy-connection-type = "sgmii";
3491 + };
3492 +
3493 + ethernet@e2000 {
3494 + phy-handle = <&sgmii_phy_s4_p1>;
3495 + phy-connection-type = "sgmii";
3496 + };
3497 +
3498 + ethernet@e4000 {
3499 + phy-handle = <&rgmii_phy1>;
3500 + phy-connection-type = "rgmii";
3501 + };
3502 +
3503 + ethernet@e6000 {
3504 + phy-handle = <&rgmii_phy2>;
3505 + phy-connection-type = "rgmii";
3506 + };
3507 +
3508 + ethernet@e8000 {
3509 + phy-handle = <&sgmii_phy_s1_p3>;
3510 + phy-connection-type = "sgmii";
3511 + };
3512 +
3513 + ethernet@ea000 {
3514 + phy-handle = <&sgmii_phy_s1_p4>;
3515 + phy-connection-type = "sgmii";
3516 + };
3517 +
3518 + ethernet@f0000 { /* DTSEC9/10GEC1 */
3519 + phy-handle = <&sgmii_phy_s1_p1>;
3520 + phy-connection-type = "xgmii";
3521 + };
3522 +
3523 + ethernet@f2000 { /* DTSEC10/10GEC2 */
3524 + phy-handle = <&sgmii_phy_s1_p2>;
3525 + phy-connection-type = "xgmii";
3526 + };
3527 +};
3528 +
3529 +&fpga {
3530 + #address-cells = <1>;
3531 + #size-cells = <1>;
3532 + mdio-mux-emi1 {
3533 + compatible = "mdio-mux-mmioreg", "mdio-mux";
3534 + mdio-parent-bus = <&mdio0>;
3535 + #address-cells = <1>;
3536 + #size-cells = <0>;
3537 + reg = <0x54 1>; /* BRDCFG4 */
3538 + mux-mask = <0xe0>; /* EMI1 */
3539 +
3540 + /* On-board RGMII1 PHY */
3541 + ls1046mdio0: mdio@0 {
3542 + reg = <0>;
3543 + #address-cells = <1>;
3544 + #size-cells = <0>;
3545 +
3546 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
3547 + reg = <0x1>;
3548 + };
3549 + };
3550 +
3551 + /* On-board RGMII2 PHY */
3552 + ls1046mdio1: mdio@1 {
3553 + reg = <0x20>;
3554 + #address-cells = <1>;
3555 + #size-cells = <0>;
3556 +
3557 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
3558 + reg = <0x2>;
3559 + };
3560 + };
3561 +
3562 + /* Slot 1 */
3563 + ls1046mdio_s1: mdio@2 {
3564 + reg = <0x40>;
3565 + #address-cells = <1>;
3566 + #size-cells = <0>;
3567 + status = "disabled";
3568 +
3569 + sgmii_phy_s1_p1: ethernet-phy@1c {
3570 + reg = <0x1c>;
3571 + };
3572 +
3573 + sgmii_phy_s1_p2: ethernet-phy@1d {
3574 + reg = <0x1d>;
3575 + };
3576 +
3577 + sgmii_phy_s1_p3: ethernet-phy@1e {
3578 + reg = <0x1e>;
3579 + };
3580 +
3581 + sgmii_phy_s1_p4: ethernet-phy@1f {
3582 + reg = <0x1f>;
3583 + };
3584 + };
3585 +
3586 + /* Slot 2 */
3587 + ls1046mdio_s2: mdio@3 {
3588 + reg = <0x60>;
3589 + #address-cells = <1>;
3590 + #size-cells = <0>;
3591 + status = "disabled";
3592 +
3593 + qsgmii_phy_s2_p1: ethernet-phy@8 {
3594 + reg = <0x8>;
3595 + };
3596 + qsgmii_phy_s2_p2: ethernet-phy@9 {
3597 + reg = <0x9>;
3598 + };
3599 + qsgmii_phy_s2_p3: ethernet-phy@a {
3600 + reg = <0xa>;
3601 + };
3602 + qsgmii_phy_s2_p4: ethernet-phy@b {
3603 + reg = <0xb>;
3604 + };
3605 + };
3606 +
3607 + /* Slot 4 */
3608 + ls1046mdio_s4: mdio@5 {
3609 + reg = <0x80>;
3610 + #address-cells = <1>;
3611 + #size-cells = <0>;
3612 + status = "disabled";
3613 +
3614 + sgmii_phy_s4_p1: ethernet-phy@1c {
3615 + reg = <0x1c>;
3616 + };
3617 + };
3618 + };
3619 +};
3620 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
3621 new file mode 100644
3622 index 00000000..bfe2f36c
3623 --- /dev/null
3624 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
3625 @@ -0,0 +1,76 @@
3626 +/*
3627 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3628 + *
3629 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3630 + *
3631 + * Mingkai Hu <Mingkai.hu@freescale.com>
3632 + *
3633 + * This file is dual-licensed: you can use it either under the terms
3634 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3635 + * licensing only applies to this file, and not this project as a
3636 + * whole.
3637 + *
3638 + * a) This library is free software; you can redistribute it and/or
3639 + * modify it under the terms of the GNU General Public License as
3640 + * published by the Free Software Foundation; either version 2 of the
3641 + * License, or (at your option) any later version.
3642 + *
3643 + * This library is distributed in the hope that it will be useful,
3644 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3645 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3646 + * GNU General Public License for more details.
3647 + *
3648 + * Or, alternatively,
3649 + *
3650 + * b) Permission is hereby granted, free of charge, to any person
3651 + * obtaining a copy of this software and associated documentation
3652 + * files (the "Software"), to deal in the Software without
3653 + * restriction, including without limitation the rights to use,
3654 + * copy, modify, merge, publish, distribute, sublicense, and/or
3655 + * sell copies of the Software, and to permit persons to whom the
3656 + * Software is furnished to do so, subject to the following
3657 + * conditions:
3658 + *
3659 + * The above copyright notice and this permission notice shall be
3660 + * included in all copies or substantial portions of the Software.
3661 + *
3662 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3663 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3664 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3665 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3666 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3667 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3668 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3669 + * OTHER DEALINGS IN THE SOFTWARE.
3670 + */
3671 +
3672 +#include "fsl-ls1046a-rdb.dts"
3673 +
3674 +&bman_fbpr {
3675 + compatible = "fsl,bman-fbpr";
3676 + alloc-ranges = <0 0 0x10000 0>;
3677 +};
3678 +&qman_fqd {
3679 + compatible = "fsl,qman-fqd";
3680 + alloc-ranges = <0 0 0x10000 0>;
3681 +};
3682 +&qman_pfdr {
3683 + compatible = "fsl,qman-pfdr";
3684 + alloc-ranges = <0 0 0x10000 0>;
3685 +};
3686 +
3687 +&soc {
3688 +#include "qoriq-dpaa-eth.dtsi"
3689 +#include "qoriq-fman3-0-6oh.dtsi"
3690 +};
3691 +
3692 +&fsldpaa {
3693 + ethernet@9 {
3694 + compatible = "fsl,dpa-ethernet";
3695 + fsl,fman-mac = <&enet7>;
3696 + };
3697 +};
3698 +
3699 +&fman0 {
3700 + compatible = "fsl,fman", "simple-bus";
3701 +};
3702 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
3703 new file mode 100644
3704 index 00000000..54336aa6
3705 --- /dev/null
3706 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
3707 @@ -0,0 +1,110 @@
3708 +/*
3709 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3710 + *
3711 + * Copyright 2016 Freescale Semiconductor, Inc.
3712 + *
3713 + * This file is licensed under the terms of the GNU General Public
3714 + * License version 2. This program is licensed "as is" without any
3715 + * warranty of any kind, whether express or implied.
3716 + */
3717 +
3718 +#include "fsl-ls1046a-rdb-sdk.dts"
3719 +
3720 +&soc {
3721 + bp7: buffer-pool@7 {
3722 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3723 + fsl,bpid = <7>;
3724 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
3725 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
3726 + };
3727 +
3728 + bp8: buffer-pool@8 {
3729 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3730 + fsl,bpid = <8>;
3731 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
3732 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3733 + };
3734 +
3735 + bp9: buffer-pool@9 {
3736 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3737 + fsl,bpid = <9>;
3738 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
3739 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3740 + };
3741 +
3742 + fsl,dpaa {
3743 + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
3744 +
3745 + ethernet@2 {
3746 + compatible = "fsl,dpa-ethernet-init";
3747 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3748 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
3749 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
3750 + };
3751 +
3752 + ethernet@3 {
3753 + compatible = "fsl,dpa-ethernet-init";
3754 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3755 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
3756 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
3757 + };
3758 +
3759 + ethernet@4 {
3760 + compatible = "fsl,dpa-ethernet-init";
3761 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3762 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
3763 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
3764 + };
3765 +
3766 + ethernet@5 {
3767 + compatible = "fsl,dpa-ethernet-init";
3768 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3769 + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
3770 + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
3771 + };
3772 +
3773 + ethernet@8 {
3774 + compatible = "fsl,dpa-ethernet-init";
3775 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3776 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
3777 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
3778 + };
3779 +
3780 + ethernet@9 {
3781 + compatible = "fsl,dpa-ethernet-init";
3782 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3783 + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
3784 + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
3785 + };
3786 +
3787 + dpa-fman0-oh@2 {
3788 + compatible = "fsl,dpa-oh";
3789 + /* Define frame queues for the OH port*/
3790 + /* <OH Rx error, OH Rx default> */
3791 + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
3792 + fsl,fman-oh-port = <&fman0_oh2>;
3793 + };
3794 + };
3795 +};
3796 +/ {
3797 + reserved-memory {
3798 + #address-cells = <2>;
3799 + #size-cells = <2>;
3800 + ranges;
3801 +
3802 + usdpaa_mem: usdpaa_mem {
3803 + compatible = "fsl,usdpaa-mem";
3804 + alloc-ranges = <0 0 0x10000 0>;
3805 + size = <0 0x10000000>;
3806 + alignment = <0 0x10000000>;
3807 + };
3808 + };
3809 +};
3810 +
3811 +&fman0 {
3812 + fman0_oh2: port@83000 {
3813 + cell-index = <1>;
3814 + compatible = "fsl,fman-port-oh";
3815 + reg = <0x83000 0x1000>;
3816 + };
3817 +};
3818 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
3819 new file mode 100644
3820 index 00000000..be9b62ca
3821 --- /dev/null
3822 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
3823 @@ -0,0 +1,218 @@
3824 +/*
3825 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3826 + *
3827 + * Copyright 2016 Freescale Semiconductor, Inc.
3828 + *
3829 + * Mingkai Hu <mingkai.hu@nxp.com>
3830 + *
3831 + * This file is dual-licensed: you can use it either under the terms
3832 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3833 + * licensing only applies to this file, and not this project as a
3834 + * whole.
3835 + *
3836 + * a) This library is free software; you can redistribute it and/or
3837 + * modify it under the terms of the GNU General Public License as
3838 + * published by the Free Software Foundation; either version 2 of the
3839 + * License, or (at your option) any later version.
3840 + *
3841 + * This library is distributed in the hope that it will be useful,
3842 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3843 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3844 + * GNU General Public License for more details.
3845 + *
3846 + * Or, alternatively,
3847 + *
3848 + * b) Permission is hereby granted, free of charge, to any person
3849 + * obtaining a copy of this software and associated documentation
3850 + * files (the "Software"), to deal in the Software without
3851 + * restriction, including without limitation the rights to use,
3852 + * copy, modify, merge, publish, distribute, sublicense, and/or
3853 + * sell copies of the Software, and to permit persons to whom the
3854 + * Software is furnished to do so, subject to the following
3855 + * conditions:
3856 + *
3857 + * The above copyright notice and this permission notice shall be
3858 + * included in all copies or substantial portions of the Software.
3859 + *
3860 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3861 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3862 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3863 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3864 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3865 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3866 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3867 + * OTHER DEALINGS IN THE SOFTWARE.
3868 + */
3869 +
3870 +/dts-v1/;
3871 +
3872 +#include "fsl-ls1046a.dtsi"
3873 +
3874 +/ {
3875 + model = "LS1046A RDB Board";
3876 + compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
3877 +
3878 + aliases {
3879 + serial0 = &duart0;
3880 + serial1 = &duart1;
3881 + serial2 = &duart2;
3882 + serial3 = &duart3;
3883 + };
3884 +
3885 + chosen {
3886 + stdout-path = "serial0:115200n8";
3887 + };
3888 +};
3889 +
3890 +&esdhc {
3891 + mmc-hs200-1_8v;
3892 + sd-uhs-sdr104;
3893 + sd-uhs-sdr50;
3894 + sd-uhs-sdr25;
3895 + sd-uhs-sdr12;
3896 +};
3897 +
3898 +&duart0 {
3899 + status = "okay";
3900 +};
3901 +
3902 +&duart1 {
3903 + status = "okay";
3904 +};
3905 +
3906 +&i2c0 {
3907 + status = "okay";
3908 +
3909 + ina220@40 {
3910 + compatible = "ti,ina220";
3911 + reg = <0x40>;
3912 + shunt-resistor = <1000>;
3913 + };
3914 +
3915 + temp-sensor@4c {
3916 + compatible = "adi,adt7461";
3917 + reg = <0x4c>;
3918 + };
3919 +
3920 + eeprom@56 {
3921 + compatible = "atmel,24c512";
3922 + reg = <0x52>;
3923 + };
3924 +
3925 + eeprom@57 {
3926 + compatible = "atmel,24c512";
3927 + reg = <0x53>;
3928 + };
3929 +};
3930 +
3931 +&i2c3 {
3932 + status = "okay";
3933 +
3934 + rtc@51 {
3935 + compatible = "nxp,pcf2129";
3936 + reg = <0x51>;
3937 + };
3938 +};
3939 +
3940 +&ifc {
3941 + #address-cells = <2>;
3942 + #size-cells = <1>;
3943 + /* NAND Flashe and CPLD on board */
3944 + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
3945 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3946 + status = "okay";
3947 +
3948 + nand@0,0 {
3949 + compatible = "fsl,ifc-nand";
3950 + #address-cells = <1>;
3951 + #size-cells = <1>;
3952 + reg = <0x0 0x0 0x10000>;
3953 + };
3954 +
3955 + cpld: board-control@2,0 {
3956 + compatible = "fsl,ls1046ardb-cpld";
3957 + reg = <0x2 0x0 0x0000100>;
3958 + };
3959 +};
3960 +
3961 +&qspi {
3962 + num-cs = <2>;
3963 + bus-num = <0>;
3964 + status = "okay";
3965 +
3966 + qflash0: s25fs512s@0 {
3967 + compatible = "spansion,m25p80";
3968 + #address-cells = <1>;
3969 + #size-cells = <1>;
3970 + spi-max-frequency = <20000000>;
3971 + reg = <0>;
3972 + };
3973 +
3974 + qflash1: s25fs512s@1 {
3975 + compatible = "spansion,m25p80";
3976 + #address-cells = <1>;
3977 + #size-cells = <1>;
3978 + spi-max-frequency = <20000000>;
3979 + reg = <1>;
3980 + };
3981 +};
3982 +
3983 +#include "fsl-ls1046-post.dtsi"
3984 +
3985 +&fman0 {
3986 + ethernet@e4000 {
3987 + phy-handle = <&rgmii_phy1>;
3988 + phy-connection-type = "rgmii";
3989 + };
3990 +
3991 + ethernet@e6000 {
3992 + phy-handle = <&rgmii_phy2>;
3993 + phy-connection-type = "rgmii";
3994 + };
3995 +
3996 + ethernet@e8000 {
3997 + phy-handle = <&sgmii_phy1>;
3998 + phy-connection-type = "sgmii";
3999 + };
4000 +
4001 + ethernet@ea000 {
4002 + phy-handle = <&sgmii_phy2>;
4003 + phy-connection-type = "sgmii";
4004 + };
4005 +
4006 + ethernet@f0000 { /* 10GEC1 */
4007 + phy-handle = <&aqr106_phy>;
4008 + phy-connection-type = "xgmii";
4009 + };
4010 +
4011 + ethernet@f2000 { /* 10GEC2 */
4012 + fixed-link = <0 1 1000 0 0>;
4013 + phy-connection-type = "xgmii";
4014 + };
4015 +
4016 + mdio@fc000 {
4017 + rgmii_phy1: ethernet-phy@1 {
4018 + reg = <0x1>;
4019 + };
4020 +
4021 + rgmii_phy2: ethernet-phy@2 {
4022 + reg = <0x2>;
4023 + };
4024 +
4025 + sgmii_phy1: ethernet-phy@3 {
4026 + reg = <0x3>;
4027 + };
4028 +
4029 + sgmii_phy2: ethernet-phy@4 {
4030 + reg = <0x4>;
4031 + };
4032 + };
4033 +
4034 + mdio@fd000 {
4035 + aqr106_phy: ethernet-phy@0 {
4036 + compatible = "ethernet-phy-ieee802.3-c45";
4037 + interrupts = <0 131 4>;
4038 + reg = <0x0>;
4039 + };
4040 + };
4041 +};
4042 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
4043 new file mode 100644
4044 index 00000000..f7fe73c4
4045 --- /dev/null
4046 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
4047 @@ -0,0 +1,793 @@
4048 +/*
4049 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4050 + *
4051 + * Copyright 2016 Freescale Semiconductor, Inc.
4052 + *
4053 + * Mingkai Hu <mingkai.hu@nxp.com>
4054 + *
4055 + * This file is dual-licensed: you can use it either under the terms
4056 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4057 + * licensing only applies to this file, and not this project as a
4058 + * whole.
4059 + *
4060 + * a) This library is free software; you can redistribute it and/or
4061 + * modify it under the terms of the GNU General Public License as
4062 + * published by the Free Software Foundation; either version 2 of the
4063 + * License, or (at your option) any later version.
4064 + *
4065 + * This library is distributed in the hope that it will be useful,
4066 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4067 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4068 + * GNU General Public License for more details.
4069 + *
4070 + * Or, alternatively,
4071 + *
4072 + * b) Permission is hereby granted, free of charge, to any person
4073 + * obtaining a copy of this software and associated documentation
4074 + * files (the "Software"), to deal in the Software without
4075 + * restriction, including without limitation the rights to use,
4076 + * copy, modify, merge, publish, distribute, sublicense, and/or
4077 + * sell copies of the Software, and to permit persons to whom the
4078 + * Software is furnished to do so, subject to the following
4079 + * conditions:
4080 + *
4081 + * The above copyright notice and this permission notice shall be
4082 + * included in all copies or substantial portions of the Software.
4083 + *
4084 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4085 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4086 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4087 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4088 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4089 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4090 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4091 + * OTHER DEALINGS IN THE SOFTWARE.
4092 + */
4093 +
4094 +#include <dt-bindings/interrupt-controller/arm-gic.h>
4095 +#include <dt-bindings/thermal/thermal.h>
4096 +
4097 +/ {
4098 + compatible = "fsl,ls1046a";
4099 + interrupt-parent = <&gic>;
4100 + #address-cells = <2>;
4101 + #size-cells = <2>;
4102 +
4103 + aliases {
4104 + crypto = &crypto;
4105 + fman0 = &fman0;
4106 + ethernet0 = &enet0;
4107 + ethernet1 = &enet1;
4108 + ethernet2 = &enet2;
4109 + ethernet3 = &enet3;
4110 + ethernet4 = &enet4;
4111 + ethernet5 = &enet5;
4112 + ethernet6 = &enet6;
4113 + ethernet7 = &enet7;
4114 + };
4115 +
4116 + cpus {
4117 + #address-cells = <1>;
4118 + #size-cells = <0>;
4119 +
4120 + cpu0: cpu@0 {
4121 + device_type = "cpu";
4122 + compatible = "arm,cortex-a72";
4123 + reg = <0x0>;
4124 + clocks = <&clockgen 1 0>;
4125 + next-level-cache = <&l2>;
4126 + cpu-idle-states = <&CPU_PH20>;
4127 + #cooling-cells = <2>;
4128 + };
4129 +
4130 + cpu1: cpu@1 {
4131 + device_type = "cpu";
4132 + compatible = "arm,cortex-a72";
4133 + reg = <0x1>;
4134 + clocks = <&clockgen 1 0>;
4135 + next-level-cache = <&l2>;
4136 + cpu-idle-states = <&CPU_PH20>;
4137 + };
4138 +
4139 + cpu2: cpu@2 {
4140 + device_type = "cpu";
4141 + compatible = "arm,cortex-a72";
4142 + reg = <0x2>;
4143 + clocks = <&clockgen 1 0>;
4144 + next-level-cache = <&l2>;
4145 + cpu-idle-states = <&CPU_PH20>;
4146 + };
4147 +
4148 + cpu3: cpu@3 {
4149 + device_type = "cpu";
4150 + compatible = "arm,cortex-a72";
4151 + reg = <0x3>;
4152 + clocks = <&clockgen 1 0>;
4153 + next-level-cache = <&l2>;
4154 + cpu-idle-states = <&CPU_PH20>;
4155 + };
4156 +
4157 + l2: l2-cache {
4158 + compatible = "cache";
4159 + };
4160 + };
4161 +
4162 + idle-states {
4163 + /*
4164 + * PSCI node is not added default, U-boot will add missing
4165 + * parts if it determines to use PSCI.
4166 + */
4167 + entry-method = "arm,psci";
4168 +
4169 + CPU_PH20: cpu-ph20 {
4170 + compatible = "arm,idle-state";
4171 + idle-state-name = "PH20";
4172 + arm,psci-suspend-param = <0x0>;
4173 + entry-latency-us = <1000>;
4174 + exit-latency-us = <1000>;
4175 + min-residency-us = <3000>;
4176 + };
4177 + };
4178 +
4179 + memory@80000000 {
4180 + device_type = "memory";
4181 + };
4182 +
4183 + sysclk: sysclk {
4184 + compatible = "fixed-clock";
4185 + #clock-cells = <0>;
4186 + clock-frequency = <100000000>;
4187 + clock-output-names = "sysclk";
4188 + };
4189 +
4190 + reboot {
4191 + compatible ="syscon-reboot";
4192 + regmap = <&dcfg>;
4193 + offset = <0xb0>;
4194 + mask = <0x02>;
4195 + };
4196 +
4197 + timer {
4198 + compatible = "arm,armv8-timer";
4199 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
4200 + IRQ_TYPE_LEVEL_LOW)>,
4201 + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
4202 + IRQ_TYPE_LEVEL_LOW)>,
4203 + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
4204 + IRQ_TYPE_LEVEL_LOW)>,
4205 + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
4206 + IRQ_TYPE_LEVEL_LOW)>;
4207 + };
4208 +
4209 + pmu {
4210 + compatible = "arm,cortex-a72-pmu";
4211 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4212 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4213 + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
4214 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
4215 + interrupt-affinity = <&cpu0>,
4216 + <&cpu1>,
4217 + <&cpu2>,
4218 + <&cpu3>;
4219 + };
4220 +
4221 + gic: interrupt-controller@1400000 {
4222 + compatible = "arm,gic-400";
4223 + #interrupt-cells = <3>;
4224 + interrupt-controller;
4225 + reg = <0x0 0x1410000 0 0x10000>, /* GICD */
4226 + <0x0 0x1420000 0 0x20000>, /* GICC */
4227 + <0x0 0x1440000 0 0x20000>, /* GICH */
4228 + <0x0 0x1460000 0 0x20000>; /* GICV */
4229 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
4230 + IRQ_TYPE_LEVEL_LOW)>;
4231 + };
4232 +
4233 + soc: soc {
4234 + compatible = "simple-bus";
4235 + #address-cells = <2>;
4236 + #size-cells = <2>;
4237 + ranges;
4238 +
4239 + ddr: memory-controller@1080000 {
4240 + compatible = "fsl,qoriq-memory-controller";
4241 + reg = <0x0 0x1080000 0x0 0x1000>;
4242 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
4243 + big-endian;
4244 + };
4245 +
4246 + ifc: ifc@1530000 {
4247 + compatible = "fsl,ifc", "simple-bus";
4248 + reg = <0x0 0x1530000 0x0 0x10000>;
4249 + big-endian;
4250 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
4251 + };
4252 +
4253 + qspi: quadspi@1550000 {
4254 + compatible = "fsl,ls1021a-qspi";
4255 + #address-cells = <1>;
4256 + #size-cells = <0>;
4257 + reg = <0x0 0x1550000 0x0 0x10000>,
4258 + <0x0 0x40000000 0x0 0x10000000>;
4259 + reg-names = "QuadSPI", "QuadSPI-memory";
4260 + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
4261 + clock-names = "qspi_en", "qspi";
4262 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
4263 + big-endian;
4264 + fsl,qspi-has-second-chip;
4265 + status = "disabled";
4266 + };
4267 +
4268 + esdhc: esdhc@1560000 {
4269 + compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
4270 + reg = <0x0 0x1560000 0x0 0x10000>;
4271 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
4272 + clocks = <&clockgen 2 1>;
4273 + voltage-ranges = <1800 1800 3300 3300>;
4274 + sdhci,auto-cmd12;
4275 + big-endian;
4276 + bus-width = <4>;
4277 + };
4278 +
4279 + scfg: scfg@1570000 {
4280 + compatible = "fsl,ls1046a-scfg", "syscon";
4281 + reg = <0x0 0x1570000 0x0 0x10000>;
4282 + big-endian;
4283 + };
4284 +
4285 + crypto: crypto@1700000 {
4286 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
4287 + "fsl,sec-v4.0";
4288 + fsl,sec-era = <8>;
4289 + #address-cells = <1>;
4290 + #size-cells = <1>;
4291 + ranges = <0x0 0x00 0x1700000 0x100000>;
4292 + reg = <0x00 0x1700000 0x0 0x100000>;
4293 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4294 +
4295 + sec_jr0: jr@10000 {
4296 + compatible = "fsl,sec-v5.4-job-ring",
4297 + "fsl,sec-v5.0-job-ring",
4298 + "fsl,sec-v4.0-job-ring";
4299 + reg = <0x10000 0x10000>;
4300 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
4301 + };
4302 +
4303 + sec_jr1: jr@20000 {
4304 + compatible = "fsl,sec-v5.4-job-ring",
4305 + "fsl,sec-v5.0-job-ring",
4306 + "fsl,sec-v4.0-job-ring";
4307 + reg = <0x20000 0x10000>;
4308 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4309 + };
4310 +
4311 + sec_jr2: jr@30000 {
4312 + compatible = "fsl,sec-v5.4-job-ring",
4313 + "fsl,sec-v5.0-job-ring",
4314 + "fsl,sec-v4.0-job-ring";
4315 + reg = <0x30000 0x10000>;
4316 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
4317 + };
4318 +
4319 + sec_jr3: jr@40000 {
4320 + compatible = "fsl,sec-v5.4-job-ring",
4321 + "fsl,sec-v5.0-job-ring",
4322 + "fsl,sec-v4.0-job-ring";
4323 + reg = <0x40000 0x10000>;
4324 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
4325 + };
4326 + };
4327 +
4328 + qman: qman@1880000 {
4329 + compatible = "fsl,qman";
4330 + reg = <0x00 0x1880000 0x0 0x10000>;
4331 + interrupts = <0 45 0x4>;
4332 + memory-region = <&qman_fqd &qman_pfdr>;
4333 +
4334 + };
4335 +
4336 + bman: bman@1890000 {
4337 + compatible = "fsl,bman";
4338 + reg = <0x00 0x1890000 0x0 0x10000>;
4339 + interrupts = <0 45 0x4>;
4340 + memory-region = <&bman_fbpr>;
4341 +
4342 + };
4343 +
4344 + qportals: qman-portals@500000000 {
4345 + ranges = <0x0 0x5 0x00000000 0x8000000>;
4346 + };
4347 +
4348 + bportals: bman-portals@508000000 {
4349 + ranges = <0x0 0x5 0x08000000 0x8000000>;
4350 + };
4351 +
4352 + dcfg: dcfg@1ee0000 {
4353 + compatible = "fsl,ls1046a-dcfg", "syscon";
4354 + reg = <0x0 0x1ee0000 0x0 0x1000>;
4355 + big-endian;
4356 + };
4357 +
4358 + clockgen: clocking@1ee1000 {
4359 + compatible = "fsl,ls1046a-clockgen";
4360 + reg = <0x0 0x1ee1000 0x0 0x1000>;
4361 + #clock-cells = <2>;
4362 + clocks = <&sysclk>;
4363 + };
4364 +
4365 + tmu: tmu@1f00000 {
4366 + compatible = "fsl,qoriq-tmu";
4367 + reg = <0x0 0x1f00000 0x0 0x10000>;
4368 + interrupts = <0 33 0x4>;
4369 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
4370 + fsl,tmu-calibration =
4371 + /* Calibration data group 1 */
4372 + <0x00000000 0x00000026
4373 + 0x00000001 0x0000002d
4374 + 0x00000002 0x00000032
4375 + 0x00000003 0x00000039
4376 + 0x00000004 0x0000003f
4377 + 0x00000005 0x00000046
4378 + 0x00000006 0x0000004d
4379 + 0x00000007 0x00000054
4380 + 0x00000008 0x0000005a
4381 + 0x00000009 0x00000061
4382 + 0x0000000a 0x0000006a
4383 + 0x0000000b 0x00000071
4384 + /* Calibration data group 2 */
4385 + 0x00010000 0x00000025
4386 + 0x00010001 0x0000002c
4387 + 0x00010002 0x00000035
4388 + 0x00010003 0x0000003d
4389 + 0x00010004 0x00000045
4390 + 0x00010005 0x0000004e
4391 + 0x00010006 0x00000057
4392 + 0x00010007 0x00000061
4393 + 0x00010008 0x0000006b
4394 + 0x00010009 0x00000076
4395 + /* Calibration data group 3 */
4396 + 0x00020000 0x00000029
4397 + 0x00020001 0x00000033
4398 + 0x00020002 0x0000003d
4399 + 0x00020003 0x00000049
4400 + 0x00020004 0x00000056
4401 + 0x00020005 0x00000061
4402 + 0x00020006 0x0000006d
4403 + /* Calibration data group 4 */
4404 + 0x00030000 0x00000021
4405 + 0x00030001 0x0000002a
4406 + 0x00030002 0x0000003c
4407 + 0x00030003 0x0000004e>;
4408 + big-endian;
4409 + #thermal-sensor-cells = <1>;
4410 + };
4411 +
4412 + thermal-zones {
4413 + cpu_thermal: cpu-thermal {
4414 + polling-delay-passive = <1000>;
4415 + polling-delay = <5000>;
4416 + thermal-sensors = <&tmu 3>;
4417 +
4418 + trips {
4419 + cpu_alert: cpu-alert {
4420 + temperature = <85000>;
4421 + hysteresis = <2000>;
4422 + type = "passive";
4423 + };
4424 +
4425 + cpu_crit: cpu-crit {
4426 + temperature = <95000>;
4427 + hysteresis = <2000>;
4428 + type = "critical";
4429 + };
4430 + };
4431 +
4432 + cooling-maps {
4433 + map0 {
4434 + trip = <&cpu_alert>;
4435 + cooling-device =
4436 + <&cpu0 THERMAL_NO_LIMIT
4437 + THERMAL_NO_LIMIT>;
4438 + };
4439 + };
4440 + };
4441 + };
4442 +
4443 + dspi: dspi@2100000 {
4444 + compatible = "fsl,ls1021a-v1.0-dspi";
4445 + #address-cells = <1>;
4446 + #size-cells = <0>;
4447 + reg = <0x0 0x2100000 0x0 0x10000>;
4448 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
4449 + clock-names = "dspi";
4450 + clocks = <&clockgen 4 1>;
4451 + spi-num-chipselects = <5>;
4452 + big-endian;
4453 + status = "disabled";
4454 + };
4455 +
4456 + i2c0: i2c@2180000 {
4457 + compatible = "fsl,vf610-i2c";
4458 + #address-cells = <1>;
4459 + #size-cells = <0>;
4460 + reg = <0x0 0x2180000 0x0 0x10000>;
4461 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
4462 + clocks = <&clockgen 4 1>;
4463 + dmas = <&edma0 1 39>,
4464 + <&edma0 1 38>;
4465 + dma-names = "tx", "rx";
4466 + status = "disabled";
4467 + };
4468 +
4469 + i2c1: i2c@2190000 {
4470 + compatible = "fsl,vf610-i2c";
4471 + #address-cells = <1>;
4472 + #size-cells = <0>;
4473 + reg = <0x0 0x2190000 0x0 0x10000>;
4474 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
4475 + clocks = <&clockgen 4 1>;
4476 + status = "disabled";
4477 + };
4478 +
4479 + i2c2: i2c@21a0000 {
4480 + compatible = "fsl,vf610-i2c";
4481 + #address-cells = <1>;
4482 + #size-cells = <0>;
4483 + reg = <0x0 0x21a0000 0x0 0x10000>;
4484 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
4485 + clocks = <&clockgen 4 1>;
4486 + status = "disabled";
4487 + };
4488 +
4489 + i2c3: i2c@21b0000 {
4490 + compatible = "fsl,vf610-i2c";
4491 + #address-cells = <1>;
4492 + #size-cells = <0>;
4493 + reg = <0x0 0x21b0000 0x0 0x10000>;
4494 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
4495 + clocks = <&clockgen 4 1>;
4496 + status = "disabled";
4497 + };
4498 +
4499 + duart0: serial@21c0500 {
4500 + compatible = "fsl,ns16550", "ns16550a";
4501 + reg = <0x00 0x21c0500 0x0 0x100>;
4502 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4503 + clocks = <&clockgen 4 1>;
4504 + };
4505 +
4506 + duart1: serial@21c0600 {
4507 + compatible = "fsl,ns16550", "ns16550a";
4508 + reg = <0x00 0x21c0600 0x0 0x100>;
4509 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4510 + clocks = <&clockgen 4 1>;
4511 + };
4512 +
4513 + duart2: serial@21d0500 {
4514 + compatible = "fsl,ns16550", "ns16550a";
4515 + reg = <0x0 0x21d0500 0x0 0x100>;
4516 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4517 + clocks = <&clockgen 4 1>;
4518 + };
4519 +
4520 + duart3: serial@21d0600 {
4521 + compatible = "fsl,ns16550", "ns16550a";
4522 + reg = <0x0 0x21d0600 0x0 0x100>;
4523 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4524 + clocks = <&clockgen 4 1>;
4525 + };
4526 +
4527 + gpio0: gpio@2300000 {
4528 + compatible = "fsl,qoriq-gpio";
4529 + reg = <0x0 0x2300000 0x0 0x10000>;
4530 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
4531 + gpio-controller;
4532 + #gpio-cells = <2>;
4533 + interrupt-controller;
4534 + #interrupt-cells = <2>;
4535 + };
4536 +
4537 + gpio1: gpio@2310000 {
4538 + compatible = "fsl,qoriq-gpio";
4539 + reg = <0x0 0x2310000 0x0 0x10000>;
4540 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
4541 + gpio-controller;
4542 + #gpio-cells = <2>;
4543 + interrupt-controller;
4544 + #interrupt-cells = <2>;
4545 + };
4546 +
4547 + gpio2: gpio@2320000 {
4548 + compatible = "fsl,qoriq-gpio";
4549 + reg = <0x0 0x2320000 0x0 0x10000>;
4550 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
4551 + gpio-controller;
4552 + #gpio-cells = <2>;
4553 + interrupt-controller;
4554 + #interrupt-cells = <2>;
4555 + };
4556 +
4557 + gpio3: gpio@2330000 {
4558 + compatible = "fsl,qoriq-gpio";
4559 + reg = <0x0 0x2330000 0x0 0x10000>;
4560 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
4561 + gpio-controller;
4562 + #gpio-cells = <2>;
4563 + interrupt-controller;
4564 + #interrupt-cells = <2>;
4565 + };
4566 +
4567 + lpuart0: serial@2950000 {
4568 + compatible = "fsl,ls1021a-lpuart";
4569 + reg = <0x0 0x2950000 0x0 0x1000>;
4570 + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
4571 + clocks = <&clockgen 4 0>;
4572 + clock-names = "ipg";
4573 + status = "disabled";
4574 + };
4575 +
4576 + lpuart1: serial@2960000 {
4577 + compatible = "fsl,ls1021a-lpuart";
4578 + reg = <0x0 0x2960000 0x0 0x1000>;
4579 + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4580 + clocks = <&clockgen 4 1>;
4581 + clock-names = "ipg";
4582 + status = "disabled";
4583 + };
4584 +
4585 + lpuart2: serial@2970000 {
4586 + compatible = "fsl,ls1021a-lpuart";
4587 + reg = <0x0 0x2970000 0x0 0x1000>;
4588 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
4589 + clocks = <&clockgen 4 1>;
4590 + clock-names = "ipg";
4591 + status = "disabled";
4592 + };
4593 +
4594 + lpuart3: serial@2980000 {
4595 + compatible = "fsl,ls1021a-lpuart";
4596 + reg = <0x0 0x2980000 0x0 0x1000>;
4597 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4598 + clocks = <&clockgen 4 1>;
4599 + clock-names = "ipg";
4600 + status = "disabled";
4601 + };
4602 +
4603 + lpuart4: serial@2990000 {
4604 + compatible = "fsl,ls1021a-lpuart";
4605 + reg = <0x0 0x2990000 0x0 0x1000>;
4606 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
4607 + clocks = <&clockgen 4 1>;
4608 + clock-names = "ipg";
4609 + status = "disabled";
4610 + };
4611 +
4612 + lpuart5: serial@29a0000 {
4613 + compatible = "fsl,ls1021a-lpuart";
4614 + reg = <0x0 0x29a0000 0x0 0x1000>;
4615 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4616 + clocks = <&clockgen 4 1>;
4617 + clock-names = "ipg";
4618 + status = "disabled";
4619 + };
4620 +
4621 + ftm0: ftm0@29d0000 {
4622 + compatible = "fsl,ls1046a-ftm";
4623 + reg = <0x0 0x29d0000 0x0 0x10000>,
4624 + <0x0 0x1ee2140 0x0 0x4>;
4625 + reg-names = "ftm", "FlexTimer1";
4626 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
4627 + big-endian;
4628 + };
4629 +
4630 + wdog0: watchdog@2ad0000 {
4631 + compatible = "fsl,imx21-wdt";
4632 + reg = <0x0 0x2ad0000 0x0 0x10000>;
4633 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4634 + clocks = <&clockgen 4 1>;
4635 + big-endian;
4636 + };
4637 +
4638 + edma0: edma@2c00000 {
4639 + #dma-cells = <2>;
4640 + compatible = "fsl,vf610-edma";
4641 + reg = <0x0 0x2c00000 0x0 0x10000>,
4642 + <0x0 0x2c10000 0x0 0x10000>,
4643 + <0x0 0x2c20000 0x0 0x10000>;
4644 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4645 + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
4646 + interrupt-names = "edma-tx", "edma-err";
4647 + dma-channels = <32>;
4648 + big-endian;
4649 + clock-names = "dmamux0", "dmamux1";
4650 + clocks = <&clockgen 4 1>,
4651 + <&clockgen 4 1>;
4652 + };
4653 +
4654 + usb0: usb@2f00000 {
4655 + compatible = "snps,dwc3";
4656 + reg = <0x0 0x2f00000 0x0 0x10000>;
4657 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
4658 + dr_mode = "host";
4659 + snps,quirk-frame-length-adjustment = <0x20>;
4660 + snps,dis_rxdet_inp3_quirk;
4661 + };
4662 +
4663 + usb1: usb@3000000 {
4664 + compatible = "snps,dwc3";
4665 + reg = <0x0 0x3000000 0x0 0x10000>;
4666 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
4667 + dr_mode = "host";
4668 + snps,quirk-frame-length-adjustment = <0x20>;
4669 + snps,dis_rxdet_inp3_quirk;
4670 + };
4671 +
4672 + usb2: usb@3100000 {
4673 + compatible = "snps,dwc3";
4674 + reg = <0x0 0x3100000 0x0 0x10000>;
4675 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
4676 + dr_mode = "host";
4677 + snps,quirk-frame-length-adjustment = <0x20>;
4678 + snps,dis_rxdet_inp3_quirk;
4679 + };
4680 +
4681 + sata: sata@3200000 {
4682 + compatible = "fsl,ls1046a-ahci";
4683 + reg = <0x0 0x3200000 0x0 0x10000>,
4684 + <0x0 0x20140520 0x0 0x4>;
4685 + reg-names = "ahci", "sata-ecc";
4686 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
4687 + clocks = <&clockgen 4 1>;
4688 + dma-coherent;
4689 + };
4690 +
4691 + qdma: qdma@8380000 {
4692 + compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
4693 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
4694 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
4695 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
4696 + interrupts = <0 153 0x4>,
4697 + <0 39 0x4>;
4698 + interrupt-names = "qdma-error", "qdma-queue";
4699 + channels = <8>;
4700 + queues = <2>;
4701 + status-sizes = <64>;
4702 + queue-sizes = <64 64>;
4703 + big-endian;
4704 + };
4705 +
4706 + msi1: msi-controller@1580000 {
4707 + compatible = "fsl,ls1046a-msi";
4708 + msi-controller;
4709 + reg = <0x0 0x1580000 0x0 0x10000>;
4710 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4711 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4712 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4713 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
4714 + };
4715 +
4716 + msi2: msi-controller@1590000 {
4717 + compatible = "fsl,ls1046a-msi";
4718 + msi-controller;
4719 + reg = <0x0 0x1590000 0x0 0x10000>;
4720 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
4721 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
4722 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
4723 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
4724 + };
4725 +
4726 + msi3: msi-controller@15a0000 {
4727 + compatible = "fsl,ls1046a-msi";
4728 + msi-controller;
4729 + reg = <0x0 0x15a0000 0x0 0x10000>;
4730 + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4731 + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
4732 + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
4733 + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
4734 + };
4735 +
4736 + pcie@3400000 {
4737 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4738 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
4739 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
4740 + reg-names = "regs", "config";
4741 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
4742 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
4743 + interrupt-names = "pme", "aer";
4744 + #address-cells = <3>;
4745 + #size-cells = <2>;
4746 + device_type = "pci";
4747 + dma-coherent;
4748 + num-lanes = <4>;
4749 + bus-range = <0x0 0xff>;
4750 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
4751 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4752 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4753 + #interrupt-cells = <1>;
4754 + interrupt-map-mask = <0 0 0 7>;
4755 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4756 + <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4757 + <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4758 + <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
4759 + };
4760 +
4761 + pcie@3500000 {
4762 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4763 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
4764 + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
4765 + reg-names = "regs", "config";
4766 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
4767 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
4768 + interrupt-names = "pme", "aer";
4769 + #address-cells = <3>;
4770 + #size-cells = <2>;
4771 + device_type = "pci";
4772 + dma-coherent;
4773 + num-lanes = <2>;
4774 + bus-range = <0x0 0xff>;
4775 + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
4776 + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4777 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4778 + #interrupt-cells = <1>;
4779 + interrupt-map-mask = <0 0 0 7>;
4780 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4781 + <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4782 + <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4783 + <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
4784 + };
4785 +
4786 + pcie@3600000 {
4787 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4788 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
4789 + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
4790 + reg-names = "regs", "config";
4791 + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
4792 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
4793 + interrupt-names = "pme", "aer";
4794 + #address-cells = <3>;
4795 + #size-cells = <2>;
4796 + device_type = "pci";
4797 + dma-coherent;
4798 + num-lanes = <2>;
4799 + bus-range = <0x0 0xff>;
4800 + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
4801 + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4802 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4803 + #interrupt-cells = <1>;
4804 + interrupt-map-mask = <0 0 0 7>;
4805 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4806 + <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4807 + <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4808 + <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
4809 + };
4810 +
4811 + };
4812 +
4813 + reserved-memory {
4814 + #address-cells = <2>;
4815 + #size-cells = <2>;
4816 + ranges;
4817 +
4818 + bman_fbpr: bman-fbpr {
4819 + compatible = "shared-dma-pool";
4820 + size = <0 0x1000000>;
4821 + alignment = <0 0x1000000>;
4822 + no-map;
4823 + };
4824 + qman_fqd: qman-fqd {
4825 + compatible = "shared-dma-pool";
4826 + size = <0 0x800000>;
4827 + alignment = <0 0x800000>;
4828 + no-map;
4829 + };
4830 + qman_pfdr: qman-pfdr {
4831 + compatible = "shared-dma-pool";
4832 + size = <0 0x2000000>;
4833 + alignment = <0 0x2000000>;
4834 + no-map;
4835 + };
4836 + };
4837 +};
4838 +
4839 +#include "qoriq-qman1-portals.dtsi"
4840 +#include "qoriq-bman1-portals.dtsi"
4841 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
4842 new file mode 100644
4843 index 00000000..f61ec261
4844 --- /dev/null
4845 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
4846 @@ -0,0 +1,173 @@
4847 +/*
4848 + * Device Tree file for NXP LS1088A QDS Board.
4849 + *
4850 + * Copyright 2017 NXP
4851 + *
4852 + * Harninder Rai <harninder.rai@nxp.com>
4853 + *
4854 + * This file is dual-licensed: you can use it either under the terms
4855 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4856 + * licensing only applies to this file, and not this project as a
4857 + * whole.
4858 + *
4859 + * a) This library is free software; you can redistribute it and/or
4860 + * modify it under the terms of the GNU General Public License as
4861 + * published by the Free Software Foundation; either version 2 of the
4862 + * License, or (at your option) any later version.
4863 + *
4864 + * This library is distributed in the hope that it will be useful,
4865 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4866 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4867 + * GNU General Public License for more details.
4868 + *
4869 + * Or, alternatively,
4870 + *
4871 + * b) Permission is hereby granted, free of charge, to any person
4872 + * obtaining a copy of this software and associated documentation
4873 + * files (the "Software"), to deal in the Software without
4874 + * restriction, including without limitation the rights to use,
4875 + * copy, modify, merge, publish, distribute, sublicense, and/or
4876 + * sell copies of the Software, and to permit persons to whom the
4877 + * Software is furnished to do so, subject to the following
4878 + * conditions:
4879 + *
4880 + * The above copyright notice and this permission notice shall be
4881 + * included in all copies or substantial portions of the Software.
4882 + *
4883 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4884 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4885 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4886 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4887 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4888 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4889 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4890 + * OTHER DEALINGS IN THE SOFTWARE.
4891 + */
4892 +
4893 +/dts-v1/;
4894 +
4895 +#include "fsl-ls1088a.dtsi"
4896 +
4897 +/ {
4898 + model = "LS1088A QDS Board";
4899 + compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
4900 +};
4901 +
4902 +&i2c0 {
4903 + status = "okay";
4904 +
4905 + i2c-switch@77 {
4906 + compatible = "nxp,pca9547";
4907 + reg = <0x77>;
4908 + #address-cells = <1>;
4909 + #size-cells = <0>;
4910 +
4911 + i2c@2 {
4912 + #address-cells = <1>;
4913 + #size-cells = <0>;
4914 + reg = <0x2>;
4915 +
4916 + ina220@40 {
4917 + compatible = "ti,ina220";
4918 + reg = <0x40>;
4919 + shunt-resistor = <1000>;
4920 + };
4921 +
4922 + ina220@41 {
4923 + compatible = "ti,ina220";
4924 + reg = <0x41>;
4925 + shunt-resistor = <1000>;
4926 + };
4927 + };
4928 +
4929 + i2c@3 {
4930 + #address-cells = <1>;
4931 + #size-cells = <0>;
4932 + reg = <0x3>;
4933 +
4934 + temp-sensor@4c {
4935 + compatible = "adi,adt7461a";
4936 + reg = <0x4c>;
4937 + };
4938 +
4939 + rtc@51 {
4940 + compatible = "nxp,pcf2129";
4941 + reg = <0x51>;
4942 + /* IRQ10_B */
4943 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
4944 + };
4945 +
4946 + eeprom@56 {
4947 + compatible = "atmel,24c512";
4948 + reg = <0x56>;
4949 + };
4950 +
4951 + eeprom@57 {
4952 + compatible = "atmel,24c512";
4953 + reg = <0x57>;
4954 + };
4955 + };
4956 + };
4957 +};
4958 +
4959 +&qspi {
4960 + status = "okay";
4961 + qflash0: s25fs512s@0 {
4962 + compatible = "spansion,m25p80";
4963 + #address-cells = <1>;
4964 + #size-cells = <1>;
4965 + spi-max-frequency = <20000000>;
4966 + m25p,fast-read;
4967 + reg = <0>;
4968 + };
4969 +
4970 + qflash1: s25fs512s@1 {
4971 + compatible = "spansion,m25p80";
4972 + #address-cells = <1>;
4973 + #size-cells = <1>;
4974 + spi-max-frequency = <20000000>;
4975 + m25p,fast-read;
4976 + reg = <1>;
4977 + };
4978 +};
4979 +
4980 +&ifc {
4981 + status = "okay";
4982 +
4983 + ranges = <0 0 0x5 0x80000000 0x08000000
4984 + 2 0 0x5 0x30000000 0x00010000
4985 + 3 0 0x5 0x20000000 0x00010000>;
4986 +
4987 + nor@0,0 {
4988 + compatible = "cfi-flash";
4989 + reg = <0x0 0x0 0x8000000>;
4990 + bank-width = <2>;
4991 + device-width = <1>;
4992 + };
4993 +
4994 + nand@2,0 {
4995 + compatible = "fsl,ifc-nand";
4996 + reg = <0x2 0x0 0x10000>;
4997 + };
4998 +
4999 + fpga: board-control@3,0 {
5000 + compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
5001 + reg = <0x3 0x0 0x0000100>;
5002 + };
5003 +};
5004 +
5005 +&duart0 {
5006 + status = "okay";
5007 +};
5008 +
5009 +&duart1 {
5010 + status = "okay";
5011 +};
5012 +
5013 +&esdhc {
5014 + status = "okay";
5015 +};
5016 +
5017 +&sata {
5018 + status = "okay";
5019 +};
5020 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
5021 new file mode 100644
5022 index 00000000..a4cbc2d5
5023 --- /dev/null
5024 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
5025 @@ -0,0 +1,236 @@
5026 +/*
5027 + * Device Tree file for NXP LS1088A RDB Board.
5028 + *
5029 + * Copyright 2017 NXP
5030 + *
5031 + * Harninder Rai <harninder.rai@nxp.com>
5032 + *
5033 + * This file is dual-licensed: you can use it either under the terms
5034 + * of the GPLv2 or the X11 license, at your option. Note that this dual
5035 + * licensing only applies to this file, and not this project as a
5036 + * whole.
5037 + *
5038 + * a) This library is free software; you can redistribute it and/or
5039 + * modify it under the terms of the GNU General Public License as
5040 + * published by the Free Software Foundation; either version 2 of the
5041 + * License, or (at your option) any later version.
5042 + *
5043 + * This library is distributed in the hope that it will be useful,
5044 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5045 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5046 + * GNU General Public License for more details.
5047 + *
5048 + * Or, alternatively,
5049 + *
5050 + * b) Permission is hereby granted, free of charge, to any person
5051 + * obtaining a copy of this software and associated documentation
5052 + * files (the "Software"), to deal in the Software without
5053 + * restriction, including without limitation the rights to use,
5054 + * copy, modify, merge, publish, distribute, sublicense, and/or
5055 + * sell copies of the Software, and to permit persons to whom the
5056 + * Software is furnished to do so, subject to the following
5057 + * conditions:
5058 + *
5059 + * The above copyright notice and this permission notice shall be
5060 + * included in all copies or substantial portions of the Software.
5061 + *
5062 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5063 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5064 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5065 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5066 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5067 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5068 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5069 + * OTHER DEALINGS IN THE SOFTWARE.
5070 + */
5071 +
5072 +/dts-v1/;
5073 +
5074 +#include "fsl-ls1088a.dtsi"
5075 +
5076 +/ {
5077 + model = "L1088A RDB Board";
5078 + compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
5079 +};
5080 +
5081 +&i2c0 {
5082 + status = "okay";
5083 +
5084 + i2c-switch@77 {
5085 + compatible = "nxp,pca9547";
5086 + reg = <0x77>;
5087 + #address-cells = <1>;
5088 + #size-cells = <0>;
5089 +
5090 + i2c@2 {
5091 + #address-cells = <1>;
5092 + #size-cells = <0>;
5093 + reg = <0x2>;
5094 +
5095 + ina220@40 {
5096 + compatible = "ti,ina220";
5097 + reg = <0x40>;
5098 + shunt-resistor = <1000>;
5099 + };
5100 + };
5101 +
5102 + i2c@3 {
5103 + #address-cells = <1>;
5104 + #size-cells = <0>;
5105 + reg = <0x3>;
5106 +
5107 + temp-sensor@4c {
5108 + compatible = "adi,adt7461a";
5109 + reg = <0x4c>;
5110 + };
5111 +
5112 + rtc@51 {
5113 + compatible = "nxp,pcf2129";
5114 + reg = <0x51>;
5115 + /* IRQ10_B */
5116 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
5117 + };
5118 + };
5119 + };
5120 +};
5121 +
5122 +&qspi {
5123 + status = "okay";
5124 + qflash0: s25fs512s@0 {
5125 + compatible = "spansion,m25p80";
5126 + #address-cells = <1>;
5127 + #size-cells = <1>;
5128 + m25p,fast-read;
5129 + spi-max-frequency = <20000000>;
5130 + reg = <0>;
5131 + };
5132 +
5133 + qflash1: s25fs512s@1 {
5134 + compatible = "spansion,m25p80";
5135 + #address-cells = <1>;
5136 + #size-cells = <1>;
5137 + m25p,fast-read;
5138 + spi-max-frequency = <20000000>;
5139 + reg = <1>;
5140 + };
5141 +};
5142 +
5143 +&ifc {
5144 + status = "okay";
5145 +
5146 + ranges = <0 0 0x5 0x30000000 0x00010000
5147 + 2 0 0x5 0x20000000 0x00010000>;
5148 +
5149 + nand@0,0 {
5150 + compatible = "fsl,ifc-nand";
5151 + reg = <0x0 0x0 0x10000>;
5152 + };
5153 +
5154 + fpga: board-control@2,0 {
5155 + compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
5156 + reg = <0x2 0x0 0x0000100>;
5157 + };
5158 +};
5159 +
5160 +&duart0 {
5161 + status = "okay";
5162 +};
5163 +
5164 +&duart1 {
5165 + status = "okay";
5166 +};
5167 +
5168 +&usb0 {
5169 + status = "okay";
5170 +};
5171 +
5172 +&usb1 {
5173 + status = "okay";
5174 +};
5175 +
5176 +&esdhc {
5177 + status = "okay";
5178 +};
5179 +
5180 +&sata {
5181 + status = "okay";
5182 +};
5183 +
5184 +&emdio1 {
5185 + /* Freescale F104 PHY1 */
5186 + mdio1_phy1: emdio1_phy@1 {
5187 + reg = <0x1c>;
5188 + phy-connection-type = "qsgmii";
5189 + };
5190 + mdio1_phy2: emdio1_phy@2 {
5191 + reg = <0x1d>;
5192 + phy-connection-type = "qsgmii";
5193 + };
5194 + mdio1_phy3: emdio1_phy@3 {
5195 + reg = <0x1e>;
5196 + phy-connection-type = "qsgmii";
5197 + };
5198 + mdio1_phy4: emdio1_phy@4 {
5199 + reg = <0x1f>;
5200 + phy-connection-type = "qsgmii";
5201 + };
5202 + /* F104 PHY2 */
5203 + mdio1_phy5: emdio1_phy@5 {
5204 + reg = <0x0c>;
5205 + phy-connection-type = "qsgmii";
5206 + };
5207 + mdio1_phy6: emdio1_phy@6 {
5208 + reg = <0x0d>;
5209 + phy-connection-type = "qsgmii";
5210 + };
5211 + mdio1_phy7: emdio1_phy@7 {
5212 + reg = <0x0e>;
5213 + phy-connection-type = "qsgmii";
5214 + };
5215 + mdio1_phy8: emdio1_phy@8 {
5216 + reg = <0x0f>;
5217 + phy-connection-type = "qsgmii";
5218 + };
5219 +};
5220 +
5221 +&emdio2 {
5222 + /* Aquantia AQR105 10G PHY */
5223 + mdio2_phy1: emdio2_phy@1 {
5224 + compatible = "ethernet-phy-ieee802.3-c45";
5225 + interrupts = <0 2 0x4>;
5226 + reg = <0x0>;
5227 + phy-connection-type = "xfi";
5228 + };
5229 +};
5230 +
5231 +/* DPMAC connections to external PHYs
5232 + * based on LS1088A RM RevC - $24.1.2 SerDes Options
5233 + */
5234 +/* DPMAC1 is 10G SFP+, fixed link */
5235 +&dpmac2 {
5236 + phy-handle = <&mdio2_phy1>;
5237 +};
5238 +&dpmac3 {
5239 + phy-handle = <&mdio1_phy5>;
5240 +};
5241 +&dpmac4 {
5242 + phy-handle = <&mdio1_phy6>;
5243 +};
5244 +&dpmac5 {
5245 + phy-handle = <&mdio1_phy7>;
5246 +};
5247 +&dpmac6 {
5248 + phy-handle = <&mdio1_phy8>;
5249 +};
5250 +&dpmac7 {
5251 + phy-handle = <&mdio1_phy1>;
5252 +};
5253 +&dpmac8 {
5254 + phy-handle = <&mdio1_phy2>;
5255 +};
5256 +&dpmac9 {
5257 + phy-handle = <&mdio1_phy3>;
5258 +};
5259 +&dpmac10 {
5260 + phy-handle = <&mdio1_phy4>;
5261 +};
5262 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
5263 new file mode 100644
5264 index 00000000..fd5f1e84
5265 --- /dev/null
5266 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
5267 @@ -0,0 +1,818 @@
5268 +/*
5269 + * Device Tree Include file for NXP Layerscape-1088A family SoC.
5270 + *
5271 + * Copyright 2017 NXP
5272 + *
5273 + * Harninder Rai <harninder.rai@nxp.com>
5274 + *
5275 + * This file is dual-licensed: you can use it either under the terms
5276 + * of the GPLv2 or the X11 license, at your option. Note that this dual
5277 + * licensing only applies to this file, and not this project as a
5278 + * whole.
5279 + *
5280 + * a) This library is free software; you can redistribute it and/or
5281 + * modify it under the terms of the GNU General Public License as
5282 + * published by the Free Software Foundation; either version 2 of the
5283 + * License, or (at your option) any later version.
5284 + *
5285 + * This library is distributed in the hope that it will be useful,
5286 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5287 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5288 + * GNU General Public License for more details.
5289 + *
5290 + * Or, alternatively,
5291 + *
5292 + * b) Permission is hereby granted, free of charge, to any person
5293 + * obtaining a copy of this software and associated documentation
5294 + * files (the "Software"), to deal in the Software without
5295 + * restriction, including without limitation the rights to use,
5296 + * copy, modify, merge, publish, distribute, sublicense, and/or
5297 + * sell copies of the Software, and to permit persons to whom the
5298 + * Software is furnished to do so, subject to the following
5299 + * conditions:
5300 + *
5301 + * The above copyright notice and this permission notice shall be
5302 + * included in all copies or substantial portions of the Software.
5303 + *
5304 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5305 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5306 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5307 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5308 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5309 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5310 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5311 + * OTHER DEALINGS IN THE SOFTWARE.
5312 + */
5313 +#include <dt-bindings/interrupt-controller/arm-gic.h>
5314 +#include <dt-bindings/thermal/thermal.h>
5315 +
5316 +/ {
5317 + compatible = "fsl,ls1088a";
5318 + interrupt-parent = <&gic>;
5319 + #address-cells = <2>;
5320 + #size-cells = <2>;
5321 +
5322 + aliases {
5323 + crypto = &crypto;
5324 + };
5325 +
5326 + cpus {
5327 + #address-cells = <1>;
5328 + #size-cells = <0>;
5329 +
5330 + /* We have 2 clusters having 4 Cortex-A53 cores each */
5331 + cpu0: cpu@0 {
5332 + device_type = "cpu";
5333 + compatible = "arm,cortex-a53";
5334 + reg = <0x0>;
5335 + clocks = <&clockgen 1 0>;
5336 + #cooling-cells = <2>;
5337 + cpu-idle-states = <&CPU_PH20>;
5338 + };
5339 +
5340 + cpu1: cpu@1 {
5341 + device_type = "cpu";
5342 + compatible = "arm,cortex-a53";
5343 + reg = <0x1>;
5344 + clocks = <&clockgen 1 0>;
5345 + cpu-idle-states = <&CPU_PH20>;
5346 + };
5347 +
5348 + cpu2: cpu@2 {
5349 + device_type = "cpu";
5350 + compatible = "arm,cortex-a53";
5351 + reg = <0x2>;
5352 + clocks = <&clockgen 1 0>;
5353 + cpu-idle-states = <&CPU_PH20>;
5354 + };
5355 +
5356 + cpu3: cpu@3 {
5357 + device_type = "cpu";
5358 + compatible = "arm,cortex-a53";
5359 + reg = <0x3>;
5360 + clocks = <&clockgen 1 0>;
5361 + cpu-idle-states = <&CPU_PH20>;
5362 + };
5363 +
5364 + cpu4: cpu@100 {
5365 + device_type = "cpu";
5366 + compatible = "arm,cortex-a53";
5367 + reg = <0x100>;
5368 + clocks = <&clockgen 1 1>;
5369 + #cooling-cells = <2>;
5370 + cpu-idle-states = <&CPU_PH20>;
5371 + };
5372 +
5373 + cpu5: cpu@101 {
5374 + device_type = "cpu";
5375 + compatible = "arm,cortex-a53";
5376 + reg = <0x101>;
5377 + clocks = <&clockgen 1 1>;
5378 + cpu-idle-states = <&CPU_PH20>;
5379 + };
5380 +
5381 + cpu6: cpu@102 {
5382 + device_type = "cpu";
5383 + compatible = "arm,cortex-a53";
5384 + reg = <0x102>;
5385 + clocks = <&clockgen 1 1>;
5386 + cpu-idle-states = <&CPU_PH20>;
5387 + };
5388 +
5389 + cpu7: cpu@103 {
5390 + device_type = "cpu";
5391 + compatible = "arm,cortex-a53";
5392 + reg = <0x103>;
5393 + clocks = <&clockgen 1 1>;
5394 + cpu-idle-states = <&CPU_PH20>;
5395 + };
5396 + };
5397 +
5398 + idle-states {
5399 + /*
5400 + * PSCI node is not added default, U-boot will add missing
5401 + * parts if it determines to use PSCI.
5402 + */
5403 + entry-method = "arm,psci";
5404 +
5405 + CPU_PH20: cpu-ph20 {
5406 + compatible = "arm,idle-state";
5407 + idle-state-name = "PH20";
5408 + arm,psci-suspend-param = <0x0>;
5409 + entry-latency-us = <1000>;
5410 + exit-latency-us = <1000>;
5411 + min-residency-us = <3000>;
5412 + };
5413 + };
5414 +
5415 + gic: interrupt-controller@6000000 {
5416 + compatible = "arm,gic-v3";
5417 + #interrupt-cells = <3>;
5418 + #address-cells = <2>;
5419 + #size-cells = <2>;
5420 + ranges;
5421 + interrupt-controller;
5422 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
5423 + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
5424 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
5425 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
5426 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
5427 + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
5428 +
5429 + its: gic-its@6020000 {
5430 + compatible = "arm,gic-v3-its";
5431 + msi-controller;
5432 + reg = <0x0 0x6020000 0 0x20000>;
5433 + };
5434 + };
5435 +
5436 + timer {
5437 + compatible = "arm,armv8-timer";
5438 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
5439 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
5440 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
5441 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
5442 + };
5443 +
5444 + fsl_mc: fsl-mc@80c000000 {
5445 + compatible = "fsl,qoriq-mc";
5446 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
5447 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
5448 + msi-parent = <&its>;
5449 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
5450 + #address-cells = <3>;
5451 + #size-cells = <1>;
5452 +
5453 + /*
5454 + * Region type 0x0 - MC portals
5455 + * Region type 0x1 - QBMAN portals
5456 + */
5457 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
5458 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
5459 +
5460 + dpmacs {
5461 + #address-cells = <1>;
5462 + #size-cells = <0>;
5463 +
5464 + dpmac1: dpmac@1 {
5465 + compatible = "fsl,qoriq-mc-dpmac";
5466 + reg = <1>;
5467 + };
5468 + dpmac2: dpmac@2 {
5469 + compatible = "fsl,qoriq-mc-dpmac";
5470 + reg = <2>;
5471 + };
5472 + dpmac3: dpmac@3 {
5473 + compatible = "fsl,qoriq-mc-dpmac";
5474 + reg = <3>;
5475 + };
5476 + dpmac4: dpmac@4 {
5477 + compatible = "fsl,qoriq-mc-dpmac";
5478 + reg = <4>;
5479 + };
5480 + dpmac5: dpmac@5 {
5481 + compatible = "fsl,qoriq-mc-dpmac";
5482 + reg = <5>;
5483 + };
5484 + dpmac6: dpmac@6 {
5485 + compatible = "fsl,qoriq-mc-dpmac";
5486 + reg = <6>;
5487 + };
5488 + dpmac7: dpmac@7 {
5489 + compatible = "fsl,qoriq-mc-dpmac";
5490 + reg = <7>;
5491 + };
5492 + dpmac8: dpmac@8 {
5493 + compatible = "fsl,qoriq-mc-dpmac";
5494 + reg = <8>;
5495 + };
5496 + dpmac9: dpmac@9 {
5497 + compatible = "fsl,qoriq-mc-dpmac";
5498 + reg = <9>;
5499 + };
5500 + dpmac10: dpmac@10 {
5501 + compatible = "fsl,qoriq-mc-dpmac";
5502 + reg = <0xa>;
5503 + };
5504 + };
5505 +
5506 + };
5507 +
5508 + sysclk: sysclk {
5509 + compatible = "fixed-clock";
5510 + #clock-cells = <0>;
5511 + clock-frequency = <100000000>;
5512 + clock-output-names = "sysclk";
5513 + };
5514 +
5515 + dcfg: dcfg@1e00000 {
5516 + compatible = "fsl,ls1088a-dcfg", "syscon";
5517 + reg = <0x0 0x1e00000 0x0 0x10000>;
5518 + little-endian;
5519 + };
5520 +
5521 + rstcr: syscon@1e60000 {
5522 + compatible = "fsl,ls1088a-rstcr", "syscon";
5523 + reg = <0x0 0x1e60000 0x0 0x4>;
5524 + };
5525 +
5526 + reboot {
5527 + compatible = "syscon-reboot";
5528 + regmap = <&rstcr>;
5529 + offset = <0x0>;
5530 + mask = <0x02>;
5531 + };
5532 +
5533 +
5534 + soc {
5535 + compatible = "simple-bus";
5536 + #address-cells = <2>;
5537 + #size-cells = <2>;
5538 + ranges;
5539 +
5540 + clockgen: clocking@1300000 {
5541 + compatible = "fsl,ls1088a-clockgen";
5542 + reg = <0 0x1300000 0 0xa0000>;
5543 + #clock-cells = <2>;
5544 + clocks = <&sysclk>;
5545 + };
5546 +
5547 + tmu: tmu@1f80000 {
5548 + compatible = "fsl,qoriq-tmu";
5549 + reg = <0x0 0x1f80000 0x0 0x10000>;
5550 + interrupts = <0 23 0x4>;
5551 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
5552 + fsl,tmu-calibration =
5553 + /* Calibration data group 1 */
5554 + <0x00000000 0x00000026
5555 + 0x00000001 0x0000002d
5556 + 0x00000002 0x00000032
5557 + 0x00000003 0x00000039
5558 + 0x00000004 0x0000003f
5559 + 0x00000005 0x00000046
5560 + 0x00000006 0x0000004d
5561 + 0x00000007 0x00000054
5562 + 0x00000008 0x0000005a
5563 + 0x00000009 0x00000061
5564 + 0x0000000a 0x0000006a
5565 + 0x0000000b 0x00000071
5566 + /* Calibration data group 2 */
5567 + 0x00010000 0x00000025
5568 + 0x00010001 0x0000002c
5569 + 0x00010002 0x00000035
5570 + 0x00010003 0x0000003d
5571 + 0x00010004 0x00000045
5572 + 0x00010005 0x0000004e
5573 + 0x00010006 0x00000057
5574 + 0x00010007 0x00000061
5575 + 0x00010008 0x0000006b
5576 + 0x00010009 0x00000076
5577 + /* Calibration data group 3 */
5578 + 0x00020000 0x00000029
5579 + 0x00020001 0x00000033
5580 + 0x00020002 0x0000003d
5581 + 0x00020003 0x00000049
5582 + 0x00020004 0x00000056
5583 + 0x00020005 0x00000061
5584 + 0x00020006 0x0000006d
5585 + /* Calibration data group 4 */
5586 + 0x00030000 0x00000021
5587 + 0x00030001 0x0000002a
5588 + 0x00030002 0x0000003c
5589 + 0x00030003 0x0000004e>;
5590 + little-endian;
5591 + #thermal-sensor-cells = <1>;
5592 + };
5593 +
5594 + thermal-zones {
5595 + cpu_thermal: cpu-thermal {
5596 + polling-delay-passive = <1000>;
5597 + polling-delay = <5000>;
5598 + thermal-sensors = <&tmu 0>;
5599 +
5600 + trips {
5601 + cpu_alert: cpu-alert {
5602 + temperature = <85000>;
5603 + hysteresis = <2000>;
5604 + type = "passive";
5605 + };
5606 +
5607 + cpu_crit: cpu-crit {
5608 + temperature = <95000>;
5609 + hysteresis = <2000>;
5610 + type = "critical";
5611 + };
5612 + };
5613 +
5614 + cooling-maps {
5615 + map0 {
5616 + trip = <&cpu_alert>;
5617 + cooling-device =
5618 + <&cpu0 THERMAL_NO_LIMIT
5619 + THERMAL_NO_LIMIT>;
5620 + };
5621 + map1 {
5622 + trip = <&cpu_alert>;
5623 + cooling-device =
5624 + <&cpu4 THERMAL_NO_LIMIT
5625 + THERMAL_NO_LIMIT>;
5626 + };
5627 + };
5628 + };
5629 + };
5630 +
5631 + duart0: serial@21c0500 {
5632 + compatible = "fsl,ns16550", "ns16550a";
5633 + reg = <0x0 0x21c0500 0x0 0x100>;
5634 + clocks = <&clockgen 4 3>;
5635 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5636 + status = "disabled";
5637 + };
5638 +
5639 + duart1: serial@21c0600 {
5640 + compatible = "fsl,ns16550", "ns16550a";
5641 + reg = <0x0 0x21c0600 0x0 0x100>;
5642 + clocks = <&clockgen 4 3>;
5643 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5644 + status = "disabled";
5645 + };
5646 +
5647 + cluster1_core0_watchdog: wdt@c000000 {
5648 + compatible = "arm,sp805-wdt", "arm,primecell";
5649 + reg = <0x0 0xc000000 0x0 0x1000>;
5650 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5651 + clock-names = "apb_pclk", "wdog_clk";
5652 + };
5653 +
5654 + cluster1_core1_watchdog: wdt@c010000 {
5655 + compatible = "arm,sp805-wdt", "arm,primecell";
5656 + reg = <0x0 0xc010000 0x0 0x1000>;
5657 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5658 + clock-names = "apb_pclk", "wdog_clk";
5659 + };
5660 +
5661 + cluster1_core2_watchdog: wdt@c020000 {
5662 + compatible = "arm,sp805-wdt", "arm,primecell";
5663 + reg = <0x0 0xc020000 0x0 0x1000>;
5664 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5665 + clock-names = "apb_pclk", "wdog_clk";
5666 + };
5667 +
5668 + cluster1_core3_watchdog: wdt@c030000 {
5669 + compatible = "arm,sp805-wdt", "arm,primecell";
5670 + reg = <0x0 0xc030000 0x0 0x1000>;
5671 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5672 + clock-names = "apb_pclk", "wdog_clk";
5673 + };
5674 +
5675 + cluster2_core0_watchdog: wdt@c100000 {
5676 + compatible = "arm,sp805-wdt", "arm,primecell";
5677 + reg = <0x0 0xc100000 0x0 0x1000>;
5678 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5679 + clock-names = "apb_pclk", "wdog_clk";
5680 + };
5681 +
5682 + cluster2_core1_watchdog: wdt@c110000 {
5683 + compatible = "arm,sp805-wdt", "arm,primecell";
5684 + reg = <0x0 0xc110000 0x0 0x1000>;
5685 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5686 + clock-names = "apb_pclk", "wdog_clk";
5687 + };
5688 +
5689 + cluster2_core2_watchdog: wdt@c120000 {
5690 + compatible = "arm,sp805-wdt", "arm,primecell";
5691 + reg = <0x0 0xc120000 0x0 0x1000>;
5692 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5693 + clock-names = "apb_pclk", "wdog_clk";
5694 + };
5695 +
5696 + cluster2_core3_watchdog: wdt@c130000 {
5697 + compatible = "arm,sp805-wdt", "arm,primecell";
5698 + reg = <0x0 0xc130000 0x0 0x1000>;
5699 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5700 + clock-names = "apb_pclk", "wdog_clk";
5701 + };
5702 +
5703 + gpio0: gpio@2300000 {
5704 + compatible = "fsl,qoriq-gpio";
5705 + reg = <0x0 0x2300000 0x0 0x10000>;
5706 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5707 + gpio-controller;
5708 + #gpio-cells = <2>;
5709 + interrupt-controller;
5710 + #interrupt-cells = <2>;
5711 + };
5712 +
5713 + gpio1: gpio@2310000 {
5714 + compatible = "fsl,qoriq-gpio";
5715 + reg = <0x0 0x2310000 0x0 0x10000>;
5716 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5717 + gpio-controller;
5718 + #gpio-cells = <2>;
5719 + interrupt-controller;
5720 + #interrupt-cells = <2>;
5721 + };
5722 +
5723 + gpio2: gpio@2320000 {
5724 + compatible = "fsl,qoriq-gpio";
5725 + reg = <0x0 0x2320000 0x0 0x10000>;
5726 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5727 + gpio-controller;
5728 + #gpio-cells = <2>;
5729 + interrupt-controller;
5730 + #interrupt-cells = <2>;
5731 + };
5732 +
5733 + gpio3: gpio@2330000 {
5734 + compatible = "fsl,qoriq-gpio";
5735 + reg = <0x0 0x2330000 0x0 0x10000>;
5736 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5737 + gpio-controller;
5738 + #gpio-cells = <2>;
5739 + interrupt-controller;
5740 + #interrupt-cells = <2>;
5741 + };
5742 +
5743 + /* TODO: WRIOP (CCSR?) */
5744 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
5745 + * E-MDIO1: 0x1_6000
5746 + */
5747 + compatible = "fsl,fman-memac-mdio";
5748 + reg = <0x0 0x8B96000 0x0 0x1000>;
5749 + device_type = "mdio";
5750 + little-endian; /* force the driver in LE mode */
5751 +
5752 + /* Not necessary on the QDS, but needed on the RDB */
5753 + #address-cells = <1>;
5754 + #size-cells = <0>;
5755 + };
5756 +
5757 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
5758 + * E-MDIO2: 0x1_7000
5759 + */
5760 + compatible = "fsl,fman-memac-mdio";
5761 + reg = <0x0 0x8B97000 0x0 0x1000>;
5762 + device_type = "mdio";
5763 + little-endian; /* force the driver in LE mode */
5764 +
5765 + #address-cells = <1>;
5766 + #size-cells = <0>;
5767 + };
5768 +
5769 + ifc: ifc@2240000 {
5770 + compatible = "fsl,ifc", "simple-bus";
5771 + reg = <0x0 0x2240000 0x0 0x20000>;
5772 + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
5773 + little-endian;
5774 + #address-cells = <2>;
5775 + #size-cells = <1>;
5776 +
5777 + };
5778 +
5779 + ftm0: ftm0@2800000 {
5780 + compatible = "fsl,ls1088a-ftm";
5781 + reg = <0x0 0x2800000 0x0 0x10000>,
5782 + <0x0 0x1e34050 0x0 0x4>;
5783 + interrupts = <0 44 4>;
5784 + reg-names = "ftm", "FlexTimer1";
5785 + };
5786 +
5787 + i2c0: i2c@2000000 {
5788 + compatible = "fsl,vf610-i2c";
5789 + #address-cells = <1>;
5790 + #size-cells = <0>;
5791 + reg = <0x0 0x2000000 0x0 0x10000>;
5792 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5793 + clocks = <&clockgen 4 3>;
5794 + status = "disabled";
5795 + };
5796 +
5797 + i2c1: i2c@2010000 {
5798 + compatible = "fsl,vf610-i2c";
5799 + #address-cells = <1>;
5800 + #size-cells = <0>;
5801 + reg = <0x0 0x2010000 0x0 0x10000>;
5802 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5803 + clocks = <&clockgen 4 3>;
5804 + status = "disabled";
5805 + };
5806 +
5807 + i2c2: i2c@2020000 {
5808 + compatible = "fsl,vf610-i2c";
5809 + #address-cells = <1>;
5810 + #size-cells = <0>;
5811 + reg = <0x0 0x2020000 0x0 0x10000>;
5812 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5813 + clocks = <&clockgen 4 3>;
5814 + status = "disabled";
5815 + };
5816 +
5817 + i2c3: i2c@2030000 {
5818 + compatible = "fsl,vf610-i2c";
5819 + #address-cells = <1>;
5820 + #size-cells = <0>;
5821 + reg = <0x0 0x2030000 0x0 0x10000>;
5822 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5823 + clocks = <&clockgen 4 3>;
5824 + status = "disabled";
5825 + };
5826 +
5827 + qspi: quadspi@20c0000 {
5828 + compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
5829 + #address-cells = <1>;
5830 + #size-cells = <0>;
5831 + reg = <0x0 0x20c0000 0x0 0x10000>,
5832 + <0x0 0x20000000 0x0 0x10000000>;
5833 + reg-names = "QuadSPI", "QuadSPI-memory";
5834 + interrupts = <0 25 0x4>; /* Level high type */
5835 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5836 + clock-names = "qspi_en", "qspi";
5837 + fsl,qspi-has-second-chip;
5838 + };
5839 +
5840 + esdhc: esdhc@2140000 {
5841 + compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
5842 + reg = <0x0 0x2140000 0x0 0x10000>;
5843 + interrupts = <0 28 0x4>; /* Level high type */
5844 + clock-frequency = <0>;
5845 + voltage-ranges = <1800 1800 3300 3300>;
5846 + sdhci,auto-cmd12;
5847 + little-endian;
5848 + bus-width = <4>;
5849 + status = "disabled";
5850 + };
5851 +
5852 + usb0: usb3@3100000 {
5853 + compatible = "snps,dwc3";
5854 + reg = <0x0 0x3100000 0x0 0x10000>;
5855 + interrupts = <0 80 0x4>; /* Level high type */
5856 + dr_mode = "host";
5857 + configure-gfladj;
5858 + snps,dis_rxdet_inp3_quirk;
5859 + };
5860 +
5861 + usb1: usb3@3110000 {
5862 + compatible = "snps,dwc3";
5863 + reg = <0x0 0x3110000 0x0 0x10000>;
5864 + interrupts = <0 81 0x4>; /* Level high type */
5865 + dr_mode = "host";
5866 + configure-gfladj;
5867 + snps,dis_rxdet_inp3_quirk;
5868 + };
5869 +
5870 + sata: sata@3200000 {
5871 + compatible = "fsl,ls1088a-ahci";
5872 + reg = <0x0 0x3200000 0x0 0x10000>,
5873 + <0x7 0x100520 0x0 0x4>;
5874 + reg-names = "ahci", "sata-ecc";
5875 + interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
5876 + clocks = <&clockgen 4 3>;
5877 + dma-coherent;
5878 + status = "disabled";
5879 + };
5880 +
5881 + pcie@3400000 {
5882 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5883 + "snps,dw-pcie";
5884 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
5885 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
5886 + reg-names = "regs", "config";
5887 + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5888 + interrupt-names = "aer";
5889 + #address-cells = <3>;
5890 + #size-cells = <2>;
5891 + device_type = "pci";
5892 + dma-coherent;
5893 + num-lanes = <4>;
5894 + bus-range = <0x0 0xff>;
5895 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
5896 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5897 + msi-parent = <&its>;
5898 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5899 + #interrupt-cells = <1>;
5900 + interrupt-map-mask = <0 0 0 7>;
5901 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
5902 + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
5903 + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
5904 + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
5905 + };
5906 +
5907 + pcie@3500000 {
5908 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5909 + "snps,dw-pcie";
5910 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
5911 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
5912 + reg-names = "regs", "config";
5913 + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5914 + interrupt-names = "aer";
5915 + #address-cells = <3>;
5916 + #size-cells = <2>;
5917 + device_type = "pci";
5918 + dma-coherent;
5919 + num-lanes = <4>;
5920 + bus-range = <0x0 0xff>;
5921 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
5922 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5923 + msi-parent = <&its>;
5924 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5925 + #interrupt-cells = <1>;
5926 + interrupt-map-mask = <0 0 0 7>;
5927 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
5928 + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
5929 + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
5930 + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
5931 + };
5932 +
5933 + pcie@3600000 {
5934 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5935 + "snps,dw-pcie";
5936 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
5937 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
5938 + reg-names = "regs", "config";
5939 + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5940 + interrupt-names = "aer";
5941 + #address-cells = <3>;
5942 + #size-cells = <2>;
5943 + device_type = "pci";
5944 + dma-coherent;
5945 + num-lanes = <8>;
5946 + bus-range = <0x0 0xff>;
5947 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
5948 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5949 + msi-parent = <&its>;
5950 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5951 + #interrupt-cells = <1>;
5952 + interrupt-map-mask = <0 0 0 7>;
5953 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
5954 + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
5955 + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
5956 + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
5957 + };
5958 +
5959 + smmu: iommu@5000000 {
5960 + compatible = "arm,mmu-500";
5961 + reg = <0 0x5000000 0 0x800000>;
5962 + #global-interrupts = <12>;
5963 + #iommu-cells = <1>;
5964 + stream-match-mask = <0x7C00>;
5965 + interrupts = <0 13 4>, /* global secure fault */
5966 + <0 14 4>, /* combined secure interrupt */
5967 + <0 15 4>, /* global non-secure fault */
5968 + <0 16 4>, /* combined non-secure interrupt */
5969 + /* performance counter interrupts 0-7 */
5970 + <0 211 4>,
5971 + <0 212 4>,
5972 + <0 213 4>,
5973 + <0 214 4>,
5974 + <0 215 4>,
5975 + <0 216 4>,
5976 + <0 217 4>,
5977 + <0 218 4>,
5978 + /* per context interrupt, 64 interrupts */
5979 + <0 146 4>,
5980 + <0 147 4>,
5981 + <0 148 4>,
5982 + <0 149 4>,
5983 + <0 150 4>,
5984 + <0 151 4>,
5985 + <0 152 4>,
5986 + <0 153 4>,
5987 + <0 154 4>,
5988 + <0 155 4>,
5989 + <0 156 4>,
5990 + <0 157 4>,
5991 + <0 158 4>,
5992 + <0 159 4>,
5993 + <0 160 4>,
5994 + <0 161 4>,
5995 + <0 162 4>,
5996 + <0 163 4>,
5997 + <0 164 4>,
5998 + <0 165 4>,
5999 + <0 166 4>,
6000 + <0 167 4>,
6001 + <0 168 4>,
6002 + <0 169 4>,
6003 + <0 170 4>,
6004 + <0 171 4>,
6005 + <0 172 4>,
6006 + <0 173 4>,
6007 + <0 174 4>,
6008 + <0 175 4>,
6009 + <0 176 4>,
6010 + <0 177 4>,
6011 + <0 178 4>,
6012 + <0 179 4>,
6013 + <0 180 4>,
6014 + <0 181 4>,
6015 + <0 182 4>,
6016 + <0 183 4>,
6017 + <0 184 4>,
6018 + <0 185 4>,
6019 + <0 186 4>,
6020 + <0 187 4>,
6021 + <0 188 4>,
6022 + <0 189 4>,
6023 + <0 190 4>,
6024 + <0 191 4>,
6025 + <0 192 4>,
6026 + <0 193 4>,
6027 + <0 194 4>,
6028 + <0 195 4>,
6029 + <0 196 4>,
6030 + <0 197 4>,
6031 + <0 198 4>,
6032 + <0 199 4>,
6033 + <0 200 4>,
6034 + <0 201 4>,
6035 + <0 202 4>,
6036 + <0 203 4>,
6037 + <0 204 4>,
6038 + <0 205 4>,
6039 + <0 206 4>,
6040 + <0 207 4>,
6041 + <0 208 4>,
6042 + <0 209 4>;
6043 + };
6044 +
6045 + crypto: crypto@8000000 {
6046 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
6047 + fsl,sec-era = <8>;
6048 + #address-cells = <1>;
6049 + #size-cells = <1>;
6050 + ranges = <0x0 0x00 0x8000000 0x100000>;
6051 + reg = <0x00 0x8000000 0x0 0x100000>;
6052 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
6053 + dma-coherent;
6054 +
6055 + sec_jr0: jr@10000 {
6056 + compatible = "fsl,sec-v5.0-job-ring",
6057 + "fsl,sec-v4.0-job-ring";
6058 + reg = <0x10000 0x10000>;
6059 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
6060 + };
6061 +
6062 + sec_jr1: jr@20000 {
6063 + compatible = "fsl,sec-v5.0-job-ring",
6064 + "fsl,sec-v4.0-job-ring";
6065 + reg = <0x20000 0x10000>;
6066 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
6067 + };
6068 +
6069 + sec_jr2: jr@30000 {
6070 + compatible = "fsl,sec-v5.0-job-ring",
6071 + "fsl,sec-v4.0-job-ring";
6072 + reg = <0x30000 0x10000>;
6073 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
6074 + };
6075 +
6076 + sec_jr3: jr@40000 {
6077 + compatible = "fsl,sec-v5.0-job-ring",
6078 + "fsl,sec-v4.0-job-ring";
6079 + reg = <0x40000 0x10000>;
6080 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
6081 + };
6082 + };
6083 + };
6084 +
6085 +};
6086 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
6087 index b0dd0109..ba1a79dd 100644
6088 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
6089 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
6090 @@ -1,8 +1,10 @@
6091 /*
6092 * Device Tree file for Freescale LS2080a QDS Board.
6093 *
6094 - * Copyright (C) 2015, Freescale Semiconductor
6095 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
6096 + * Copyright 2017 NXP
6097 *
6098 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6099 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6100 *
6101 * This file is dual-licensed: you can use it either under the terms
6102 @@ -46,169 +48,76 @@
6103
6104 /dts-v1/;
6105
6106 -/include/ "fsl-ls2080a.dtsi"
6107 +#include "fsl-ls2080a.dtsi"
6108 +#include "fsl-ls208xa-qds.dtsi"
6109
6110 / {
6111 model = "Freescale Layerscape 2080a QDS Board";
6112 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
6113
6114 - aliases {
6115 - serial0 = &serial0;
6116 - serial1 = &serial1;
6117 - };
6118 -
6119 chosen {
6120 stdout-path = "serial0:115200n8";
6121 };
6122 };
6123
6124 -&esdhc {
6125 - status = "okay";
6126 -};
6127 -
6128 &ifc {
6129 - status = "okay";
6130 - #address-cells = <2>;
6131 - #size-cells = <1>;
6132 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6133 - 0x2 0x0 0x5 0x30000000 0x00010000
6134 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6135 -
6136 - nor@0,0 {
6137 + boardctrl: board-control@3,0 {
6138 #address-cells = <1>;
6139 #size-cells = <1>;
6140 - compatible = "cfi-flash";
6141 - reg = <0x0 0x0 0x8000000>;
6142 - bank-width = <2>;
6143 - device-width = <1>;
6144 - };
6145 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
6146 + reg = <3 0 0x300>; /* TODO check address */
6147 + ranges = <0 3 0 0x300>;
6148
6149 - nand@2,0 {
6150 - compatible = "fsl,ifc-nand";
6151 - reg = <0x2 0x0 0x10000>;
6152 - };
6153 + mdio_mux_emi1 {
6154 + compatible = "mdio-mux-mmioreg", "mdio-mux";
6155 + mdio-parent-bus = <&emdio1>;
6156 + reg = <0x54 1>; /* BRDCFG4 */
6157 + mux-mask = <0xe0>; /* EMI1_MDIO */
6158
6159 - cpld@3,0 {
6160 - reg = <0x3 0x0 0x10000>;
6161 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6162 - };
6163 -};
6164 -
6165 -&i2c0 {
6166 - status = "okay";
6167 - pca9547@77 {
6168 - compatible = "nxp,pca9547";
6169 - reg = <0x77>;
6170 - #address-cells = <1>;
6171 - #size-cells = <0>;
6172 - i2c@0 {
6173 - #address-cells = <1>;
6174 + #address-cells=<1>;
6175 #size-cells = <0>;
6176 - reg = <0x00>;
6177 - rtc@68 {
6178 - compatible = "dallas,ds3232";
6179 - reg = <0x68>;
6180 - };
6181 - };
6182
6183 - i2c@2 {
6184 - #address-cells = <1>;
6185 - #size-cells = <0>;
6186 - reg = <0x02>;
6187 -
6188 - ina220@40 {
6189 - compatible = "ti,ina220";
6190 - reg = <0x40>;
6191 - shunt-resistor = <500>;
6192 - };
6193 -
6194 - ina220@41 {
6195 - compatible = "ti,ina220";
6196 - reg = <0x41>;
6197 - shunt-resistor = <1000>;
6198 - };
6199 - };
6200 -
6201 - i2c@3 {
6202 - #address-cells = <1>;
6203 - #size-cells = <0>;
6204 - reg = <0x3>;
6205 -
6206 - adt7481@4c {
6207 - compatible = "adi,adt7461";
6208 - reg = <0x4c>;
6209 + /* Child MDIO buses, one for each riser card:
6210 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
6211 + * VSC8234 PHYs on the riser cards.
6212 + */
6213 +
6214 + mdio_mux3: mdio@60 {
6215 + reg = <0x60>;
6216 + #address-cells = <1>;
6217 + #size-cells = <0>;
6218 +
6219 + mdio0_phy12: mdio_phy0@1c {
6220 + reg = <0x1c>;
6221 + phy-connection-type = "sgmii";
6222 + };
6223 + mdio0_phy13: mdio_phy1@1d {
6224 + reg = <0x1d>;
6225 + phy-connection-type = "sgmii";
6226 + };
6227 + mdio0_phy14: mdio_phy2@1e {
6228 + reg = <0x1e>;
6229 + phy-connection-type = "sgmii";
6230 + };
6231 + mdio0_phy15: mdio_phy3@1f {
6232 + reg = <0x1f>;
6233 + phy-connection-type = "sgmii";
6234 + };
6235 };
6236 };
6237 };
6238 };
6239
6240 -&i2c1 {
6241 - status = "disabled";
6242 -};
6243 -
6244 -&i2c2 {
6245 - status = "disabled";
6246 -};
6247 -
6248 -&i2c3 {
6249 - status = "disabled";
6250 -};
6251 -
6252 -&dspi {
6253 - status = "okay";
6254 - dflash0: n25q128a {
6255 - #address-cells = <1>;
6256 - #size-cells = <1>;
6257 - compatible = "st,m25p80";
6258 - spi-max-frequency = <3000000>;
6259 - reg = <0>;
6260 - };
6261 - dflash1: sst25wf040b {
6262 - #address-cells = <1>;
6263 - #size-cells = <1>;
6264 - compatible = "st,m25p80";
6265 - spi-max-frequency = <3000000>;
6266 - reg = <1>;
6267 - };
6268 - dflash2: en25s64 {
6269 - #address-cells = <1>;
6270 - #size-cells = <1>;
6271 - compatible = "st,m25p80";
6272 - spi-max-frequency = <3000000>;
6273 - reg = <2>;
6274 - };
6275 -};
6276 -
6277 -&qspi {
6278 - status = "okay";
6279 - flash0: s25fl256s1@0 {
6280 - #address-cells = <1>;
6281 - #size-cells = <1>;
6282 - compatible = "st,m25p80";
6283 - spi-max-frequency = <20000000>;
6284 - reg = <0>;
6285 - };
6286 - flash2: s25fl256s1@2 {
6287 - #address-cells = <1>;
6288 - #size-cells = <1>;
6289 - compatible = "st,m25p80";
6290 - spi-max-frequency = <20000000>;
6291 - reg = <0>;
6292 - };
6293 -};
6294 -
6295 -&sata0 {
6296 - status = "okay";
6297 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
6298 +&dpmac9 {
6299 + phy-handle = <&mdio0_phy12>;
6300 };
6301 -
6302 -&sata1 {
6303 - status = "okay";
6304 +&dpmac10 {
6305 + phy-handle = <&mdio0_phy13>;
6306 };
6307 -
6308 -&usb0 {
6309 - status = "okay";
6310 +&dpmac11 {
6311 + phy-handle = <&mdio0_phy14>;
6312 };
6313 -
6314 -&usb1 {
6315 - status = "okay";
6316 +&dpmac12 {
6317 + phy-handle = <&mdio0_phy15>;
6318 };
6319 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6320 index ad0ebb8a..025f0f54 100644
6321 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6322 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6323 @@ -1,8 +1,10 @@
6324 /*
6325 * Device Tree file for Freescale LS2080a RDB Board.
6326 *
6327 - * Copyright (C) 2015, Freescale Semiconductor
6328 + * Copyright 2016 Freescale Semiconductor, Inc.
6329 + * Copyright 2017 NXP
6330 *
6331 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6332 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6333 *
6334 * This file is dual-licensed: you can use it either under the terms
6335 @@ -46,125 +48,94 @@
6336
6337 /dts-v1/;
6338
6339 -/include/ "fsl-ls2080a.dtsi"
6340 +#include "fsl-ls2080a.dtsi"
6341 +#include "fsl-ls208xa-rdb.dtsi"
6342
6343 / {
6344 model = "Freescale Layerscape 2080a RDB Board";
6345 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
6346
6347 - aliases {
6348 - serial0 = &serial0;
6349 - serial1 = &serial1;
6350 - };
6351 -
6352 chosen {
6353 stdout-path = "serial1:115200n8";
6354 };
6355 };
6356
6357 -&esdhc {
6358 - status = "okay";
6359 -};
6360 -
6361 -&ifc {
6362 - status = "okay";
6363 - #address-cells = <2>;
6364 - #size-cells = <1>;
6365 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6366 - 0x2 0x0 0x5 0x30000000 0x00010000
6367 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6368 -
6369 - nor@0,0 {
6370 - #address-cells = <1>;
6371 - #size-cells = <1>;
6372 - compatible = "cfi-flash";
6373 - reg = <0x0 0x0 0x8000000>;
6374 - bank-width = <2>;
6375 - device-width = <1>;
6376 +&emdio1 {
6377 + status = "disabled";
6378 + /* CS4340 PHYs */
6379 + mdio1_phy1: emdio1_phy@1 {
6380 + reg = <0x10>;
6381 + phy-connection-type = "xfi";
6382 };
6383 -
6384 - nand@2,0 {
6385 - compatible = "fsl,ifc-nand";
6386 - reg = <0x2 0x0 0x10000>;
6387 + mdio1_phy2: emdio1_phy@2 {
6388 + reg = <0x11>;
6389 + phy-connection-type = "xfi";
6390 };
6391 -
6392 - cpld@3,0 {
6393 - reg = <0x3 0x0 0x10000>;
6394 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6395 + mdio1_phy3: emdio1_phy@3 {
6396 + reg = <0x12>;
6397 + phy-connection-type = "xfi";
6398 };
6399 -
6400 -};
6401 -
6402 -&i2c0 {
6403 - status = "okay";
6404 - pca9547@75 {
6405 - compatible = "nxp,pca9547";
6406 - reg = <0x75>;
6407 - #address-cells = <1>;
6408 - #size-cells = <0>;
6409 - status = "disabled";
6410 - i2c@1 {
6411 - #address-cells = <1>;
6412 - #size-cells = <0>;
6413 - reg = <0x01>;
6414 - rtc@68 {
6415 - compatible = "dallas,ds3232";
6416 - reg = <0x68>;
6417 - };
6418 - };
6419 -
6420 - i2c@3 {
6421 - #address-cells = <1>;
6422 - #size-cells = <0>;
6423 - reg = <0x3>;
6424 -
6425 - adt7481@4c {
6426 - compatible = "adi,adt7461";
6427 - reg = <0x4c>;
6428 - };
6429 - };
6430 + mdio1_phy4: emdio1_phy@4 {
6431 + reg = <0x13>;
6432 + phy-connection-type = "xfi";
6433 };
6434 };
6435
6436 -&i2c1 {
6437 - status = "disabled";
6438 -};
6439 -
6440 -&i2c2 {
6441 - status = "disabled";
6442 -};
6443 -
6444 -&i2c3 {
6445 - status = "disabled";
6446 -};
6447 -
6448 -&dspi {
6449 - status = "okay";
6450 - dflash0: n25q512a {
6451 - #address-cells = <1>;
6452 - #size-cells = <1>;
6453 - compatible = "st,m25p80";
6454 - spi-max-frequency = <3000000>;
6455 - reg = <0>;
6456 +&emdio2 {
6457 + /* AQR405 PHYs */
6458 + mdio2_phy1: emdio2_phy@1 {
6459 + compatible = "ethernet-phy-ieee802.3-c45";
6460 + interrupts = <0 1 0x4>; /* Level high type */
6461 + reg = <0x0>;
6462 + phy-connection-type = "xfi";
6463 + };
6464 + mdio2_phy2: emdio2_phy@2 {
6465 + compatible = "ethernet-phy-ieee802.3-c45";
6466 + interrupts = <0 2 0x4>; /* Level high type */
6467 + reg = <0x1>;
6468 + phy-connection-type = "xfi";
6469 + };
6470 + mdio2_phy3: emdio2_phy@3 {
6471 + compatible = "ethernet-phy-ieee802.3-c45";
6472 + interrupts = <0 4 0x4>; /* Level high type */
6473 + reg = <0x2>;
6474 + phy-connection-type = "xfi";
6475 + };
6476 + mdio2_phy4: emdio2_phy@4 {
6477 + compatible = "ethernet-phy-ieee802.3-c45";
6478 + interrupts = <0 5 0x4>; /* Level high type */
6479 + reg = <0x3>;
6480 + phy-connection-type = "xfi";
6481 };
6482 };
6483
6484 -&qspi {
6485 - status = "disabled";
6486 -};
6487 +/* Update DPMAC connections to external PHYs, under the assumption of
6488 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
6489 + */
6490 +/* Leave Cortina nodes commented out until driver is integrated
6491 + *&dpmac1 {
6492 + * phy-handle = <&mdio1_phy1>;
6493 + *};
6494 + *&dpmac2 {
6495 + * phy-handle = <&mdio1_phy2>;
6496 + *};
6497 + *&dpmac3 {
6498 + * phy-handle = <&mdio1_phy3>;
6499 + *};
6500 + *&dpmac4 {
6501 + * phy-handle = <&mdio1_phy4>;
6502 + *};
6503 + */
6504
6505 -&sata0 {
6506 - status = "okay";
6507 +&dpmac5 {
6508 + phy-handle = <&mdio2_phy1>;
6509 };
6510 -
6511 -&sata1 {
6512 - status = "okay";
6513 +&dpmac6 {
6514 + phy-handle = <&mdio2_phy2>;
6515 };
6516 -
6517 -&usb0 {
6518 - status = "okay";
6519 +&dpmac7 {
6520 + phy-handle = <&mdio2_phy3>;
6521 };
6522 -
6523 -&usb1 {
6524 - status = "okay";
6525 +&dpmac8 {
6526 + phy-handle = <&mdio2_phy4>;
6527 };
6528 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6529 index 505d0380..fbbb73e5 100644
6530 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6531 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6532 @@ -1,7 +1,7 @@
6533 /*
6534 * Device Tree file for Freescale LS2080a software Simulator model
6535 *
6536 - * Copyright (C) 2014-2015, Freescale Semiconductor
6537 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
6538 *
6539 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6540 *
6541 @@ -46,17 +46,12 @@
6542
6543 /dts-v1/;
6544
6545 -/include/ "fsl-ls2080a.dtsi"
6546 +#include "fsl-ls2080a.dtsi"
6547
6548 / {
6549 model = "Freescale Layerscape 2080a software Simulator model";
6550 compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
6551
6552 - aliases {
6553 - serial0 = &serial0;
6554 - serial1 = &serial1;
6555 - };
6556 -
6557 ethernet@2210000 {
6558 compatible = "smsc,lan91c111";
6559 reg = <0x0 0x2210000 0x0 0x100>;
6560 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6561 index 7f0dc13b..71f15fab 100644
6562 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6563 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6564 @@ -1,8 +1,9 @@
6565 /*
6566 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6567 *
6568 - * Copyright (C) 2014-2015, Freescale Semiconductor
6569 + * Copyright 2014-2016 Freescale Semiconductor, Inc.
6570 *
6571 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6572 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6573 *
6574 * This file is dual-licensed: you can use it either under the terms
6575 @@ -44,696 +45,132 @@
6576 * OTHER DEALINGS IN THE SOFTWARE.
6577 */
6578
6579 -/ {
6580 - compatible = "fsl,ls2080a";
6581 - interrupt-parent = <&gic>;
6582 - #address-cells = <2>;
6583 - #size-cells = <2>;
6584 +#include "fsl-ls208xa.dtsi"
6585
6586 - cpus {
6587 - #address-cells = <1>;
6588 - #size-cells = <0>;
6589 -
6590 - /*
6591 - * We expect the enable-method for cpu's to be "psci", but this
6592 - * is dependent on the SoC FW, which will fill this in.
6593 - *
6594 - * Currently supported enable-method is psci v0.2
6595 - */
6596 -
6597 - /* We have 4 clusters having 2 Cortex-A57 cores each */
6598 - cpu@0 {
6599 - device_type = "cpu";
6600 - compatible = "arm,cortex-a57";
6601 - reg = <0x0>;
6602 - clocks = <&clockgen 1 0>;
6603 - next-level-cache = <&cluster0_l2>;
6604 - };
6605 -
6606 - cpu@1 {
6607 - device_type = "cpu";
6608 - compatible = "arm,cortex-a57";
6609 - reg = <0x1>;
6610 - clocks = <&clockgen 1 0>;
6611 - next-level-cache = <&cluster0_l2>;
6612 - };
6613 -
6614 - cpu@100 {
6615 - device_type = "cpu";
6616 - compatible = "arm,cortex-a57";
6617 - reg = <0x100>;
6618 - clocks = <&clockgen 1 1>;
6619 - next-level-cache = <&cluster1_l2>;
6620 - };
6621 -
6622 - cpu@101 {
6623 - device_type = "cpu";
6624 - compatible = "arm,cortex-a57";
6625 - reg = <0x101>;
6626 - clocks = <&clockgen 1 1>;
6627 - next-level-cache = <&cluster1_l2>;
6628 - };
6629 -
6630 - cpu@200 {
6631 - device_type = "cpu";
6632 - compatible = "arm,cortex-a57";
6633 - reg = <0x200>;
6634 - clocks = <&clockgen 1 2>;
6635 - next-level-cache = <&cluster2_l2>;
6636 - };
6637 -
6638 - cpu@201 {
6639 - device_type = "cpu";
6640 - compatible = "arm,cortex-a57";
6641 - reg = <0x201>;
6642 - clocks = <&clockgen 1 2>;
6643 - next-level-cache = <&cluster2_l2>;
6644 - };
6645 -
6646 - cpu@300 {
6647 - device_type = "cpu";
6648 - compatible = "arm,cortex-a57";
6649 - reg = <0x300>;
6650 - clocks = <&clockgen 1 3>;
6651 - next-level-cache = <&cluster3_l2>;
6652 - };
6653 -
6654 - cpu@301 {
6655 - device_type = "cpu";
6656 - compatible = "arm,cortex-a57";
6657 - reg = <0x301>;
6658 - clocks = <&clockgen 1 3>;
6659 - next-level-cache = <&cluster3_l2>;
6660 - };
6661 -
6662 - cluster0_l2: l2-cache0 {
6663 - compatible = "cache";
6664 - };
6665 -
6666 - cluster1_l2: l2-cache1 {
6667 - compatible = "cache";
6668 - };
6669 -
6670 - cluster2_l2: l2-cache2 {
6671 - compatible = "cache";
6672 - };
6673 -
6674 - cluster3_l2: l2-cache3 {
6675 - compatible = "cache";
6676 - };
6677 +&cpu {
6678 + cpu0: cpu@0 {
6679 + device_type = "cpu";
6680 + compatible = "arm,cortex-a57";
6681 + reg = <0x0>;
6682 + clocks = <&clockgen 1 0>;
6683 + next-level-cache = <&cluster0_l2>;
6684 + #cooling-cells = <2>;
6685 };
6686
6687 - memory@80000000 {
6688 - device_type = "memory";
6689 - reg = <0x00000000 0x80000000 0 0x80000000>;
6690 - /* DRAM space - 1, size : 2 GB DRAM */
6691 + cpu1: cpu@1 {
6692 + device_type = "cpu";
6693 + compatible = "arm,cortex-a57";
6694 + reg = <0x1>;
6695 + clocks = <&clockgen 1 0>;
6696 + next-level-cache = <&cluster0_l2>;
6697 };
6698
6699 - sysclk: sysclk {
6700 - compatible = "fixed-clock";
6701 - #clock-cells = <0>;
6702 - clock-frequency = <100000000>;
6703 - clock-output-names = "sysclk";
6704 + cpu2: cpu@100 {
6705 + device_type = "cpu";
6706 + compatible = "arm,cortex-a57";
6707 + reg = <0x100>;
6708 + clocks = <&clockgen 1 1>;
6709 + next-level-cache = <&cluster1_l2>;
6710 + #cooling-cells = <2>;
6711 };
6712
6713 - gic: interrupt-controller@6000000 {
6714 - compatible = "arm,gic-v3";
6715 - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
6716 - <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
6717 - <0x0 0x0c0c0000 0 0x2000>, /* GICC */
6718 - <0x0 0x0c0d0000 0 0x1000>, /* GICH */
6719 - <0x0 0x0c0e0000 0 0x20000>; /* GICV */
6720 - #interrupt-cells = <3>;
6721 - #address-cells = <2>;
6722 - #size-cells = <2>;
6723 - ranges;
6724 - interrupt-controller;
6725 - interrupts = <1 9 0x4>;
6726 -
6727 - its: gic-its@6020000 {
6728 - compatible = "arm,gic-v3-its";
6729 - msi-controller;
6730 - reg = <0x0 0x6020000 0 0x20000>;
6731 - };
6732 + cpu3: cpu@101 {
6733 + device_type = "cpu";
6734 + compatible = "arm,cortex-a57";
6735 + reg = <0x101>;
6736 + clocks = <&clockgen 1 1>;
6737 + next-level-cache = <&cluster1_l2>;
6738 };
6739
6740 - rstcr: syscon@1e60000 {
6741 - compatible = "fsl,ls2080a-rstcr", "syscon";
6742 - reg = <0x0 0x1e60000 0x0 0x4>;
6743 + cpu4: cpu@200 {
6744 + device_type = "cpu";
6745 + compatible = "arm,cortex-a57";
6746 + reg = <0x200>;
6747 + clocks = <&clockgen 1 2>;
6748 + next-level-cache = <&cluster2_l2>;
6749 + #cooling-cells = <2>;
6750 };
6751
6752 - reboot {
6753 - compatible ="syscon-reboot";
6754 - regmap = <&rstcr>;
6755 - offset = <0x0>;
6756 - mask = <0x2>;
6757 + cpu5: cpu@201 {
6758 + device_type = "cpu";
6759 + compatible = "arm,cortex-a57";
6760 + reg = <0x201>;
6761 + clocks = <&clockgen 1 2>;
6762 + next-level-cache = <&cluster2_l2>;
6763 };
6764
6765 - timer {
6766 - compatible = "arm,armv8-timer";
6767 - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
6768 - <1 14 4>, /* Physical Non-Secure PPI, active-low */
6769 - <1 11 4>, /* Virtual PPI, active-low */
6770 - <1 10 4>; /* Hypervisor PPI, active-low */
6771 - fsl,erratum-a008585;
6772 + cpu6: cpu@300 {
6773 + device_type = "cpu";
6774 + compatible = "arm,cortex-a57";
6775 + reg = <0x300>;
6776 + clocks = <&clockgen 1 3>;
6777 + next-level-cache = <&cluster3_l2>;
6778 + #cooling-cells = <2>;
6779 };
6780
6781 - pmu {
6782 - compatible = "arm,armv8-pmuv3";
6783 - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
6784 + cpu7: cpu@301 {
6785 + device_type = "cpu";
6786 + compatible = "arm,cortex-a57";
6787 + reg = <0x301>;
6788 + clocks = <&clockgen 1 3>;
6789 + next-level-cache = <&cluster3_l2>;
6790 };
6791
6792 - soc {
6793 - compatible = "simple-bus";
6794 - #address-cells = <2>;
6795 - #size-cells = <2>;
6796 - ranges;
6797 -
6798 - clockgen: clocking@1300000 {
6799 - compatible = "fsl,ls2080a-clockgen";
6800 - reg = <0 0x1300000 0 0xa0000>;
6801 - #clock-cells = <2>;
6802 - clocks = <&sysclk>;
6803 - };
6804 -
6805 - serial0: serial@21c0500 {
6806 - compatible = "fsl,ns16550", "ns16550a";
6807 - reg = <0x0 0x21c0500 0x0 0x100>;
6808 - clocks = <&clockgen 4 3>;
6809 - interrupts = <0 32 0x4>; /* Level high type */
6810 - };
6811 -
6812 - serial1: serial@21c0600 {
6813 - compatible = "fsl,ns16550", "ns16550a";
6814 - reg = <0x0 0x21c0600 0x0 0x100>;
6815 - clocks = <&clockgen 4 3>;
6816 - interrupts = <0 32 0x4>; /* Level high type */
6817 - };
6818 -
6819 - cluster1_core0_watchdog: wdt@c000000 {
6820 - compatible = "arm,sp805-wdt", "arm,primecell";
6821 - reg = <0x0 0xc000000 0x0 0x1000>;
6822 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6823 - clock-names = "apb_pclk", "wdog_clk";
6824 - };
6825 -
6826 - cluster1_core1_watchdog: wdt@c010000 {
6827 - compatible = "arm,sp805-wdt", "arm,primecell";
6828 - reg = <0x0 0xc010000 0x0 0x1000>;
6829 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6830 - clock-names = "apb_pclk", "wdog_clk";
6831 - };
6832 -
6833 - cluster2_core0_watchdog: wdt@c100000 {
6834 - compatible = "arm,sp805-wdt", "arm,primecell";
6835 - reg = <0x0 0xc100000 0x0 0x1000>;
6836 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6837 - clock-names = "apb_pclk", "wdog_clk";
6838 - };
6839 -
6840 - cluster2_core1_watchdog: wdt@c110000 {
6841 - compatible = "arm,sp805-wdt", "arm,primecell";
6842 - reg = <0x0 0xc110000 0x0 0x1000>;
6843 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6844 - clock-names = "apb_pclk", "wdog_clk";
6845 - };
6846 -
6847 - cluster3_core0_watchdog: wdt@c200000 {
6848 - compatible = "arm,sp805-wdt", "arm,primecell";
6849 - reg = <0x0 0xc200000 0x0 0x1000>;
6850 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6851 - clock-names = "apb_pclk", "wdog_clk";
6852 - };
6853 -
6854 - cluster3_core1_watchdog: wdt@c210000 {
6855 - compatible = "arm,sp805-wdt", "arm,primecell";
6856 - reg = <0x0 0xc210000 0x0 0x1000>;
6857 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6858 - clock-names = "apb_pclk", "wdog_clk";
6859 - };
6860 -
6861 - cluster4_core0_watchdog: wdt@c300000 {
6862 - compatible = "arm,sp805-wdt", "arm,primecell";
6863 - reg = <0x0 0xc300000 0x0 0x1000>;
6864 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6865 - clock-names = "apb_pclk", "wdog_clk";
6866 - };
6867 -
6868 - cluster4_core1_watchdog: wdt@c310000 {
6869 - compatible = "arm,sp805-wdt", "arm,primecell";
6870 - reg = <0x0 0xc310000 0x0 0x1000>;
6871 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6872 - clock-names = "apb_pclk", "wdog_clk";
6873 - };
6874 -
6875 - fsl_mc: fsl-mc@80c000000 {
6876 - compatible = "fsl,qoriq-mc";
6877 - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
6878 - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
6879 - msi-parent = <&its>;
6880 - #address-cells = <3>;
6881 - #size-cells = <1>;
6882 -
6883 - /*
6884 - * Region type 0x0 - MC portals
6885 - * Region type 0x1 - QBMAN portals
6886 - */
6887 - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
6888 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
6889 -
6890 - /*
6891 - * Define the maximum number of MACs present on the SoC.
6892 - */
6893 - dpmacs {
6894 - #address-cells = <1>;
6895 - #size-cells = <0>;
6896 -
6897 - dpmac1: dpmac@1 {
6898 - compatible = "fsl,qoriq-mc-dpmac";
6899 - reg = <0x1>;
6900 - };
6901 -
6902 - dpmac2: dpmac@2 {
6903 - compatible = "fsl,qoriq-mc-dpmac";
6904 - reg = <0x2>;
6905 - };
6906 -
6907 - dpmac3: dpmac@3 {
6908 - compatible = "fsl,qoriq-mc-dpmac";
6909 - reg = <0x3>;
6910 - };
6911 -
6912 - dpmac4: dpmac@4 {
6913 - compatible = "fsl,qoriq-mc-dpmac";
6914 - reg = <0x4>;
6915 - };
6916 -
6917 - dpmac5: dpmac@5 {
6918 - compatible = "fsl,qoriq-mc-dpmac";
6919 - reg = <0x5>;
6920 - };
6921 -
6922 - dpmac6: dpmac@6 {
6923 - compatible = "fsl,qoriq-mc-dpmac";
6924 - reg = <0x6>;
6925 - };
6926 -
6927 - dpmac7: dpmac@7 {
6928 - compatible = "fsl,qoriq-mc-dpmac";
6929 - reg = <0x7>;
6930 - };
6931 -
6932 - dpmac8: dpmac@8 {
6933 - compatible = "fsl,qoriq-mc-dpmac";
6934 - reg = <0x8>;
6935 - };
6936 -
6937 - dpmac9: dpmac@9 {
6938 - compatible = "fsl,qoriq-mc-dpmac";
6939 - reg = <0x9>;
6940 - };
6941 -
6942 - dpmac10: dpmac@a {
6943 - compatible = "fsl,qoriq-mc-dpmac";
6944 - reg = <0xa>;
6945 - };
6946 -
6947 - dpmac11: dpmac@b {
6948 - compatible = "fsl,qoriq-mc-dpmac";
6949 - reg = <0xb>;
6950 - };
6951 -
6952 - dpmac12: dpmac@c {
6953 - compatible = "fsl,qoriq-mc-dpmac";
6954 - reg = <0xc>;
6955 - };
6956 -
6957 - dpmac13: dpmac@d {
6958 - compatible = "fsl,qoriq-mc-dpmac";
6959 - reg = <0xd>;
6960 - };
6961 -
6962 - dpmac14: dpmac@e {
6963 - compatible = "fsl,qoriq-mc-dpmac";
6964 - reg = <0xe>;
6965 - };
6966 -
6967 - dpmac15: dpmac@f {
6968 - compatible = "fsl,qoriq-mc-dpmac";
6969 - reg = <0xf>;
6970 - };
6971 -
6972 - dpmac16: dpmac@10 {
6973 - compatible = "fsl,qoriq-mc-dpmac";
6974 - reg = <0x10>;
6975 - };
6976 - };
6977 - };
6978 -
6979 - smmu: iommu@5000000 {
6980 - compatible = "arm,mmu-500";
6981 - reg = <0 0x5000000 0 0x800000>;
6982 - #global-interrupts = <12>;
6983 - interrupts = <0 13 4>, /* global secure fault */
6984 - <0 14 4>, /* combined secure interrupt */
6985 - <0 15 4>, /* global non-secure fault */
6986 - <0 16 4>, /* combined non-secure interrupt */
6987 - /* performance counter interrupts 0-7 */
6988 - <0 211 4>, <0 212 4>,
6989 - <0 213 4>, <0 214 4>,
6990 - <0 215 4>, <0 216 4>,
6991 - <0 217 4>, <0 218 4>,
6992 - /* per context interrupt, 64 interrupts */
6993 - <0 146 4>, <0 147 4>,
6994 - <0 148 4>, <0 149 4>,
6995 - <0 150 4>, <0 151 4>,
6996 - <0 152 4>, <0 153 4>,
6997 - <0 154 4>, <0 155 4>,
6998 - <0 156 4>, <0 157 4>,
6999 - <0 158 4>, <0 159 4>,
7000 - <0 160 4>, <0 161 4>,
7001 - <0 162 4>, <0 163 4>,
7002 - <0 164 4>, <0 165 4>,
7003 - <0 166 4>, <0 167 4>,
7004 - <0 168 4>, <0 169 4>,
7005 - <0 170 4>, <0 171 4>,
7006 - <0 172 4>, <0 173 4>,
7007 - <0 174 4>, <0 175 4>,
7008 - <0 176 4>, <0 177 4>,
7009 - <0 178 4>, <0 179 4>,
7010 - <0 180 4>, <0 181 4>,
7011 - <0 182 4>, <0 183 4>,
7012 - <0 184 4>, <0 185 4>,
7013 - <0 186 4>, <0 187 4>,
7014 - <0 188 4>, <0 189 4>,
7015 - <0 190 4>, <0 191 4>,
7016 - <0 192 4>, <0 193 4>,
7017 - <0 194 4>, <0 195 4>,
7018 - <0 196 4>, <0 197 4>,
7019 - <0 198 4>, <0 199 4>,
7020 - <0 200 4>, <0 201 4>,
7021 - <0 202 4>, <0 203 4>,
7022 - <0 204 4>, <0 205 4>,
7023 - <0 206 4>, <0 207 4>,
7024 - <0 208 4>, <0 209 4>;
7025 - mmu-masters = <&fsl_mc 0x300 0>;
7026 - };
7027 -
7028 - dspi: dspi@2100000 {
7029 - status = "disabled";
7030 - compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
7031 - #address-cells = <1>;
7032 - #size-cells = <0>;
7033 - reg = <0x0 0x2100000 0x0 0x10000>;
7034 - interrupts = <0 26 0x4>; /* Level high type */
7035 - clocks = <&clockgen 4 3>;
7036 - clock-names = "dspi";
7037 - spi-num-chipselects = <5>;
7038 - bus-num = <0>;
7039 - };
7040 -
7041 - esdhc: esdhc@2140000 {
7042 - status = "disabled";
7043 - compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
7044 - reg = <0x0 0x2140000 0x0 0x10000>;
7045 - interrupts = <0 28 0x4>; /* Level high type */
7046 - clock-frequency = <0>; /* Updated by bootloader */
7047 - voltage-ranges = <1800 1800 3300 3300>;
7048 - sdhci,auto-cmd12;
7049 - little-endian;
7050 - bus-width = <4>;
7051 - };
7052 -
7053 - gpio0: gpio@2300000 {
7054 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7055 - reg = <0x0 0x2300000 0x0 0x10000>;
7056 - interrupts = <0 36 0x4>; /* Level high type */
7057 - gpio-controller;
7058 - little-endian;
7059 - #gpio-cells = <2>;
7060 - interrupt-controller;
7061 - #interrupt-cells = <2>;
7062 - };
7063 -
7064 - gpio1: gpio@2310000 {
7065 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7066 - reg = <0x0 0x2310000 0x0 0x10000>;
7067 - interrupts = <0 36 0x4>; /* Level high type */
7068 - gpio-controller;
7069 - little-endian;
7070 - #gpio-cells = <2>;
7071 - interrupt-controller;
7072 - #interrupt-cells = <2>;
7073 - };
7074 -
7075 - gpio2: gpio@2320000 {
7076 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7077 - reg = <0x0 0x2320000 0x0 0x10000>;
7078 - interrupts = <0 37 0x4>; /* Level high type */
7079 - gpio-controller;
7080 - little-endian;
7081 - #gpio-cells = <2>;
7082 - interrupt-controller;
7083 - #interrupt-cells = <2>;
7084 - };
7085 -
7086 - gpio3: gpio@2330000 {
7087 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
7088 - reg = <0x0 0x2330000 0x0 0x10000>;
7089 - interrupts = <0 37 0x4>; /* Level high type */
7090 - gpio-controller;
7091 - little-endian;
7092 - #gpio-cells = <2>;
7093 - interrupt-controller;
7094 - #interrupt-cells = <2>;
7095 - };
7096 -
7097 - i2c0: i2c@2000000 {
7098 - status = "disabled";
7099 - compatible = "fsl,vf610-i2c";
7100 - #address-cells = <1>;
7101 - #size-cells = <0>;
7102 - reg = <0x0 0x2000000 0x0 0x10000>;
7103 - interrupts = <0 34 0x4>; /* Level high type */
7104 - clock-names = "i2c";
7105 - clocks = <&clockgen 4 3>;
7106 - };
7107 -
7108 - i2c1: i2c@2010000 {
7109 - status = "disabled";
7110 - compatible = "fsl,vf610-i2c";
7111 - #address-cells = <1>;
7112 - #size-cells = <0>;
7113 - reg = <0x0 0x2010000 0x0 0x10000>;
7114 - interrupts = <0 34 0x4>; /* Level high type */
7115 - clock-names = "i2c";
7116 - clocks = <&clockgen 4 3>;
7117 - };
7118 -
7119 - i2c2: i2c@2020000 {
7120 - status = "disabled";
7121 - compatible = "fsl,vf610-i2c";
7122 - #address-cells = <1>;
7123 - #size-cells = <0>;
7124 - reg = <0x0 0x2020000 0x0 0x10000>;
7125 - interrupts = <0 35 0x4>; /* Level high type */
7126 - clock-names = "i2c";
7127 - clocks = <&clockgen 4 3>;
7128 - };
7129 -
7130 - i2c3: i2c@2030000 {
7131 - status = "disabled";
7132 - compatible = "fsl,vf610-i2c";
7133 - #address-cells = <1>;
7134 - #size-cells = <0>;
7135 - reg = <0x0 0x2030000 0x0 0x10000>;
7136 - interrupts = <0 35 0x4>; /* Level high type */
7137 - clock-names = "i2c";
7138 - clocks = <&clockgen 4 3>;
7139 - };
7140 -
7141 - ifc: ifc@2240000 {
7142 - compatible = "fsl,ifc", "simple-bus";
7143 - reg = <0x0 0x2240000 0x0 0x20000>;
7144 - interrupts = <0 21 0x4>; /* Level high type */
7145 - little-endian;
7146 - #address-cells = <2>;
7147 - #size-cells = <1>;
7148 + cluster0_l2: l2-cache0 {
7149 + compatible = "cache";
7150 + };
7151
7152 - ranges = <0 0 0x5 0x80000000 0x08000000
7153 - 2 0 0x5 0x30000000 0x00010000
7154 - 3 0 0x5 0x20000000 0x00010000>;
7155 - };
7156 + cluster1_l2: l2-cache1 {
7157 + compatible = "cache";
7158 + };
7159
7160 - qspi: quadspi@20c0000 {
7161 - status = "disabled";
7162 - compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
7163 - #address-cells = <1>;
7164 - #size-cells = <0>;
7165 - reg = <0x0 0x20c0000 0x0 0x10000>,
7166 - <0x0 0x20000000 0x0 0x10000000>;
7167 - reg-names = "QuadSPI", "QuadSPI-memory";
7168 - interrupts = <0 25 0x4>; /* Level high type */
7169 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
7170 - clock-names = "qspi_en", "qspi";
7171 - };
7172 + cluster2_l2: l2-cache2 {
7173 + compatible = "cache";
7174 + };
7175
7176 - pcie@3400000 {
7177 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7178 - "snps,dw-pcie";
7179 - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7180 - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7181 - reg-names = "regs", "config";
7182 - interrupts = <0 108 0x4>; /* Level high type */
7183 - interrupt-names = "intr";
7184 - #address-cells = <3>;
7185 - #size-cells = <2>;
7186 - device_type = "pci";
7187 - dma-coherent;
7188 - num-lanes = <4>;
7189 - bus-range = <0x0 0xff>;
7190 - ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7191 - 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7192 - msi-parent = <&its>;
7193 - #interrupt-cells = <1>;
7194 - interrupt-map-mask = <0 0 0 7>;
7195 - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
7196 - <0000 0 0 2 &gic 0 0 0 110 4>,
7197 - <0000 0 0 3 &gic 0 0 0 111 4>,
7198 - <0000 0 0 4 &gic 0 0 0 112 4>;
7199 - };
7200 + cluster3_l2: l2-cache3 {
7201 + compatible = "cache";
7202 + };
7203 +};
7204
7205 - pcie@3500000 {
7206 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7207 - "snps,dw-pcie";
7208 - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7209 - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7210 - reg-names = "regs", "config";
7211 - interrupts = <0 113 0x4>; /* Level high type */
7212 - interrupt-names = "intr";
7213 - #address-cells = <3>;
7214 - #size-cells = <2>;
7215 - device_type = "pci";
7216 - dma-coherent;
7217 - num-lanes = <4>;
7218 - bus-range = <0x0 0xff>;
7219 - ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7220 - 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7221 - msi-parent = <&its>;
7222 - #interrupt-cells = <1>;
7223 - interrupt-map-mask = <0 0 0 7>;
7224 - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
7225 - <0000 0 0 2 &gic 0 0 0 115 4>,
7226 - <0000 0 0 3 &gic 0 0 0 116 4>,
7227 - <0000 0 0 4 &gic 0 0 0 117 4>;
7228 - };
7229 +&usb0 {
7230 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7231 + snps,dma-snooping;
7232 +};
7233
7234 - pcie@3600000 {
7235 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7236 - "snps,dw-pcie";
7237 - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7238 - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7239 - reg-names = "regs", "config";
7240 - interrupts = <0 118 0x4>; /* Level high type */
7241 - interrupt-names = "intr";
7242 - #address-cells = <3>;
7243 - #size-cells = <2>;
7244 - device_type = "pci";
7245 - dma-coherent;
7246 - num-lanes = <8>;
7247 - bus-range = <0x0 0xff>;
7248 - ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7249 - 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7250 - msi-parent = <&its>;
7251 - #interrupt-cells = <1>;
7252 - interrupt-map-mask = <0 0 0 7>;
7253 - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
7254 - <0000 0 0 2 &gic 0 0 0 120 4>,
7255 - <0000 0 0 3 &gic 0 0 0 121 4>,
7256 - <0000 0 0 4 &gic 0 0 0 122 4>;
7257 - };
7258 +&usb1 {
7259 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7260 + snps,dma-snooping;
7261 +};
7262
7263 - pcie@3700000 {
7264 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7265 - "snps,dw-pcie";
7266 - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7267 - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7268 - reg-names = "regs", "config";
7269 - interrupts = <0 123 0x4>; /* Level high type */
7270 - interrupt-names = "intr";
7271 - #address-cells = <3>;
7272 - #size-cells = <2>;
7273 - device_type = "pci";
7274 - dma-coherent;
7275 - num-lanes = <4>;
7276 - bus-range = <0x0 0xff>;
7277 - ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7278 - 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7279 - msi-parent = <&its>;
7280 - #interrupt-cells = <1>;
7281 - interrupt-map-mask = <0 0 0 7>;
7282 - interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
7283 - <0000 0 0 2 &gic 0 0 0 125 4>,
7284 - <0000 0 0 3 &gic 0 0 0 126 4>,
7285 - <0000 0 0 4 &gic 0 0 0 127 4>;
7286 - };
7287 +&pcie1 {
7288 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7289 + 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7290
7291 - sata0: sata@3200000 {
7292 - status = "disabled";
7293 - compatible = "fsl,ls2080a-ahci";
7294 - reg = <0x0 0x3200000 0x0 0x10000>;
7295 - interrupts = <0 133 0x4>; /* Level high type */
7296 - clocks = <&clockgen 4 3>;
7297 - dma-coherent;
7298 - };
7299 + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7300 + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7301 +};
7302
7303 - sata1: sata@3210000 {
7304 - status = "disabled";
7305 - compatible = "fsl,ls2080a-ahci";
7306 - reg = <0x0 0x3210000 0x0 0x10000>;
7307 - interrupts = <0 136 0x4>; /* Level high type */
7308 - clocks = <&clockgen 4 3>;
7309 - dma-coherent;
7310 - };
7311 +&pcie2 {
7312 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7313 + 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7314
7315 - usb0: usb3@3100000 {
7316 - status = "disabled";
7317 - compatible = "snps,dwc3";
7318 - reg = <0x0 0x3100000 0x0 0x10000>;
7319 - interrupts = <0 80 0x4>; /* Level high type */
7320 - dr_mode = "host";
7321 - snps,quirk-frame-length-adjustment = <0x20>;
7322 - snps,dis_rxdet_inp3_quirk;
7323 - };
7324 + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7325 + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7326 +};
7327
7328 - usb1: usb3@3110000 {
7329 - status = "disabled";
7330 - compatible = "snps,dwc3";
7331 - reg = <0x0 0x3110000 0x0 0x10000>;
7332 - interrupts = <0 81 0x4>; /* Level high type */
7333 - dr_mode = "host";
7334 - snps,quirk-frame-length-adjustment = <0x20>;
7335 - snps,dis_rxdet_inp3_quirk;
7336 - };
7337 +&pcie3 {
7338 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7339 + 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7340
7341 - ccn@4000000 {
7342 - compatible = "arm,ccn-504";
7343 - reg = <0x0 0x04000000 0x0 0x01000000>;
7344 - interrupts = <0 12 4>;
7345 - };
7346 - };
7347 + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7348 + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7349 +};
7350
7351 - ddr1: memory-controller@1080000 {
7352 - compatible = "fsl,qoriq-memory-controller";
7353 - reg = <0x0 0x1080000 0x0 0x1000>;
7354 - interrupts = <0 17 0x4>;
7355 - little-endian;
7356 - };
7357 +&pcie4 {
7358 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7359 + 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7360
7361 - ddr2: memory-controller@1090000 {
7362 - compatible = "fsl,qoriq-memory-controller";
7363 - reg = <0x0 0x1090000 0x0 0x1000>;
7364 - interrupts = <0 18 0x4>;
7365 - little-endian;
7366 - };
7367 + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7368 + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7369 };
7370 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
7371 new file mode 100644
7372 index 00000000..c3375bf7
7373 --- /dev/null
7374 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
7375 @@ -0,0 +1,161 @@
7376 +/*
7377 + * Device Tree file for NXP LS2081A RDB Board.
7378 + *
7379 + * Copyright 2017 NXP
7380 + *
7381 + * Priyanka Jain <priyanka.jain@nxp.com>
7382 + *
7383 + * This file is dual-licensed: you can use it either under the terms
7384 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7385 + * licensing only applies to this file, and not this project as a
7386 + * whole.
7387 + *
7388 + * a) This library is free software; you can redistribute it and/or
7389 + * modify it under the terms of the GNU General Public License as
7390 + * published by the Free Software Foundation; either version 2 of the
7391 + * License, or (at your option) any later version.
7392 + *
7393 + * This library is distributed in the hope that it will be useful,
7394 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7395 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7396 + * GNU General Public License for more details.
7397 + *
7398 + * Or, alternatively,
7399 + *
7400 + * b) Permission is hereby granted, free of charge, to any person
7401 + * obtaining a copy of this software and associated documentation
7402 + * files (the "Software"), to deal in the Software without
7403 + * restriction, including without limitation the rights to use,
7404 + * copy, modify, merge, publish, distribute, sublicense, and/or
7405 + * sell copies of the Software, and to permit persons to whom the
7406 + * Software is furnished to do so, subject to the following
7407 + * conditions:
7408 + *
7409 + * The above copyright notice and this permission notice shall be
7410 + * included in all copies or substantial portions of the Software.
7411 + *
7412 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7413 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7414 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7415 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7416 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7417 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7418 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7419 + * OTHER DEALINGS IN THE SOFTWARE.
7420 + */
7421 +
7422 +/dts-v1/;
7423 +
7424 +#include "fsl-ls2088a.dtsi"
7425 +
7426 +/ {
7427 + model = "NXP Layerscape 2081A RDB Board";
7428 + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
7429 +
7430 + aliases {
7431 + serial0 = &serial0;
7432 + serial1 = &serial1;
7433 + };
7434 +
7435 + chosen {
7436 + stdout-path = "serial1:115200n8";
7437 + };
7438 +};
7439 +
7440 +&esdhc {
7441 + status = "okay";
7442 +};
7443 +
7444 +&ifc {
7445 + status = "disabled";
7446 +};
7447 +
7448 +&i2c0 {
7449 + status = "okay";
7450 + pca9547@75 {
7451 + compatible = "nxp,pca9547";
7452 + reg = <0x75>;
7453 + #address-cells = <1>;
7454 + #size-cells = <0>;
7455 + i2c@1 {
7456 + #address-cells = <1>;
7457 + #size-cells = <0>;
7458 + reg = <0x01>;
7459 + rtc@51 {
7460 + compatible = "nxp,pcf2129";
7461 + reg = <0x51>;
7462 + };
7463 + };
7464 +
7465 + i2c@2 {
7466 + #address-cells = <1>;
7467 + #size-cells = <0>;
7468 + reg = <0x02>;
7469 +
7470 + ina220@40 {
7471 + compatible = "ti,ina220";
7472 + reg = <0x40>;
7473 + shunt-resistor = <500>;
7474 + };
7475 + };
7476 +
7477 + i2c@3 {
7478 + #address-cells = <1>;
7479 + #size-cells = <0>;
7480 + reg = <0x3>;
7481 +
7482 + adt7481@4c {
7483 + compatible = "adi,adt7461";
7484 + reg = <0x4c>;
7485 + };
7486 + };
7487 + };
7488 +};
7489 +
7490 +&dspi {
7491 + status = "okay";
7492 + dflash0: n25q512a {
7493 + #address-cells = <1>;
7494 + #size-cells = <1>;
7495 + compatible = "st,m25p80";
7496 + spi-max-frequency = <3000000>;
7497 + reg = <0>;
7498 + };
7499 +};
7500 +
7501 +&qspi {
7502 + status = "okay";
7503 + fsl,qspi-has-second-chip;
7504 + flash0: s25fs512s@0 {
7505 + #address-cells = <1>;
7506 + #size-cells = <1>;
7507 + compatible = "spansion,m25p80";
7508 + m25p,fast-read;
7509 + spi-max-frequency = <20000000>;
7510 + reg = <0>;
7511 + };
7512 + flash1: s25fs512s@1 {
7513 + #address-cells = <1>;
7514 + #size-cells = <1>;
7515 + compatible = "spansion,m25p80";
7516 + m25p,fast-read;
7517 + spi-max-frequency = <20000000>;
7518 + reg = <1>;
7519 + };
7520 +};
7521 +
7522 +&sata0 {
7523 + status = "okay";
7524 +};
7525 +
7526 +&sata1 {
7527 + status = "okay";
7528 +};
7529 +
7530 +&usb0 {
7531 + status = "okay";
7532 +};
7533 +
7534 +&usb1 {
7535 + status = "okay";
7536 +};
7537 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
7538 new file mode 100644
7539 index 00000000..1dbc7aa8
7540 --- /dev/null
7541 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
7542 @@ -0,0 +1,162 @@
7543 +/*
7544 + * Device Tree file for Freescale LS2088A QDS Board.
7545 + *
7546 + * Copyright 2016 Freescale Semiconductor, Inc.
7547 + * Copyright 2017 NXP
7548 + *
7549 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7550 + *
7551 + * This file is dual-licensed: you can use it either under the terms
7552 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7553 + * licensing only applies to this file, and not this project as a
7554 + * whole.
7555 + *
7556 + * a) This library is free software; you can redistribute it and/or
7557 + * modify it under the terms of the GNU General Public License as
7558 + * published by the Free Software Foundation; either version 2 of the
7559 + * License, or (at your option) any later version.
7560 + *
7561 + * This library is distributed in the hope that it will be useful,
7562 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7563 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7564 + * GNU General Public License for more details.
7565 + *
7566 + * Or, alternatively,
7567 + *
7568 + * b) Permission is hereby granted, free of charge, to any person
7569 + * obtaining a copy of this software and associated documentation
7570 + * files (the "Software"), to deal in the Software without
7571 + * restriction, including without limitation the rights to use,
7572 + * copy, modify, merge, publish, distribute, sublicense, and/or
7573 + * sell copies of the Software, and to permit persons to whom the
7574 + * Software is furnished to do so, subject to the following
7575 + * conditions:
7576 + *
7577 + * The above copyright notice and this permission notice shall be
7578 + * included in all copies or substantial portions of the Software.
7579 + *
7580 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7581 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7582 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7583 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7584 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7585 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7586 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7587 + * OTHER DEALINGS IN THE SOFTWARE.
7588 + */
7589 +
7590 +/dts-v1/;
7591 +
7592 +#include "fsl-ls2088a.dtsi"
7593 +#include "fsl-ls208xa-qds.dtsi"
7594 +
7595 +/ {
7596 + model = "Freescale Layerscape 2088A QDS Board";
7597 + compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
7598 +
7599 + chosen {
7600 + stdout-path = "serial0:115200n8";
7601 + };
7602 +};
7603 +
7604 +&ifc {
7605 + boardctrl: board-control@3,0 {
7606 + #address-cells = <1>;
7607 + #size-cells = <1>;
7608 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
7609 + reg = <3 0 0x300>; /* TODO check address */
7610 + ranges = <0 3 0 0x300>;
7611 +
7612 + mdio_mux_emi1 {
7613 + compatible = "mdio-mux-mmioreg", "mdio-mux";
7614 + mdio-parent-bus = <&emdio1>;
7615 + reg = <0x54 1>; /* BRDCFG4 */
7616 + mux-mask = <0xe0>; /* EMI1_MDIO */
7617 +
7618 + #address-cells=<1>;
7619 + #size-cells = <0>;
7620 +
7621 + /* Child MDIO buses, one for each riser card:
7622 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
7623 + * VSC8234 PHYs on the riser cards.
7624 + */
7625 +
7626 + mdio_mux3: mdio@60 {
7627 + reg = <0x60>;
7628 + #address-cells = <1>;
7629 + #size-cells = <0>;
7630 +
7631 + mdio0_phy12: mdio_phy0@1c {
7632 + reg = <0x1c>;
7633 + phy-connection-type = "sgmii";
7634 + };
7635 + mdio0_phy13: mdio_phy1@1d {
7636 + reg = <0x1d>;
7637 + phy-connection-type = "sgmii";
7638 + };
7639 + mdio0_phy14: mdio_phy2@1e {
7640 + reg = <0x1e>;
7641 + phy-connection-type = "sgmii";
7642 + };
7643 + mdio0_phy15: mdio_phy3@1f {
7644 + reg = <0x1f>;
7645 + phy-connection-type = "sgmii";
7646 + };
7647 + };
7648 + };
7649 + };
7650 +};
7651 +
7652 +&pcs_mdio1 {
7653 + pcs_phy1: ethernet-phy@0 {
7654 + backplane-mode = "10gbase-kr";
7655 + compatible = "ethernet-phy-ieee802.3-c45";
7656 + reg = <0x0>;
7657 + fsl,lane-handle = <&serdes1>;
7658 + fsl,lane-reg = <0x9C0 0x40>;/* lane H */
7659 + };
7660 +};
7661 +
7662 +&pcs_mdio2 {
7663 + pcs_phy2: ethernet-phy@0 {
7664 + backplane-mode = "10gbase-kr";
7665 + compatible = "ethernet-phy-ieee802.3-c45";
7666 + reg = <0x0>;
7667 + fsl,lane-handle = <&serdes1>;
7668 + fsl,lane-reg = <0x980 0x40>;/* lane G */
7669 + };
7670 +};
7671 +
7672 +&pcs_mdio3 {
7673 + pcs_phy3: ethernet-phy@0 {
7674 + backplane-mode = "10gbase-kr";
7675 + compatible = "ethernet-phy-ieee802.3-c45";
7676 + reg = <0x0>;
7677 + fsl,lane-handle = <&serdes1>;
7678 + fsl,lane-reg = <0x940 0x40>;/* lane F */
7679 + };
7680 +};
7681 +
7682 +&pcs_mdio4 {
7683 + pcs_phy4: ethernet-phy@0 {
7684 + backplane-mode = "10gbase-kr";
7685 + compatible = "ethernet-phy-ieee802.3-c45";
7686 + reg = <0x0>;
7687 + fsl,lane-handle = <&serdes1>;
7688 + fsl,lane-reg = <0x900 0x40>;/* lane E */
7689 + };
7690 +};
7691 +
7692 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
7693 +&dpmac9 {
7694 + phy-handle = <&mdio0_phy12>;
7695 +};
7696 +&dpmac10 {
7697 + phy-handle = <&mdio0_phy13>;
7698 +};
7699 +&dpmac11 {
7700 + phy-handle = <&mdio0_phy14>;
7701 +};
7702 +&dpmac12 {
7703 + phy-handle = <&mdio0_phy15>;
7704 +};
7705 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
7706 new file mode 100644
7707 index 00000000..9300119b
7708 --- /dev/null
7709 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
7710 @@ -0,0 +1,140 @@
7711 +/*
7712 + * Device Tree file for Freescale LS2088A RDB Board.
7713 + *
7714 + * Copyright 2016 Freescale Semiconductor, Inc.
7715 + * Copyright 2017 NXP
7716 + *
7717 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7718 + *
7719 + * This file is dual-licensed: you can use it either under the terms
7720 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7721 + * licensing only applies to this file, and not this project as a
7722 + * whole.
7723 + *
7724 + * a) This library is free software; you can redistribute it and/or
7725 + * modify it under the terms of the GNU General Public License as
7726 + * published by the Free Software Foundation; either version 2 of the
7727 + * License, or (at your option) any later version.
7728 + *
7729 + * This library is distributed in the hope that it will be useful,
7730 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7731 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7732 + * GNU General Public License for more details.
7733 + *
7734 + * Or, alternatively,
7735 + *
7736 + * b) Permission is hereby granted, free of charge, to any person
7737 + * obtaining a copy of this software and associated documentation
7738 + * files (the "Software"), to deal in the Software without
7739 + * restriction, including without limitation the rights to use,
7740 + * copy, modify, merge, publish, distribute, sublicense, and/or
7741 + * sell copies of the Software, and to permit persons to whom the
7742 + * Software is furnished to do so, subject to the following
7743 + * conditions:
7744 + *
7745 + * The above copyright notice and this permission notice shall be
7746 + * included in all copies or substantial portions of the Software.
7747 + *
7748 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7749 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7750 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7751 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7752 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7753 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7754 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7755 + * OTHER DEALINGS IN THE SOFTWARE.
7756 + */
7757 +
7758 +/dts-v1/;
7759 +
7760 +#include "fsl-ls2088a.dtsi"
7761 +#include "fsl-ls208xa-rdb.dtsi"
7762 +
7763 +/ {
7764 + model = "Freescale Layerscape 2088A RDB Board";
7765 + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
7766 +
7767 + chosen {
7768 + stdout-path = "serial1:115200n8";
7769 + };
7770 +};
7771 +
7772 +&emdio1 {
7773 + status = "disabled";
7774 + /* CS4340 PHYs */
7775 + mdio1_phy1: emdio1_phy@1 {
7776 + reg = <0x10>;
7777 + phy-connection-type = "xfi";
7778 + };
7779 + mdio1_phy2: emdio1_phy@2 {
7780 + reg = <0x11>;
7781 + phy-connection-type = "xfi";
7782 + };
7783 + mdio1_phy3: emdio1_phy@3 {
7784 + reg = <0x12>;
7785 + phy-connection-type = "xfi";
7786 + };
7787 + mdio1_phy4: emdio1_phy@4 {
7788 + reg = <0x13>;
7789 + phy-connection-type = "xfi";
7790 + };
7791 +};
7792 +
7793 +&emdio2 {
7794 + /* AQR405 PHYs */
7795 + mdio2_phy1: emdio2_phy@1 {
7796 + compatible = "ethernet-phy-ieee802.3-c45";
7797 + interrupts = <0 1 0x4>; /* Level high type */
7798 + reg = <0x0>;
7799 + phy-connection-type = "xfi";
7800 + };
7801 + mdio2_phy2: emdio2_phy@2 {
7802 + compatible = "ethernet-phy-ieee802.3-c45";
7803 + interrupts = <0 2 0x4>; /* Level high type */
7804 + reg = <0x1>;
7805 + phy-connection-type = "xfi";
7806 + };
7807 + mdio2_phy3: emdio2_phy@3 {
7808 + compatible = "ethernet-phy-ieee802.3-c45";
7809 + interrupts = <0 4 0x4>; /* Level high type */
7810 + reg = <0x2>;
7811 + phy-connection-type = "xfi";
7812 + };
7813 + mdio2_phy4: emdio2_phy@4 {
7814 + compatible = "ethernet-phy-ieee802.3-c45";
7815 + interrupts = <0 5 0x4>; /* Level high type */
7816 + reg = <0x3>;
7817 + phy-connection-type = "xfi";
7818 + };
7819 +};
7820 +
7821 +/* Update DPMAC connections to external PHYs, under the assumption of
7822 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
7823 + */
7824 +/* Leave Cortina PHYs commented out until proper driver is integrated
7825 + *&dpmac1 {
7826 + * phy-handle = <&mdio1_phy1>;
7827 + *};
7828 + *&dpmac2 {
7829 + * phy-handle = <&mdio1_phy2>;
7830 + *};
7831 + *&dpmac3 {
7832 + * phy-handle = <&mdio1_phy3>;
7833 + *};
7834 + *&dpmac4 {
7835 + * phy-handle = <&mdio1_phy4>;
7836 + *};
7837 + */
7838 +
7839 +&dpmac5 {
7840 + phy-handle = <&mdio2_phy1>;
7841 +};
7842 +&dpmac6 {
7843 + phy-handle = <&mdio2_phy2>;
7844 +};
7845 +&dpmac7 {
7846 + phy-handle = <&mdio2_phy3>;
7847 +};
7848 +&dpmac8 {
7849 + phy-handle = <&mdio2_phy4>;
7850 +};
7851 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
7852 new file mode 100644
7853 index 00000000..833699ea
7854 --- /dev/null
7855 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
7856 @@ -0,0 +1,195 @@
7857 +/*
7858 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
7859 + *
7860 + * Copyright 2016 Freescale Semiconductor, Inc.
7861 + * Copyright 2017 NXP
7862 + *
7863 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7864 + *
7865 + * This file is dual-licensed: you can use it either under the terms
7866 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7867 + * licensing only applies to this file, and not this project as a
7868 + * whole.
7869 + *
7870 + * a) This library is free software; you can redistribute it and/or
7871 + * modify it under the terms of the GNU General Public License as
7872 + * published by the Free Software Foundation; either version 2 of the
7873 + * License, or (at your option) any later version.
7874 + *
7875 + * This library is distributed in the hope that it will be useful,
7876 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7877 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7878 + * GNU General Public License for more details.
7879 + *
7880 + * Or, alternatively,
7881 + *
7882 + * b) Permission is hereby granted, free of charge, to any person
7883 + * obtaining a copy of this software and associated documentation
7884 + * files (the "Software"), to deal in the Software without
7885 + * restriction, including without limitation the rights to use,
7886 + * copy, modify, merge, publish, distribute, sublicense, and/or
7887 + * sell copies of the Software, and to permit persons to whom the
7888 + * Software is furnished to do so, subject to the following
7889 + * conditions:
7890 + *
7891 + * The above copyright notice and this permission notice shall be
7892 + * included in all copies or substantial portions of the Software.
7893 + *
7894 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7895 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7896 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7897 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7898 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7899 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7900 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7901 + * OTHER DEALINGS IN THE SOFTWARE.
7902 + */
7903 +
7904 +#include "fsl-ls208xa.dtsi"
7905 +
7906 +&cpu {
7907 + cpu0: cpu@0 {
7908 + device_type = "cpu";
7909 + compatible = "arm,cortex-a72";
7910 + reg = <0x0>;
7911 + clocks = <&clockgen 1 0>;
7912 + next-level-cache = <&cluster0_l2>;
7913 + #cooling-cells = <2>;
7914 + cpu-idle-states = <&CPU_PH20>;
7915 + };
7916 +
7917 + cpu1: cpu@1 {
7918 + device_type = "cpu";
7919 + compatible = "arm,cortex-a72";
7920 + reg = <0x1>;
7921 + clocks = <&clockgen 1 0>;
7922 + next-level-cache = <&cluster0_l2>;
7923 + cpu-idle-states = <&CPU_PH20>;
7924 + };
7925 +
7926 + cpu2: cpu@100 {
7927 + device_type = "cpu";
7928 + compatible = "arm,cortex-a72";
7929 + reg = <0x100>;
7930 + clocks = <&clockgen 1 1>;
7931 + next-level-cache = <&cluster1_l2>;
7932 + #cooling-cells = <2>;
7933 + cpu-idle-states = <&CPU_PH20>;
7934 + };
7935 +
7936 + cpu3: cpu@101 {
7937 + device_type = "cpu";
7938 + compatible = "arm,cortex-a72";
7939 + reg = <0x101>;
7940 + clocks = <&clockgen 1 1>;
7941 + next-level-cache = <&cluster1_l2>;
7942 + cpu-idle-states = <&CPU_PH20>;
7943 + };
7944 +
7945 + cpu4: cpu@200 {
7946 + device_type = "cpu";
7947 + compatible = "arm,cortex-a72";
7948 + reg = <0x200>;
7949 + clocks = <&clockgen 1 2>;
7950 + next-level-cache = <&cluster2_l2>;
7951 + #cooling-cells = <2>;
7952 + cpu-idle-states = <&CPU_PH20>;
7953 + };
7954 +
7955 + cpu5: cpu@201 {
7956 + device_type = "cpu";
7957 + compatible = "arm,cortex-a72";
7958 + reg = <0x201>;
7959 + clocks = <&clockgen 1 2>;
7960 + next-level-cache = <&cluster2_l2>;
7961 + cpu-idle-states = <&CPU_PH20>;
7962 + };
7963 +
7964 + cpu6: cpu@300 {
7965 + device_type = "cpu";
7966 + compatible = "arm,cortex-a72";
7967 + reg = <0x300>;
7968 + clocks = <&clockgen 1 3>;
7969 + next-level-cache = <&cluster3_l2>;
7970 + #cooling-cells = <2>;
7971 + cpu-idle-states = <&CPU_PH20>;
7972 + };
7973 +
7974 + cpu7: cpu@301 {
7975 + device_type = "cpu";
7976 + compatible = "arm,cortex-a72";
7977 + reg = <0x301>;
7978 + clocks = <&clockgen 1 3>;
7979 + next-level-cache = <&cluster3_l2>;
7980 + cpu-idle-states = <&CPU_PH20>;
7981 + };
7982 +
7983 + idle-states {
7984 + /*
7985 + * PSCI node is not added default, U-boot will add missing
7986 + * parts if it determines to use PSCI.
7987 + */
7988 + entry-method = "arm,psci";
7989 +
7990 + CPU_PH20: cpu-ph20 {
7991 + compatible = "arm,idle-state";
7992 + idle-state-name = "PH20";
7993 + arm,psci-suspend-param = <0x0>;
7994 + entry-latency-us = <1000>;
7995 + exit-latency-us = <1000>;
7996 + min-residency-us = <3000>;
7997 + };
7998 + };
7999 +
8000 + cluster0_l2: l2-cache0 {
8001 + compatible = "cache";
8002 + };
8003 +
8004 + cluster1_l2: l2-cache1 {
8005 + compatible = "cache";
8006 + };
8007 +
8008 + cluster2_l2: l2-cache2 {
8009 + compatible = "cache";
8010 + };
8011 +
8012 + cluster3_l2: l2-cache3 {
8013 + compatible = "cache";
8014 + };
8015 +};
8016 +
8017 +&pcie1 {
8018 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8019 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
8020 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
8021 +
8022 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
8023 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
8024 +};
8025 +
8026 +&pcie2 {
8027 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8028 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
8029 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
8030 +
8031 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
8032 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
8033 +};
8034 +
8035 +&pcie3 {
8036 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8037 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
8038 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
8039 +
8040 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
8041 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
8042 +};
8043 +
8044 +&pcie4 {
8045 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
8046 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
8047 + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
8048 +
8049 + ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
8050 + 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
8051 +};
8052 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
8053 new file mode 100644
8054 index 00000000..b2374469
8055 --- /dev/null
8056 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
8057 @@ -0,0 +1,198 @@
8058 +/*
8059 + * Device Tree file for Freescale LS2080A QDS Board.
8060 + *
8061 + * Copyright 2016 Freescale Semiconductor, Inc.
8062 + * Copyright 2017 NXP
8063 + *
8064 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8065 + *
8066 + * This file is dual-licensed: you can use it either under the terms
8067 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8068 + * licensing only applies to this file, and not this project as a
8069 + * whole.
8070 + *
8071 + * a) This library is free software; you can redistribute it and/or
8072 + * modify it under the terms of the GNU General Public License as
8073 + * published by the Free Software Foundation; either version 2 of the
8074 + * License, or (at your option) any later version.
8075 + *
8076 + * This library is distributed in the hope that it will be useful,
8077 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8078 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8079 + * GNU General Public License for more details.
8080 + *
8081 + * Or, alternatively,
8082 + *
8083 + * b) Permission is hereby granted, free of charge, to any person
8084 + * obtaining a copy of this software and associated documentation
8085 + * files (the "Software"), to deal in the Software without
8086 + * restriction, including without limitation the rights to use,
8087 + * copy, modify, merge, publish, distribute, sublicense, and/or
8088 + * sell copies of the Software, and to permit persons to whom the
8089 + * Software is furnished to do so, subject to the following
8090 + * conditions:
8091 + *
8092 + * The above copyright notice and this permission notice shall be
8093 + * included in all copies or substantial portions of the Software.
8094 + *
8095 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8096 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8097 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8098 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8099 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8100 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8101 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8102 + * OTHER DEALINGS IN THE SOFTWARE.
8103 + */
8104 +
8105 +&esdhc {
8106 + mmc-hs200-1_8v;
8107 + status = "okay";
8108 +};
8109 +
8110 +&ifc {
8111 + status = "okay";
8112 + #address-cells = <2>;
8113 + #size-cells = <1>;
8114 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8115 + 0x2 0x0 0x5 0x30000000 0x00010000
8116 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8117 +
8118 + nor@0,0 {
8119 + #address-cells = <1>;
8120 + #size-cells = <1>;
8121 + compatible = "cfi-flash";
8122 + reg = <0x0 0x0 0x8000000>;
8123 + bank-width = <2>;
8124 + device-width = <1>;
8125 + };
8126 +
8127 + nand@2,0 {
8128 + compatible = "fsl,ifc-nand";
8129 + reg = <0x2 0x0 0x10000>;
8130 + };
8131 +
8132 + cpld@3,0 {
8133 + reg = <0x3 0x0 0x10000>;
8134 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8135 + };
8136 +};
8137 +
8138 +&i2c0 {
8139 + status = "okay";
8140 + pca9547@77 {
8141 + compatible = "nxp,pca9547";
8142 + reg = <0x77>;
8143 + #address-cells = <1>;
8144 + #size-cells = <0>;
8145 + i2c@0 {
8146 + #address-cells = <1>;
8147 + #size-cells = <0>;
8148 + reg = <0x00>;
8149 + rtc@68 {
8150 + compatible = "dallas,ds3232";
8151 + reg = <0x68>;
8152 + };
8153 + };
8154 +
8155 + i2c@2 {
8156 + #address-cells = <1>;
8157 + #size-cells = <0>;
8158 + reg = <0x02>;
8159 +
8160 + ina220@40 {
8161 + compatible = "ti,ina220";
8162 + reg = <0x40>;
8163 + shunt-resistor = <500>;
8164 + };
8165 +
8166 + ina220@41 {
8167 + compatible = "ti,ina220";
8168 + reg = <0x41>;
8169 + shunt-resistor = <1000>;
8170 + };
8171 + };
8172 +
8173 + i2c@3 {
8174 + #address-cells = <1>;
8175 + #size-cells = <0>;
8176 + reg = <0x3>;
8177 +
8178 + adt7481@4c {
8179 + compatible = "adi,adt7461";
8180 + reg = <0x4c>;
8181 + };
8182 + };
8183 + };
8184 +};
8185 +
8186 +&i2c1 {
8187 + status = "disabled";
8188 +};
8189 +
8190 +&i2c2 {
8191 + status = "disabled";
8192 +};
8193 +
8194 +&i2c3 {
8195 + status = "disabled";
8196 +};
8197 +
8198 +&dspi {
8199 + status = "okay";
8200 + dflash0: n25q128a {
8201 + #address-cells = <1>;
8202 + #size-cells = <1>;
8203 + compatible = "st,m25p80";
8204 + spi-max-frequency = <3000000>;
8205 + reg = <0>;
8206 + };
8207 + dflash1: sst25wf040b {
8208 + #address-cells = <1>;
8209 + #size-cells = <1>;
8210 + compatible = "st,m25p80";
8211 + spi-max-frequency = <3000000>;
8212 + reg = <1>;
8213 + };
8214 + dflash2: en25s64 {
8215 + #address-cells = <1>;
8216 + #size-cells = <1>;
8217 + compatible = "st,m25p80";
8218 + spi-max-frequency = <3000000>;
8219 + reg = <2>;
8220 + };
8221 +};
8222 +
8223 +&qspi {
8224 + status = "okay";
8225 + flash0: s25fl256s1@0 {
8226 + #address-cells = <1>;
8227 + #size-cells = <1>;
8228 + compatible = "st,m25p80";
8229 + spi-max-frequency = <20000000>;
8230 + reg = <0>;
8231 + };
8232 + flash2: s25fl256s1@2 {
8233 + #address-cells = <1>;
8234 + #size-cells = <1>;
8235 + compatible = "st,m25p80";
8236 + spi-max-frequency = <20000000>;
8237 + reg = <0>;
8238 + };
8239 +};
8240 +
8241 +&sata0 {
8242 + status = "okay";
8243 +};
8244 +
8245 +&sata1 {
8246 + status = "okay";
8247 +};
8248 +
8249 +&usb0 {
8250 + status = "okay";
8251 +};
8252 +
8253 +&usb1 {
8254 + status = "okay";
8255 +};
8256 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
8257 new file mode 100644
8258 index 00000000..8e919dc8
8259 --- /dev/null
8260 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
8261 @@ -0,0 +1,161 @@
8262 +/*
8263 + * Device Tree file for Freescale LS2080A RDB Board.
8264 + *
8265 + * Copyright 2016 Freescale Semiconductor, Inc.
8266 + * Copyright 2017 NXP
8267 + *
8268 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8269 + *
8270 + * This file is dual-licensed: you can use it either under the terms
8271 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8272 + * licensing only applies to this file, and not this project as a
8273 + * whole.
8274 + *
8275 + * a) This library is free software; you can redistribute it and/or
8276 + * modify it under the terms of the GNU General Public License as
8277 + * published by the Free Software Foundation; either version 2 of the
8278 + * License, or (at your option) any later version.
8279 + *
8280 + * This library is distributed in the hope that it will be useful,
8281 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8282 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8283 + * GNU General Public License for more details.
8284 + *
8285 + * Or, alternatively,
8286 + *
8287 + * b) Permission is hereby granted, free of charge, to any person
8288 + * obtaining a copy of this software and associated documentation
8289 + * files (the "Software"), to deal in the Software without
8290 + * restriction, including without limitation the rights to use,
8291 + * copy, modify, merge, publish, distribute, sublicense, and/or
8292 + * sell copies of the Software, and to permit persons to whom the
8293 + * Software is furnished to do so, subject to the following
8294 + * conditions:
8295 + *
8296 + * The above copyright notice and this permission notice shall be
8297 + * included in all copies or substantial portions of the Software.
8298 + *
8299 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8300 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8301 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8302 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8303 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8304 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8305 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8306 + * OTHER DEALINGS IN THE SOFTWARE.
8307 + */
8308 +
8309 +&esdhc {
8310 + status = "okay";
8311 +};
8312 +
8313 +&ifc {
8314 + status = "okay";
8315 + #address-cells = <2>;
8316 + #size-cells = <1>;
8317 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8318 + 0x2 0x0 0x5 0x30000000 0x00010000
8319 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8320 +
8321 + nor@0,0 {
8322 + #address-cells = <1>;
8323 + #size-cells = <1>;
8324 + compatible = "cfi-flash";
8325 + reg = <0x0 0x0 0x8000000>;
8326 + bank-width = <2>;
8327 + device-width = <1>;
8328 + };
8329 +
8330 + nand@2,0 {
8331 + compatible = "fsl,ifc-nand";
8332 + reg = <0x2 0x0 0x10000>;
8333 + };
8334 +
8335 + cpld@3,0 {
8336 + reg = <0x3 0x0 0x10000>;
8337 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8338 + };
8339 +
8340 +};
8341 +
8342 +&i2c0 {
8343 + status = "okay";
8344 + pca9547@75 {
8345 + compatible = "nxp,pca9547";
8346 + reg = <0x75>;
8347 + #address-cells = <1>;
8348 + #size-cells = <0>;
8349 + i2c-mux-never-disable;
8350 + i2c@1 {
8351 + #address-cells = <1>;
8352 + #size-cells = <0>;
8353 + reg = <0x01>;
8354 + rtc@68 {
8355 + compatible = "dallas,ds3232";
8356 + reg = <0x68>;
8357 + };
8358 + };
8359 +
8360 + i2c@3 {
8361 + #address-cells = <1>;
8362 + #size-cells = <0>;
8363 + reg = <0x3>;
8364 +
8365 + adt7481@4c {
8366 + compatible = "adi,adt7461";
8367 + reg = <0x4c>;
8368 + };
8369 + };
8370 + };
8371 +};
8372 +
8373 +&i2c1 {
8374 + status = "disabled";
8375 +};
8376 +
8377 +&i2c2 {
8378 + status = "disabled";
8379 +};
8380 +
8381 +&i2c3 {
8382 + status = "disabled";
8383 +};
8384 +
8385 +&dspi {
8386 + status = "okay";
8387 + dflash0: n25q512a {
8388 + #address-cells = <1>;
8389 + #size-cells = <1>;
8390 + compatible = "st,m25p80";
8391 + spi-max-frequency = <3000000>;
8392 + reg = <0>;
8393 + };
8394 +};
8395 +
8396 +&qspi {
8397 + status = "okay";
8398 + flash0: s25fs512s@0 {
8399 + #address-cells = <1>;
8400 + #size-cells = <1>;
8401 + compatible = "spansion,m25p80";
8402 + m25p,fast-read;
8403 + spi-max-frequency = <20000000>;
8404 + reg = <0>;
8405 + };
8406 +};
8407 +
8408 +&sata0 {
8409 + status = "okay";
8410 +};
8411 +
8412 +&sata1 {
8413 + status = "okay";
8414 +};
8415 +
8416 +&usb0 {
8417 + status = "okay";
8418 +};
8419 +
8420 +&usb1 {
8421 + status = "okay";
8422 +};
8423 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
8424 new file mode 100644
8425 index 00000000..dbc3a3d0
8426 --- /dev/null
8427 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
8428 @@ -0,0 +1,912 @@
8429 +/*
8430 + * Device Tree Include file for Freescale Layerscape-2080A family SoC.
8431 + *
8432 + * Copyright 2016 Freescale Semiconductor, Inc.
8433 + * Copyright 2017 NXP
8434 + *
8435 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8436 + *
8437 + * This file is dual-licensed: you can use it either under the terms
8438 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8439 + * licensing only applies to this file, and not this project as a
8440 + * whole.
8441 + *
8442 + * a) This library is free software; you can redistribute it and/or
8443 + * modify it under the terms of the GNU General Public License as
8444 + * published by the Free Software Foundation; either version 2 of the
8445 + * License, or (at your option) any later version.
8446 + *
8447 + * This library is distributed in the hope that it will be useful,
8448 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8449 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8450 + * GNU General Public License for more details.
8451 + *
8452 + * Or, alternatively,
8453 + *
8454 + * b) Permission is hereby granted, free of charge, to any person
8455 + * obtaining a copy of this software and associated documentation
8456 + * files (the "Software"), to deal in the Software without
8457 + * restriction, including without limitation the rights to use,
8458 + * copy, modify, merge, publish, distribute, sublicense, and/or
8459 + * sell copies of the Software, and to permit persons to whom the
8460 + * Software is furnished to do so, subject to the following
8461 + * conditions:
8462 + *
8463 + * The above copyright notice and this permission notice shall be
8464 + * included in all copies or substantial portions of the Software.
8465 + *
8466 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8467 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8468 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8469 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8470 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8471 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8472 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8473 + * OTHER DEALINGS IN THE SOFTWARE.
8474 + */
8475 +
8476 +#include <dt-bindings/thermal/thermal.h>
8477 +#include <dt-bindings/interrupt-controller/arm-gic.h>
8478 +
8479 +/ {
8480 + compatible = "fsl,ls2080a";
8481 + interrupt-parent = <&gic>;
8482 + #address-cells = <2>;
8483 + #size-cells = <2>;
8484 +
8485 + aliases {
8486 + crypto = &crypto;
8487 + serial0 = &serial0;
8488 + serial1 = &serial1;
8489 + };
8490 +
8491 + cpu: cpus {
8492 + #address-cells = <1>;
8493 + #size-cells = <0>;
8494 + };
8495 +
8496 + memory@80000000 {
8497 + device_type = "memory";
8498 + reg = <0x00000000 0x80000000 0 0x80000000>;
8499 + /* DRAM space - 1, size : 2 GB DRAM */
8500 + };
8501 +
8502 + sysclk: sysclk {
8503 + compatible = "fixed-clock";
8504 + #clock-cells = <0>;
8505 + clock-frequency = <100000000>;
8506 + clock-output-names = "sysclk";
8507 + };
8508 +
8509 + gic: interrupt-controller@6000000 {
8510 + compatible = "arm,gic-v3";
8511 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
8512 + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
8513 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
8514 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
8515 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
8516 + #interrupt-cells = <3>;
8517 + #address-cells = <2>;
8518 + #size-cells = <2>;
8519 + ranges;
8520 + interrupt-controller;
8521 + interrupts = <1 9 0x4>;
8522 +
8523 + its: gic-its@6020000 {
8524 + compatible = "arm,gic-v3-its";
8525 + msi-controller;
8526 + reg = <0x0 0x6020000 0 0x20000>;
8527 + };
8528 + };
8529 +
8530 + rstcr: syscon@1e60000 {
8531 + compatible = "fsl,ls2080a-rstcr", "syscon";
8532 + reg = <0x0 0x1e60000 0x0 0x4>;
8533 + };
8534 +
8535 + reboot {
8536 + compatible ="syscon-reboot";
8537 + regmap = <&rstcr>;
8538 + offset = <0x0>;
8539 + mask = <0x2>;
8540 + };
8541 +
8542 + timer {
8543 + compatible = "arm,armv8-timer";
8544 + interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
8545 + <1 14 4>, /* Physical Non-Secure PPI, active-low */
8546 + <1 11 4>, /* Virtual PPI, active-low */
8547 + <1 10 4>; /* Hypervisor PPI, active-low */
8548 + fsl,erratum-a008585;
8549 + };
8550 +
8551 + pmu {
8552 + compatible = "arm,armv8-pmuv3";
8553 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
8554 + };
8555 +
8556 + soc {
8557 + compatible = "simple-bus";
8558 + #address-cells = <2>;
8559 + #size-cells = <2>;
8560 + ranges;
8561 +
8562 + clockgen: clocking@1300000 {
8563 + compatible = "fsl,ls2080a-clockgen";
8564 + reg = <0 0x1300000 0 0xa0000>;
8565 + #clock-cells = <2>;
8566 + clocks = <&sysclk>;
8567 + };
8568 +
8569 + dcfg: dcfg@1e00000 {
8570 + compatible = "fsl,ls2080a-dcfg", "syscon";
8571 + reg = <0x0 0x1e00000 0x0 0x10000>;
8572 + little-endian;
8573 + };
8574 +
8575 + tmu: tmu@1f80000 {
8576 + compatible = "fsl,qoriq-tmu";
8577 + reg = <0x0 0x1f80000 0x0 0x10000>;
8578 + interrupts = <0 23 0x4>;
8579 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
8580 + fsl,tmu-calibration = <0x00000000 0x00000026
8581 + 0x00000001 0x0000002d
8582 + 0x00000002 0x00000032
8583 + 0x00000003 0x00000039
8584 + 0x00000004 0x0000003f
8585 + 0x00000005 0x00000046
8586 + 0x00000006 0x0000004d
8587 + 0x00000007 0x00000054
8588 + 0x00000008 0x0000005a
8589 + 0x00000009 0x00000061
8590 + 0x0000000a 0x0000006a
8591 + 0x0000000b 0x00000071
8592 +
8593 + 0x00010000 0x00000025
8594 + 0x00010001 0x0000002c
8595 + 0x00010002 0x00000035
8596 + 0x00010003 0x0000003d
8597 + 0x00010004 0x00000045
8598 + 0x00010005 0x0000004e
8599 + 0x00010006 0x00000057
8600 + 0x00010007 0x00000061
8601 + 0x00010008 0x0000006b
8602 + 0x00010009 0x00000076
8603 +
8604 + 0x00020000 0x00000029
8605 + 0x00020001 0x00000033
8606 + 0x00020002 0x0000003d
8607 + 0x00020003 0x00000049
8608 + 0x00020004 0x00000056
8609 + 0x00020005 0x00000061
8610 + 0x00020006 0x0000006d
8611 +
8612 + 0x00030000 0x00000021
8613 + 0x00030001 0x0000002a
8614 + 0x00030002 0x0000003c
8615 + 0x00030003 0x0000004e>;
8616 + little-endian;
8617 + #thermal-sensor-cells = <1>;
8618 + };
8619 +
8620 + thermal-zones {
8621 + cpu_thermal: cpu-thermal {
8622 + polling-delay-passive = <1000>;
8623 + polling-delay = <5000>;
8624 +
8625 + thermal-sensors = <&tmu 4>;
8626 +
8627 + trips {
8628 + cpu_alert: cpu-alert {
8629 + temperature = <75000>;
8630 + hysteresis = <2000>;
8631 + type = "passive";
8632 + };
8633 + cpu_crit: cpu-crit {
8634 + temperature = <85000>;
8635 + hysteresis = <2000>;
8636 + type = "critical";
8637 + };
8638 + };
8639 +
8640 + cooling-maps {
8641 + map0 {
8642 + trip = <&cpu_alert>;
8643 + cooling-device =
8644 + <&cpu0 THERMAL_NO_LIMIT
8645 + THERMAL_NO_LIMIT>;
8646 + };
8647 + map1 {
8648 + trip = <&cpu_alert>;
8649 + cooling-device =
8650 + <&cpu2 THERMAL_NO_LIMIT
8651 + THERMAL_NO_LIMIT>;
8652 + };
8653 + map2 {
8654 + trip = <&cpu_alert>;
8655 + cooling-device =
8656 + <&cpu4 THERMAL_NO_LIMIT
8657 + THERMAL_NO_LIMIT>;
8658 + };
8659 + map3 {
8660 + trip = <&cpu_alert>;
8661 + cooling-device =
8662 + <&cpu6 THERMAL_NO_LIMIT
8663 + THERMAL_NO_LIMIT>;
8664 + };
8665 + };
8666 + };
8667 + };
8668 +
8669 + serial0: serial@21c0500 {
8670 + compatible = "fsl,ns16550", "ns16550a";
8671 + reg = <0x0 0x21c0500 0x0 0x100>;
8672 + clocks = <&clockgen 4 3>;
8673 + interrupts = <0 32 0x4>; /* Level high type */
8674 + };
8675 +
8676 + serial1: serial@21c0600 {
8677 + compatible = "fsl,ns16550", "ns16550a";
8678 + reg = <0x0 0x21c0600 0x0 0x100>;
8679 + clocks = <&clockgen 4 3>;
8680 + interrupts = <0 32 0x4>; /* Level high type */
8681 + };
8682 +
8683 + cluster1_core0_watchdog: wdt@c000000 {
8684 + compatible = "arm,sp805-wdt", "arm,primecell";
8685 + reg = <0x0 0xc000000 0x0 0x1000>;
8686 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8687 + clock-names = "apb_pclk", "wdog_clk";
8688 + };
8689 +
8690 + cluster1_core1_watchdog: wdt@c010000 {
8691 + compatible = "arm,sp805-wdt", "arm,primecell";
8692 + reg = <0x0 0xc010000 0x0 0x1000>;
8693 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8694 + clock-names = "apb_pclk", "wdog_clk";
8695 + };
8696 +
8697 + cluster2_core0_watchdog: wdt@c100000 {
8698 + compatible = "arm,sp805-wdt", "arm,primecell";
8699 + reg = <0x0 0xc100000 0x0 0x1000>;
8700 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8701 + clock-names = "apb_pclk", "wdog_clk";
8702 + };
8703 +
8704 + cluster2_core1_watchdog: wdt@c110000 {
8705 + compatible = "arm,sp805-wdt", "arm,primecell";
8706 + reg = <0x0 0xc110000 0x0 0x1000>;
8707 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8708 + clock-names = "apb_pclk", "wdog_clk";
8709 + };
8710 +
8711 + cluster3_core0_watchdog: wdt@c200000 {
8712 + compatible = "arm,sp805-wdt", "arm,primecell";
8713 + reg = <0x0 0xc200000 0x0 0x1000>;
8714 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8715 + clock-names = "apb_pclk", "wdog_clk";
8716 + };
8717 +
8718 + cluster3_core1_watchdog: wdt@c210000 {
8719 + compatible = "arm,sp805-wdt", "arm,primecell";
8720 + reg = <0x0 0xc210000 0x0 0x1000>;
8721 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8722 + clock-names = "apb_pclk", "wdog_clk";
8723 + };
8724 +
8725 + cluster4_core0_watchdog: wdt@c300000 {
8726 + compatible = "arm,sp805-wdt", "arm,primecell";
8727 + reg = <0x0 0xc300000 0x0 0x1000>;
8728 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8729 + clock-names = "apb_pclk", "wdog_clk";
8730 + };
8731 +
8732 + cluster4_core1_watchdog: wdt@c310000 {
8733 + compatible = "arm,sp805-wdt", "arm,primecell";
8734 + reg = <0x0 0xc310000 0x0 0x1000>;
8735 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8736 + clock-names = "apb_pclk", "wdog_clk";
8737 + };
8738 +
8739 + crypto: crypto@8000000 {
8740 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
8741 + fsl,sec-era = <8>;
8742 + #address-cells = <1>;
8743 + #size-cells = <1>;
8744 + ranges = <0x0 0x00 0x8000000 0x100000>;
8745 + reg = <0x00 0x8000000 0x0 0x100000>;
8746 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
8747 + dma-coherent;
8748 +
8749 + sec_jr0: jr@10000 {
8750 + compatible = "fsl,sec-v5.0-job-ring",
8751 + "fsl,sec-v4.0-job-ring";
8752 + reg = <0x10000 0x10000>;
8753 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
8754 + };
8755 +
8756 + sec_jr1: jr@20000 {
8757 + compatible = "fsl,sec-v5.0-job-ring",
8758 + "fsl,sec-v4.0-job-ring";
8759 + reg = <0x20000 0x10000>;
8760 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
8761 + };
8762 +
8763 + sec_jr2: jr@30000 {
8764 + compatible = "fsl,sec-v5.0-job-ring",
8765 + "fsl,sec-v4.0-job-ring";
8766 + reg = <0x30000 0x10000>;
8767 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
8768 + };
8769 +
8770 + sec_jr3: jr@40000 {
8771 + compatible = "fsl,sec-v5.0-job-ring",
8772 + "fsl,sec-v4.0-job-ring";
8773 + reg = <0x40000 0x10000>;
8774 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
8775 + };
8776 + };
8777 +
8778 + fsl_mc: fsl-mc@80c000000 {
8779 + compatible = "fsl,qoriq-mc";
8780 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
8781 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
8782 + msi-parent = <&its>;
8783 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
8784 + #address-cells = <3>;
8785 + #size-cells = <1>;
8786 +
8787 + /*
8788 + * Region type 0x0 - MC portals
8789 + * Region type 0x1 - QBMAN portals
8790 + */
8791 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
8792 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
8793 +
8794 + /*
8795 + * Define the maximum number of MACs present on the SoC.
8796 + */
8797 + dpmacs {
8798 + #address-cells = <1>;
8799 + #size-cells = <0>;
8800 +
8801 + dpmac1: dpmac@1 {
8802 + compatible = "fsl,qoriq-mc-dpmac";
8803 + reg = <0x1>;
8804 + };
8805 +
8806 + dpmac2: dpmac@2 {
8807 + compatible = "fsl,qoriq-mc-dpmac";
8808 + reg = <0x2>;
8809 + };
8810 +
8811 + dpmac3: dpmac@3 {
8812 + compatible = "fsl,qoriq-mc-dpmac";
8813 + reg = <0x3>;
8814 + };
8815 +
8816 + dpmac4: dpmac@4 {
8817 + compatible = "fsl,qoriq-mc-dpmac";
8818 + reg = <0x4>;
8819 + };
8820 +
8821 + dpmac5: dpmac@5 {
8822 + compatible = "fsl,qoriq-mc-dpmac";
8823 + reg = <0x5>;
8824 + };
8825 +
8826 + dpmac6: dpmac@6 {
8827 + compatible = "fsl,qoriq-mc-dpmac";
8828 + reg = <0x6>;
8829 + };
8830 +
8831 + dpmac7: dpmac@7 {
8832 + compatible = "fsl,qoriq-mc-dpmac";
8833 + reg = <0x7>;
8834 + };
8835 +
8836 + dpmac8: dpmac@8 {
8837 + compatible = "fsl,qoriq-mc-dpmac";
8838 + reg = <0x8>;
8839 + };
8840 +
8841 + dpmac9: dpmac@9 {
8842 + compatible = "fsl,qoriq-mc-dpmac";
8843 + reg = <0x9>;
8844 + };
8845 +
8846 + dpmac10: dpmac@a {
8847 + compatible = "fsl,qoriq-mc-dpmac";
8848 + reg = <0xa>;
8849 + };
8850 +
8851 + dpmac11: dpmac@b {
8852 + compatible = "fsl,qoriq-mc-dpmac";
8853 + reg = <0xb>;
8854 + };
8855 +
8856 + dpmac12: dpmac@c {
8857 + compatible = "fsl,qoriq-mc-dpmac";
8858 + reg = <0xc>;
8859 + };
8860 +
8861 + dpmac13: dpmac@d {
8862 + compatible = "fsl,qoriq-mc-dpmac";
8863 + reg = <0xd>;
8864 + };
8865 +
8866 + dpmac14: dpmac@e {
8867 + compatible = "fsl,qoriq-mc-dpmac";
8868 + reg = <0xe>;
8869 + };
8870 +
8871 + dpmac15: dpmac@f {
8872 + compatible = "fsl,qoriq-mc-dpmac";
8873 + reg = <0xf>;
8874 + };
8875 +
8876 + dpmac16: dpmac@10 {
8877 + compatible = "fsl,qoriq-mc-dpmac";
8878 + reg = <0x10>;
8879 + };
8880 + };
8881 + };
8882 +
8883 + smmu: iommu@5000000 {
8884 + compatible = "arm,mmu-500";
8885 + reg = <0 0x5000000 0 0x800000>;
8886 + #global-interrupts = <12>;
8887 + #iommu-cells = <1>;
8888 + stream-match-mask = <0x7C00>;
8889 + interrupts = <0 13 4>, /* global secure fault */
8890 + <0 14 4>, /* combined secure interrupt */
8891 + <0 15 4>, /* global non-secure fault */
8892 + <0 16 4>, /* combined non-secure interrupt */
8893 + /* performance counter interrupts 0-7 */
8894 + <0 211 4>, <0 212 4>,
8895 + <0 213 4>, <0 214 4>,
8896 + <0 215 4>, <0 216 4>,
8897 + <0 217 4>, <0 218 4>,
8898 + /* per context interrupt, 64 interrupts */
8899 + <0 146 4>, <0 147 4>,
8900 + <0 148 4>, <0 149 4>,
8901 + <0 150 4>, <0 151 4>,
8902 + <0 152 4>, <0 153 4>,
8903 + <0 154 4>, <0 155 4>,
8904 + <0 156 4>, <0 157 4>,
8905 + <0 158 4>, <0 159 4>,
8906 + <0 160 4>, <0 161 4>,
8907 + <0 162 4>, <0 163 4>,
8908 + <0 164 4>, <0 165 4>,
8909 + <0 166 4>, <0 167 4>,
8910 + <0 168 4>, <0 169 4>,
8911 + <0 170 4>, <0 171 4>,
8912 + <0 172 4>, <0 173 4>,
8913 + <0 174 4>, <0 175 4>,
8914 + <0 176 4>, <0 177 4>,
8915 + <0 178 4>, <0 179 4>,
8916 + <0 180 4>, <0 181 4>,
8917 + <0 182 4>, <0 183 4>,
8918 + <0 184 4>, <0 185 4>,
8919 + <0 186 4>, <0 187 4>,
8920 + <0 188 4>, <0 189 4>,
8921 + <0 190 4>, <0 191 4>,
8922 + <0 192 4>, <0 193 4>,
8923 + <0 194 4>, <0 195 4>,
8924 + <0 196 4>, <0 197 4>,
8925 + <0 198 4>, <0 199 4>,
8926 + <0 200 4>, <0 201 4>,
8927 + <0 202 4>, <0 203 4>,
8928 + <0 204 4>, <0 205 4>,
8929 + <0 206 4>, <0 207 4>,
8930 + <0 208 4>, <0 209 4>;
8931 + };
8932 +
8933 + dspi: dspi@2100000 {
8934 + status = "disabled";
8935 + compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
8936 + #address-cells = <1>;
8937 + #size-cells = <0>;
8938 + reg = <0x0 0x2100000 0x0 0x10000>;
8939 + interrupts = <0 26 0x4>; /* Level high type */
8940 + clocks = <&clockgen 4 3>;
8941 + clock-names = "dspi";
8942 + spi-num-chipselects = <5>;
8943 + bus-num = <0>;
8944 + };
8945 +
8946 + esdhc: esdhc@2140000 {
8947 + status = "disabled";
8948 + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
8949 + reg = <0x0 0x2140000 0x0 0x10000>;
8950 + interrupts = <0 28 0x4>; /* Level high type */
8951 + clocks = <&clockgen 4 1>;
8952 + voltage-ranges = <1800 1800 3300 3300>;
8953 + sdhci,auto-cmd12;
8954 + little-endian;
8955 + bus-width = <4>;
8956 + };
8957 +
8958 + gpio0: gpio@2300000 {
8959 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8960 + reg = <0x0 0x2300000 0x0 0x10000>;
8961 + interrupts = <0 36 0x4>; /* Level high type */
8962 + gpio-controller;
8963 + little-endian;
8964 + #gpio-cells = <2>;
8965 + interrupt-controller;
8966 + #interrupt-cells = <2>;
8967 + };
8968 +
8969 + gpio1: gpio@2310000 {
8970 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8971 + reg = <0x0 0x2310000 0x0 0x10000>;
8972 + interrupts = <0 36 0x4>; /* Level high type */
8973 + gpio-controller;
8974 + little-endian;
8975 + #gpio-cells = <2>;
8976 + interrupt-controller;
8977 + #interrupt-cells = <2>;
8978 + };
8979 +
8980 + gpio2: gpio@2320000 {
8981 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8982 + reg = <0x0 0x2320000 0x0 0x10000>;
8983 + interrupts = <0 37 0x4>; /* Level high type */
8984 + gpio-controller;
8985 + little-endian;
8986 + #gpio-cells = <2>;
8987 + interrupt-controller;
8988 + #interrupt-cells = <2>;
8989 + };
8990 +
8991 + gpio3: gpio@2330000 {
8992 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8993 + reg = <0x0 0x2330000 0x0 0x10000>;
8994 + interrupts = <0 37 0x4>; /* Level high type */
8995 + gpio-controller;
8996 + little-endian;
8997 + #gpio-cells = <2>;
8998 + interrupt-controller;
8999 + #interrupt-cells = <2>;
9000 + };
9001 +
9002 + /* TODO: WRIOP (CCSR?) */
9003 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
9004 + * E-MDIO1: 0x1_6000
9005 + */
9006 + compatible = "fsl,fman-memac-mdio";
9007 + reg = <0x0 0x8B96000 0x0 0x1000>;
9008 + device_type = "mdio"; /* TODO: is this necessary? */
9009 + little-endian; /* force the driver in LE mode */
9010 +
9011 + /* Not necessary on the QDS, but needed on the RDB */
9012 + #address-cells = <1>;
9013 + #size-cells = <0>;
9014 + };
9015 +
9016 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
9017 + * E-MDIO2: 0x1_7000
9018 + */
9019 + compatible = "fsl,fman-memac-mdio";
9020 + reg = <0x0 0x8B97000 0x0 0x1000>;
9021 + device_type = "mdio"; /* TODO: is this necessary? */
9022 + little-endian; /* force the driver in LE mode */
9023 +
9024 + #address-cells = <1>;
9025 + #size-cells = <0>;
9026 + };
9027 +
9028 + pcs_mdio1: mdio@0x8c07000 {
9029 + compatible = "fsl,fman-memac-mdio";
9030 + reg = <0x0 0x8c07000 0x0 0x1000>;
9031 + device_type = "mdio";
9032 + little-endian;
9033 +
9034 + #address-cells = <1>;
9035 + #size-cells = <0>;
9036 + };
9037 +
9038 + pcs_mdio2: mdio@0x8c0b000 {
9039 + compatible = "fsl,fman-memac-mdio";
9040 + reg = <0x0 0x8c0b000 0x0 0x1000>;
9041 + device_type = "mdio";
9042 + little-endian;
9043 +
9044 + #address-cells = <1>;
9045 + #size-cells = <0>;
9046 + };
9047 +
9048 + pcs_mdio3: mdio@0x8c0f000 {
9049 + compatible = "fsl,fman-memac-mdio";
9050 + reg = <0x0 0x8c0f000 0x0 0x1000>;
9051 + device_type = "mdio";
9052 + little-endian;
9053 +
9054 + #address-cells = <1>;
9055 + #size-cells = <0>;
9056 + };
9057 +
9058 + pcs_mdio4: mdio@0x8c13000 {
9059 + compatible = "fsl,fman-memac-mdio";
9060 + reg = <0x0 0x8c13000 0x0 0x1000>;
9061 + device_type = "mdio";
9062 + little-endian;
9063 +
9064 + #address-cells = <1>;
9065 + #size-cells = <0>;
9066 + };
9067 +
9068 + pcs_mdio5: mdio@0x8c17000 {
9069 + status = "disabled";
9070 + compatible = "fsl,fman-memac-mdio";
9071 + reg = <0x0 0x8c17000 0x0 0x1000>;
9072 + device_type = "mdio";
9073 + little-endian;
9074 +
9075 + #address-cells = <1>;
9076 + #size-cells = <0>;
9077 + };
9078 +
9079 + pcs_mdio6: mdio@0x8c1b000 {
9080 + status = "disabled";
9081 + compatible = "fsl,fman-memac-mdio";
9082 + reg = <0x0 0x8c1b000 0x0 0x1000>;
9083 + device_type = "mdio";
9084 + little-endian;
9085 +
9086 + #address-cells = <1>;
9087 + #size-cells = <0>;
9088 + };
9089 +
9090 + pcs_mdio7: mdio@0x8c1f000 {
9091 + status = "disabled";
9092 + compatible = "fsl,fman-memac-mdio";
9093 + reg = <0x0 0x8c1f000 0x0 0x1000>;
9094 + device_type = "mdio";
9095 + little-endian;
9096 +
9097 + #address-cells = <1>;
9098 + #size-cells = <0>;
9099 + };
9100 +
9101 + pcs_mdio8: mdio@0x8c23000 {
9102 + status = "disabled";
9103 + compatible = "fsl,fman-memac-mdio";
9104 + reg = <0x0 0x8c23000 0x0 0x1000>;
9105 + device_type = "mdio";
9106 + little-endian;
9107 +
9108 + #address-cells = <1>;
9109 + #size-cells = <0>;
9110 + };
9111 +
9112 + i2c0: i2c@2000000 {
9113 + status = "disabled";
9114 + compatible = "fsl,vf610-i2c";
9115 + #address-cells = <1>;
9116 + #size-cells = <0>;
9117 + reg = <0x0 0x2000000 0x0 0x10000>;
9118 + interrupts = <0 34 0x4>; /* Level high type */
9119 + clock-names = "i2c";
9120 + clocks = <&clockgen 4 3>;
9121 + };
9122 +
9123 + i2c1: i2c@2010000 {
9124 + status = "disabled";
9125 + compatible = "fsl,vf610-i2c";
9126 + #address-cells = <1>;
9127 + #size-cells = <0>;
9128 + reg = <0x0 0x2010000 0x0 0x10000>;
9129 + interrupts = <0 34 0x4>; /* Level high type */
9130 + clock-names = "i2c";
9131 + clocks = <&clockgen 4 3>;
9132 + };
9133 +
9134 + i2c2: i2c@2020000 {
9135 + status = "disabled";
9136 + compatible = "fsl,vf610-i2c";
9137 + #address-cells = <1>;
9138 + #size-cells = <0>;
9139 + reg = <0x0 0x2020000 0x0 0x10000>;
9140 + interrupts = <0 35 0x4>; /* Level high type */
9141 + clock-names = "i2c";
9142 + clocks = <&clockgen 4 3>;
9143 + };
9144 +
9145 + i2c3: i2c@2030000 {
9146 + status = "disabled";
9147 + compatible = "fsl,vf610-i2c";
9148 + #address-cells = <1>;
9149 + #size-cells = <0>;
9150 + reg = <0x0 0x2030000 0x0 0x10000>;
9151 + interrupts = <0 35 0x4>; /* Level high type */
9152 + clock-names = "i2c";
9153 + clocks = <&clockgen 4 3>;
9154 + };
9155 +
9156 + ifc: ifc@2240000 {
9157 + compatible = "fsl,ifc", "simple-bus";
9158 + reg = <0x0 0x2240000 0x0 0x20000>;
9159 + interrupts = <0 21 0x4>; /* Level high type */
9160 + little-endian;
9161 + #address-cells = <2>;
9162 + #size-cells = <1>;
9163 +
9164 + ranges = <0 0 0x5 0x80000000 0x08000000
9165 + 2 0 0x5 0x30000000 0x00010000
9166 + 3 0 0x5 0x20000000 0x00010000>;
9167 + };
9168 +
9169 + qspi: quadspi@20c0000 {
9170 + status = "disabled";
9171 + compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
9172 + #address-cells = <1>;
9173 + #size-cells = <0>;
9174 + reg = <0x0 0x20c0000 0x0 0x10000>,
9175 + <0x0 0x20000000 0x0 0x10000000>;
9176 + reg-names = "QuadSPI", "QuadSPI-memory";
9177 + interrupts = <0 25 0x4>; /* Level high type */
9178 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
9179 + clock-names = "qspi_en", "qspi";
9180 + };
9181 +
9182 + pcie1: pcie@3400000 {
9183 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9184 + "snps,dw-pcie";
9185 + reg-names = "regs", "config";
9186 + interrupts = <0 108 0x4>; /* aer interrupt */
9187 + interrupt-names = "aer";
9188 + #address-cells = <3>;
9189 + #size-cells = <2>;
9190 + device_type = "pci";
9191 + dma-coherent;
9192 + num-lanes = <4>;
9193 + bus-range = <0x0 0xff>;
9194 + msi-parent = <&its>;
9195 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9196 + #interrupt-cells = <1>;
9197 + interrupt-map-mask = <0 0 0 7>;
9198 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
9199 + <0000 0 0 2 &gic 0 0 0 110 4>,
9200 + <0000 0 0 3 &gic 0 0 0 111 4>,
9201 + <0000 0 0 4 &gic 0 0 0 112 4>;
9202 + };
9203 +
9204 + pcie2: pcie@3500000 {
9205 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9206 + "snps,dw-pcie";
9207 + reg-names = "regs", "config";
9208 + interrupts = <0 113 0x4>; /* aer interrupt */
9209 + interrupt-names = "aer";
9210 + #address-cells = <3>;
9211 + #size-cells = <2>;
9212 + device_type = "pci";
9213 + dma-coherent;
9214 + num-lanes = <4>;
9215 + bus-range = <0x0 0xff>;
9216 + msi-parent = <&its>;
9217 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9218 + #interrupt-cells = <1>;
9219 + interrupt-map-mask = <0 0 0 7>;
9220 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
9221 + <0000 0 0 2 &gic 0 0 0 115 4>,
9222 + <0000 0 0 3 &gic 0 0 0 116 4>,
9223 + <0000 0 0 4 &gic 0 0 0 117 4>;
9224 + };
9225 +
9226 + pcie3: pcie@3600000 {
9227 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9228 + "snps,dw-pcie";
9229 + reg-names = "regs", "config";
9230 + interrupts = <0 118 0x4>; /* aer interrupt */
9231 + interrupt-names = "aer";
9232 + #address-cells = <3>;
9233 + #size-cells = <2>;
9234 + device_type = "pci";
9235 + dma-coherent;
9236 + num-lanes = <8>;
9237 + bus-range = <0x0 0xff>;
9238 + msi-parent = <&its>;
9239 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9240 + #interrupt-cells = <1>;
9241 + interrupt-map-mask = <0 0 0 7>;
9242 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
9243 + <0000 0 0 2 &gic 0 0 0 120 4>,
9244 + <0000 0 0 3 &gic 0 0 0 121 4>,
9245 + <0000 0 0 4 &gic 0 0 0 122 4>;
9246 + };
9247 +
9248 + pcie4: pcie@3700000 {
9249 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9250 + "snps,dw-pcie";
9251 + reg-names = "regs", "config";
9252 + interrupts = <0 123 0x4>; /* aer interrupt */
9253 + interrupt-names = "aer";
9254 + #address-cells = <3>;
9255 + #size-cells = <2>;
9256 + device_type = "pci";
9257 + dma-coherent;
9258 + num-lanes = <4>;
9259 + bus-range = <0x0 0xff>;
9260 + msi-parent = <&its>;
9261 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9262 + #interrupt-cells = <1>;
9263 + interrupt-map-mask = <0 0 0 7>;
9264 + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
9265 + <0000 0 0 2 &gic 0 0 0 125 4>,
9266 + <0000 0 0 3 &gic 0 0 0 126 4>,
9267 + <0000 0 0 4 &gic 0 0 0 127 4>;
9268 + };
9269 +
9270 + sata0: sata@3200000 {
9271 + status = "disabled";
9272 + compatible = "fsl,ls2080a-ahci";
9273 + reg = <0x0 0x3200000 0x0 0x10000>;
9274 + interrupts = <0 133 0x4>; /* Level high type */
9275 + clocks = <&clockgen 4 3>;
9276 + dma-coherent;
9277 + };
9278 +
9279 + sata1: sata@3210000 {
9280 + status = "disabled";
9281 + compatible = "fsl,ls2080a-ahci";
9282 + reg = <0x0 0x3210000 0x0 0x10000>;
9283 + interrupts = <0 136 0x4>; /* Level high type */
9284 + clocks = <&clockgen 4 3>;
9285 + dma-coherent;
9286 + };
9287 +
9288 + usb0: usb3@3100000 {
9289 + status = "disabled";
9290 + compatible = "snps,dwc3";
9291 + reg = <0x0 0x3100000 0x0 0x10000>;
9292 + interrupts = <0 80 0x4>; /* Level high type */
9293 + dr_mode = "host";
9294 + snps,quirk-frame-length-adjustment = <0x20>;
9295 + snps,dis_rxdet_inp3_quirk;
9296 + };
9297 +
9298 + usb1: usb3@3110000 {
9299 + status = "disabled";
9300 + compatible = "snps,dwc3";
9301 + reg = <0x0 0x3110000 0x0 0x10000>;
9302 + interrupts = <0 81 0x4>; /* Level high type */
9303 + dr_mode = "host";
9304 + snps,quirk-frame-length-adjustment = <0x20>;
9305 + snps,dis_rxdet_inp3_quirk;
9306 + };
9307 +
9308 + serdes1: serdes@1ea0000 {
9309 + reg = <0x0 0x1ea0000 0 0x00002000>;
9310 + };
9311 +
9312 + ccn@4000000 {
9313 + compatible = "arm,ccn-504";
9314 + reg = <0x0 0x04000000 0x0 0x01000000>;
9315 + interrupts = <0 12 4>;
9316 + };
9317 +
9318 + ftm0: ftm0@2800000 {
9319 + compatible = "fsl,ls208xa-ftm";
9320 + reg = <0x0 0x2800000 0x0 0x10000>,
9321 + <0x0 0x1e34050 0x0 0x4>;
9322 + interrupts = <0 44 4>;
9323 + reg-names = "ftm", "FlexTimer1";
9324 + };
9325 + };
9326 +
9327 + ddr1: memory-controller@1080000 {
9328 + compatible = "fsl,qoriq-memory-controller";
9329 + reg = <0x0 0x1080000 0x0 0x1000>;
9330 + interrupts = <0 17 0x4>;
9331 + little-endian;
9332 + };
9333 +
9334 + ddr2: memory-controller@1090000 {
9335 + compatible = "fsl,qoriq-memory-controller";
9336 + reg = <0x0 0x1090000 0x0 0x1000>;
9337 + interrupts = <0 18 0x4>;
9338 + little-endian;
9339 + };
9340 +};
9341 diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
9342 new file mode 100644
9343 index 00000000..14680adb
9344 --- /dev/null
9345 +++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
9346 @@ -0,0 +1,81 @@
9347 +/*
9348 + * QorIQ BMan Portals device tree
9349 + *
9350 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9351 + *
9352 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9353 + */
9354 +
9355 +&bportals {
9356 + #address-cells = <1>;
9357 + #size-cells = <1>;
9358 + compatible = "simple-bus";
9359 +
9360 + bman-portal@0 {
9361 + cell-index = <0>;
9362 + compatible = "fsl,bman-portal";
9363 + reg = <0x0 0x4000 0x4000000 0x4000>;
9364 + interrupts = <0 173 0x4>;
9365 + };
9366 +
9367 + bman-portal@10000 {
9368 + cell-index = <1>;
9369 + compatible = "fsl,bman-portal";
9370 + reg = <0x10000 0x4000 0x4010000 0x4000>;
9371 + interrupts = <0 175 0x4>;
9372 + };
9373 +
9374 + bman-portal@20000 {
9375 + cell-index = <2>;
9376 + compatible = "fsl,bman-portal";
9377 + reg = <0x20000 0x4000 0x4020000 0x4000>;
9378 + interrupts = <0 177 0x4>;
9379 + };
9380 +
9381 + bman-portal@30000 {
9382 + cell-index = <3>;
9383 + compatible = "fsl,bman-portal";
9384 + reg = <0x30000 0x4000 0x4030000 0x4000>;
9385 + interrupts = <0 179 0x4>;
9386 + };
9387 +
9388 + bman-portal@40000 {
9389 + cell-index = <4>;
9390 + compatible = "fsl,bman-portal";
9391 + reg = <0x40000 0x4000 0x4040000 0x4000>;
9392 + interrupts = <0 181 0x4>;
9393 + };
9394 +
9395 + bman-portal@50000 {
9396 + cell-index = <5>;
9397 + compatible = "fsl,bman-portal";
9398 + reg = <0x50000 0x4000 0x4050000 0x4000>;
9399 + interrupts = <0 183 0x4>;
9400 + };
9401 +
9402 + bman-portal@60000 {
9403 + cell-index = <6>;
9404 + compatible = "fsl,bman-portal";
9405 + reg = <0x60000 0x4000 0x4060000 0x4000>;
9406 + interrupts = <0 185 0x4>;
9407 + };
9408 +
9409 + bman-portal@70000 {
9410 + cell-index = <7>;
9411 + compatible = "fsl,bman-portal";
9412 + reg = <0x70000 0x4000 0x4070000 0x4000>;
9413 + interrupts = <0 187 0x4>;
9414 + };
9415 +
9416 + bman-portal@80000 {
9417 + cell-index = <8>;
9418 + compatible = "fsl,bman-portal";
9419 + reg = <0x80000 0x4000 0x4080000 0x4000>;
9420 + interrupts = <0 189 0x4>;
9421 + };
9422 +
9423 + bman-bpids@0 {
9424 + compatible = "fsl,bpid-range";
9425 + fsl,bpid-range = <32 32>;
9426 + };
9427 +};
9428 diff --git a/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
9429 new file mode 100644
9430 index 00000000..eb5af912
9431 --- /dev/null
9432 +++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
9433 @@ -0,0 +1,66 @@
9434 +/*
9435 + * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
9436 + *
9437 + * Copyright 2012 - 2015 Freescale Semiconductor Inc.
9438 + *
9439 + * Redistribution and use in source and binary forms, with or without
9440 + * modification, are permitted provided that the following conditions are met:
9441 + * * Redistributions of source code must retain the above copyright
9442 + * notice, this list of conditions and the following disclaimer.
9443 + * * Redistributions in binary form must reproduce the above copyright
9444 + * notice, this list of conditions and the following disclaimer in the
9445 + * documentation and/or other materials provided with the distribution.
9446 + * * Neither the name of Freescale Semiconductor nor the
9447 + * names of its contributors may be used to endorse or promote products
9448 + * derived from this software without specific prior written permission.
9449 + *
9450 + *
9451 + * ALTERNATIVELY, this software may be distributed under the terms of the
9452 + * GNU General Public License ("GPL") as published by the Free Software
9453 + * Foundation, either version 2 of that License or (at your option) any
9454 + * later version.
9455 + *
9456 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9457 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9458 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9459 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9460 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9461 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9462 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9463 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9464 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9465 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9466 + */
9467 +
9468 +fsldpaa: fsl,dpaa {
9469 + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
9470 + ethernet@0 {
9471 + compatible = "fsl,dpa-ethernet";
9472 + fsl,fman-mac = <&enet0>;
9473 + };
9474 + ethernet@1 {
9475 + compatible = "fsl,dpa-ethernet";
9476 + fsl,fman-mac = <&enet1>;
9477 + };
9478 + ethernet@2 {
9479 + compatible = "fsl,dpa-ethernet";
9480 + fsl,fman-mac = <&enet2>;
9481 + };
9482 + ethernet@3 {
9483 + compatible = "fsl,dpa-ethernet";
9484 + fsl,fman-mac = <&enet3>;
9485 + };
9486 + ethernet@4 {
9487 + compatible = "fsl,dpa-ethernet";
9488 + fsl,fman-mac = <&enet4>;
9489 + };
9490 + ethernet@5 {
9491 + compatible = "fsl,dpa-ethernet";
9492 + fsl,fman-mac = <&enet5>;
9493 + };
9494 + ethernet@8 {
9495 + compatible = "fsl,dpa-ethernet";
9496 + fsl,fman-mac = <&enet6>;
9497 + };
9498 +};
9499 +
9500 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
9501 new file mode 100644
9502 index 00000000..474bff5e
9503 --- /dev/null
9504 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
9505 @@ -0,0 +1,43 @@
9506 +/*
9507 + * QorIQ FMan v3 10g port #0 device tree
9508 + *
9509 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9510 + *
9511 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9512 + */
9513 +
9514 +fman@1a00000 {
9515 + fman0_rx_0x10: port@90000 {
9516 + cell-index = <0x10>;
9517 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9518 + reg = <0x90000 0x1000>;
9519 + fsl,fman-10g-port;
9520 + };
9521 +
9522 + fman0_tx_0x30: port@b0000 {
9523 + cell-index = <0x30>;
9524 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9525 + reg = <0xb0000 0x1000>;
9526 + fsl,fman-10g-port;
9527 + fsl,qman-channel-id = <0x800>;
9528 + };
9529 +
9530 + ethernet@f0000 {
9531 + cell-index = <0x8>;
9532 + compatible = "fsl,fman-memac";
9533 + reg = <0xf0000 0x1000>;
9534 + fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
9535 + pcsphy-handle = <&pcsphy6>;
9536 + };
9537 +
9538 + mdio@f1000 {
9539 + #address-cells = <1>;
9540 + #size-cells = <0>;
9541 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9542 + reg = <0xf1000 0x1000>;
9543 +
9544 + pcsphy6: ethernet-phy@0 {
9545 + reg = <0x0>;
9546 + };
9547 + };
9548 +};
9549 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
9550 new file mode 100644
9551 index 00000000..d4326f85
9552 --- /dev/null
9553 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
9554 @@ -0,0 +1,43 @@
9555 +/*
9556 + * QorIQ FMan v3 10g port #1 device tree
9557 + *
9558 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9559 + *
9560 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9561 + */
9562 +
9563 +fman@1a00000 {
9564 + fman0_rx_0x11: port@91000 {
9565 + cell-index = <0x11>;
9566 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9567 + reg = <0x91000 0x1000>;
9568 + fsl,fman-10g-port;
9569 + };
9570 +
9571 + fman0_tx_0x31: port@b1000 {
9572 + cell-index = <0x31>;
9573 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9574 + reg = <0xb1000 0x1000>;
9575 + fsl,fman-10g-port;
9576 + fsl,qman-channel-id = <0x801>;
9577 + };
9578 +
9579 + ethernet@f2000 {
9580 + cell-index = <0x9>;
9581 + compatible = "fsl,fman-memac";
9582 + reg = <0xf2000 0x1000>;
9583 + fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
9584 + pcsphy-handle = <&pcsphy7>;
9585 + };
9586 +
9587 + mdio@f3000 {
9588 + #address-cells = <1>;
9589 + #size-cells = <0>;
9590 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9591 + reg = <0xf3000 0x1000>;
9592 +
9593 + pcsphy7: ethernet-phy@0 {
9594 + reg = <0x0>;
9595 + };
9596 + };
9597 +};
9598 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
9599 new file mode 100644
9600 index 00000000..7170cab9
9601 --- /dev/null
9602 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
9603 @@ -0,0 +1,42 @@
9604 +/*
9605 + * QorIQ FMan v3 1g port #0 device tree
9606 + *
9607 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9608 + *
9609 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9610 + */
9611 +
9612 +fman@1a00000 {
9613 + fman0_rx_0x08: port@88000 {
9614 + cell-index = <0x8>;
9615 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9616 + reg = <0x88000 0x1000>;
9617 + };
9618 +
9619 + fman0_tx_0x28: port@a8000 {
9620 + cell-index = <0x28>;
9621 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9622 + reg = <0xa8000 0x1000>;
9623 + fsl,qman-channel-id = <0x802>;
9624 + };
9625 +
9626 + ethernet@e0000 {
9627 + cell-index = <0>;
9628 + compatible = "fsl,fman-memac";
9629 + reg = <0xe0000 0x1000>;
9630 + fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
9631 + ptp-timer = <&ptp_timer0>;
9632 + pcsphy-handle = <&pcsphy0>;
9633 + };
9634 +
9635 + mdio@e1000 {
9636 + #address-cells = <1>;
9637 + #size-cells = <0>;
9638 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9639 + reg = <0xe1000 0x1000>;
9640 +
9641 + pcsphy0: ethernet-phy@0 {
9642 + reg = <0x0>;
9643 + };
9644 + };
9645 +};
9646 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
9647 new file mode 100644
9648 index 00000000..c7eb8b6e
9649 --- /dev/null
9650 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
9651 @@ -0,0 +1,42 @@
9652 +/*
9653 + * QorIQ FMan v3 1g port #1 device tree
9654 + *
9655 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9656 + *
9657 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9658 + */
9659 +
9660 +fman@1a00000 {
9661 + fman0_rx_0x09: port@89000 {
9662 + cell-index = <0x9>;
9663 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9664 + reg = <0x89000 0x1000>;
9665 + };
9666 +
9667 + fman0_tx_0x29: port@a9000 {
9668 + cell-index = <0x29>;
9669 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9670 + reg = <0xa9000 0x1000>;
9671 + fsl,qman-channel-id = <0x803>;
9672 + };
9673 +
9674 + ethernet@e2000 {
9675 + cell-index = <1>;
9676 + compatible = "fsl,fman-memac";
9677 + reg = <0xe2000 0x1000>;
9678 + fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
9679 + ptp-timer = <&ptp_timer0>;
9680 + pcsphy-handle = <&pcsphy1>;
9681 + };
9682 +
9683 + mdio@e3000 {
9684 + #address-cells = <1>;
9685 + #size-cells = <0>;
9686 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9687 + reg = <0xe3000 0x1000>;
9688 +
9689 + pcsphy1: ethernet-phy@0 {
9690 + reg = <0x0>;
9691 + };
9692 + };
9693 +};
9694 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
9695 new file mode 100644
9696 index 00000000..56f9f0dd
9697 --- /dev/null
9698 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
9699 @@ -0,0 +1,42 @@
9700 +/*
9701 + * QorIQ FMan v3 1g port #2 device tree
9702 + *
9703 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9704 + *
9705 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9706 + */
9707 +
9708 +fman@1a00000 {
9709 + fman0_rx_0x0a: port@8a000 {
9710 + cell-index = <0xa>;
9711 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9712 + reg = <0x8a000 0x1000>;
9713 + };
9714 +
9715 + fman0_tx_0x2a: port@aa000 {
9716 + cell-index = <0x2a>;
9717 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9718 + reg = <0xaa000 0x1000>;
9719 + fsl,qman-channel-id = <0x804>;
9720 + };
9721 +
9722 + ethernet@e4000 {
9723 + cell-index = <2>;
9724 + compatible = "fsl,fman-memac";
9725 + reg = <0xe4000 0x1000>;
9726 + fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
9727 + ptp-timer = <&ptp_timer0>;
9728 + pcsphy-handle = <&pcsphy2>;
9729 + };
9730 +
9731 + mdio@e5000 {
9732 + #address-cells = <1>;
9733 + #size-cells = <0>;
9734 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9735 + reg = <0xe5000 0x1000>;
9736 +
9737 + pcsphy2: ethernet-phy@0 {
9738 + reg = <0x0>;
9739 + };
9740 + };
9741 +};
9742 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
9743 new file mode 100644
9744 index 00000000..bbe7dbaf
9745 --- /dev/null
9746 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
9747 @@ -0,0 +1,42 @@
9748 +/*
9749 + * QorIQ FMan v3 1g port #3 device tree
9750 + *
9751 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9752 + *
9753 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9754 + */
9755 +
9756 +fman@1a00000 {
9757 + fman0_rx_0x0b: port@8b000 {
9758 + cell-index = <0xb>;
9759 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9760 + reg = <0x8b000 0x1000>;
9761 + };
9762 +
9763 + fman0_tx_0x2b: port@ab000 {
9764 + cell-index = <0x2b>;
9765 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9766 + reg = <0xab000 0x1000>;
9767 + fsl,qman-channel-id = <0x805>;
9768 + };
9769 +
9770 + ethernet@e6000 {
9771 + cell-index = <3>;
9772 + compatible = "fsl,fman-memac";
9773 + reg = <0xe6000 0x1000>;
9774 + fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
9775 + ptp-timer = <&ptp_timer0>;
9776 + pcsphy-handle = <&pcsphy3>;
9777 + };
9778 +
9779 + mdio@e7000 {
9780 + #address-cells = <1>;
9781 + #size-cells = <0>;
9782 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9783 + reg = <0xe7000 0x1000>;
9784 +
9785 + pcsphy3: ethernet-phy@0 {
9786 + reg = <0x0>;
9787 + };
9788 + };
9789 +};
9790 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
9791 new file mode 100644
9792 index 00000000..ead4f062
9793 --- /dev/null
9794 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
9795 @@ -0,0 +1,42 @@
9796 +/*
9797 + * QorIQ FMan v3 1g port #4 device tree
9798 + *
9799 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9800 + *
9801 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9802 + */
9803 +
9804 +fman@1a00000 {
9805 + fman0_rx_0x0c: port@8c000 {
9806 + cell-index = <0xc>;
9807 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9808 + reg = <0x8c000 0x1000>;
9809 + };
9810 +
9811 + fman0_tx_0x2c: port@ac000 {
9812 + cell-index = <0x2c>;
9813 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9814 + reg = <0xac000 0x1000>;
9815 + fsl,qman-channel-id = <0x806>;
9816 + };
9817 +
9818 + ethernet@e8000 {
9819 + cell-index = <4>;
9820 + compatible = "fsl,fman-memac";
9821 + reg = <0xe8000 0x1000>;
9822 + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
9823 + ptp-timer = <&ptp_timer0>;
9824 + pcsphy-handle = <&pcsphy4>;
9825 + };
9826 +
9827 + mdio@e9000 {
9828 + #address-cells = <1>;
9829 + #size-cells = <0>;
9830 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9831 + reg = <0xe9000 0x1000>;
9832 +
9833 + pcsphy4: ethernet-phy@0 {
9834 + reg = <0x0>;
9835 + };
9836 + };
9837 +};
9838 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
9839 new file mode 100644
9840 index 00000000..389eadaf
9841 --- /dev/null
9842 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
9843 @@ -0,0 +1,42 @@
9844 +/*
9845 + * QorIQ FMan v3 1g port #5 device tree
9846 + *
9847 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9848 + *
9849 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9850 + */
9851 +
9852 +fman@1a00000 {
9853 + fman0_rx_0x0d: port@8d000 {
9854 + cell-index = <0xd>;
9855 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9856 + reg = <0x8d000 0x1000>;
9857 + };
9858 +
9859 + fman0_tx_0x2d: port@ad000 {
9860 + cell-index = <0x2d>;
9861 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9862 + reg = <0xad000 0x1000>;
9863 + fsl,qman-channel-id = <0x807>;
9864 + };
9865 +
9866 + ethernet@ea000 {
9867 + cell-index = <5>;
9868 + compatible = "fsl,fman-memac";
9869 + reg = <0xea000 0x1000>;
9870 + fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
9871 + ptp-timer = <&ptp_timer0>;
9872 + pcsphy-handle = <&pcsphy5>;
9873 + };
9874 +
9875 + mdio@eb000 {
9876 + #address-cells = <1>;
9877 + #size-cells = <0>;
9878 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9879 + reg = <0xeb000 0x1000>;
9880 +
9881 + pcsphy5: ethernet-phy@0 {
9882 + reg = <0x0>;
9883 + };
9884 + };
9885 +};
9886 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
9887 new file mode 100644
9888 index 00000000..2d0df20d
9889 --- /dev/null
9890 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
9891 @@ -0,0 +1,47 @@
9892 +/*
9893 + * QorIQ FMan v3 OH ports device tree
9894 + *
9895 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9896 + *
9897 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9898 + */
9899 +
9900 +fman@1a00000 {
9901 +
9902 + fman0_oh1: port@82000 {
9903 + cell-index = <0>;
9904 + compatible = "fsl,fman-port-oh";
9905 + reg = <0x82000 0x1000>;
9906 + };
9907 +
9908 + fman0_oh2: port@83000 {
9909 + cell-index = <1>;
9910 + compatible = "fsl,fman-port-oh";
9911 + reg = <0x83000 0x1000>;
9912 + };
9913 +
9914 + fman0_oh3: port@84000 {
9915 + cell-index = <2>;
9916 + compatible = "fsl,fman-port-oh";
9917 + reg = <0x84000 0x1000>;
9918 + };
9919 +
9920 + fman0_oh4: port@85000 {
9921 + cell-index = <3>;
9922 + compatible = "fsl,fman-port-oh";
9923 + reg = <0x85000 0x1000>;
9924 + };
9925 +
9926 + fman0_oh5: port@86000 {
9927 + cell-index = <4>;
9928 + compatible = "fsl,fman-port-oh";
9929 + reg = <0x86000 0x1000>;
9930 + };
9931 +
9932 + fman0_oh6: port@87000 {
9933 + cell-index = <5>;
9934 + compatible = "fsl,fman-port-oh";
9935 + reg = <0x87000 0x1000>;
9936 + };
9937 +
9938 +};
9939 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
9940 new file mode 100644
9941 index 00000000..8e089f0c
9942 --- /dev/null
9943 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
9944 @@ -0,0 +1,130 @@
9945 +/*
9946 + * QorIQ FMan v3 device tree
9947 + *
9948 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9949 + *
9950 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9951 + */
9952 +
9953 +fman0: fman@1a00000 {
9954 + #address-cells = <1>;
9955 + #size-cells = <1>;
9956 + cell-index = <0>;
9957 + compatible = "fsl,fman";
9958 + ranges = <0x0 0x00 0x1a00000 0x100000>;
9959 + reg = <0x0 0x1a00000 0x0 0x100000>;
9960 + interrupts = <0 44 0x4>, <0 45 0x4>;
9961 + clocks = <&clockgen 3 0>;
9962 + clock-names = "fmanclk";
9963 + fsl,qman-channel-range = <0x800 0x10>;
9964 +
9965 + cc {
9966 + compatible = "fsl,fman-cc";
9967 + };
9968 +
9969 + muram@0 {
9970 + compatible = "fsl,fman-muram";
9971 + reg = <0x0 0x60000>;
9972 + };
9973 +
9974 + bmi@80000 {
9975 + compatible = "fsl,fman-bmi";
9976 + reg = <0x80000 0x400>;
9977 + };
9978 +
9979 + qmi@80400 {
9980 + compatible = "fsl,fman-qmi";
9981 + reg = <0x80400 0x400>;
9982 + };
9983 +
9984 + fman0_oh_0x2: port@82000 {
9985 + cell-index = <0x2>;
9986 + compatible = "fsl,fman-v3-port-oh";
9987 + reg = <0x82000 0x1000>;
9988 + fsl,qman-channel-id = <0x809>;
9989 + };
9990 +
9991 + fman0_oh_0x3: port@83000 {
9992 + cell-index = <0x3>;
9993 + compatible = "fsl,fman-v3-port-oh";
9994 + reg = <0x83000 0x1000>;
9995 + fsl,qman-channel-id = <0x80a>;
9996 + };
9997 +
9998 + fman0_oh_0x4: port@84000 {
9999 + cell-index = <0x4>;
10000 + compatible = "fsl,fman-v3-port-oh";
10001 + reg = <0x84000 0x1000>;
10002 + fsl,qman-channel-id = <0x80b>;
10003 + };
10004 +
10005 + fman0_oh_0x5: port@85000 {
10006 + cell-index = <0x5>;
10007 + compatible = "fsl,fman-v3-port-oh";
10008 + reg = <0x85000 0x1000>;
10009 + fsl,qman-channel-id = <0x80c>;
10010 + };
10011 +
10012 + fman0_oh_0x6: port@86000 {
10013 + cell-index = <0x6>;
10014 + compatible = "fsl,fman-v3-port-oh";
10015 + reg = <0x86000 0x1000>;
10016 + fsl,qman-channel-id = <0x80d>;
10017 + };
10018 +
10019 + fman0_oh_0x7: port@87000 {
10020 + cell-index = <0x7>;
10021 + compatible = "fsl,fman-v3-port-oh";
10022 + reg = <0x87000 0x1000>;
10023 + fsl,qman-channel-id = <0x80e>;
10024 + };
10025 +
10026 + policer@c0000 {
10027 + compatible = "fsl,fman-policer";
10028 + reg = <0xc0000 0x1000>;
10029 + };
10030 +
10031 + keygen@c1000 {
10032 + compatible = "fsl,fman-keygen";
10033 + reg = <0xc1000 0x1000>;
10034 + };
10035 +
10036 + dma@c2000 {
10037 + compatible = "fsl,fman-dma";
10038 + reg = <0xc2000 0x1000>;
10039 + };
10040 +
10041 + fpm@c3000 {
10042 + compatible = "fsl,fman-fpm";
10043 + reg = <0xc3000 0x1000>;
10044 + };
10045 +
10046 + parser@c7000 {
10047 + compatible = "fsl,fman-parser";
10048 + reg = <0xc7000 0x1000>;
10049 + };
10050 +
10051 + vsps@dc000 {
10052 + compatible = "fsl,fman-vsps";
10053 + reg = <0xdc000 0x1000>;
10054 + };
10055 +
10056 + mdio0: mdio@fc000 {
10057 + #address-cells = <1>;
10058 + #size-cells = <0>;
10059 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10060 + reg = <0xfc000 0x1000>;
10061 + };
10062 +
10063 + xmdio0: mdio@fd000 {
10064 + #address-cells = <1>;
10065 + #size-cells = <0>;
10066 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
10067 + reg = <0xfd000 0x1000>;
10068 + };
10069 +
10070 + ptp_timer0: ptp-timer@fe000 {
10071 + compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
10072 + reg = <0xfe000 0x1000>;
10073 + };
10074 +};
10075 diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
10076 new file mode 100644
10077 index 00000000..4f7edf48
10078 --- /dev/null
10079 +++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
10080 @@ -0,0 +1,104 @@
10081 +/*
10082 + * QorIQ QMan Portals device tree
10083 + *
10084 + * Copyright 2011-2016 Freescale Semiconductor Inc.
10085 + *
10086 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
10087 + */
10088 +
10089 +&qportals {
10090 + #address-cells = <1>;
10091 + #size-cells = <1>;
10092 + compatible = "simple-bus";
10093 +
10094 + qportal0: qman-portal@0 {
10095 + compatible = "fsl,qman-portal";
10096 + reg = <0x0 0x4000 0x4000000 0x4000>;
10097 + interrupts = <0 172 0x4>;
10098 + cell-index = <0>;
10099 + };
10100 +
10101 + qportal1: qman-portal@10000 {
10102 + compatible = "fsl,qman-portal";
10103 + reg = <0x10000 0x4000 0x4010000 0x4000>;
10104 + interrupts = <0 174 0x4>;
10105 + cell-index = <1>;
10106 + };
10107 +
10108 + qportal2: qman-portal@20000 {
10109 + compatible = "fsl,qman-portal";
10110 + reg = <0x20000 0x4000 0x4020000 0x4000>;
10111 + interrupts = <0 176 0x4>;
10112 + cell-index = <2>;
10113 + };
10114 +
10115 + qportal3: qman-portal@30000 {
10116 + compatible = "fsl,qman-portal";
10117 + reg = <0x30000 0x4000 0x4030000 0x4000>;
10118 + interrupts = <0 178 0x4>;
10119 + cell-index = <3>;
10120 + };
10121 +
10122 + qportal4: qman-portal@40000 {
10123 + compatible = "fsl,qman-portal";
10124 + reg = <0x40000 0x4000 0x4040000 0x4000>;
10125 + interrupts = <0 180 0x4>;
10126 + cell-index = <4>;
10127 + };
10128 +
10129 + qportal5: qman-portal@50000 {
10130 + compatible = "fsl,qman-portal";
10131 + reg = <0x50000 0x4000 0x4050000 0x4000>;
10132 + interrupts = <0 182 0x4>;
10133 + cell-index = <5>;
10134 + };
10135 +
10136 + qportal6: qman-portal@60000 {
10137 + compatible = "fsl,qman-portal";
10138 + reg = <0x60000 0x4000 0x4060000 0x4000>;
10139 + interrupts = <0 184 0x4>;
10140 + cell-index = <6>;
10141 + };
10142 +
10143 + qportal7: qman-portal@70000 {
10144 + compatible = "fsl,qman-portal";
10145 + reg = <0x70000 0x4000 0x4070000 0x4000>;
10146 + interrupts = <0 186 0x4>;
10147 + cell-index = <7>;
10148 + };
10149 +
10150 + qportal8: qman-portal@80000 {
10151 + compatible = "fsl,qman-portal";
10152 + reg = <0x80000 0x4000 0x4080000 0x4000>;
10153 + interrupts = <0 188 0x4>;
10154 + cell-index = <8>;
10155 + };
10156 +
10157 + qman-fqids@0 {
10158 + compatible = "fsl,fqid-range";
10159 + fsl,fqid-range = <256 256>;
10160 + };
10161 +
10162 + qman-fqids@1 {
10163 + compatible = "fsl,fqid-range";
10164 + fsl,fqid-range = <32768 32768>;
10165 + };
10166 +
10167 + qman-pools@0 {
10168 + compatible = "fsl,pool-channel-range";
10169 + fsl,pool-channel-range = <0x401 0xf>;
10170 + };
10171 +
10172 + qman-cgrids@0 {
10173 + compatible = "fsl,cgrid-range";
10174 + fsl,cgrid-range = <0 256>;
10175 + };
10176 +
10177 + qman-ceetm@0 {
10178 + compatible = "fsl,qman-ceetm";
10179 + fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
10180 + fsl,ceetm-sp-range = <0 12>;
10181 + fsl,ceetm-lni-range = <0 8>;
10182 + fsl,ceetm-channel-range = <0 32>;
10183 + };
10184 +};
10185 diff --git a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10186 index 5022432e..65701ada 100644
10187 --- a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10188 +++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
10189 @@ -38,51 +38,61 @@
10190 compatible = "simple-bus";
10191
10192 bman-portal@0 {
10193 + cell-index = <0>;
10194 compatible = "fsl,bman-portal";
10195 reg = <0x0 0x4000>, <0x100000 0x1000>;
10196 interrupts = <105 2 0 0>;
10197 };
10198 bman-portal@4000 {
10199 + cell-index = <1>;
10200 compatible = "fsl,bman-portal";
10201 reg = <0x4000 0x4000>, <0x101000 0x1000>;
10202 interrupts = <107 2 0 0>;
10203 };
10204 bman-portal@8000 {
10205 + cell-index = <2>;
10206 compatible = "fsl,bman-portal";
10207 reg = <0x8000 0x4000>, <0x102000 0x1000>;
10208 interrupts = <109 2 0 0>;
10209 };
10210 bman-portal@c000 {
10211 + cell-index = <3>;
10212 compatible = "fsl,bman-portal";
10213 reg = <0xc000 0x4000>, <0x103000 0x1000>;
10214 interrupts = <111 2 0 0>;
10215 };
10216 bman-portal@10000 {
10217 + cell-index = <4>;
10218 compatible = "fsl,bman-portal";
10219 reg = <0x10000 0x4000>, <0x104000 0x1000>;
10220 interrupts = <113 2 0 0>;
10221 };
10222 bman-portal@14000 {
10223 + cell-index = <5>;
10224 compatible = "fsl,bman-portal";
10225 reg = <0x14000 0x4000>, <0x105000 0x1000>;
10226 interrupts = <115 2 0 0>;
10227 };
10228 bman-portal@18000 {
10229 + cell-index = <6>;
10230 compatible = "fsl,bman-portal";
10231 reg = <0x18000 0x4000>, <0x106000 0x1000>;
10232 interrupts = <117 2 0 0>;
10233 };
10234 bman-portal@1c000 {
10235 + cell-index = <7>;
10236 compatible = "fsl,bman-portal";
10237 reg = <0x1c000 0x4000>, <0x107000 0x1000>;
10238 interrupts = <119 2 0 0>;
10239 };
10240 bman-portal@20000 {
10241 + cell-index = <8>;
10242 compatible = "fsl,bman-portal";
10243 reg = <0x20000 0x4000>, <0x108000 0x1000>;
10244 interrupts = <121 2 0 0>;
10245 };
10246 bman-portal@24000 {
10247 + cell-index = <9>;
10248 compatible = "fsl,bman-portal";
10249 reg = <0x24000 0x4000>, <0x109000 0x1000>;
10250 interrupts = <123 2 0 0>;
10251 diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10252 index c288f3c6..dd200e28 100644
10253 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10254 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10255 @@ -35,14 +35,14 @@
10256 fman@400000 {
10257 fman0_rx_0x10: port@90000 {
10258 cell-index = <0x10>;
10259 - compatible = "fsl,fman-v3-port-rx";
10260 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10261 reg = <0x90000 0x1000>;
10262 fsl,fman-10g-port;
10263 };
10264
10265 fman0_tx_0x30: port@b0000 {
10266 cell-index = <0x30>;
10267 - compatible = "fsl,fman-v3-port-tx";
10268 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10269 reg = <0xb0000 0x1000>;
10270 fsl,fman-10g-port;
10271 };
10272 diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10273 index 94a76982..365770c9 100644
10274 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10275 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10276 @@ -35,14 +35,14 @@
10277 fman@400000 {
10278 fman0_rx_0x11: port@91000 {
10279 cell-index = <0x11>;
10280 - compatible = "fsl,fman-v3-port-rx";
10281 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10282 reg = <0x91000 0x1000>;
10283 fsl,fman-10g-port;
10284 };
10285
10286 fman0_tx_0x31: port@b1000 {
10287 cell-index = <0x31>;
10288 - compatible = "fsl,fman-v3-port-tx";
10289 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10290 reg = <0xb1000 0x1000>;
10291 fsl,fman-10g-port;
10292 };
10293 --
10294 2.14.1
10295
OpenWrt Source Repository