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c3dcd73b6029dd4a369974bab797e55a17571c98
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 702-pci-support-layerscape.patch
1 From c4813da334b0c31e9c55eea015f1e898e84ff45b Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 11:04:10 +0800
4 Subject: [PATCH] pci: support layerscape
5
6 This is a integrated patch for layerscape pcie support.
7
8 Signed-off-by: Po Liu <po.liu@nxp.com>
9 Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
10 Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
11 Signed-off-by: hongbo.wang <hongbo.wang@nxp.com>
12 Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
13 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
14 Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
15 Signed-off-by: Christoph Hellwig <hch@lst.de>
16 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
17 ---
18 drivers/irqchip/irq-ls-scfg-msi.c | 256 +++++++--
19 drivers/pci/host/Makefile | 2 +-
20 drivers/pci/host/pci-layerscape-ep-debugfs.c | 758 +++++++++++++++++++++++++++
21 drivers/pci/host/pci-layerscape-ep.c | 309 +++++++++++
22 drivers/pci/host/pci-layerscape-ep.h | 115 ++++
23 drivers/pci/host/pci-layerscape.c | 37 +-
24 drivers/pci/host/pcie-designware.c | 6 +
25 drivers/pci/host/pcie-designware.h | 1 +
26 drivers/pci/pcie/portdrv_core.c | 181 +++----
27 include/linux/pci.h | 1 +
28 10 files changed, 1518 insertions(+), 148 deletions(-)
29 create mode 100644 drivers/pci/host/pci-layerscape-ep-debugfs.c
30 create mode 100644 drivers/pci/host/pci-layerscape-ep.c
31 create mode 100644 drivers/pci/host/pci-layerscape-ep.h
32
33 diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
34 index 02cca74c..119f4ef0 100644
35 --- a/drivers/irqchip/irq-ls-scfg-msi.c
36 +++ b/drivers/irqchip/irq-ls-scfg-msi.c
37 @@ -17,13 +17,32 @@
38 #include <linux/irq.h>
39 #include <linux/irqchip/chained_irq.h>
40 #include <linux/irqdomain.h>
41 +#include <linux/of_irq.h>
42 #include <linux/of_pci.h>
43 #include <linux/of_platform.h>
44 #include <linux/spinlock.h>
45
46 -#define MSI_MAX_IRQS 32
47 -#define MSI_IBS_SHIFT 3
48 -#define MSIR 4
49 +#define MSI_IRQS_PER_MSIR 32
50 +#define MSI_MSIR_OFFSET 4
51 +
52 +#define MSI_LS1043V1_1_IRQS_PER_MSIR 8
53 +#define MSI_LS1043V1_1_MSIR_OFFSET 0x10
54 +
55 +struct ls_scfg_msi_cfg {
56 + u32 ibs_shift; /* Shift of interrupt bit select */
57 + u32 msir_irqs; /* The irq number per MSIR */
58 + u32 msir_base; /* The base address of MSIR */
59 +};
60 +
61 +struct ls_scfg_msir {
62 + struct ls_scfg_msi *msi_data;
63 + unsigned int index;
64 + unsigned int gic_irq;
65 + unsigned int bit_start;
66 + unsigned int bit_end;
67 + unsigned int srs; /* Shared interrupt register select */
68 + void __iomem *reg;
69 +};
70
71 struct ls_scfg_msi {
72 spinlock_t lock;
73 @@ -32,8 +51,11 @@ struct ls_scfg_msi {
74 struct irq_domain *msi_domain;
75 void __iomem *regs;
76 phys_addr_t msiir_addr;
77 - int irq;
78 - DECLARE_BITMAP(used, MSI_MAX_IRQS);
79 + struct ls_scfg_msi_cfg *cfg;
80 + u32 msir_num;
81 + struct ls_scfg_msir *msir;
82 + u32 irqs_num;
83 + unsigned long *used;
84 };
85
86 static struct irq_chip ls_scfg_msi_irq_chip = {
87 @@ -49,19 +71,56 @@ static struct msi_domain_info ls_scfg_msi_domain_info = {
88 .chip = &ls_scfg_msi_irq_chip,
89 };
90
91 +static int msi_affinity_flag = 1;
92 +
93 +static int __init early_parse_ls_scfg_msi(char *p)
94 +{
95 + if (p && strncmp(p, "no-affinity", 11) == 0)
96 + msi_affinity_flag = 0;
97 + else
98 + msi_affinity_flag = 1;
99 +
100 + return 0;
101 +}
102 +early_param("lsmsi", early_parse_ls_scfg_msi);
103 +
104 static void ls_scfg_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
105 {
106 struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(data);
107
108 msg->address_hi = upper_32_bits(msi_data->msiir_addr);
109 msg->address_lo = lower_32_bits(msi_data->msiir_addr);
110 - msg->data = data->hwirq << MSI_IBS_SHIFT;
111 + msg->data = data->hwirq;
112 +
113 + if (msi_affinity_flag)
114 + msg->data |= cpumask_first(data->common->affinity);
115 }
116
117 static int ls_scfg_msi_set_affinity(struct irq_data *irq_data,
118 const struct cpumask *mask, bool force)
119 {
120 - return -EINVAL;
121 + struct ls_scfg_msi *msi_data = irq_data_get_irq_chip_data(irq_data);
122 + u32 cpu;
123 +
124 + if (!msi_affinity_flag)
125 + return -EINVAL;
126 +
127 + if (!force)
128 + cpu = cpumask_any_and(mask, cpu_online_mask);
129 + else
130 + cpu = cpumask_first(mask);
131 +
132 + if (cpu >= msi_data->msir_num)
133 + return -EINVAL;
134 +
135 + if (msi_data->msir[cpu].gic_irq <= 0) {
136 + pr_warn("cannot bind the irq to cpu%d\n", cpu);
137 + return -EINVAL;
138 + }
139 +
140 + cpumask_copy(irq_data->common->affinity, mask);
141 +
142 + return IRQ_SET_MASK_OK;
143 }
144
145 static struct irq_chip ls_scfg_msi_parent_chip = {
146 @@ -81,8 +140,8 @@ static int ls_scfg_msi_domain_irq_alloc(struct irq_domain *domain,
147 WARN_ON(nr_irqs != 1);
148
149 spin_lock(&msi_data->lock);
150 - pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS);
151 - if (pos < MSI_MAX_IRQS)
152 + pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
153 + if (pos < msi_data->irqs_num)
154 __set_bit(pos, msi_data->used);
155 else
156 err = -ENOSPC;
157 @@ -106,7 +165,7 @@ static void ls_scfg_msi_domain_irq_free(struct irq_domain *domain,
158 int pos;
159
160 pos = d->hwirq;
161 - if (pos < 0 || pos >= MSI_MAX_IRQS) {
162 + if (pos < 0 || pos >= msi_data->irqs_num) {
163 pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
164 return;
165 }
166 @@ -123,15 +182,22 @@ static const struct irq_domain_ops ls_scfg_msi_domain_ops = {
167
168 static void ls_scfg_msi_irq_handler(struct irq_desc *desc)
169 {
170 - struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc);
171 + struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
172 + struct ls_scfg_msi *msi_data = msir->msi_data;
173 unsigned long val;
174 - int pos, virq;
175 + int pos, size, virq, hwirq;
176
177 chained_irq_enter(irq_desc_get_chip(desc), desc);
178
179 - val = ioread32be(msi_data->regs + MSIR);
180 - for_each_set_bit(pos, &val, MSI_MAX_IRQS) {
181 - virq = irq_find_mapping(msi_data->parent, (31 - pos));
182 + val = ioread32be(msir->reg);
183 +
184 + pos = msir->bit_start;
185 + size = msir->bit_end + 1;
186 +
187 + for_each_set_bit_from(pos, &val, size) {
188 + hwirq = ((msir->bit_end - pos) << msi_data->cfg->ibs_shift) |
189 + msir->srs;
190 + virq = irq_find_mapping(msi_data->parent, hwirq);
191 if (virq)
192 generic_handle_irq(virq);
193 }
194 @@ -143,7 +209,7 @@ static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
195 {
196 /* Initialize MSI domain parent */
197 msi_data->parent = irq_domain_add_linear(NULL,
198 - MSI_MAX_IRQS,
199 + msi_data->irqs_num,
200 &ls_scfg_msi_domain_ops,
201 msi_data);
202 if (!msi_data->parent) {
203 @@ -164,16 +230,117 @@ static int ls_scfg_msi_domains_init(struct ls_scfg_msi *msi_data)
204 return 0;
205 }
206
207 +static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int index)
208 +{
209 + struct ls_scfg_msir *msir;
210 + int virq, i, hwirq;
211 +
212 + virq = platform_get_irq(msi_data->pdev, index);
213 + if (virq <= 0)
214 + return -ENODEV;
215 +
216 + msir = &msi_data->msir[index];
217 + msir->index = index;
218 + msir->msi_data = msi_data;
219 + msir->gic_irq = virq;
220 + msir->reg = msi_data->regs + msi_data->cfg->msir_base + 4 * index;
221 +
222 + if (msi_data->cfg->msir_irqs == MSI_LS1043V1_1_IRQS_PER_MSIR) {
223 + msir->bit_start = 32 - ((msir->index + 1) *
224 + MSI_LS1043V1_1_IRQS_PER_MSIR);
225 + msir->bit_end = msir->bit_start +
226 + MSI_LS1043V1_1_IRQS_PER_MSIR - 1;
227 + } else {
228 + msir->bit_start = 0;
229 + msir->bit_end = msi_data->cfg->msir_irqs - 1;
230 + }
231 +
232 + irq_set_chained_handler_and_data(msir->gic_irq,
233 + ls_scfg_msi_irq_handler,
234 + msir);
235 +
236 + if (msi_affinity_flag) {
237 + /* Associate MSIR interrupt to the cpu */
238 + irq_set_affinity(msir->gic_irq, get_cpu_mask(index));
239 + msir->srs = 0; /* This value is determined by the CPU */
240 + } else
241 + msir->srs = index;
242 +
243 + /* Release the hwirqs corresponding to this MSIR */
244 + if (!msi_affinity_flag || msir->index == 0) {
245 + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
246 + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
247 + bitmap_clear(msi_data->used, hwirq, 1);
248 + }
249 + }
250 +
251 + return 0;
252 +}
253 +
254 +static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir)
255 +{
256 + struct ls_scfg_msi *msi_data = msir->msi_data;
257 + int i, hwirq;
258 +
259 + if (msir->gic_irq > 0)
260 + irq_set_chained_handler_and_data(msir->gic_irq, NULL, NULL);
261 +
262 + for (i = 0; i < msi_data->cfg->msir_irqs; i++) {
263 + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
264 + bitmap_set(msi_data->used, hwirq, 1);
265 + }
266 +
267 + return 0;
268 +}
269 +
270 +static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
271 + .ibs_shift = 3,
272 + .msir_irqs = MSI_IRQS_PER_MSIR,
273 + .msir_base = MSI_MSIR_OFFSET,
274 +};
275 +
276 +static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
277 + .ibs_shift = 2,
278 + .msir_irqs = MSI_IRQS_PER_MSIR,
279 + .msir_base = MSI_MSIR_OFFSET,
280 +};
281 +
282 +static struct ls_scfg_msi_cfg ls1043_v1_1_msi_cfg = {
283 + .ibs_shift = 2,
284 + .msir_irqs = MSI_LS1043V1_1_IRQS_PER_MSIR,
285 + .msir_base = MSI_LS1043V1_1_MSIR_OFFSET,
286 +};
287 +
288 +static const struct of_device_id ls_scfg_msi_id[] = {
289 + /* The following two misspelled compatibles are obsolete */
290 + { .compatible = "fsl,1s1021a-msi", .data = &ls1021_msi_cfg},
291 + { .compatible = "fsl,1s1043a-msi", .data = &ls1021_msi_cfg},
292 +
293 + { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
294 + { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
295 + { .compatible = "fsl,ls1043a-v1.1-msi", .data = &ls1043_v1_1_msi_cfg },
296 + { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
297 + {},
298 +};
299 +MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
300 +
301 static int ls_scfg_msi_probe(struct platform_device *pdev)
302 {
303 + const struct of_device_id *match;
304 struct ls_scfg_msi *msi_data;
305 struct resource *res;
306 - int ret;
307 + int i, ret;
308 +
309 + match = of_match_device(ls_scfg_msi_id, &pdev->dev);
310 + if (!match)
311 + return -ENODEV;
312
313 msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL);
314 if (!msi_data)
315 return -ENOMEM;
316
317 + msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data;
318 +
319 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
320 msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
321 if (IS_ERR(msi_data->regs)) {
322 @@ -182,23 +349,48 @@ static int ls_scfg_msi_probe(struct platform_device *pdev)
323 }
324 msi_data->msiir_addr = res->start;
325
326 - msi_data->irq = platform_get_irq(pdev, 0);
327 - if (msi_data->irq <= 0) {
328 - dev_err(&pdev->dev, "failed to get MSI irq\n");
329 - return -ENODEV;
330 - }
331 -
332 msi_data->pdev = pdev;
333 spin_lock_init(&msi_data->lock);
334
335 + msi_data->irqs_num = MSI_IRQS_PER_MSIR *
336 + (1 << msi_data->cfg->ibs_shift);
337 + msi_data->used = devm_kcalloc(&pdev->dev,
338 + BITS_TO_LONGS(msi_data->irqs_num),
339 + sizeof(*msi_data->used),
340 + GFP_KERNEL);
341 + if (!msi_data->used)
342 + return -ENOMEM;
343 + /*
344 + * Reserve all the hwirqs
345 + * The available hwirqs will be released in ls1_msi_setup_hwirq()
346 + */
347 + bitmap_set(msi_data->used, 0, msi_data->irqs_num);
348 +
349 + msi_data->msir_num = of_irq_count(pdev->dev.of_node);
350 +
351 + if (msi_affinity_flag) {
352 + u32 cpu_num;
353 +
354 + cpu_num = num_possible_cpus();
355 + if (msi_data->msir_num >= cpu_num)
356 + msi_data->msir_num = cpu_num;
357 + else
358 + msi_affinity_flag = 0;
359 + }
360 +
361 + msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
362 + sizeof(*msi_data->msir),
363 + GFP_KERNEL);
364 + if (!msi_data->msir)
365 + return -ENOMEM;
366 +
367 + for (i = 0; i < msi_data->msir_num; i++)
368 + ls_scfg_msi_setup_hwirq(msi_data, i);
369 +
370 ret = ls_scfg_msi_domains_init(msi_data);
371 if (ret)
372 return ret;
373
374 - irq_set_chained_handler_and_data(msi_data->irq,
375 - ls_scfg_msi_irq_handler,
376 - msi_data);
377 -
378 platform_set_drvdata(pdev, msi_data);
379
380 return 0;
381 @@ -207,8 +399,10 @@ static int ls_scfg_msi_probe(struct platform_device *pdev)
382 static int ls_scfg_msi_remove(struct platform_device *pdev)
383 {
384 struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
385 + int i;
386
387 - irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL);
388 + for (i = 0; i < msi_data->msir_num; i++)
389 + ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
390
391 irq_domain_remove(msi_data->msi_domain);
392 irq_domain_remove(msi_data->parent);
393 @@ -218,12 +412,6 @@ static int ls_scfg_msi_remove(struct platform_device *pdev)
394 return 0;
395 }
396
397 -static const struct of_device_id ls_scfg_msi_id[] = {
398 - { .compatible = "fsl,1s1021a-msi", },
399 - { .compatible = "fsl,1s1043a-msi", },
400 - {},
401 -};
402 -
403 static struct platform_driver ls_scfg_msi_driver = {
404 .driver = {
405 .name = "ls-scfg-msi",
406 diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
407 index 084cb498..88e87704 100644
408 --- a/drivers/pci/host/Makefile
409 +++ b/drivers/pci/host/Makefile
410 @@ -17,7 +17,7 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
411 obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o
412 obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
413 obj-$(CONFIG_PCI_XGENE_MSI) += pci-xgene-msi.o
414 -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
415 +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o pci-layerscape-ep-debugfs.o
416 obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
417 obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o
418 obj-$(CONFIG_PCIE_IPROC_MSI) += pcie-iproc-msi.o
419 diff --git a/drivers/pci/host/pci-layerscape-ep-debugfs.c b/drivers/pci/host/pci-layerscape-ep-debugfs.c
420 new file mode 100644
421 index 00000000..5f4870ba
422 --- /dev/null
423 +++ b/drivers/pci/host/pci-layerscape-ep-debugfs.c
424 @@ -0,0 +1,758 @@
425 +/*
426 + * PCIe Endpoint driver for Freescale Layerscape SoCs
427 + *
428 + * Copyright (C) 2015 Freescale Semiconductor.
429 + *
430 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
431 + *
432 + * This program is free software; you can redistribute it and/or modify
433 + * it under the terms of the GNU General Public License version 2 as
434 + * published by the Free Software Foundation.
435 + */
436 +
437 +#include <linux/kernel.h>
438 +#include <linux/module.h>
439 +#include <linux/debugfs.h>
440 +#include <linux/time.h>
441 +#include <linux/uaccess.h>
442 +#include <linux/kthread.h>
443 +#include <linux/slab.h>
444 +#include <linux/dmaengine.h>
445 +#include <linux/dma-mapping.h>
446 +#include <linux/freezer.h>
447 +
448 +#include <linux/completion.h>
449 +
450 +#include "pci-layerscape-ep.h"
451 +
452 +#define PCIE_ATU_INDEX3 (0x3 << 0)
453 +#define PCIE_ATU_INDEX2 (0x2 << 0)
454 +#define PCIE_ATU_INDEX1 (0x1 << 0)
455 +#define PCIE_ATU_INDEX0 (0x0 << 0)
456 +
457 +#define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
458 +#define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
459 +#define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
460 +#define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
461 +#define PCIE_MSI_OB_SIZE (4 * 1024) /* 4K */
462 +
463 +#define PCIE_MSI_MSG_ADDR_OFF 0x54
464 +#define PCIE_MSI_MSG_DATA_OFF 0x5c
465 +
466 +enum test_type {
467 + TEST_TYPE_DMA,
468 + TEST_TYPE_MEMCPY
469 +};
470 +
471 +enum test_dirt {
472 + TEST_DIRT_READ,
473 + TEST_DIRT_WRITE
474 +};
475 +
476 +enum test_status {
477 + TEST_IDLE,
478 + TEST_BUSY
479 +};
480 +
481 +struct ls_ep_test {
482 + struct ls_ep_dev *ep;
483 + void __iomem *cfg;
484 + void __iomem *buf;
485 + void __iomem *out;
486 + void __iomem *msi;
487 + dma_addr_t cfg_addr;
488 + dma_addr_t buf_addr;
489 + dma_addr_t out_addr;
490 + dma_addr_t bus_addr;
491 + dma_addr_t msi_addr;
492 + u64 msi_msg_addr;
493 + u16 msi_msg_data;
494 + struct task_struct *thread;
495 + spinlock_t lock;
496 + struct completion done;
497 + u32 len;
498 + int loop;
499 + char data;
500 + enum test_dirt dirt;
501 + enum test_type type;
502 + enum test_status status;
503 + u64 result; /* Mbps */
504 + char cmd[256];
505 +};
506 +
507 +static int ls_pcie_ep_trigger_msi(struct ls_ep_test *test)
508 +{
509 + if (!test->msi)
510 + return -EINVAL;
511 +
512 + iowrite32(test->msi_msg_data, test->msi);
513 +
514 + return 0;
515 +}
516 +
517 +static int ls_pcie_ep_test_try_run(struct ls_ep_test *test)
518 +{
519 + int ret;
520 +
521 + spin_lock(&test->lock);
522 + if (test->status == TEST_IDLE) {
523 + test->status = TEST_BUSY;
524 + ret = 0;
525 + } else
526 + ret = -EBUSY;
527 + spin_unlock(&test->lock);
528 +
529 + return ret;
530 +}
531 +
532 +static void ls_pcie_ep_test_done(struct ls_ep_test *test)
533 +{
534 + spin_lock(&test->lock);
535 + test->status = TEST_IDLE;
536 + spin_unlock(&test->lock);
537 +}
538 +
539 +static void ls_pcie_ep_test_dma_cb(void *arg)
540 +{
541 + struct ls_ep_test *test = arg;
542 +
543 + complete(&test->done);
544 +}
545 +
546 +static int ls_pcie_ep_test_dma(struct ls_ep_test *test)
547 +{
548 + dma_cap_mask_t mask;
549 + struct dma_chan *chan;
550 + struct dma_device *dma_dev;
551 + dma_addr_t src, dst;
552 + enum dma_data_direction direction;
553 + enum dma_ctrl_flags dma_flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
554 + struct timespec start, end, period;
555 + int i = 0;
556 +
557 + dma_cap_zero(mask);
558 + dma_cap_set(DMA_MEMCPY, mask);
559 +
560 + chan = dma_request_channel(mask, NULL, test);
561 + if (!chan) {
562 + pr_err("failed to request dma channel\n");
563 + return -EINVAL;
564 + }
565 +
566 + memset(test->buf, test->data, test->len);
567 +
568 + if (test->dirt == TEST_DIRT_WRITE) {
569 + src = test->buf_addr;
570 + dst = test->out_addr;
571 + direction = DMA_TO_DEVICE;
572 + } else {
573 + src = test->out_addr;
574 + dst = test->buf_addr;
575 + direction = DMA_FROM_DEVICE;
576 + }
577 +
578 + dma_dev = chan->device;
579 + dma_flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
580 +
581 + dma_sync_single_for_device(&test->ep->dev, test->buf_addr,
582 + test->len, direction);
583 +
584 + set_freezable();
585 +
586 + getrawmonotonic(&start);
587 + while (!kthread_should_stop() && (i < test->loop)) {
588 + struct dma_async_tx_descriptor *dma_desc;
589 + dma_cookie_t dma_cookie = {0};
590 + unsigned long tmo;
591 + int status;
592 +
593 + init_completion(&test->done);
594 +
595 + dma_desc = dma_dev->device_prep_dma_memcpy(chan,
596 + dst, src,
597 + test->len,
598 + dma_flags);
599 + if (!dma_desc) {
600 + pr_err("DMA desc constr failed...\n");
601 + goto _err;
602 + }
603 +
604 + dma_desc->callback = ls_pcie_ep_test_dma_cb;
605 + dma_desc->callback_param = test;
606 + dma_cookie = dmaengine_submit(dma_desc);
607 +
608 + if (dma_submit_error(dma_cookie)) {
609 + pr_err("DMA submit error....\n");
610 + goto _err;
611 + }
612 +
613 + /* Trigger the transaction */
614 + dma_async_issue_pending(chan);
615 +
616 + tmo = wait_for_completion_timeout(&test->done,
617 + msecs_to_jiffies(5 * test->len));
618 + if (tmo == 0) {
619 + pr_err("Self-test copy timed out, disabling\n");
620 + goto _err;
621 + }
622 +
623 + status = dma_async_is_tx_complete(chan, dma_cookie,
624 + NULL, NULL);
625 + if (status != DMA_COMPLETE) {
626 + pr_err("got completion callback, but status is %s\n",
627 + status == DMA_ERROR ? "error" : "in progress");
628 + goto _err;
629 + }
630 +
631 + i++;
632 + }
633 +
634 + getrawmonotonic(&end);
635 + period = timespec_sub(end, start);
636 + test->result = test->len * 8ULL * i * 1000;
637 + do_div(test->result, period.tv_sec * 1000 * 1000 * 1000 + period.tv_nsec);
638 + dma_release_channel(chan);
639 +
640 + return 0;
641 +
642 +_err:
643 + dma_release_channel(chan);
644 + test->result = 0;
645 + return -EINVAL;
646 +}
647 +
648 +static int ls_pcie_ep_test_cpy(struct ls_ep_test *test)
649 +{
650 + void *dst, *src;
651 + struct timespec start, end, period;
652 + int i = 0;
653 +
654 + memset(test->buf, test->data, test->len);
655 +
656 + if (test->dirt == TEST_DIRT_WRITE) {
657 + dst = test->out;
658 + src = test->buf;
659 + } else {
660 + dst = test->buf;
661 + src = test->out;
662 + }
663 +
664 + getrawmonotonic(&start);
665 + while (!kthread_should_stop() && i < test->loop) {
666 + memcpy(dst, src, test->len);
667 + i++;
668 + }
669 + getrawmonotonic(&end);
670 +
671 + period = timespec_sub(end, start);
672 + test->result = test->len * 8ULL * i * 1000;
673 + do_div(test->result, period.tv_sec * 1000 * 1000 * 1000 + period.tv_nsec);
674 +
675 + return 0;
676 +}
677 +
678 +int ls_pcie_ep_test_thread(void *arg)
679 +{
680 + int ret;
681 +
682 + struct ls_ep_test *test = arg;
683 +
684 + if (test->type == TEST_TYPE_DMA)
685 + ret = ls_pcie_ep_test_dma(test);
686 + else
687 + ret = ls_pcie_ep_test_cpy(test);
688 +
689 + if (ret) {
690 + pr_err("\n%s \ttest failed\n",
691 + test->cmd);
692 + test->result = 0;
693 + } else
694 + pr_err("\n%s \tthroughput:%lluMbps\n",
695 + test->cmd, test->result);
696 +
697 + ls_pcie_ep_test_done(test);
698 +
699 + ls_pcie_ep_trigger_msi(test);
700 +
701 + do_exit(0);
702 +}
703 +
704 +static int ls_pcie_ep_free_test(struct ls_ep_dev *ep)
705 +{
706 + struct ls_ep_test *test = ep->driver_data;
707 +
708 + if (!test)
709 + return 0;
710 +
711 + if (test->status == TEST_BUSY) {
712 + kthread_stop(test->thread);
713 + dev_info(&ep->dev,
714 + "test is running please wait and run again\n");
715 + return -EBUSY;
716 + }
717 +
718 + if (test->buf)
719 + free_pages((unsigned long)test->buf,
720 + get_order(PCIE_BAR4_SIZE));
721 +
722 + if (test->cfg)
723 + free_pages((unsigned long)test->cfg,
724 + get_order(PCIE_BAR2_SIZE));
725 +
726 + if (test->out)
727 + iounmap(test->out);
728 +
729 + kfree(test);
730 + ep->driver_data = NULL;
731 +
732 + return 0;
733 +}
734 +
735 +static int ls_pcie_ep_init_test(struct ls_ep_dev *ep, u64 bus_addr)
736 +{
737 + struct ls_pcie *pcie = ep->pcie;
738 + struct ls_ep_test *test = ep->driver_data;
739 + int err;
740 +
741 + if (test) {
742 + dev_info(&ep->dev,
743 + "Please use 'free' to remove the exiting test\n");
744 + return -EBUSY;
745 + }
746 +
747 + test = kzalloc(sizeof(*test), GFP_KERNEL);
748 + if (!test)
749 + return -ENOMEM;
750 + ep->driver_data = test;
751 + test->ep = ep;
752 + spin_lock_init(&test->lock);
753 + test->status = TEST_IDLE;
754 +
755 + test->buf = dma_alloc_coherent(pcie->dev, get_order(PCIE_BAR4_SIZE),
756 + &test->buf_addr,
757 + GFP_KERNEL);
758 + if (!test->buf) {
759 + dev_info(&ep->dev, "failed to get mem for bar4\n");
760 + err = -ENOMEM;
761 + goto _err;
762 + }
763 +
764 + test->cfg = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
765 + get_order(PCIE_BAR2_SIZE));
766 + if (!test->cfg) {
767 + dev_info(&ep->dev, "failed to get mem for bar4\n");
768 + err = -ENOMEM;
769 + goto _err;
770 + }
771 + test->cfg_addr = virt_to_phys(test->cfg);
772 +
773 + test->out_addr = pcie->out_base;
774 + test->out = ioremap(test->out_addr, PCIE_BAR4_SIZE);
775 + if (!test->out) {
776 + dev_info(&ep->dev, "failed to map out\n");
777 + err = -ENOMEM;
778 + goto _err;
779 + }
780 +
781 + test->bus_addr = bus_addr;
782 +
783 + test->msi_addr = test->out_addr + PCIE_BAR4_SIZE;
784 + test->msi = ioremap(test->msi_addr, PCIE_MSI_OB_SIZE);
785 + if (!test->msi)
786 + dev_info(&ep->dev, "failed to map MSI outbound region\n");
787 +
788 + test->msi_msg_addr = ioread32(pcie->dbi + PCIE_MSI_MSG_ADDR_OFF) |
789 + (((u64)ioread32(pcie->dbi + PCIE_MSI_MSG_ADDR_OFF + 4)) << 32);
790 + test->msi_msg_data = ioread16(pcie->dbi + PCIE_MSI_MSG_DATA_OFF);
791 +
792 + ls_pcie_ep_dev_cfg_enable(ep);
793 +
794 + /* outbound iATU for memory */
795 + ls_pcie_iatu_outbound_set(pcie, 0, PCIE_ATU_TYPE_MEM,
796 + test->out_addr, bus_addr, PCIE_BAR4_SIZE);
797 + /* outbound iATU for MSI */
798 + ls_pcie_iatu_outbound_set(pcie, 1, PCIE_ATU_TYPE_MEM,
799 + test->msi_addr, test->msi_msg_addr,
800 + PCIE_MSI_OB_SIZE);
801 +
802 + /* ATU 0 : INBOUND : map BAR0 */
803 + ls_pcie_iatu_inbound_set(pcie, 0, 0, test->cfg_addr);
804 + /* ATU 2 : INBOUND : map BAR2 */
805 + ls_pcie_iatu_inbound_set(pcie, 2, 2, test->cfg_addr);
806 + /* ATU 3 : INBOUND : map BAR4 */
807 + ls_pcie_iatu_inbound_set(pcie, 3, 4, test->buf_addr);
808 +
809 + return 0;
810 +
811 +_err:
812 + ls_pcie_ep_free_test(ep);
813 + return err;
814 +}
815 +
816 +static int ls_pcie_ep_start_test(struct ls_ep_dev *ep, char *cmd)
817 +{
818 + struct ls_ep_test *test = ep->driver_data;
819 + enum test_type type;
820 + enum test_dirt dirt;
821 + u32 cnt, len, loop;
822 + unsigned int data;
823 + char dirt_str[2];
824 + int ret;
825 +
826 + if (strncmp(cmd, "dma", 3) == 0)
827 + type = TEST_TYPE_DMA;
828 + else
829 + type = TEST_TYPE_MEMCPY;
830 +
831 + cnt = sscanf(&cmd[4], "%1s %u %u %x", dirt_str, &len, &loop, &data);
832 + if (cnt != 4) {
833 + dev_info(&ep->dev, "format error %s", cmd);
834 + dev_info(&ep->dev, "dma/cpy <r/w> <packet_size> <loop> <data>\n");
835 + return -EINVAL;
836 + }
837 +
838 + if (strncmp(dirt_str, "r", 1) == 0)
839 + dirt = TEST_DIRT_READ;
840 + else
841 + dirt = TEST_DIRT_WRITE;
842 +
843 + if (len > PCIE_BAR4_SIZE) {
844 + dev_err(&ep->dev, "max len is %d", PCIE_BAR4_SIZE);
845 + return -EINVAL;
846 + }
847 +
848 + if (!test) {
849 + dev_err(&ep->dev, "Please first run init command\n");
850 + return -EINVAL;
851 + }
852 +
853 + if (ls_pcie_ep_test_try_run(test)) {
854 + dev_err(&ep->dev, "There is already a test running\n");
855 + return -EINVAL;
856 + }
857 +
858 + test->len = len;
859 + test->loop = loop;
860 + test->type = type;
861 + test->data = (char)data;
862 + test->dirt = dirt;
863 + strcpy(test->cmd, cmd);
864 + test->thread = kthread_run(ls_pcie_ep_test_thread, test,
865 + "pcie ep test");
866 + if (IS_ERR(test->thread)) {
867 + dev_err(&ep->dev, "fork failed for pcie ep test\n");
868 + ls_pcie_ep_test_done(test);
869 + ret = PTR_ERR(test->thread);
870 + }
871 +
872 + return ret;
873 +}
874 +
875 +
876 +/**
877 + * ls_pcie_reg_ops_read - read for regs data
878 + * @filp: the opened file
879 + * @buffer: where to write the data for the user to read
880 + * @count: the size of the user's buffer
881 + * @ppos: file position offset
882 + **/
883 +static ssize_t ls_pcie_ep_dbg_regs_read(struct file *filp, char __user *buffer,
884 + size_t count, loff_t *ppos)
885 +{
886 + struct ls_ep_dev *ep = filp->private_data;
887 + struct ls_pcie *pcie = ep->pcie;
888 + char *buf;
889 + int desc = 0, i, len;
890 +
891 + buf = kmalloc(4 * 1024, GFP_KERNEL);
892 + if (!buf)
893 + return -ENOMEM;
894 +
895 + ls_pcie_ep_dev_cfg_enable(ep);
896 +
897 + desc += sprintf(buf + desc, "%s", "reg info:");
898 + for (i = 0; i < 0x200; i += 4) {
899 + if (i % 16 == 0)
900 + desc += sprintf(buf + desc, "\n%08x:", i);
901 + desc += sprintf(buf + desc, " %08x", readl(pcie->dbi + i));
902 + }
903 +
904 + desc += sprintf(buf + desc, "\n%s", "outbound iATU info:\n");
905 + for (i = 0; i < 6; i++) {
906 + writel(PCIE_ATU_REGION_OUTBOUND | i,
907 + pcie->dbi + PCIE_ATU_VIEWPORT);
908 + desc += sprintf(buf + desc, "iATU%d", i);
909 + desc += sprintf(buf + desc, "\tLOWER PHYS 0x%08x\n",
910 + readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
911 + desc += sprintf(buf + desc, "\tUPPER PHYS 0x%08x\n",
912 + readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
913 + desc += sprintf(buf + desc, "\tLOWER BUS 0x%08x\n",
914 + readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
915 + desc += sprintf(buf + desc, "\tUPPER BUS 0x%08x\n",
916 + readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
917 + desc += sprintf(buf + desc, "\tLIMIT 0x%08x\n",
918 + readl(pcie->dbi + PCIE_ATU_LIMIT));
919 + desc += sprintf(buf + desc, "\tCR1 0x%08x\n",
920 + readl(pcie->dbi + PCIE_ATU_CR1));
921 + desc += sprintf(buf + desc, "\tCR2 0x%08x\n",
922 + readl(pcie->dbi + PCIE_ATU_CR2));
923 + }
924 +
925 + desc += sprintf(buf + desc, "\n%s", "inbound iATU info:\n");
926 + for (i = 0; i < 6; i++) {
927 + writel(PCIE_ATU_REGION_INBOUND | i,
928 + pcie->dbi + PCIE_ATU_VIEWPORT);
929 + desc += sprintf(buf + desc, "iATU%d", i);
930 + desc += sprintf(buf + desc, "\tLOWER BUS 0x%08x\n",
931 + readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
932 + desc += sprintf(buf + desc, "\tUPPER BUSs 0x%08x\n",
933 + readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
934 + desc += sprintf(buf + desc, "\tLOWER PHYS 0x%08x\n",
935 + readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
936 + desc += sprintf(buf + desc, "\tUPPER PHYS 0x%08x\n",
937 + readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
938 + desc += sprintf(buf + desc, "\tLIMIT 0x%08x\n",
939 + readl(pcie->dbi + PCIE_ATU_LIMIT));
940 + desc += sprintf(buf + desc, "\tCR1 0x%08x\n",
941 + readl(pcie->dbi + PCIE_ATU_CR1));
942 + desc += sprintf(buf + desc, "\tCR2 0x%08x\n",
943 + readl(pcie->dbi + PCIE_ATU_CR2));
944 + }
945 +
946 + len = simple_read_from_buffer(buffer, count, ppos, buf, desc);
947 + kfree(buf);
948 +
949 + return len;
950 +}
951 +
952 +/**
953 + * ls_pcie_ep_dbg_regs_write - write into regs datum
954 + * @filp: the opened file
955 + * @buffer: where to find the user's data
956 + * @count: the length of the user's data
957 + * @ppos: file position offset
958 + **/
959 +static ssize_t ls_pcie_ep_dbg_regs_write(struct file *filp,
960 + const char __user *buffer,
961 + size_t count, loff_t *ppos)
962 +{
963 + struct ls_ep_dev *ep = filp->private_data;
964 + struct ls_pcie *pcie = ep->pcie;
965 + char buf[256];
966 +
967 + if (count >= sizeof(buf))
968 + return -ENOSPC;
969 +
970 + memset(buf, 0, sizeof(buf));
971 +
972 + if (copy_from_user(buf, buffer, count))
973 + return -EFAULT;
974 +
975 + ls_pcie_ep_dev_cfg_enable(ep);
976 +
977 + if (strncmp(buf, "reg", 3) == 0) {
978 + u32 reg, value;
979 + int cnt;
980 +
981 + cnt = sscanf(&buf[3], "%x %x", &reg, &value);
982 + if (cnt == 2) {
983 + writel(value, pcie->dbi + reg);
984 + value = readl(pcie->dbi + reg);
985 + dev_info(&ep->dev, "reg 0x%08x: 0x%08x\n",
986 + reg, value);
987 + } else {
988 + dev_info(&ep->dev, "reg <reg> <value>\n");
989 + }
990 + } else if (strncmp(buf, "atu", 3) == 0) {
991 + /* to do */
992 + dev_info(&ep->dev, " Not support atu command\n");
993 + } else {
994 + dev_info(&ep->dev, "Unknown command %s\n", buf);
995 + dev_info(&ep->dev, "Available commands:\n");
996 + dev_info(&ep->dev, " reg <reg> <value>\n");
997 + }
998 +
999 + return count;
1000 +}
1001 +
1002 +static const struct file_operations ls_pcie_ep_dbg_regs_fops = {
1003 + .owner = THIS_MODULE,
1004 + .open = simple_open,
1005 + .read = ls_pcie_ep_dbg_regs_read,
1006 + .write = ls_pcie_ep_dbg_regs_write,
1007 +};
1008 +
1009 +static ssize_t ls_pcie_ep_dbg_test_read(struct file *filp,
1010 + char __user *buffer,
1011 + size_t count, loff_t *ppos)
1012 +{
1013 + struct ls_ep_dev *ep = filp->private_data;
1014 + struct ls_ep_test *test = ep->driver_data;
1015 + char buf[512];
1016 + int desc = 0, len;
1017 +
1018 + if (!test) {
1019 + dev_info(&ep->dev, " there is NO test\n");
1020 + return 0;
1021 + }
1022 +
1023 + if (test->status != TEST_IDLE) {
1024 + dev_info(&ep->dev, "test %s is running\n", test->cmd);
1025 + return 0;
1026 + }
1027 +
1028 + desc = sprintf(buf, "MSI ADDR:0x%llx MSI DATA:0x%x\n",
1029 + test->msi_msg_addr, test->msi_msg_data);
1030 +
1031 + desc += sprintf(buf + desc, "%s throughput:%lluMbps\n",
1032 + test->cmd, test->result);
1033 +
1034 + len = simple_read_from_buffer(buffer, count, ppos,
1035 + buf, desc);
1036 +
1037 + return len;
1038 +}
1039 +
1040 +static ssize_t ls_pcie_ep_dbg_test_write(struct file *filp,
1041 + const char __user *buffer,
1042 + size_t count, loff_t *ppos)
1043 +{
1044 + struct ls_ep_dev *ep = filp->private_data;
1045 + char buf[256];
1046 +
1047 + if (count >= sizeof(buf))
1048 + return -ENOSPC;
1049 +
1050 + memset(buf, 0, sizeof(buf));
1051 +
1052 + if (copy_from_user(buf, buffer, count))
1053 + return -EFAULT;
1054 +
1055 + if (strncmp(buf, "init", 4) == 0) {
1056 + int i = 4;
1057 + u64 bus_addr;
1058 +
1059 + while (buf[i] == ' ')
1060 + i++;
1061 +
1062 + if (kstrtou64(&buf[i], 0, &bus_addr))
1063 + dev_info(&ep->dev, "command: init <bus_addr>\n");
1064 + else {
1065 + if (ls_pcie_ep_init_test(ep, bus_addr))
1066 + dev_info(&ep->dev, "failed to init test\n");
1067 + }
1068 + } else if (strncmp(buf, "free", 4) == 0)
1069 + ls_pcie_ep_free_test(ep);
1070 + else if (strncmp(buf, "dma", 3) == 0 ||
1071 + strncmp(buf, "cpy", 3) == 0)
1072 + ls_pcie_ep_start_test(ep, buf);
1073 + else {
1074 + dev_info(&ep->dev, "Unknown command: %s\n", buf);
1075 + dev_info(&ep->dev, "Available commands:\n");
1076 + dev_info(&ep->dev, "\tinit <bus_addr>\n");
1077 + dev_info(&ep->dev, "\t<dma/cpy> <r/w> <packet_size> <loop>\n");
1078 + dev_info(&ep->dev, "\tfree\n");
1079 + }
1080 +
1081 + return count;
1082 +}
1083 +
1084 +static const struct file_operations ls_pcie_ep_dbg_test_fops = {
1085 + .owner = THIS_MODULE,
1086 + .open = simple_open,
1087 + .read = ls_pcie_ep_dbg_test_read,
1088 + .write = ls_pcie_ep_dbg_test_write,
1089 +};
1090 +
1091 +static ssize_t ls_pcie_ep_dbg_dump_read(struct file *filp,
1092 + char __user *buffer,
1093 + size_t count, loff_t *ppos)
1094 +{
1095 + struct ls_ep_dev *ep = filp->private_data;
1096 + struct ls_ep_test *test = ep->driver_data;
1097 + char *buf;
1098 + int desc = 0, i, len;
1099 +
1100 + buf = kmalloc(4 * 1024, GFP_KERNEL);
1101 + if (!buf)
1102 + return -ENOMEM;
1103 +
1104 + if (!test) {
1105 + dev_info(&ep->dev, " there is NO test\n");
1106 + kfree(buf);
1107 + return 0;
1108 + }
1109 +
1110 + desc += sprintf(buf + desc, "%s", "dump info:");
1111 + for (i = 0; i < 256; i += 4) {
1112 + if (i % 16 == 0)
1113 + desc += sprintf(buf + desc, "\n%08x:", i);
1114 + desc += sprintf(buf + desc, " %08x", readl(test->buf + i));
1115 + }
1116 +
1117 + desc += sprintf(buf + desc, "\n");
1118 + len = simple_read_from_buffer(buffer, count, ppos, buf, desc);
1119 +
1120 + kfree(buf);
1121 +
1122 + return len;
1123 +}
1124 +
1125 +static const struct file_operations ls_pcie_ep_dbg_dump_fops = {
1126 + .owner = THIS_MODULE,
1127 + .open = simple_open,
1128 + .read = ls_pcie_ep_dbg_dump_read,
1129 +};
1130 +
1131 +static int ls_pcie_ep_dev_dbgfs_init(struct ls_ep_dev *ep)
1132 +{
1133 + struct ls_pcie *pcie = ep->pcie;
1134 + struct dentry *pfile;
1135 +
1136 + ls_pcie_ep_dev_cfg_enable(ep);
1137 +
1138 + ep->dir = debugfs_create_dir(dev_name(&ep->dev), pcie->dir);
1139 + if (!ep->dir)
1140 + return -ENOMEM;
1141 +
1142 + pfile = debugfs_create_file("regs", 0600, ep->dir, ep,
1143 + &ls_pcie_ep_dbg_regs_fops);
1144 + if (!pfile)
1145 + dev_info(&ep->dev, "debugfs regs for failed\n");
1146 +
1147 + pfile = debugfs_create_file("test", 0600, ep->dir, ep,
1148 + &ls_pcie_ep_dbg_test_fops);
1149 + if (!pfile)
1150 + dev_info(&ep->dev, "debugfs test for failed\n");
1151 +
1152 + pfile = debugfs_create_file("dump", 0600, ep->dir, ep,
1153 + &ls_pcie_ep_dbg_dump_fops);
1154 + if (!pfile)
1155 + dev_info(&ep->dev, "debugfs dump for failed\n");
1156 +
1157 + return 0;
1158 +}
1159 +
1160 +int ls_pcie_ep_dbgfs_init(struct ls_pcie *pcie)
1161 +{
1162 + struct ls_ep_dev *ep;
1163 +
1164 + pcie->dir = debugfs_create_dir(dev_name(pcie->dev), NULL);
1165 + if (!pcie->dir)
1166 + return -ENOMEM;
1167 +
1168 + list_for_each_entry(ep, &pcie->ep_list, node)
1169 + ls_pcie_ep_dev_dbgfs_init(ep);
1170 +
1171 + return 0;
1172 +}
1173 +
1174 +int ls_pcie_ep_dbgfs_remove(struct ls_pcie *pcie)
1175 +{
1176 + debugfs_remove_recursive(pcie->dir);
1177 + return 0;
1178 +}
1179 +
1180 +MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
1181 +MODULE_DESCRIPTION("Freescale Layerscape PCIe EP controller driver");
1182 +MODULE_LICENSE("GPL v2");
1183 diff --git a/drivers/pci/host/pci-layerscape-ep.c b/drivers/pci/host/pci-layerscape-ep.c
1184 new file mode 100644
1185 index 00000000..8f1cca6e
1186 --- /dev/null
1187 +++ b/drivers/pci/host/pci-layerscape-ep.c
1188 @@ -0,0 +1,309 @@
1189 +/*
1190 + * PCIe Endpoint driver for Freescale Layerscape SoCs
1191 + *
1192 + * Copyright (C) 2015 Freescale Semiconductor.
1193 + *
1194 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
1195 + *
1196 + * This program is free software; you can redistribute it and/or modify
1197 + * it under the terms of the GNU General Public License version 2 as
1198 + * published by the Free Software Foundation.
1199 + */
1200 +
1201 +#include <linux/kernel.h>
1202 +#include <linux/delay.h>
1203 +#include <linux/interrupt.h>
1204 +#include <linux/module.h>
1205 +#include <linux/of_pci.h>
1206 +#include <linux/of_platform.h>
1207 +#include <linux/of_irq.h>
1208 +#include <linux/of_address.h>
1209 +#include <linux/pci.h>
1210 +#include <linux/platform_device.h>
1211 +#include <linux/resource.h>
1212 +#include <linux/debugfs.h>
1213 +#include <linux/time.h>
1214 +#include <linux/uaccess.h>
1215 +
1216 +#include "pci-layerscape-ep.h"
1217 +
1218 +struct ls_ep_dev *
1219 +ls_pci_ep_find(struct ls_pcie *pcie, int dev_id)
1220 +{
1221 + struct ls_ep_dev *ep;
1222 +
1223 + list_for_each_entry(ep, &pcie->ep_list, node) {
1224 + if (ep->dev_id == dev_id)
1225 + return ep;
1226 + }
1227 +
1228 + return NULL;
1229 +}
1230 +
1231 +static void ls_pcie_try_cfg2(struct ls_pcie *pcie, int pf, int vf)
1232 +{
1233 + if (pcie->sriov)
1234 + writel(PCIE_LCTRL0_VAL(pf, vf),
1235 + pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
1236 +}
1237 +
1238 +static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
1239 +{
1240 + u32 header_type = 0;
1241 +
1242 + header_type = readl(pcie->dbi + (PCI_HEADER_TYPE & ~0x3));
1243 + header_type = (header_type >> 16) & 0x7f;
1244 +
1245 + return header_type == PCI_HEADER_TYPE_BRIDGE;
1246 +}
1247 +
1248 +void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
1249 + u64 cpu_addr, u64 pci_addr, u32 size)
1250 +{
1251 + writel(PCIE_ATU_REGION_OUTBOUND | idx,
1252 + pcie->dbi + PCIE_ATU_VIEWPORT);
1253 + writel(lower_32_bits(cpu_addr),
1254 + pcie->dbi + PCIE_ATU_LOWER_BASE);
1255 + writel(upper_32_bits(cpu_addr),
1256 + pcie->dbi + PCIE_ATU_UPPER_BASE);
1257 + writel(lower_32_bits(cpu_addr + size - 1),
1258 + pcie->dbi + PCIE_ATU_LIMIT);
1259 + writel(lower_32_bits(pci_addr),
1260 + pcie->dbi + PCIE_ATU_LOWER_TARGET);
1261 + writel(upper_32_bits(pci_addr),
1262 + pcie->dbi + PCIE_ATU_UPPER_TARGET);
1263 + writel(type, pcie->dbi + PCIE_ATU_CR1);
1264 + writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
1265 +}
1266 +
1267 +/* Use bar match mode and MEM type as default */
1268 +void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
1269 + int bar, u64 phys)
1270 +{
1271 + writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
1272 + writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
1273 + writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
1274 + writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
1275 + writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
1276 + PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
1277 +}
1278 +
1279 +void ls_pcie_ep_dev_cfg_enable(struct ls_ep_dev *ep)
1280 +{
1281 + ls_pcie_try_cfg2(ep->pcie, ep->pf_idx, ep->vf_idx);
1282 +}
1283 +
1284 +void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
1285 +{
1286 + if (size < 4 * 1024)
1287 + return;
1288 +
1289 + switch (bar) {
1290 + case 0:
1291 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
1292 + break;
1293 + case 1:
1294 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
1295 + break;
1296 + case 2:
1297 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
1298 + writel(0, bar_base + PCI_BASE_ADDRESS_3);
1299 + break;
1300 + case 4:
1301 + writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
1302 + writel(0, bar_base + PCI_BASE_ADDRESS_5);
1303 + break;
1304 + default:
1305 + break;
1306 + }
1307 +}
1308 +
1309 +void ls_pcie_ep_dev_setup_bar(struct ls_ep_dev *ep, int bar, u32 size)
1310 +{
1311 + struct ls_pcie *pcie = ep->pcie;
1312 + void *bar_base;
1313 +
1314 + if (size < 4 * 1024)
1315 + return;
1316 +
1317 + if (pcie->sriov)
1318 + bar_base = pcie->dbi;
1319 + else
1320 + bar_base = pcie->dbi + PCIE_NO_SRIOV_BAR_BASE;
1321 +
1322 + ls_pcie_ep_dev_cfg_enable(ep);
1323 + ls_pcie_ep_setup_bar(bar_base, bar, size);
1324 +}
1325 +
1326 +static int ls_pcie_ep_dev_init(struct ls_pcie *pcie, int pf_idx, int vf_idx)
1327 +{
1328 + struct ls_ep_dev *ep;
1329 +
1330 + ep = devm_kzalloc(pcie->dev, sizeof(*ep), GFP_KERNEL);
1331 + if (!ep)
1332 + return -ENOMEM;
1333 +
1334 + ep->pcie = pcie;
1335 + ep->pf_idx = pf_idx;
1336 + ep->vf_idx = vf_idx;
1337 + if (vf_idx)
1338 + ep->dev_id = pf_idx + 4 + 4 * (vf_idx - 1);
1339 + else
1340 + ep->dev_id = pf_idx;
1341 +
1342 + if (ep->vf_idx)
1343 + dev_set_name(&ep->dev, "pf%d-vf%d",
1344 + ep->pf_idx,
1345 + ep->vf_idx);
1346 + else
1347 + dev_set_name(&ep->dev, "pf%d",
1348 + ep->pf_idx);
1349 +
1350 + list_add_tail(&ep->node, &pcie->ep_list);
1351 +
1352 + return 0;
1353 +}
1354 +
1355 +static int ls_pcie_ep_init(struct ls_pcie *pcie)
1356 +{
1357 + u32 sriov_header;
1358 + int pf, vf, i, j;
1359 +
1360 + sriov_header = readl(pcie->dbi + PCIE_SRIOV_POS);
1361 +
1362 + if (PCI_EXT_CAP_ID(sriov_header) == PCI_EXT_CAP_ID_SRIOV) {
1363 + pcie->sriov = PCIE_SRIOV_POS;
1364 + pf = PCIE_PF_NUM;
1365 + vf = PCIE_VF_NUM;
1366 + } else {
1367 + pcie->sriov = 0;
1368 + pf = 1;
1369 + vf = 0;
1370 + }
1371 +
1372 + for (i = 0; i < pf; i++) {
1373 + for (j = 0; j <= vf; j++)
1374 + ls_pcie_ep_dev_init(pcie, i, j);
1375 + }
1376 +
1377 + return 0;
1378 +}
1379 +
1380 +static struct ls_pcie_ep_drvdata ls1043_drvdata = {
1381 + .lut_offset = 0x10000,
1382 + .ltssm_shift = 24,
1383 + .lut_dbg = 0x7fc,
1384 +};
1385 +
1386 +static struct ls_pcie_ep_drvdata ls1046_drvdata = {
1387 + .lut_offset = 0x80000,
1388 + .ltssm_shift = 24,
1389 + .lut_dbg = 0x407fc,
1390 +};
1391 +
1392 +static struct ls_pcie_ep_drvdata ls2080_drvdata = {
1393 + .lut_offset = 0x80000,
1394 + .ltssm_shift = 0,
1395 + .lut_dbg = 0x7fc,
1396 +};
1397 +
1398 +static const struct of_device_id ls_pcie_ep_of_match[] = {
1399 + { .compatible = "fsl,ls1021a-pcie", },
1400 + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1401 + { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1402 + { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
1403 + { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
1404 + { },
1405 +};
1406 +MODULE_DEVICE_TABLE(of, ls_pcie_ep_of_match);
1407 +
1408 +static int ls_pcie_ep_probe(struct platform_device *pdev)
1409 +{
1410 + struct ls_pcie *pcie;
1411 + struct resource *dbi_base, *cfg_res;
1412 + const struct of_device_id *match;
1413 + int ret;
1414 +
1415 + match = of_match_device(ls_pcie_ep_of_match, &pdev->dev);
1416 + if (!match)
1417 + return -ENODEV;
1418 +
1419 + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1420 + if (!pcie)
1421 + return -ENOMEM;
1422 +
1423 + pcie->dev = &pdev->dev;
1424 + INIT_LIST_HEAD(&pcie->ep_list);
1425 +
1426 + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1427 + pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
1428 + if (IS_ERR(pcie->dbi)) {
1429 + dev_err(&pdev->dev, "missing *regs* space\n");
1430 + return PTR_ERR(pcie->dbi);
1431 + }
1432 +
1433 + pcie->drvdata = match->data;
1434 + pcie->lut = pcie->dbi + pcie->drvdata->lut_offset;
1435 +
1436 + if (ls_pcie_is_bridge(pcie))
1437 + return -ENODEV;
1438 +
1439 + dev_info(pcie->dev, "in EP mode\n");
1440 +
1441 + cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
1442 + if (cfg_res)
1443 + pcie->out_base = cfg_res->start;
1444 + else {
1445 + dev_err(&pdev->dev, "missing *config* space\n");
1446 + return -ENODEV;
1447 + }
1448 +
1449 + ret = ls_pcie_ep_init(pcie);
1450 + if (ret)
1451 + return ret;
1452 +
1453 + ls_pcie_ep_dbgfs_init(pcie);
1454 +
1455 + platform_set_drvdata(pdev, pcie);
1456 +
1457 + return 0;
1458 +}
1459 +
1460 +static int ls_pcie_ep_dev_remove(struct ls_ep_dev *ep)
1461 +{
1462 + list_del(&ep->node);
1463 +
1464 + return 0;
1465 +}
1466 +
1467 +static int ls_pcie_ep_remove(struct platform_device *pdev)
1468 +{
1469 + struct ls_pcie *pcie = platform_get_drvdata(pdev);
1470 + struct ls_ep_dev *ep, *tmp;
1471 +
1472 + if (!pcie)
1473 + return 0;
1474 +
1475 + ls_pcie_ep_dbgfs_remove(pcie);
1476 +
1477 + list_for_each_entry_safe(ep, tmp, &pcie->ep_list, node)
1478 + ls_pcie_ep_dev_remove(ep);
1479 +
1480 + return 0;
1481 +}
1482 +
1483 +static struct platform_driver ls_pcie_ep_driver = {
1484 + .driver = {
1485 + .name = "ls-pcie-ep",
1486 + .owner = THIS_MODULE,
1487 + .of_match_table = ls_pcie_ep_of_match,
1488 + },
1489 + .probe = ls_pcie_ep_probe,
1490 + .remove = ls_pcie_ep_remove,
1491 +};
1492 +
1493 +module_platform_driver(ls_pcie_ep_driver);
1494 +
1495 +MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
1496 +MODULE_DESCRIPTION("Freescale Layerscape PCIe EP driver");
1497 +MODULE_LICENSE("GPL v2");
1498 diff --git a/drivers/pci/host/pci-layerscape-ep.h b/drivers/pci/host/pci-layerscape-ep.h
1499 new file mode 100644
1500 index 00000000..990c0ff5
1501 --- /dev/null
1502 +++ b/drivers/pci/host/pci-layerscape-ep.h
1503 @@ -0,0 +1,115 @@
1504 +/*
1505 + * PCIe Endpoint driver for Freescale Layerscape SoCs
1506 + *
1507 + * Copyright (C) 2015 Freescale Semiconductor.
1508 + *
1509 + * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
1510 + *
1511 + * This program is free software; you can redistribute it and/or modify
1512 + * it under the terms of the GNU General Public License version 2 as
1513 + * published by the Free Software Foundation.
1514 + */
1515 +
1516 +
1517 +#ifndef _PCIE_LAYERSCAPE_EP_H
1518 +#define _PCIE_LAYERSCAPE_EP_H
1519 +
1520 +#include <linux/device.h>
1521 +
1522 +/* Synopsis specific PCIE configuration registers */
1523 +#define PCIE_ATU_VIEWPORT 0x900
1524 +#define PCIE_ATU_REGION_INBOUND (0x1 << 31)
1525 +#define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
1526 +#define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
1527 +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
1528 +#define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
1529 +#define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
1530 +#define PCIE_ATU_CR1 0x904
1531 +#define PCIE_ATU_TYPE_MEM (0x0 << 0)
1532 +#define PCIE_ATU_TYPE_IO (0x2 << 0)
1533 +#define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
1534 +#define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
1535 +#define PCIE_ATU_CR2 0x908
1536 +#define PCIE_ATU_ENABLE (0x1 << 31)
1537 +#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
1538 +#define PCIE_ATU_LOWER_BASE 0x90C
1539 +#define PCIE_ATU_UPPER_BASE 0x910
1540 +#define PCIE_ATU_LIMIT 0x914
1541 +#define PCIE_ATU_LOWER_TARGET 0x918
1542 +#define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
1543 +#define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
1544 +#define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
1545 +#define PCIE_ATU_UPPER_TARGET 0x91C
1546 +
1547 +/* PEX internal configuration registers */
1548 +#define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
1549 +
1550 +/* PEX LUT registers */
1551 +#define PCIE_LUT_BASE 0x80000
1552 +#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug register */
1553 +
1554 +#define PCIE_LUT_LCTRL0 0x7F8
1555 +
1556 +#define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
1557 +#define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
1558 +#define PCIE_LCTRL0_VF(vf) ((vf) << 22)
1559 +#define PCIE_LCTRL0_PF(pf) ((pf) << 16)
1560 +#define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
1561 +#define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
1562 + PCIE_LCTRL0_VF(vf) | \
1563 + ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
1564 + PCIE_LCTRL0_CFG2_ENABLE)
1565 +
1566 +#define PCIE_NO_SRIOV_BAR_BASE 0x1000
1567 +
1568 +#define PCIE_SRIOV_POS 0x178
1569 +#define PCIE_PF_NUM 2
1570 +#define PCIE_VF_NUM 64
1571 +
1572 +struct ls_pcie_ep_drvdata {
1573 + u32 lut_offset;
1574 + u32 ltssm_shift;
1575 + u32 lut_dbg;
1576 +};
1577 +
1578 +struct ls_pcie {
1579 + struct list_head ep_list;
1580 + struct device *dev;
1581 + struct dentry *dir;
1582 + const struct ls_pcie_ep_drvdata *drvdata;
1583 + void __iomem *dbi;
1584 + void __iomem *lut;
1585 + phys_addr_t out_base;
1586 + int sriov;
1587 + int index;
1588 +};
1589 +
1590 +struct ls_ep_dev {
1591 + struct list_head node;
1592 + struct ls_pcie *pcie;
1593 + struct device dev;
1594 + struct dentry *dir;
1595 + int pf_idx;
1596 + int vf_idx;
1597 + int dev_id;
1598 + void *driver_data;
1599 +};
1600 +
1601 +struct ls_ep_dev *ls_pci_ep_find(struct ls_pcie *pcie, int dev_id);
1602 +
1603 +void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
1604 + u64 cpu_addr, u64 pci_addr, u32 size);
1605 +
1606 +/* Use bar match mode and MEM type as default */
1607 +void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
1608 + int bar, u64 phys);
1609 +
1610 +void ls_pcie_ep_dev_setup_bar(struct ls_ep_dev *ep, int bar, u32 size);
1611 +
1612 +
1613 +void ls_pcie_ep_dev_cfg_enable(struct ls_ep_dev *ep);
1614 +
1615 +int ls_pcie_ep_dbgfs_init(struct ls_pcie *pcie);
1616 +int ls_pcie_ep_dbgfs_remove(struct ls_pcie *pcie);
1617 +
1618 +#endif /* _PCIE_LAYERSCAPE_EP_H */
1619 diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c
1620 index 65370799..4713b872 100644
1621 --- a/drivers/pci/host/pci-layerscape.c
1622 +++ b/drivers/pci/host/pci-layerscape.c
1623 @@ -35,12 +35,14 @@
1624 #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
1625 #define PCIE_DBI_RO_WR_EN 0x8bc /* DBI Read-Only Write Enable Register */
1626
1627 -/* PEX LUT registers */
1628 -#define PCIE_LUT_DBG 0x7FC /* PEX LUT Debug Register */
1629 +#define PCIE_IATU_NUM 6
1630 +
1631 +static void ls_pcie_host_init(struct pcie_port *pp);
1632
1633 struct ls_pcie_drvdata {
1634 u32 lut_offset;
1635 u32 ltssm_shift;
1636 + u32 lut_dbg;
1637 struct pcie_host_ops *ops;
1638 };
1639
1640 @@ -86,6 +88,14 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
1641 iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
1642 }
1643
1644 +static void ls_pcie_disable_outbound_atus(struct ls_pcie *pcie)
1645 +{
1646 + int i;
1647 +
1648 + for (i = 0; i < PCIE_IATU_NUM; i++)
1649 + dw_pcie_disable_outbound_atu(&pcie->pp, i);
1650 +}
1651 +
1652 static int ls1021_pcie_link_up(struct pcie_port *pp)
1653 {
1654 u32 state;
1655 @@ -134,7 +144,7 @@ static int ls_pcie_link_up(struct pcie_port *pp)
1656 struct ls_pcie *pcie = to_ls_pcie(pp);
1657 u32 state;
1658
1659 - state = (ioread32(pcie->lut + PCIE_LUT_DBG) >>
1660 + state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
1661 pcie->drvdata->ltssm_shift) &
1662 LTSSM_STATE_MASK;
1663
1664 @@ -153,6 +163,9 @@ static void ls_pcie_host_init(struct pcie_port *pp)
1665 ls_pcie_clear_multifunction(pcie);
1666 ls_pcie_drop_msg_tlp(pcie);
1667 iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
1668 +
1669 + ls_pcie_disable_outbound_atus(pcie);
1670 + dw_pcie_setup_rc(pp);
1671 }
1672
1673 static int ls_pcie_msi_host_init(struct pcie_port *pp,
1674 @@ -196,20 +209,38 @@ static struct ls_pcie_drvdata ls1021_drvdata = {
1675 static struct ls_pcie_drvdata ls1043_drvdata = {
1676 .lut_offset = 0x10000,
1677 .ltssm_shift = 24,
1678 + .lut_dbg = 0x7fc,
1679 + .ops = &ls_pcie_host_ops,
1680 +};
1681 +
1682 +static struct ls_pcie_drvdata ls1046_drvdata = {
1683 + .lut_offset = 0x80000,
1684 + .ltssm_shift = 24,
1685 + .lut_dbg = 0x407fc,
1686 .ops = &ls_pcie_host_ops,
1687 };
1688
1689 static struct ls_pcie_drvdata ls2080_drvdata = {
1690 .lut_offset = 0x80000,
1691 .ltssm_shift = 0,
1692 + .lut_dbg = 0x7fc,
1693 + .ops = &ls_pcie_host_ops,
1694 +};
1695 +
1696 +static struct ls_pcie_drvdata ls2088_drvdata = {
1697 + .lut_offset = 0x80000,
1698 + .ltssm_shift = 0,
1699 + .lut_dbg = 0x407fc,
1700 .ops = &ls_pcie_host_ops,
1701 };
1702
1703 static const struct of_device_id ls_pcie_of_match[] = {
1704 { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
1705 { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
1706 + { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
1707 { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
1708 { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
1709 + { .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
1710 { },
1711 };
1712
1713 diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
1714 index af8f6e92..2358e049 100644
1715 --- a/drivers/pci/host/pcie-designware.c
1716 +++ b/drivers/pci/host/pcie-designware.c
1717 @@ -478,6 +478,12 @@ int dw_pcie_wait_for_link(struct pcie_port *pp)
1718 return -ETIMEDOUT;
1719 }
1720
1721 +void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index)
1722 +{
1723 + dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT, PCIE_ATU_REGION_OUTBOUND | index);
1724 + dw_pcie_writel_rc(pp, PCIE_ATU_CR2, 0);
1725 +}
1726 +
1727 int dw_pcie_link_up(struct pcie_port *pp)
1728 {
1729 u32 val;
1730 diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
1731 index a567ea28..4e6672b2 100644
1732 --- a/drivers/pci/host/pcie-designware.h
1733 +++ b/drivers/pci/host/pcie-designware.h
1734 @@ -82,5 +82,6 @@ int dw_pcie_wait_for_link(struct pcie_port *pp);
1735 int dw_pcie_link_up(struct pcie_port *pp);
1736 void dw_pcie_setup_rc(struct pcie_port *pp);
1737 int dw_pcie_host_init(struct pcie_port *pp);
1738 +void dw_pcie_disable_outbound_atu(struct pcie_port *pp, int index);
1739
1740 #endif /* _PCIE_DESIGNWARE_H */
1741 diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
1742 index e9270b40..1bad877a 100644
1743 --- a/drivers/pci/pcie/portdrv_core.c
1744 +++ b/drivers/pci/pcie/portdrv_core.c
1745 @@ -44,52 +44,30 @@ static void release_pcie_device(struct device *dev)
1746 }
1747
1748 /**
1749 - * pcie_port_msix_add_entry - add entry to given array of MSI-X entries
1750 - * @entries: Array of MSI-X entries
1751 - * @new_entry: Index of the entry to add to the array
1752 - * @nr_entries: Number of entries already in the array
1753 + * pcibios_check_service_irqs - check irqs in the device tree
1754 + * @dev: PCI Express port to handle
1755 + * @irqs: Array of irqs to populate
1756 + * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1757 + *
1758 + * Return value: 0 means no service irqs in the device tree
1759 *
1760 - * Return value: Position of the added entry in the array
1761 */
1762 -static int pcie_port_msix_add_entry(
1763 - struct msix_entry *entries, int new_entry, int nr_entries)
1764 +int __weak pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1765 {
1766 - int j;
1767 -
1768 - for (j = 0; j < nr_entries; j++)
1769 - if (entries[j].entry == new_entry)
1770 - return j;
1771 -
1772 - entries[j].entry = new_entry;
1773 - return j;
1774 + return 0;
1775 }
1776
1777 /**
1778 * pcie_port_enable_msix - try to set up MSI-X as interrupt mode for given port
1779 * @dev: PCI Express port to handle
1780 - * @vectors: Array of interrupt vectors to populate
1781 + * @irqs: Array of interrupt vectors to populate
1782 * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1783 *
1784 * Return value: 0 on success, error code on failure
1785 */
1786 -static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1787 +static int pcie_port_enable_msix(struct pci_dev *dev, int *irqs, int mask)
1788 {
1789 - struct msix_entry *msix_entries;
1790 - int idx[PCIE_PORT_DEVICE_MAXSERVICES];
1791 - int nr_entries, status, pos, i, nvec;
1792 - u16 reg16;
1793 - u32 reg32;
1794 -
1795 - nr_entries = pci_msix_vec_count(dev);
1796 - if (nr_entries < 0)
1797 - return nr_entries;
1798 - BUG_ON(!nr_entries);
1799 - if (nr_entries > PCIE_PORT_MAX_MSIX_ENTRIES)
1800 - nr_entries = PCIE_PORT_MAX_MSIX_ENTRIES;
1801 -
1802 - msix_entries = kzalloc(sizeof(*msix_entries) * nr_entries, GFP_KERNEL);
1803 - if (!msix_entries)
1804 - return -ENOMEM;
1805 + int nr_entries, entry, nvec = 0;
1806
1807 /*
1808 * Allocate as many entries as the port wants, so that we can check
1809 @@ -97,20 +75,13 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1810 * equal to the number of entries this port actually uses, we'll happily
1811 * go through without any tricks.
1812 */
1813 - for (i = 0; i < nr_entries; i++)
1814 - msix_entries[i].entry = i;
1815 -
1816 - status = pci_enable_msix_exact(dev, msix_entries, nr_entries);
1817 - if (status)
1818 - goto Exit;
1819 -
1820 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1821 - idx[i] = -1;
1822 - status = -EIO;
1823 - nvec = 0;
1824 + nr_entries = pci_alloc_irq_vectors(dev, 1, PCIE_PORT_MAX_MSIX_ENTRIES,
1825 + PCI_IRQ_MSIX);
1826 + if (nr_entries < 0)
1827 + return nr_entries;
1828
1829 if (mask & (PCIE_PORT_SERVICE_PME | PCIE_PORT_SERVICE_HP)) {
1830 - int entry;
1831 + u16 reg16;
1832
1833 /*
1834 * The code below follows the PCI Express Base Specification 2.0
1835 @@ -125,18 +96,16 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1836 pcie_capability_read_word(dev, PCI_EXP_FLAGS, &reg16);
1837 entry = (reg16 & PCI_EXP_FLAGS_IRQ) >> 9;
1838 if (entry >= nr_entries)
1839 - goto Error;
1840 + goto out_free_irqs;
1841
1842 - i = pcie_port_msix_add_entry(msix_entries, entry, nvec);
1843 - if (i == nvec)
1844 - nvec++;
1845 + irqs[PCIE_PORT_SERVICE_PME_SHIFT] = pci_irq_vector(dev, entry);
1846 + irqs[PCIE_PORT_SERVICE_HP_SHIFT] = pci_irq_vector(dev, entry);
1847
1848 - idx[PCIE_PORT_SERVICE_PME_SHIFT] = i;
1849 - idx[PCIE_PORT_SERVICE_HP_SHIFT] = i;
1850 + nvec = max(nvec, entry + 1);
1851 }
1852
1853 if (mask & PCIE_PORT_SERVICE_AER) {
1854 - int entry;
1855 + u32 reg32, pos;
1856
1857 /*
1858 * The code below follows Section 7.10.10 of the PCI Express
1859 @@ -151,13 +120,11 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1860 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &reg32);
1861 entry = reg32 >> 27;
1862 if (entry >= nr_entries)
1863 - goto Error;
1864 + goto out_free_irqs;
1865
1866 - i = pcie_port_msix_add_entry(msix_entries, entry, nvec);
1867 - if (i == nvec)
1868 - nvec++;
1869 + irqs[PCIE_PORT_SERVICE_AER_SHIFT] = pci_irq_vector(dev, entry);
1870
1871 - idx[PCIE_PORT_SERVICE_AER_SHIFT] = i;
1872 + nvec = max(nvec, entry + 1);
1873 }
1874
1875 /*
1876 @@ -165,41 +132,54 @@ static int pcie_port_enable_msix(struct pci_dev *dev, int *vectors, int mask)
1877 * what we have. Otherwise, the port has some extra entries not for the
1878 * services we know and we need to work around that.
1879 */
1880 - if (nvec == nr_entries) {
1881 - status = 0;
1882 - } else {
1883 + if (nvec != nr_entries) {
1884 /* Drop the temporary MSI-X setup */
1885 - pci_disable_msix(dev);
1886 + pci_free_irq_vectors(dev);
1887
1888 /* Now allocate the MSI-X vectors for real */
1889 - status = pci_enable_msix_exact(dev, msix_entries, nvec);
1890 - if (status)
1891 - goto Exit;
1892 + nr_entries = pci_alloc_irq_vectors(dev, nvec, nvec,
1893 + PCI_IRQ_MSIX);
1894 + if (nr_entries < 0)
1895 + return nr_entries;
1896 }
1897
1898 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1899 - vectors[i] = idx[i] >= 0 ? msix_entries[idx[i]].vector : -1;
1900 -
1901 - Exit:
1902 - kfree(msix_entries);
1903 - return status;
1904 + return 0;
1905
1906 - Error:
1907 - pci_disable_msix(dev);
1908 - goto Exit;
1909 +out_free_irqs:
1910 + pci_free_irq_vectors(dev);
1911 + return -EIO;
1912 }
1913
1914 /**
1915 - * init_service_irqs - initialize irqs for PCI Express port services
1916 + * pcie_init_service_irqs - initialize irqs for PCI Express port services
1917 * @dev: PCI Express port to handle
1918 * @irqs: Array of irqs to populate
1919 * @mask: Bitmask of port capabilities returned by get_port_device_capability()
1920 *
1921 * Return value: Interrupt mode associated with the port
1922 */
1923 -static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1924 +static int pcie_init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1925 {
1926 - int i, irq = -1;
1927 + unsigned flags = PCI_IRQ_LEGACY | PCI_IRQ_MSI;
1928 + int ret, i;
1929 + int irq = -1;
1930 +
1931 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1932 + irqs[i] = -1;
1933 +
1934 + /* Check if some platforms owns independent irq pins for AER/PME etc.
1935 + * Some platforms may own independent AER/PME interrupts and set
1936 + * them in the device tree file.
1937 + */
1938 + ret = pcibios_check_service_irqs(dev, irqs, mask);
1939 + if (ret) {
1940 + if (dev->irq)
1941 + irq = dev->irq;
1942 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1943 + if (irqs[i] == -1 && i != PCIE_PORT_SERVICE_VC_SHIFT)
1944 + irqs[i] = irq;
1945 + return 0;
1946 + }
1947
1948 /*
1949 * If MSI cannot be used for PCIe PME or hotplug, we have to use
1950 @@ -207,41 +187,25 @@ static int init_service_irqs(struct pci_dev *dev, int *irqs, int mask)
1951 */
1952 if (((mask & PCIE_PORT_SERVICE_PME) && pcie_pme_no_msi()) ||
1953 ((mask & PCIE_PORT_SERVICE_HP) && pciehp_no_msi())) {
1954 - if (dev->irq)
1955 - irq = dev->irq;
1956 - goto no_msi;
1957 + flags &= ~PCI_IRQ_MSI;
1958 + } else {
1959 + /* Try to use MSI-X if supported */
1960 + if (!pcie_port_enable_msix(dev, irqs, mask))
1961 + return 0;
1962 }
1963
1964 - /* Try to use MSI-X if supported */
1965 - if (!pcie_port_enable_msix(dev, irqs, mask))
1966 - return 0;
1967 -
1968 - /*
1969 - * We're not going to use MSI-X, so try MSI and fall back to INTx.
1970 - * If neither MSI/MSI-X nor INTx available, try other interrupt. On
1971 - * some platforms, root port doesn't support MSI/MSI-X/INTx in RC mode.
1972 - */
1973 - if (!pci_enable_msi(dev) || dev->irq)
1974 - irq = dev->irq;
1975 + ret = pci_alloc_irq_vectors(dev, 1, 1, flags);
1976 + if (ret < 0)
1977 + return -ENODEV;
1978
1979 - no_msi:
1980 - for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++)
1981 - irqs[i] = irq;
1982 - irqs[PCIE_PORT_SERVICE_VC_SHIFT] = -1;
1983 + for (i = 0; i < PCIE_PORT_DEVICE_MAXSERVICES; i++) {
1984 + if (i != PCIE_PORT_SERVICE_VC_SHIFT)
1985 + irqs[i] = pci_irq_vector(dev, 0);
1986 + }
1987
1988 - if (irq < 0)
1989 - return -ENODEV;
1990 return 0;
1991 }
1992
1993 -static void cleanup_service_irqs(struct pci_dev *dev)
1994 -{
1995 - if (dev->msix_enabled)
1996 - pci_disable_msix(dev);
1997 - else if (dev->msi_enabled)
1998 - pci_disable_msi(dev);
1999 -}
2000 -
2001 /**
2002 * get_port_device_capability - discover capabilities of a PCI Express port
2003 * @dev: PCI Express port to examine
2004 @@ -378,7 +342,7 @@ int pcie_port_device_register(struct pci_dev *dev)
2005 * that can be used in the absence of irqs. Allow them to determine
2006 * if that is to be used.
2007 */
2008 - status = init_service_irqs(dev, irqs, capabilities);
2009 + status = pcie_init_service_irqs(dev, irqs, capabilities);
2010 if (status) {
2011 capabilities &= PCIE_PORT_SERVICE_VC | PCIE_PORT_SERVICE_HP;
2012 if (!capabilities)
2013 @@ -401,7 +365,7 @@ int pcie_port_device_register(struct pci_dev *dev)
2014 return 0;
2015
2016 error_cleanup_irqs:
2017 - cleanup_service_irqs(dev);
2018 + pci_free_irq_vectors(dev);
2019 error_disable:
2020 pci_disable_device(dev);
2021 return status;
2022 @@ -469,7 +433,7 @@ static int remove_iter(struct device *dev, void *data)
2023 void pcie_port_device_remove(struct pci_dev *dev)
2024 {
2025 device_for_each_child(&dev->dev, NULL, remove_iter);
2026 - cleanup_service_irqs(dev);
2027 + pci_free_irq_vectors(dev);
2028 pci_disable_device(dev);
2029 }
2030
2031 @@ -499,7 +463,6 @@ static int pcie_port_probe_service(struct device *dev)
2032 if (status)
2033 return status;
2034
2035 - dev_printk(KERN_DEBUG, dev, "service driver %s loaded\n", driver->name);
2036 get_device(dev);
2037 return 0;
2038 }
2039 @@ -524,8 +487,6 @@ static int pcie_port_remove_service(struct device *dev)
2040 pciedev = to_pcie_device(dev);
2041 driver = to_service_driver(dev->driver);
2042 if (driver && driver->remove) {
2043 - dev_printk(KERN_DEBUG, dev, "unloading service driver %s\n",
2044 - driver->name);
2045 driver->remove(pciedev);
2046 put_device(dev);
2047 }
2048 diff --git a/include/linux/pci.h b/include/linux/pci.h
2049 index 1b711796..6738d816 100644
2050 --- a/include/linux/pci.h
2051 +++ b/include/linux/pci.h
2052 @@ -1823,6 +1823,7 @@ void pcibios_release_device(struct pci_dev *dev);
2053 void pcibios_penalize_isa_irq(int irq, int active);
2054 int pcibios_alloc_irq(struct pci_dev *dev);
2055 void pcibios_free_irq(struct pci_dev *dev);
2056 +int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask);
2057
2058 #ifdef CONFIG_HIBERNATE_CALLBACKS
2059 extern struct dev_pm_ops pcibios_pm_ops;
2060 --
2061 2.14.1
2062
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