target/linux/layerscape/patches-4.9/801-ata-support-layerscape.patch

   1 From 4c3979602db05bca439bfc98db88dc14a8663db0 Mon Sep 17 00:00:00 2001
   2 From: Yangbo Lu <yangbo.lu@nxp.com>
   3 Date: Wed, 17 Jan 2018 15:14:57 +0800
   4 Subject: [PATCH 13/30] ata: support layerscape
   5
   6 This is an integrated patch for layerscape sata support.
   7
   8 Signed-off-by: Tang Yuantian <Yuantian.Tang@nxp.com>
   9 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  10 ---
  11  drivers/ata/ahci_qoriq.c | 63 ++++++++++++++++++++++++++++++++++++++++++------
  12  1 file changed, 56 insertions(+), 7 deletions(-)
  13
  14 --- a/drivers/ata/ahci_qoriq.c
  15 +++ b/drivers/ata/ahci_qoriq.c
  16 @@ -1,7 +1,7 @@
  17  /*
  18   * Freescale QorIQ AHCI SATA platform driver
  19   *
  20 - * Copyright 2015 Freescale, Inc.
  21 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  22   *   Tang Yuantian <Yuantian.Tang@freescale.com>
  23   *
  24   * This program is free software; you can redistribute it and/or modify
  25 @@ -46,23 +46,32 @@
  26  #define LS1021A_AXICC_ADDR     0xC0
  27
  28  #define SATA_ECC_DISABLE       0x00020000
  29 +#define ECC_DIS_ARMV8_CH2      0x80000000
  30 +#define ECC_DIS_LS1088A                0x40000000
  31
  32  enum ahci_qoriq_type {
  33         AHCI_LS1021A,
  34         AHCI_LS1043A,
  35         AHCI_LS2080A,
  36 +       AHCI_LS1046A,
  37 +       AHCI_LS1088A,
  38 +       AHCI_LS2088A,
  39  };
  40
  41  struct ahci_qoriq_priv {
  42         struct ccsr_ahci *reg_base;
  43         enum ahci_qoriq_type type;
  44         void __iomem *ecc_addr;
  45 +       bool is_dmacoherent;
  46  };
  47
  48  static const struct of_device_id ahci_qoriq_of_match[] = {
  49         { .compatible = "fsl,ls1021a-ahci", .data = (void *)AHCI_LS1021A},
  50         { .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
  51         { .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
  52 +       { .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
  53 +       { .compatible = "fsl,ls1088a-ahci", .data = (void *)AHCI_LS1088A},
  54 +       { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
  55         {},
  56  };
  57  MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
  58 @@ -154,6 +163,8 @@ static int ahci_qoriq_phy_init(struct ah
  59
  60         switch (qpriv->type) {
  61         case AHCI_LS1021A:
  62 +               if (!qpriv->ecc_addr)
  63 +                       return -EINVAL;
  64                 writel(SATA_ECC_DISABLE, qpriv->ecc_addr);
  65                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  66                 writel(LS1021A_PORT_PHY2, reg_base + PORT_PHY2);
  67 @@ -161,19 +172,56 @@ static int ahci_qoriq_phy_init(struct ah
  68                 writel(LS1021A_PORT_PHY4, reg_base + PORT_PHY4);
  69                 writel(LS1021A_PORT_PHY5, reg_base + PORT_PHY5);
  70                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  71 -               writel(AHCI_PORT_AXICC_CFG, reg_base + LS1021A_AXICC_ADDR);
  72 +               if (qpriv->is_dmacoherent)
  73 +                       writel(AHCI_PORT_AXICC_CFG,
  74 +                                       reg_base + LS1021A_AXICC_ADDR);
  75                 break;
  76
  77         case AHCI_LS1043A:
  78 +               if (!qpriv->ecc_addr)
  79 +                       return -EINVAL;
  80 +               writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
  81 +                               qpriv->ecc_addr);
  82                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  83                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  84 -               writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  85 +               if (qpriv->is_dmacoherent)
  86 +                       writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  87                 break;
  88
  89         case AHCI_LS2080A:
  90                 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
  91                 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
  92 -               writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  93 +               if (qpriv->is_dmacoherent)
  94 +                       writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
  95 +               break;
  96 +
  97 +       case AHCI_LS1046A:
  98 +               if (!qpriv->ecc_addr)
  99 +                       return -EINVAL;
 100 +               writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2,
 101 +                               qpriv->ecc_addr);
 102 +               writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 103 +               writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 104 +               if (qpriv->is_dmacoherent)
 105 +                       writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 106 +               break;
 107 +
 108 +       case AHCI_LS1088A:
 109 +               if (!qpriv->ecc_addr)
 110 +                       return -EINVAL;
 111 +               writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A,
 112 +                      qpriv->ecc_addr);
 113 +               writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 114 +               writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 115 +               if (qpriv->is_dmacoherent)
 116 +                       writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 117 +               break;
 118 +
 119 +       case AHCI_LS2088A:
 120 +               writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
 121 +               writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
 122 +               if (qpriv->is_dmacoherent)
 123 +                       writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
 124                 break;
 125         }
 126
 127 @@ -204,13 +252,14 @@ static int ahci_qoriq_probe(struct platf
 128
 129         qoriq_priv->type = (enum ahci_qoriq_type)of_id->data;
 130
 131 -       if (qoriq_priv->type == AHCI_LS1021A) {
 132 -               res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 133 -                               "sata-ecc");
 134 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 135 +                       "sata-ecc");
 136 +       if (res) {
 137                 qoriq_priv->ecc_addr = devm_ioremap_resource(dev, res);
 138                 if (IS_ERR(qoriq_priv->ecc_addr))
 139                         return PTR_ERR(qoriq_priv->ecc_addr);
 140         }
 141 +       qoriq_priv->is_dmacoherent = of_dma_is_coherent(np);
 142
 143         rc = ahci_platform_enable_resources(hpriv);
 144         if (rc)