kernel: bump 4.9 to 4.9.143
[openwrt/openwrt.git] / target / linux / layerscape / patches-4.9 / 817-usb-support-layerscape.patch
1 From 1d35e363dd6e8bb1733bca0dfc186e3f70e692fe Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Thu, 5 Jul 2018 17:38:52 +0800
4 Subject: [PATCH 29/32] usb: support layerscape
5
6 This is an integrated patch for layerscape usb support.
7
8 Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
9 Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
10 Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
11 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
12 Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
15 Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
16 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
17 ---
18 drivers/net/usb/cdc_ether.c | 8 +
19 drivers/net/usb/r8152.c | 6 +
20 drivers/usb/common/common.c | 50 +++++
21 drivers/usb/core/hub.c | 8 +
22 drivers/usb/dwc3/core.c | 243 +++++++++++++++++++++-
23 drivers/usb/dwc3/core.h | 51 ++++-
24 drivers/usb/dwc3/ep0.c | 4 +-
25 drivers/usb/dwc3/gadget.c | 7 +
26 drivers/usb/dwc3/host.c | 24 ++-
27 drivers/usb/gadget/udc/fsl_udc_core.c | 46 +++--
28 drivers/usb/gadget/udc/fsl_usb2_udc.h | 16 +-
29 drivers/usb/host/Kconfig | 4 +-
30 drivers/usb/host/ehci-fsl.c | 279 ++++++++++++++++++++++++--
31 drivers/usb/host/ehci-fsl.h | 3 +
32 drivers/usb/host/ehci-hub.c | 4 +
33 drivers/usb/host/ehci.h | 9 +
34 drivers/usb/host/fsl-mph-dr-of.c | 16 +-
35 drivers/usb/host/xhci-hub.c | 22 ++
36 drivers/usb/host/xhci-plat.c | 16 +-
37 drivers/usb/host/xhci-ring.c | 29 ++-
38 drivers/usb/host/xhci.c | 38 +++-
39 drivers/usb/host/xhci.h | 6 +-
40 drivers/usb/phy/phy-fsl-usb.c | 59 ++++--
41 drivers/usb/phy/phy-fsl-usb.h | 8 +
42 include/linux/usb.h | 1 +
43 include/linux/usb/of.h | 2 +
44 26 files changed, 867 insertions(+), 92 deletions(-)
45
46 --- a/drivers/net/usb/cdc_ether.c
47 +++ b/drivers/net/usb/cdc_ether.c
48 @@ -533,6 +533,7 @@ static const struct driver_info wwan_inf
49 #define LINKSYS_VENDOR_ID 0x13b1
50 #define NVIDIA_VENDOR_ID 0x0955
51 #define HP_VENDOR_ID 0x03f0
52 +#define TPLINK_VENDOR_ID 0x2357
53
54 static const struct usb_device_id products[] = {
55 /* BLACKLIST !!
56 @@ -742,6 +743,13 @@ static const struct usb_device_id produc
57 USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
58 .driver_info = 0,
59 },
60 +
61 + /* TP-LINK UE300 USB 3.0 Ethernet Adapters (based on Realtek RTL8153) */
62 +{
63 + USB_DEVICE_AND_INTERFACE_INFO(TPLINK_VENDOR_ID, 0x0601, USB_CLASS_COMM,
64 + USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
65 + .driver_info = 0,
66 +},
67
68 /* WHITELIST!!!
69 *
70 --- a/drivers/net/usb/r8152.c
71 +++ b/drivers/net/usb/r8152.c
72 @@ -521,6 +521,7 @@ enum rtl8152_flags {
73 #define VENDOR_ID_LENOVO 0x17ef
74 #define VENDOR_ID_LINKSYS 0x13b1
75 #define VENDOR_ID_NVIDIA 0x0955
76 +#define VENDOR_ID_TPLINK 0x2357
77
78 #define MCU_TYPE_PLA 0x0100
79 #define MCU_TYPE_USB 0x0000
80 @@ -1817,6 +1818,10 @@ static int rx_bottom(struct r8152 *tp, i
81 unsigned int pkt_len;
82 struct sk_buff *skb;
83
84 + /* limite the skb numbers for rx_queue */
85 + if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
86 + break;
87 +
88 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
89 if (pkt_len < ETH_ZLEN)
90 break;
91 @@ -4513,6 +4518,7 @@ static struct usb_device_id rtl8152_tabl
92 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
93 {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
94 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
95 + {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)},
96 {}
97 };
98
99 --- a/drivers/usb/common/common.c
100 +++ b/drivers/usb/common/common.c
101 @@ -105,6 +105,56 @@ static const char *const usb_dr_modes[]
102 [USB_DR_MODE_OTG] = "otg",
103 };
104
105 +/**
106 + * of_usb_get_dr_mode - Get dual role mode for given device_node
107 + * @np: Pointer to the given device_node
108 + *
109 + * The function gets phy interface string from property 'dr_mode',
110 + * and returns the correspondig enum usb_dr_mode
111 + */
112 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np)
113 +{
114 + const char *dr_mode;
115 + int err, i;
116 +
117 + err = of_property_read_string(np, "dr_mode", &dr_mode);
118 + if (err < 0)
119 + return USB_DR_MODE_UNKNOWN;
120 +
121 + for (i = 0; i < ARRAY_SIZE(usb_dr_modes); i++)
122 + if (!strcmp(dr_mode, usb_dr_modes[i]))
123 + return i;
124 +
125 + return USB_DR_MODE_UNKNOWN;
126 +}
127 +EXPORT_SYMBOL_GPL(of_usb_get_dr_mode);
128 +
129 +/**
130 + * of_usb_get_maximum_speed - Get maximum requested speed for a given USB
131 + * controller.
132 + * @np: Pointer to the given device_node
133 + *
134 + * The function gets the maximum speed string from property "maximum-speed",
135 + * and returns the corresponding enum usb_device_speed.
136 + */
137 +enum usb_device_speed of_usb_get_maximum_speed(struct device_node *np)
138 +{
139 + const char *maximum_speed;
140 + int err;
141 + int i;
142 +
143 + err = of_property_read_string(np, "maximum-speed", &maximum_speed);
144 + if (err < 0)
145 + return USB_SPEED_UNKNOWN;
146 +
147 + for (i = 0; i < ARRAY_SIZE(speed_names); i++)
148 + if (strcmp(maximum_speed, speed_names[i]) == 0)
149 + return i;
150 +
151 + return USB_SPEED_UNKNOWN;
152 +}
153 +EXPORT_SYMBOL_GPL(of_usb_get_maximum_speed);
154 +
155 static enum usb_dr_mode usb_get_dr_mode_from_string(const char *str)
156 {
157 int ret;
158 --- a/drivers/usb/core/hub.c
159 +++ b/drivers/usb/core/hub.c
160 @@ -4433,6 +4433,14 @@ hub_port_init(struct usb_hub *hub, struc
161 else
162 speed = usb_speed_string(udev->speed);
163
164 +#if !defined(CONFIG_FSL_USB2_OTG) && !defined(CONFIG_FSL_USB2_OTG_MODULE)
165 +if (udev->speed != USB_SPEED_SUPER)
166 + dev_info(&udev->dev,
167 + "%s %s USB device number %d using %s\n",
168 + (udev->config) ? "reset" : "new", speed,
169 + devnum, udev->bus->controller->driver->name);
170 +#endif
171 +
172 if (udev->speed < USB_SPEED_SUPER)
173 dev_info(&udev->dev,
174 "%s %s USB device number %d using %s\n",
175 --- a/drivers/usb/dwc3/core.c
176 +++ b/drivers/usb/dwc3/core.c
177 @@ -58,6 +58,7 @@ static int dwc3_get_dr_mode(struct dwc3
178 enum usb_dr_mode mode;
179 struct device *dev = dwc->dev;
180 unsigned int hw_mode;
181 + struct device_node *node = dev->of_node;
182
183 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
184 dwc->dr_mode = USB_DR_MODE_OTG;
185 @@ -83,6 +84,24 @@ static int dwc3_get_dr_mode(struct dwc3
186 mode = USB_DR_MODE_HOST;
187 break;
188 default:
189 + /* Adjust Frame Length */
190 + if (dwc->configure_gfladj)
191 + dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
192 + GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
193 +
194 + /* Change burst beat and outstanding pipelined transfers requests */
195 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
196 + (dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) & ~0xff) | 0xf);
197 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG1,
198 + dwc3_readl(dwc->regs, DWC3_GSBUSCFG1) | 0xf00);
199 +
200 + /* Enable Snooping */
201 + if (node && of_dma_is_coherent(node)) {
202 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0,
203 + dwc3_readl(dwc->regs, DWC3_GSBUSCFG0) | 0x22220000);
204 + dev_dbg(dev, "enabled snooping for usb\n");
205 + }
206 +
207 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
208 mode = USB_DR_MODE_HOST;
209 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
210 @@ -227,8 +246,9 @@ static void dwc3_frame_length_adjustment
211
212 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
213 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
214 - if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
215 - "request value same as default, ignoring\n")) {
216 + if (dft == dwc->fladj) {
217 + dev_warn(dwc->dev, "request value same as default, ignoring\n");
218 + } else {
219 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
220 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
221 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
222 @@ -599,6 +619,99 @@ static int dwc3_phy_setup(struct dwc3 *d
223 return 0;
224 }
225
226 +/* set global soc bus configuration registers */
227 +static void dwc3_set_soc_bus_cfg(struct dwc3 *dwc)
228 +{
229 + struct device *dev = dwc->dev;
230 + u32 *vals;
231 + u32 cfg;
232 + int ntype;
233 + int ret;
234 + int i;
235 +
236 + cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
237 +
238 + /*
239 + * Handle property "snps,incr-burst-type-adjustment".
240 + * Get the number of value from this property:
241 + * result <= 0, means this property is not supported.
242 + * result = 1, means INCRx burst mode supported.
243 + * result > 1, means undefined length burst mode supported.
244 + */
245 + ntype = device_property_read_u32_array(dev,
246 + "snps,incr-burst-type-adjustment", NULL, 0);
247 + if (ntype > 0) {
248 + vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
249 + if (!vals) {
250 + dev_err(dev, "Error to get memory\n");
251 + return;
252 + }
253 + /* Get INCR burst type, and parse it */
254 + ret = device_property_read_u32_array(dev,
255 + "snps,incr-burst-type-adjustment", vals, ntype);
256 + if (ret) {
257 + dev_err(dev, "Error to get property\n");
258 + return;
259 + }
260 + *(dwc->incrx_type + 1) = vals[0];
261 + if (ntype > 1) {
262 + *dwc->incrx_type = 1;
263 + for (i = 1; i < ntype; i++) {
264 + if (vals[i] > *(dwc->incrx_type + 1))
265 + *(dwc->incrx_type + 1) = vals[i];
266 + }
267 + } else
268 + *dwc->incrx_type = 0;
269 +
270 + /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
271 + cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
272 + if (*dwc->incrx_type)
273 + cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
274 + switch (*(dwc->incrx_type + 1)) {
275 + case 256:
276 + cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
277 + break;
278 + case 128:
279 + cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
280 + break;
281 + case 64:
282 + cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
283 + break;
284 + case 32:
285 + cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
286 + break;
287 + case 16:
288 + cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
289 + break;
290 + case 8:
291 + cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
292 + break;
293 + case 4:
294 + cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
295 + break;
296 + case 1:
297 + break;
298 + default:
299 + dev_err(dev, "Invalid property\n");
300 + break;
301 + }
302 + }
303 +
304 + /* Handle usb snooping */
305 + if (dwc->dma_snooping_quirk) {
306 + cfg &= ~DWC3_GSBUSCFG0_SNP_MASK;
307 + cfg |= (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATARD_SHIFT) |
308 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCRD_SHIFT) |
309 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DATAWR_SHIFT) |
310 + (AXI3_CACHE_TYPE_SNP << DWC3_GSBUSCFG0_DESCWR_SHIFT);
311 + }
312 +
313 + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
314 +
315 +}
316 +
317 +
318 +
319 static void dwc3_core_exit(struct dwc3 *dwc)
320 {
321 dwc3_event_buffers_cleanup(dwc);
322 @@ -741,6 +854,8 @@ static int dwc3_core_init(struct dwc3 *d
323 if (ret)
324 goto err1;
325
326 + dwc3_set_soc_bus_cfg(dwc);
327 +
328 /* Adjust Frame Length */
329 dwc3_frame_length_adjustment(dwc);
330
331 @@ -939,11 +1054,117 @@ static void dwc3_core_exit_mode(struct d
332 }
333 }
334
335 +static void dwc3_get_properties(struct dwc3 *dwc)
336 +{
337 + struct device *dev = dwc->dev;
338 + struct device_node *node = dev->of_node;
339 + u8 lpm_nyet_threshold;
340 + u8 tx_de_emphasis;
341 + u8 hird_threshold;
342 +
343 + /* default to highest possible threshold */
344 + lpm_nyet_threshold = 0xff;
345 +
346 + /* default to -3.5dB de-emphasis */
347 + tx_de_emphasis = 1;
348 +
349 + /*
350 + * default to assert utmi_sleep_n and use maximum allowed HIRD
351 + * threshold value of 0b1100
352 + */
353 + hird_threshold = 12;
354 +
355 + dwc->maximum_speed = usb_get_maximum_speed(dev);
356 + dwc->dr_mode = usb_get_dr_mode(dev);
357 + dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
358 +
359 + dwc->sysdev_is_parent = device_property_read_bool(dev,
360 + "linux,sysdev_is_parent");
361 + if (dwc->sysdev_is_parent)
362 + dwc->sysdev = dwc->dev->parent;
363 + else
364 + dwc->sysdev = dwc->dev;
365 +
366 + dwc->has_lpm_erratum = device_property_read_bool(dev,
367 + "snps,has-lpm-erratum");
368 + device_property_read_u8(dev, "snps,lpm-nyet-threshold",
369 + &lpm_nyet_threshold);
370 + dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
371 + "snps,is-utmi-l1-suspend");
372 + device_property_read_u8(dev, "snps,hird-threshold",
373 + &hird_threshold);
374 + dwc->usb3_lpm_capable = device_property_read_bool(dev,
375 + "snps,usb3_lpm_capable");
376 + dwc->quirk_reverse_in_out = device_property_read_bool(dev,
377 + "snps,quirk_reverse_in_out");
378 + dwc->quirk_stop_transfer_in_block = device_property_read_bool(dev,
379 + "snps,quirk_stop_transfer_in_block");
380 + dwc->quirk_stop_ep_in_u1 = device_property_read_bool(dev,
381 + "snps,quirk_stop_ep_in_u1");
382 +
383 + dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
384 +
385 + dwc->configure_gfladj =
386 + of_property_read_bool(node, "configure-gfladj");
387 + dwc->dr_mode = usb_get_dr_mode(dev);
388 +
389 + dwc->disable_scramble_quirk = device_property_read_bool(dev,
390 + "snps,disable_scramble_quirk");
391 + dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
392 + "snps,u2exit_lfps_quirk");
393 + dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
394 + "snps,u2ss_inp3_quirk");
395 + dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
396 + "snps,req_p1p2p3_quirk");
397 + dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
398 + "snps,del_p1p2p3_quirk");
399 + dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
400 + "snps,del_phy_power_chg_quirk");
401 + dwc->lfps_filter_quirk = device_property_read_bool(dev,
402 + "snps,lfps_filter_quirk");
403 + dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
404 + "snps,rx_detect_poll_quirk");
405 + dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
406 + "snps,dis_u3_susphy_quirk");
407 + dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
408 + "snps,dis_u2_susphy_quirk");
409 + dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
410 + "snps,dis_enblslpm_quirk");
411 + dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
412 + "snps,dis_rxdet_inp3_quirk");
413 + dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
414 + "snps,dis-u2-freeclk-exists-quirk");
415 + dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
416 + "snps,dis-del-phy-power-chg-quirk");
417 + dwc->dma_snooping_quirk = device_property_read_bool(dev,
418 + "snps,dma-snooping");
419 +
420 + dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
421 + "snps,tx_de_emphasis_quirk");
422 + dwc->disable_devinit_u1u2_quirk = device_property_read_bool(dev,
423 + "snps,disable_devinit_u1u2");
424 + device_property_read_u8(dev, "snps,tx_de_emphasis",
425 + &tx_de_emphasis);
426 + device_property_read_string(dev, "snps,hsphy_interface",
427 + &dwc->hsphy_interface);
428 + device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
429 + &dwc->fladj);
430 +
431 + dwc->lpm_nyet_threshold = lpm_nyet_threshold;
432 + dwc->tx_de_emphasis = tx_de_emphasis;
433 +
434 + dwc->hird_threshold = hird_threshold
435 + | (dwc->is_utmi_l1_suspend << 4);
436 +
437 + dwc->imod_interval = 0;
438 +}
439 +
440 #define DWC3_ALIGN_MASK (16 - 1)
441
442 static int dwc3_probe(struct platform_device *pdev)
443 {
444 struct device *dev = &pdev->dev;
445 + struct device_node *node = dev->of_node;
446 struct resource *res;
447 struct dwc3 *dwc;
448 u8 lpm_nyet_threshold;
449 @@ -975,6 +1196,11 @@ static int dwc3_probe(struct platform_de
450 dwc->xhci_resources[0].flags = res->flags;
451 dwc->xhci_resources[0].name = res->name;
452
453 + if (node) {
454 + dwc->configure_gfladj =
455 + of_property_read_bool(node, "configure-gfladj");
456 + }
457 +
458 res->start += DWC3_GLOBALS_REGS_START;
459
460 /*
461 @@ -1017,6 +1243,12 @@ static int dwc3_probe(struct platform_de
462 dwc->usb3_lpm_capable = device_property_read_bool(dev,
463 "snps,usb3_lpm_capable");
464
465 + dwc->needs_fifo_resize = of_property_read_bool(node, "tx-fifo-resize");
466 +
467 + dwc->configure_gfladj =
468 + of_property_read_bool(node, "configure-gfladj");
469 + dwc->dr_mode = of_usb_get_dr_mode(node);
470 +
471 dwc->disable_scramble_quirk = device_property_read_bool(dev,
472 "snps,disable_scramble_quirk");
473 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
474 @@ -1061,6 +1293,8 @@ static int dwc3_probe(struct platform_de
475 dwc->hird_threshold = hird_threshold
476 | (dwc->is_utmi_l1_suspend << 4);
477
478 + dwc3_get_properties(dwc);
479 +
480 platform_set_drvdata(pdev, dwc);
481 dwc3_cache_hwparams(dwc);
482
483 @@ -1084,6 +1318,11 @@ static int dwc3_probe(struct platform_de
484 if (ret < 0)
485 goto err1;
486
487 + /* Adjust Frame Length */
488 + if (dwc->configure_gfladj)
489 + dwc3_writel(dwc->regs, DWC3_GFLADJ, GFLADJ_30MHZ_REG_SEL |
490 + GFLADJ_30MHZ(GFLADJ_30MHZ_DEFAULT));
491 +
492 pm_runtime_forbid(dev);
493
494 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
495 --- a/drivers/usb/dwc3/core.h
496 +++ b/drivers/usb/dwc3/core.h
497 @@ -26,6 +26,7 @@
498 #include <linux/dma-mapping.h>
499 #include <linux/mm.h>
500 #include <linux/debugfs.h>
501 +#include <linux/of_address.h>
502
503 #include <linux/usb/ch9.h>
504 #include <linux/usb/gadget.h>
505 @@ -154,6 +155,32 @@
506
507 /* Bit fields */
508
509 +/* Global SoC Bus Configuration Register 0 */
510 +#define AXI3_CACHE_TYPE_AW 0x8 /* write allocate */
511 +#define AXI3_CACHE_TYPE_AR 0x4 /* read allocate */
512 +#define AXI3_CACHE_TYPE_SNP 0x2 /* cacheable */
513 +#define AXI3_CACHE_TYPE_BUF 0x1 /* bufferable */
514 +#define DWC3_GSBUSCFG0_DATARD_SHIFT 28
515 +#define DWC3_GSBUSCFG0_DESCRD_SHIFT 24
516 +#define DWC3_GSBUSCFG0_DATAWR_SHIFT 20
517 +#define DWC3_GSBUSCFG0_DESCWR_SHIFT 16
518 +#define DWC3_GSBUSCFG0_SNP_MASK 0xffff0000
519 +#define DWC3_GSBUSCFG0_DATABIGEND (1 << 11)
520 +#define DWC3_GSBUSCFG0_DESCBIGEND (1 << 10)
521 +#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
522 +#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
523 +#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
524 +#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
525 +#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
526 +#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
527 +#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
528 +#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
529 +#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
530 +
531 +/* Global SoC Bus Configuration Register 1 */
532 +#define DWC3_GSBUSCFG1_1KPAGEENA (1 << 12) /* 1K page boundary enable */
533 +#define DWC3_GSBUSCFG1_PTRANSLIMIT_MASK 0xf00
534 +
535 /* Global Debug Queue/FIFO Space Available Register */
536 #define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
537 #define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
538 @@ -182,7 +209,6 @@
539 #define DWC3_GCTL_CLK_PIPE (1)
540 #define DWC3_GCTL_CLK_PIPEHALF (2)
541 #define DWC3_GCTL_CLK_MASK (3)
542 -
543 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
544 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
545 #define DWC3_GCTL_PRTCAP_HOST 1
546 @@ -294,6 +320,10 @@
547 /* Global Frame Length Adjustment Register */
548 #define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
549 #define DWC3_GFLADJ_30MHZ_MASK 0x3f
550 +#define GFLADJ_30MHZ_REG_SEL (1 << 7)
551 +#define GFLADJ_30MHZ(n) ((n) & 0x3f)
552 +#define GFLADJ_30MHZ_DEFAULT 0x20
553 +
554
555 /* Global User Control Register 2 */
556 #define DWC3_GUCTL2_RST_ACTBITLATER (1 << 14)
557 @@ -758,6 +788,7 @@ struct dwc3_scratchpad_array {
558 * @regs: base address for our registers
559 * @regs_size: address space size
560 * @fladj: frame length adjustment
561 + * @incrx_type: INCR burst type adjustment
562 * @irq_gadget: peripheral controller's IRQ number
563 * @nr_scratch: number of scratch buffers
564 * @u1u2: only used on revisions <1.83a for workaround
565 @@ -834,6 +865,7 @@ struct dwc3_scratchpad_array {
566 * 1 - -3.5dB de-emphasis
567 * 2 - No de-emphasis
568 * 3 - Reserved
569 + * @disable_devinit_u1u2_quirk: disable device-initiated U1/U2 request.
570 */
571 struct dwc3 {
572 struct usb_ctrlrequest *ctrl_req;
573 @@ -852,6 +884,7 @@ struct dwc3 {
574 spinlock_t lock;
575
576 struct device *dev;
577 + struct device *sysdev;
578
579 struct platform_device *xhci;
580 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
581 @@ -877,6 +910,12 @@ struct dwc3 {
582 enum usb_phy_interface hsphy_mode;
583
584 u32 fladj;
585 + /*
586 + * For INCR burst type.
587 + * First field: for undefined length INCR burst type enable.
588 + * Second field: for INCRx burst type enable
589 + */
590 + u32 incrx_type[2];
591 u32 irq_gadget;
592 u32 nr_scratch;
593 u32 u1u2;
594 @@ -953,9 +992,12 @@ struct dwc3 {
595 unsigned ep0_bounced:1;
596 unsigned ep0_expect_in:1;
597 unsigned has_hibernation:1;
598 + unsigned sysdev_is_parent:1;
599 unsigned has_lpm_erratum:1;
600 unsigned is_utmi_l1_suspend:1;
601 unsigned is_fpga:1;
602 + unsigned needs_fifo_resize:1;
603 + unsigned configure_gfladj:1;
604 unsigned pending_events:1;
605 unsigned pullups_connected:1;
606 unsigned setup_packet_pending:1;
607 @@ -976,9 +1018,16 @@ struct dwc3 {
608 unsigned dis_rxdet_inp3_quirk:1;
609 unsigned dis_u2_freeclk_exists_quirk:1;
610 unsigned dis_del_phy_power_chg_quirk:1;
611 + unsigned dma_snooping_quirk:1;
612
613 unsigned tx_de_emphasis_quirk:1;
614 unsigned tx_de_emphasis:2;
615 + unsigned disable_devinit_u1u2_quirk:1;
616 + unsigned quirk_reverse_in_out:1;
617 + unsigned quirk_stop_transfer_in_block:1;
618 + unsigned quirk_stop_ep_in_u1:1;
619 +
620 + u16 imod_interval;
621 };
622
623 /* -------------------------------------------------------------------------- */
624 --- a/drivers/usb/dwc3/ep0.c
625 +++ b/drivers/usb/dwc3/ep0.c
626 @@ -360,9 +360,9 @@ static int dwc3_ep0_handle_status(struct
627 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
628 (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
629 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
630 - if (reg & DWC3_DCTL_INITU1ENA)
631 + if ((reg & DWC3_DCTL_INITU1ENA) && !dwc->disable_devinit_u1u2_quirk)
632 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
633 - if (reg & DWC3_DCTL_INITU2ENA)
634 + if ((reg & DWC3_DCTL_INITU2ENA) && !dwc->disable_devinit_u1u2_quirk)
635 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
636 }
637
638 --- a/drivers/usb/dwc3/gadget.c
639 +++ b/drivers/usb/dwc3/gadget.c
640 @@ -2927,6 +2927,7 @@ static irqreturn_t dwc3_interrupt(int ir
641 int dwc3_gadget_init(struct dwc3 *dwc)
642 {
643 int ret, irq;
644 + u32 reg;
645 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
646
647 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
648 @@ -3041,6 +3042,12 @@ int dwc3_gadget_init(struct dwc3 *dwc)
649 goto err5;
650 }
651
652 + if (dwc->disable_devinit_u1u2_quirk) {
653 + reg = dwc3_readl(dwc->regs, DWC3_DCTL);
654 + reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA);
655 + dwc3_writel(dwc->regs, DWC3_DCTL, reg);
656 + }
657 +
658 return 0;
659
660 err5:
661 --- a/drivers/usb/dwc3/host.c
662 +++ b/drivers/usb/dwc3/host.c
663 @@ -17,6 +17,8 @@
664
665 #include <linux/platform_device.h>
666
667 +#include <linux/of_device.h>
668 +
669 #include "core.h"
670
671 int dwc3_host_init(struct dwc3 *dwc)
672 @@ -73,12 +75,21 @@ int dwc3_host_init(struct dwc3 *dwc)
673 return -ENOMEM;
674 }
675
676 - dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
677 + if (IS_ENABLED(CONFIG_OF) && dwc->dev->of_node)
678 + of_dma_configure(&xhci->dev, dwc->dev->of_node);
679 + else
680 + dma_set_coherent_mask(&xhci->dev, dwc->dev->coherent_dma_mask);
681
682 - xhci->dev.parent = dwc->dev;
683 + xhci->dev.parent = dwc->dev;
684 xhci->dev.dma_mask = dwc->dev->dma_mask;
685 xhci->dev.dma_parms = dwc->dev->dma_parms;
686
687 + /* set DMA operations */
688 + if (dwc->dev->of_node && of_dma_is_coherent(dwc->dev->of_node)) {
689 + xhci->dev.archdata.dma_ops = dwc->dev->archdata.dma_ops;
690 + dev_dbg(dwc->dev, "set dma_ops for usb\n");
691 + }
692 +
693 dwc->xhci = xhci;
694
695 ret = platform_device_add_resources(xhci, dwc->xhci_resources,
696 @@ -90,6 +101,15 @@ int dwc3_host_init(struct dwc3 *dwc)
697
698 memset(props, 0, sizeof(struct property_entry) * ARRAY_SIZE(props));
699
700 + if (dwc->quirk_reverse_in_out)
701 + props[prop_idx++].name = "quirk-reverse-in-out";
702 +
703 + if (dwc->quirk_stop_transfer_in_block)
704 + props[prop_idx++].name = "quirk-stop-transfer-in-block";
705 +
706 + if (dwc->quirk_stop_ep_in_u1)
707 + props[prop_idx++].name = "quirk-stop-ep-in-u1";
708 +
709 if (dwc->usb3_lpm_capable)
710 props[prop_idx++].name = "usb3-lpm-capable";
711
712 --- a/drivers/usb/gadget/udc/fsl_udc_core.c
713 +++ b/drivers/usb/gadget/udc/fsl_udc_core.c
714 @@ -198,7 +198,11 @@ __acquires(ep->udc->lock)
715
716 spin_unlock(&ep->udc->lock);
717
718 - usb_gadget_giveback_request(&ep->ep, &req->req);
719 + /* this complete() should a func implemented by gadget layer,
720 + * eg fsg->bulk_in_complete()
721 + */
722 + if (req->req.complete)
723 + usb_gadget_giveback_request(&ep->ep, &req->req);
724
725 spin_lock(&ep->udc->lock);
726 ep->stopped = stopped;
727 @@ -245,10 +249,10 @@ static int dr_controller_setup(struct fs
728 if (udc->pdata->have_sysif_regs) {
729 if (udc->pdata->controller_ver) {
730 /* controller version 1.6 or above */
731 - ctrl = __raw_readl(&usb_sys_regs->control);
732 + ctrl = ioread32be(&usb_sys_regs->control);
733 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
734 ctrl |= USB_CTRL_USB_EN;
735 - __raw_writel(ctrl, &usb_sys_regs->control);
736 + iowrite32be(ctrl, &usb_sys_regs->control);
737 }
738 }
739 portctrl |= PORTSCX_PTS_ULPI;
740 @@ -257,13 +261,14 @@ static int dr_controller_setup(struct fs
741 portctrl |= PORTSCX_PTW_16BIT;
742 /* fall through */
743 case FSL_USB2_PHY_UTMI:
744 + case FSL_USB2_PHY_UTMI_DUAL:
745 if (udc->pdata->have_sysif_regs) {
746 if (udc->pdata->controller_ver) {
747 /* controller version 1.6 or above */
748 - ctrl = __raw_readl(&usb_sys_regs->control);
749 + ctrl = ioread32be(&usb_sys_regs->control);
750 ctrl |= (USB_CTRL_UTMI_PHY_EN |
751 USB_CTRL_USB_EN);
752 - __raw_writel(ctrl, &usb_sys_regs->control);
753 + iowrite32be(ctrl, &usb_sys_regs->control);
754 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
755 PHY CLK to become stable - 10ms*/
756 }
757 @@ -329,22 +334,22 @@ static int dr_controller_setup(struct fs
758 /* Config control enable i/o output, cpu endian register */
759 #ifndef CONFIG_ARCH_MXC
760 if (udc->pdata->have_sysif_regs) {
761 - ctrl = __raw_readl(&usb_sys_regs->control);
762 + ctrl = ioread32be(&usb_sys_regs->control);
763 ctrl |= USB_CTRL_IOENB;
764 - __raw_writel(ctrl, &usb_sys_regs->control);
765 + iowrite32be(ctrl, &usb_sys_regs->control);
766 }
767 #endif
768
769 -#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
770 +#if !defined(CONFIG_NOT_COHERENT_CACHE)
771 /* Turn on cache snooping hardware, since some PowerPC platforms
772 * wholly rely on hardware to deal with cache coherent. */
773
774 if (udc->pdata->have_sysif_regs) {
775 /* Setup Snooping for all the 4GB space */
776 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
777 - __raw_writel(tmp, &usb_sys_regs->snoop1);
778 + iowrite32be(tmp, &usb_sys_regs->snoop1);
779 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
780 - __raw_writel(tmp, &usb_sys_regs->snoop2);
781 + iowrite32be(tmp, &usb_sys_regs->snoop2);
782 }
783 #endif
784
785 @@ -1057,7 +1062,7 @@ static int fsl_ep_fifo_status(struct usb
786 struct ep_queue_head *qh;
787
788 ep = container_of(_ep, struct fsl_ep, ep);
789 - if (!_ep || (!ep->ep.desc && ep_index(ep) != 0))
790 + if (!_ep || !ep->ep.desc || (ep_index(ep) == 0))
791 return -ENODEV;
792
793 udc = (struct fsl_udc *)ep->udc;
794 @@ -1599,14 +1604,13 @@ static int process_ep_req(struct fsl_udc
795 struct fsl_req *curr_req)
796 {
797 struct ep_td_struct *curr_td;
798 - int td_complete, actual, remaining_length, j, tmp;
799 + int actual, remaining_length, j, tmp;
800 int status = 0;
801 int errors = 0;
802 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
803 int direction = pipe % 2;
804
805 curr_td = curr_req->head;
806 - td_complete = 0;
807 actual = curr_req->req.length;
808
809 for (j = 0; j < curr_req->dtd_count; j++) {
810 @@ -1651,11 +1655,9 @@ static int process_ep_req(struct fsl_udc
811 status = -EPROTO;
812 break;
813 } else {
814 - td_complete++;
815 break;
816 }
817 } else {
818 - td_complete++;
819 VDBG("dTD transmitted successful");
820 }
821
822 @@ -1698,7 +1700,7 @@ static void dtd_complete_irq(struct fsl_
823 curr_ep = get_ep_by_pipe(udc, i);
824
825 /* If the ep is configured */
826 - if (!curr_ep->ep.name) {
827 + if (strncmp(curr_ep->name, "ep", 2)) {
828 WARNING("Invalid EP?");
829 continue;
830 }
831 @@ -2420,10 +2422,12 @@ static int fsl_udc_probe(struct platform
832 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
833 #endif
834
835 +#ifdef CONFIG_ARCH_MXC
836 /* Initialize USB clocks */
837 ret = fsl_udc_clk_init(pdev);
838 if (ret < 0)
839 goto err_iounmap_noclk;
840 +#endif
841
842 /* Read Device Controller Capability Parameters register */
843 dccparams = fsl_readl(&dr_regs->dccparams);
844 @@ -2463,9 +2467,11 @@ static int fsl_udc_probe(struct platform
845 dr_controller_setup(udc_controller);
846 }
847
848 +#ifdef CONFIG_ARCH_MXC
849 ret = fsl_udc_clk_finalize(pdev);
850 if (ret)
851 goto err_free_irq;
852 +#endif
853
854 /* Setup gadget structure */
855 udc_controller->gadget.ops = &fsl_gadget_ops;
856 @@ -2478,6 +2484,7 @@ static int fsl_udc_probe(struct platform
857 /* Setup gadget.dev and register with kernel */
858 dev_set_name(&udc_controller->gadget.dev, "gadget");
859 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
860 + set_dma_ops(&udc_controller->gadget.dev, pdev->dev.archdata.dma_ops);
861
862 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
863 udc_controller->gadget.is_otg = 1;
864 @@ -2529,7 +2536,9 @@ err_free_irq:
865 err_iounmap:
866 if (pdata->exit)
867 pdata->exit(pdev);
868 +#ifdef CONFIG_ARCH_MXC
869 fsl_udc_clk_release();
870 +#endif
871 err_iounmap_noclk:
872 iounmap(dr_regs);
873 err_release_mem_region:
874 @@ -2557,8 +2566,9 @@ static int fsl_udc_remove(struct platfor
875 udc_controller->done = &done;
876 usb_del_gadget_udc(&udc_controller->gadget);
877
878 +#ifdef CONFIG_ARCH_MXC
879 fsl_udc_clk_release();
880 -
881 +#endif
882 /* DR has been stopped in usb_gadget_unregister_driver() */
883 remove_proc_file();
884
885 @@ -2570,7 +2580,7 @@ static int fsl_udc_remove(struct platfor
886 dma_pool_destroy(udc_controller->td_pool);
887 free_irq(udc_controller->irq, udc_controller);
888 iounmap(dr_regs);
889 - if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
890 + if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
891 release_mem_region(res->start, resource_size(res));
892
893 /* free udc --wait for the release() finished */
894 --- a/drivers/usb/gadget/udc/fsl_usb2_udc.h
895 +++ b/drivers/usb/gadget/udc/fsl_usb2_udc.h
896 @@ -20,6 +20,10 @@
897 #define USB_MAX_CTRL_PAYLOAD 64
898 #define USB_DR_SYS_OFFSET 0x400
899
900 +#ifdef CONFIG_SOC_LS1021A
901 +#undef CONFIG_ARCH_MXC
902 +#endif
903 +
904 /* USB DR device mode registers (Little Endian) */
905 struct usb_dr_device {
906 /* Capability register */
907 @@ -597,18 +601,6 @@ struct platform_device;
908 int fsl_udc_clk_init(struct platform_device *pdev);
909 int fsl_udc_clk_finalize(struct platform_device *pdev);
910 void fsl_udc_clk_release(void);
911 -#else
912 -static inline int fsl_udc_clk_init(struct platform_device *pdev)
913 -{
914 - return 0;
915 -}
916 -static inline int fsl_udc_clk_finalize(struct platform_device *pdev)
917 -{
918 - return 0;
919 -}
920 -static inline void fsl_udc_clk_release(void)
921 -{
922 -}
923 #endif
924
925 #endif
926 --- a/drivers/usb/host/Kconfig
927 +++ b/drivers/usb/host/Kconfig
928 @@ -164,8 +164,8 @@ config XPS_USB_HCD_XILINX
929 devices only.
930
931 config USB_EHCI_FSL
932 - tristate "Support for Freescale PPC on-chip EHCI USB controller"
933 - depends on FSL_SOC
934 + tristate "Support for Freescale QorIQ(ARM/PPC) on-chip EHCI USB controller"
935 + depends on USB_EHCI_HCD
936 select USB_EHCI_ROOT_HUB_TT
937 ---help---
938 Variation of ARC USB block used in some Freescale chips.
939 --- a/drivers/usb/host/ehci-fsl.c
940 +++ b/drivers/usb/host/ehci-fsl.c
941 @@ -36,15 +36,127 @@
942 #include <linux/platform_device.h>
943 #include <linux/fsl_devices.h>
944 #include <linux/of_platform.h>
945 +#include <linux/io.h>
946 +
947 +#ifdef CONFIG_PPC
948 +#include <asm/fsl_pm.h>
949 +#include <linux/suspend.h>
950 +#endif
951
952 #include "ehci.h"
953 #include "ehci-fsl.h"
954
955 +#define FSL_USB_PHY_ADDR 0xffe214000
956 +
957 +struct ccsr_usb_port_ctrl {
958 + u32 ctrl;
959 + u32 drvvbuscfg;
960 + u32 pwrfltcfg;
961 + u32 sts;
962 + u8 res_14[0xc];
963 + u32 bistcfg;
964 + u32 biststs;
965 + u32 abistcfg;
966 + u32 abiststs;
967 + u8 res_30[0x10];
968 + u32 xcvrprg;
969 + u32 anaprg;
970 + u32 anadrv;
971 + u32 anasts;
972 +};
973 +
974 +struct ccsr_usb_phy {
975 + u32 id;
976 + struct ccsr_usb_port_ctrl port1;
977 + u8 res_50[0xc];
978 + u32 tvr;
979 + u32 pllprg[4];
980 + u8 res_70[0x4];
981 + u32 anaccfg;
982 + u32 dbg;
983 + u8 res_7c[0x4];
984 + struct ccsr_usb_port_ctrl port2;
985 + u8 res_dc[0x334];
986 +};
987 +
988 #define DRIVER_DESC "Freescale EHCI Host controller driver"
989 #define DRV_NAME "ehci-fsl"
990
991 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
992
993 +struct ehci_fsl {
994 + struct ehci_hcd ehci;
995 +
996 +#ifdef CONFIG_PM
997 +struct ehci_regs saved_regs;
998 +struct ccsr_usb_phy saved_phy_regs;
999 +/* Saved USB PHY settings, need to restore after deep sleep. */
1000 +u32 usb_ctrl;
1001 +#endif
1002 + /*
1003 + * store current hcd state for otg;
1004 + * have_hcd is true when host drv al already part of otg framework,
1005 + * otherwise false;
1006 + * hcd_add is true when otg framework wants to add host
1007 + * drv as part of otg;flase when it wants to remove it
1008 + */
1009 +unsigned have_hcd:1;
1010 +unsigned hcd_add:1;
1011 +};
1012 +
1013 +static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
1014 +{
1015 +struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1016 +
1017 +return container_of(ehci, struct ehci_fsl, ehci);
1018 +}
1019 +
1020 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1021 +static void do_change_hcd(struct work_struct *work)
1022 +{
1023 +struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
1024 + change_hcd_work);
1025 +struct usb_hcd *hcd = ehci_to_hcd(ehci);
1026 +struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1027 +void __iomem *non_ehci = hcd->regs;
1028 +int retval;
1029 +
1030 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
1031 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
1032 + /* host, gadget and otg share same int line */
1033 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
1034 + if (retval == 0)
1035 + ehci_fsl->have_hcd = 1;
1036 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
1037 + usb_remove_hcd(hcd);
1038 + ehci_fsl->have_hcd = 0;
1039 + }
1040 +}
1041 +#endif
1042 +
1043 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1044 +static void do_change_hcd(struct work_struct *work)
1045 +{
1046 + struct ehci_hcd *ehci = container_of(work, struct ehci_hcd,
1047 + change_hcd_work);
1048 + struct usb_hcd *hcd = ehci_to_hcd(ehci);
1049 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1050 + void __iomem *non_ehci = hcd->regs;
1051 + int retval;
1052 +
1053 + if (ehci_fsl->hcd_add && !ehci_fsl->have_hcd) {
1054 + writel(USBMODE_CM_HOST, non_ehci + FSL_SOC_USB_USBMODE);
1055 + /* host, gadget and otg share same int line */
1056 + retval = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
1057 + if (retval == 0)
1058 + ehci_fsl->have_hcd = 1;
1059 + } else if (!ehci_fsl->hcd_add && ehci_fsl->have_hcd) {
1060 + usb_remove_hcd(hcd);
1061 + ehci_fsl->have_hcd = 0;
1062 + }
1063 +}
1064 +#endif
1065 +
1066 /* configure so an HC device and id are always provided */
1067 /* always called with process context; sleeping is OK */
1068
1069 @@ -131,6 +243,12 @@ static int fsl_ehci_drv_probe(struct pla
1070 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
1071 CONTROL_REGISTER_W1C_MASK, 0x4);
1072
1073 + /* Set USB_EN bit to select ULPI phy for USB controller version 2.5 */
1074 + if (pdata->controller_ver == FSL_USB_VER_2_5 &&
1075 + pdata->phy_mode == FSL_USB2_PHY_ULPI)
1076 + iowrite32be(USB_CTRL_USB_EN, hcd->regs + FSL_SOC_USB_CTRL);
1077 +
1078 +
1079 /*
1080 * Enable UTMI phy and program PTS field in UTMI mode before asserting
1081 * controller reset for USB Controller version 2.5
1082 @@ -143,16 +261,20 @@ static int fsl_ehci_drv_probe(struct pla
1083
1084 /* Don't need to set host mode here. It will be done by tdi_reset() */
1085
1086 - retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
1087 + retval = usb_add_hcd(hcd, irq, IRQF_SHARED | IRQF_NO_SUSPEND);
1088 if (retval != 0)
1089 goto err2;
1090 device_wakeup_enable(hcd->self.controller);
1091
1092 -#ifdef CONFIG_USB_OTG
1093 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1094 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
1095 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1096 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1097
1098 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
1099 +
1100 + INIT_WORK(&ehci->change_hcd_work, do_change_hcd);
1101 +
1102 dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, phy=0x%p\n",
1103 hcd, ehci, hcd->usb_phy);
1104
1105 @@ -168,6 +290,11 @@ static int fsl_ehci_drv_probe(struct pla
1106 retval = -ENODEV;
1107 goto err2;
1108 }
1109 +
1110 + ehci_fsl->have_hcd = 1;
1111 + } else {
1112 + dev_err(&pdev->dev, "wrong operating mode\n");
1113 + return -ENODEV;
1114 }
1115 #endif
1116 return retval;
1117 @@ -181,6 +308,17 @@ static int fsl_ehci_drv_probe(struct pla
1118 return retval;
1119 }
1120
1121 +static bool usb_phy_clk_valid(struct usb_hcd *hcd)
1122 +{
1123 + void __iomem *non_ehci = hcd->regs;
1124 + bool ret = true;
1125 +
1126 + if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) & PHY_CLK_VALID))
1127 + ret = false;
1128 +
1129 + return ret;
1130 +}
1131 +
1132 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
1133 enum fsl_usb2_phy_modes phy_mode,
1134 unsigned int port_offset)
1135 @@ -219,6 +357,21 @@ static int ehci_fsl_setup_phy(struct usb
1136 /* fall through */
1137 case FSL_USB2_PHY_UTMI:
1138 case FSL_USB2_PHY_UTMI_DUAL:
1139 + if (pdata->has_fsl_erratum_a006918) {
1140 + pr_warn("fsl-ehci: USB PHY clock invalid\n");
1141 + return -EINVAL;
1142 + }
1143 +
1144 + /* PHY_CLK_VALID bit is de-featured from all controller
1145 + * versions below 2.4 and is to be checked only for
1146 + * internal UTMI phy
1147 + */
1148 + if (pdata->controller_ver > FSL_USB_VER_2_4 &&
1149 + pdata->have_sysif_regs && !usb_phy_clk_valid(hcd)) {
1150 + pr_err("fsl-ehci: USB PHY clock invalid\n");
1151 + return -EINVAL;
1152 + }
1153 +
1154 if (pdata->have_sysif_regs && pdata->controller_ver) {
1155 /* controller version 1.6 or above */
1156 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
1157 @@ -286,20 +439,18 @@ static int ehci_fsl_usb_setup(struct ehc
1158 if (pdata->has_fsl_erratum_a005275 == 1)
1159 ehci->has_fsl_hs_errata = 1;
1160
1161 + if (pdata->has_fsl_erratum_a005697 == 1)
1162 + ehci->has_fsl_susp_errata = 1;
1163 +
1164 if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
1165 (pdata->operating_mode == FSL_USB2_DR_OTG))
1166 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
1167 return -EINVAL;
1168
1169 if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
1170 - unsigned int chip, rev, svr;
1171 -
1172 - svr = mfspr(SPRN_SVR);
1173 - chip = svr >> 16;
1174 - rev = (svr >> 4) & 0xf;
1175
1176 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
1177 - if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
1178 + if (pdata->has_fsl_erratum_14 == 1)
1179 ehci->has_fsl_port_bug = 1;
1180
1181 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
1182 @@ -379,16 +530,57 @@ static int ehci_fsl_setup(struct usb_hcd
1183 return retval;
1184 }
1185
1186 -struct ehci_fsl {
1187 - struct ehci_hcd ehci;
1188
1189 #ifdef CONFIG_PM
1190 - /* Saved USB PHY settings, need to restore after deep sleep. */
1191 - u32 usb_ctrl;
1192 -#endif
1193 -};
1194 +void __iomem *phy_reg;
1195
1196 -#ifdef CONFIG_PM
1197 +#ifdef CONFIG_PPC
1198 +/* save usb registers */
1199 +static int ehci_fsl_save_context(struct usb_hcd *hcd)
1200 +{
1201 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1202 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1203 + void __iomem *non_ehci = hcd->regs;
1204 + struct device *dev = hcd->self.controller;
1205 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1206 +
1207 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1208 + phy_reg = ioremap(FSL_USB_PHY_ADDR,
1209 + sizeof(struct ccsr_usb_phy));
1210 + _memcpy_fromio((void *)&ehci_fsl->saved_phy_regs, phy_reg,
1211 + sizeof(struct ccsr_usb_phy));
1212 + }
1213 +
1214 + _memcpy_fromio((void *)&ehci_fsl->saved_regs, ehci->regs,
1215 + sizeof(struct ehci_regs));
1216 + ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
1217 +
1218 + return 0;
1219 +}
1220 +
1221 +/*Restore usb registers */
1222 +static int ehci_fsl_restore_context(struct usb_hcd *hcd)
1223 +{
1224 + struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1225 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1226 + void __iomem *non_ehci = hcd->regs;
1227 + struct device *dev = hcd->self.controller;
1228 + struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
1229 +
1230 + if (pdata->phy_mode == FSL_USB2_PHY_UTMI_DUAL) {
1231 + if (phy_reg)
1232 + _memcpy_toio(phy_reg,
1233 + (void *)&ehci_fsl->saved_phy_regs,
1234 + sizeof(struct ccsr_usb_phy));
1235 + }
1236 +
1237 + _memcpy_toio(ehci->regs, (void *)&ehci_fsl->saved_regs,
1238 + sizeof(struct ehci_regs));
1239 + iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
1240 +
1241 + return 0;
1242 +}
1243 +#endif
1244
1245 #ifdef CONFIG_PPC_MPC512x
1246 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
1247 @@ -535,26 +727,45 @@ static inline int ehci_fsl_mpc512x_drv_r
1248 }
1249 #endif /* CONFIG_PPC_MPC512x */
1250
1251 -static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
1252 -{
1253 - struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1254 -
1255 - return container_of(ehci, struct ehci_fsl, ehci);
1256 -}
1257 -
1258 static int ehci_fsl_drv_suspend(struct device *dev)
1259 {
1260 struct usb_hcd *hcd = dev_get_drvdata(dev);
1261 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1262 void __iomem *non_ehci = hcd->regs;
1263 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1264 + struct usb_bus host = hcd->self;
1265 +#endif
1266 +
1267 +#ifdef CONFIG_PPC
1268 +suspend_state_t pm_state;
1269 +/* FIXME:Need to port fsl_pm.h before enable below code. */
1270 +/*pm_state = pm_suspend_state();*/
1271 +pm_state = PM_SUSPEND_MEM;
1272 +
1273 +if (pm_state == PM_SUSPEND_MEM)
1274 + ehci_fsl_save_context(hcd);
1275 +#endif
1276
1277 if (of_device_is_compatible(dev->parent->of_node,
1278 "fsl,mpc5121-usb2-dr")) {
1279 return ehci_fsl_mpc512x_drv_suspend(dev);
1280 }
1281
1282 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1283 + if (host.is_otg) {
1284 + struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1285 +
1286 + /* remove hcd */
1287 + ehci_fsl->hcd_add = 0;
1288 + schedule_work(&ehci->change_hcd_work);
1289 + host.is_otg = 0;
1290 + return 0;
1291 + }
1292 +#endif
1293 +
1294 ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
1295 device_may_wakeup(dev));
1296 +
1297 if (!fsl_deep_sleep())
1298 return 0;
1299
1300 @@ -568,12 +779,36 @@ static int ehci_fsl_drv_resume(struct de
1301 struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
1302 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
1303 void __iomem *non_ehci = hcd->regs;
1304 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1305 + struct usb_bus host = hcd->self;
1306 +#endif
1307 +
1308 +#ifdef CONFIG_PPC
1309 +suspend_state_t pm_state;
1310 +/* FIXME:Need to port fsl_pm.h before enable below code.*/
1311 +/* pm_state = pm_suspend_state(); */
1312 +pm_state = PM_SUSPEND_MEM;
1313 +
1314 +if (pm_state == PM_SUSPEND_MEM)
1315 + ehci_fsl_restore_context(hcd);
1316 +#endif
1317
1318 if (of_device_is_compatible(dev->parent->of_node,
1319 "fsl,mpc5121-usb2-dr")) {
1320 return ehci_fsl_mpc512x_drv_resume(dev);
1321 }
1322
1323 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1324 + if (host.is_otg) {
1325 + /* add hcd */
1326 + ehci_fsl->hcd_add = 1;
1327 + schedule_work(&ehci->change_hcd_work);
1328 + usb_hcd_resume_root_hub(hcd);
1329 + host.is_otg = 0;
1330 + return 0;
1331 + }
1332 +#endif
1333 +
1334 ehci_prepare_ports_for_controller_resume(ehci);
1335 if (!fsl_deep_sleep())
1336 return 0;
1337 --- a/drivers/usb/host/ehci-fsl.h
1338 +++ b/drivers/usb/host/ehci-fsl.h
1339 @@ -63,4 +63,7 @@
1340 #define UTMI_PHY_EN (1<<9)
1341 #define ULPI_PHY_CLK_SEL (1<<10)
1342 #define PHY_CLK_VALID (1<<17)
1343 +
1344 +/* Retry count for checking UTMI PHY CLK validity */
1345 +#define UTMI_PHY_CLK_VALID_CHK_RETRY 5
1346 #endif /* _EHCI_FSL_H */
1347 --- a/drivers/usb/host/ehci-hub.c
1348 +++ b/drivers/usb/host/ehci-hub.c
1349 @@ -278,6 +278,8 @@ static int ehci_bus_suspend (struct usb_
1350 else if ((t1 & PORT_PE) && !(t1 & PORT_SUSPEND)) {
1351 t2 |= PORT_SUSPEND;
1352 set_bit(port, &ehci->bus_suspended);
1353 + if (ehci_has_fsl_susp_errata(ehci))
1354 + usleep_range(10000, 20000);
1355 }
1356
1357 /* enable remote wakeup on all ports, if told to do so */
1358 @@ -305,6 +307,8 @@ static int ehci_bus_suspend (struct usb_
1359 USB_PORT_STAT_HIGH_SPEED)
1360 fs_idle_delay = true;
1361 ehci_writel(ehci, t2, reg);
1362 + if (ehci_has_fsl_susp_errata(ehci))
1363 + usleep_range(10000, 20000);
1364 changed = 1;
1365 }
1366 }
1367 --- a/drivers/usb/host/ehci.h
1368 +++ b/drivers/usb/host/ehci.h
1369 @@ -180,6 +180,9 @@ struct ehci_hcd { /* one per controlle
1370 unsigned periodic_count; /* periodic activity count */
1371 unsigned uframe_periodic_max; /* max periodic time per uframe */
1372
1373 +#if defined(CONFIG_FSL_USB2_OTG) || defined(CONFIG_FSL_USB2_OTG_MODULE)
1374 + struct work_struct change_hcd_work;
1375 +#endif
1376
1377 /* list of itds & sitds completed while now_frame was still active */
1378 struct list_head cached_itd_list;
1379 @@ -219,6 +222,7 @@ struct ehci_hcd { /* one per controlle
1380 unsigned no_selective_suspend:1;
1381 unsigned has_fsl_port_bug:1; /* FreeScale */
1382 unsigned has_fsl_hs_errata:1; /* Freescale HS quirk */
1383 + unsigned has_fsl_susp_errata:1; /*Freescale SUSP quirk*/
1384 unsigned big_endian_mmio:1;
1385 unsigned big_endian_desc:1;
1386 unsigned big_endian_capbase:1;
1387 @@ -704,10 +708,15 @@ ehci_port_speed(struct ehci_hcd *ehci, u
1388 #if defined(CONFIG_PPC_85xx)
1389 /* Some Freescale processors have an erratum (USB A-005275) in which
1390 * incoming packets get corrupted in HS mode
1391 + * Some Freescale processors have an erratum (USB A-005697) in which
1392 + * we need to wait for 10ms for bus to fo into suspend mode after
1393 + * setting SUSP bit
1394 */
1395 #define ehci_has_fsl_hs_errata(e) ((e)->has_fsl_hs_errata)
1396 +#define ehci_has_fsl_susp_errata(e) ((e)->has_fsl_susp_errata)
1397 #else
1398 #define ehci_has_fsl_hs_errata(e) (0)
1399 +#define ehci_has_fsl_susp_errata(e) (0)
1400 #endif
1401
1402 /*
1403 --- a/drivers/usb/host/fsl-mph-dr-of.c
1404 +++ b/drivers/usb/host/fsl-mph-dr-of.c
1405 @@ -98,8 +98,8 @@ static struct platform_device *fsl_usb2_
1406
1407 pdev->dev.coherent_dma_mask = ofdev->dev.coherent_dma_mask;
1408
1409 - if (!pdev->dev.dma_mask)
1410 - pdev->dev.dma_mask = &ofdev->dev.coherent_dma_mask;
1411 + if (!pdev->dev.dma_mask && ofdev->dev.of_node)
1412 + of_dma_configure(&pdev->dev, ofdev->dev.of_node);
1413 else
1414 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1415
1416 @@ -226,6 +226,18 @@ static int fsl_usb2_mph_dr_of_probe(stru
1417 of_property_read_bool(np, "fsl,usb-erratum-a007792");
1418 pdata->has_fsl_erratum_a005275 =
1419 of_property_read_bool(np, "fsl,usb-erratum-a005275");
1420 + pdata->has_fsl_erratum_a005697 =
1421 + of_property_read_bool(np, "fsl,usb_erratum-a005697");
1422 + if (of_get_property(np, "fsl,erratum_a006918", NULL))
1423 + pdata->has_fsl_erratum_a006918 = 1;
1424 + else
1425 + pdata->has_fsl_erratum_a006918 = 0;
1426 +
1427 + if (of_get_property(np, "fsl,usb_erratum_14", NULL))
1428 + pdata->has_fsl_erratum_14 = 1;
1429 + else
1430 + pdata->has_fsl_erratum_14 = 0;
1431 +
1432
1433 /*
1434 * Determine whether phy_clk_valid needs to be checked
1435 --- a/drivers/usb/host/xhci-hub.c
1436 +++ b/drivers/usb/host/xhci-hub.c
1437 @@ -562,12 +562,34 @@ void xhci_set_link_state(struct xhci_hcd
1438 int port_id, u32 link_state)
1439 {
1440 u32 temp;
1441 + u32 portpmsc_u2_backup = 0;
1442 +
1443 + /* Backup U2 timeout info before initiating U3 entry erratum A-010131 */
1444 + if (xhci->shared_hcd->speed >= HCD_USB3 &&
1445 + link_state == USB_SS_PORT_LS_U3 &&
1446 + (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
1447 + portpmsc_u2_backup = readl(port_array[port_id] + PORTPMSC);
1448 + portpmsc_u2_backup &= PORT_U2_TIMEOUT_MASK;
1449 + temp = readl(port_array[port_id] + PORTPMSC);
1450 + temp |= PORT_U2_TIMEOUT_MASK;
1451 + writel(temp, port_array[port_id] + PORTPMSC);
1452 + }
1453
1454 temp = readl(port_array[port_id]);
1455 temp = xhci_port_state_to_neutral(temp);
1456 temp &= ~PORT_PLS_MASK;
1457 temp |= PORT_LINK_STROBE | link_state;
1458 writel(temp, port_array[port_id]);
1459 +
1460 + /* Restore U2 timeout info after U3 entry complete */
1461 + if (xhci->shared_hcd->speed >= HCD_USB3 &&
1462 + link_state == USB_SS_PORT_LS_U3 &&
1463 + (xhci->quirks & XHCI_DIS_U1U2_WHEN_U3)) {
1464 + temp = readl(port_array[port_id] + PORTPMSC);
1465 + temp &= ~PORT_U2_TIMEOUT_MASK;
1466 + temp |= portpmsc_u2_backup;
1467 + writel(temp, port_array[port_id] + PORTPMSC);
1468 + }
1469 }
1470
1471 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
1472 --- a/drivers/usb/host/xhci-plat.c
1473 +++ b/drivers/usb/host/xhci-plat.c
1474 @@ -220,8 +220,22 @@ static int xhci_plat_probe(struct platfo
1475 goto disable_clk;
1476 }
1477
1478 - if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable"))
1479 + if (device_property_read_bool(&pdev->dev, "usb3-lpm-capable")) {
1480 xhci->quirks |= XHCI_LPM_SUPPORT;
1481 + if (device_property_read_bool(&pdev->dev,
1482 + "snps,dis-u1u2-when-u3-quirk"))
1483 + xhci->quirks |= XHCI_DIS_U1U2_WHEN_U3;
1484 + }
1485 +
1486 + if (device_property_read_bool(&pdev->dev, "quirk-reverse-in-out"))
1487 + xhci->quirks |= XHCI_REVERSE_IN_OUT;
1488 +
1489 + if (device_property_read_bool(&pdev->dev,
1490 + "quirk-stop-transfer-in-block"))
1491 + xhci->quirks |= XHCI_STOP_TRANSFER_IN_BLOCK;
1492 +
1493 + if (device_property_read_bool(&pdev->dev, "quirk-stop-ep-in-u1"))
1494 + xhci->quirks |= XHCI_STOP_EP_IN_U1;
1495
1496 if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
1497 xhci->quirks |= XHCI_BROKEN_PORT_PED;
1498 --- a/drivers/usb/host/xhci-ring.c
1499 +++ b/drivers/usb/host/xhci-ring.c
1500 @@ -1852,14 +1852,17 @@ static int finish_td(struct xhci_hcd *xh
1501 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1502 struct xhci_virt_ep *ep, int *status, bool skip)
1503 {
1504 + struct xhci_dequeue_state deq_state;
1505 struct xhci_virt_device *xdev;
1506 struct xhci_ring *ep_ring;
1507 + unsigned int stream_id;
1508 unsigned int slot_id;
1509 int ep_index;
1510 struct urb *urb = NULL;
1511 struct xhci_ep_ctx *ep_ctx;
1512 int ret = 0;
1513 struct urb_priv *urb_priv;
1514 + u32 remaining;
1515 u32 trb_comp_code;
1516
1517 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1518 @@ -1885,13 +1888,29 @@ static int finish_td(struct xhci_hcd *xh
1519 if (trb_comp_code == COMP_STALL ||
1520 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1521 trb_comp_code)) {
1522 - /* Issue a reset endpoint command to clear the host side
1523 - * halt, followed by a set dequeue command to move the
1524 - * dequeue pointer past the TD.
1525 - * The class driver clears the device side halt later.
1526 + /*
1527 + * A-007463: After transaction error, controller switches
1528 + * control transfer data stage from IN to OUT direction.
1529 */
1530 - xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1531 + remaining = EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
1532 + if (remaining && xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1533 + trb_comp_code) &&
1534 + (xhci->quirks & XHCI_REVERSE_IN_OUT)) {
1535 + memset(&deq_state, 0, sizeof(deq_state));
1536 + xhci_find_new_dequeue_state(xhci, slot_id,
1537 + ep_index, td->urb->stream_id, td, &deq_state);
1538 + xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
1539 + stream_id, &deq_state);
1540 + xhci_ring_cmd_db(xhci);
1541 + } else {
1542 + /* Issue a reset endpoint command to clear the host side
1543 + * halt, followed by a set dequeue command to move the
1544 + * dequeue pointer past the TD.
1545 + * The class driver clears the device side halt later.
1546 + */
1547 + xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1548 ep_ring->stream_id, td, event_trb);
1549 + }
1550 } else {
1551 /* Update ring dequeue pointer */
1552 while (ep_ring->dequeue != td->last_trb)
1553 --- a/drivers/usb/host/xhci.c
1554 +++ b/drivers/usb/host/xhci.c
1555 @@ -1609,14 +1609,38 @@ int xhci_urb_dequeue(struct usb_hcd *hcd
1556 ret = -ENOMEM;
1557 goto done;
1558 }
1559 - ep->ep_state |= EP_HALT_PENDING;
1560 - ep->stop_cmds_pending++;
1561 - ep->stop_cmd_timer.expires = jiffies +
1562 + /*
1563 + *A-009611: Issuing an End Transfer command on an IN endpoint.
1564 + *when a transfer is in progress on USB blocks the transmission
1565 + *Workaround: Software must wait for all existing TRBs to
1566 + *complete before issuing End transfer command.
1567 + */
1568 + if ((ep_ring->enqueue == ep_ring->dequeue &&
1569 + (xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) ||
1570 + !(xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) {
1571 + ep->ep_state |= EP_HALT_PENDING;
1572 + ep->stop_cmds_pending++;
1573 + ep->stop_cmd_timer.expires = jiffies +
1574 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1575 - add_timer(&ep->stop_cmd_timer);
1576 - xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1577 - ep_index, 0);
1578 - xhci_ring_cmd_db(xhci);
1579 + add_timer(&ep->stop_cmd_timer);
1580 + xhci_queue_stop_endpoint(xhci, command,
1581 + urb->dev->slot_id,
1582 + ep_index, 0);
1583 + xhci_ring_cmd_db(xhci);
1584 + }
1585 +
1586 + /*
1587 + *A-009668: Stop Endpoint Command does not complete.
1588 + *Workaround: Instead of issuing a Stop Endpoint Command,
1589 + *issue a Disable Slot Command with the corresponding slot ID.
1590 + *Alternately, you can issue an Address Device Command with
1591 + *BSR=1
1592 + */
1593 + if ((urb->dev->speed <= USB_SPEED_HIGH) &&
1594 + (xhci->quirks & XHCI_STOP_EP_IN_U1)) {
1595 + xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
1596 + urb->dev->slot_id);
1597 + }
1598 }
1599 done:
1600 spin_unlock_irqrestore(&xhci->lock, flags);
1601 --- a/drivers/usb/host/xhci.h
1602 +++ b/drivers/usb/host/xhci.h
1603 @@ -1625,7 +1625,7 @@ struct xhci_hcd {
1604 #define XHCI_STATE_REMOVING (1 << 2)
1605 /* Statistics */
1606 int error_bitmask;
1607 - unsigned int quirks;
1608 + u64 quirks;
1609 #define XHCI_LINK_TRB_QUIRK (1 << 0)
1610 #define XHCI_RESET_EP_QUIRK (1 << 1)
1611 #define XHCI_NEC_HOST (1 << 2)
1612 @@ -1661,6 +1661,10 @@ struct xhci_hcd {
1613 #define XHCI_SSIC_PORT_UNUSED (1 << 22)
1614 #define XHCI_NO_64BIT_SUPPORT (1 << 23)
1615 #define XHCI_MISSING_CAS (1 << 24)
1616 +#define XHCI_REVERSE_IN_OUT (1 << 29)
1617 +#define XHCI_STOP_TRANSFER_IN_BLOCK (1 << 30)
1618 +#define XHCI_STOP_EP_IN_U1 (1 << 31)
1619 +#define XHCI_DIS_U1U2_WHEN_U3 (1 << 32)
1620 /* For controller with a broken Port Disable implementation */
1621 #define XHCI_BROKEN_PORT_PED (1 << 25)
1622 #define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26)
1623 --- a/drivers/usb/phy/phy-fsl-usb.c
1624 +++ b/drivers/usb/phy/phy-fsl-usb.c
1625 @@ -1,5 +1,5 @@
1626 /*
1627 - * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
1628 + * Copyright 2007,2008 Freescale Semiconductor, Inc.
1629 *
1630 * Author: Li Yang <LeoLi@freescale.com>
1631 * Jerry Huang <Chang-Ming.Huang@freescale.com>
1632 @@ -463,6 +463,7 @@ void otg_reset_controller(void)
1633 int fsl_otg_start_host(struct otg_fsm *fsm, int on)
1634 {
1635 struct usb_otg *otg = fsm->otg;
1636 + struct usb_bus *host = otg->host;
1637 struct device *dev;
1638 struct fsl_otg *otg_dev =
1639 container_of(otg->usb_phy, struct fsl_otg, phy);
1640 @@ -486,6 +487,7 @@ int fsl_otg_start_host(struct otg_fsm *f
1641 otg_reset_controller();
1642 VDBG("host on......\n");
1643 if (dev->driver->pm && dev->driver->pm->resume) {
1644 + host->is_otg = 1;
1645 retval = dev->driver->pm->resume(dev);
1646 if (fsm->id) {
1647 /* default-b */
1648 @@ -510,8 +512,11 @@ int fsl_otg_start_host(struct otg_fsm *f
1649 else {
1650 VDBG("host off......\n");
1651 if (dev && dev->driver) {
1652 - if (dev->driver->pm && dev->driver->pm->suspend)
1653 + if (dev->driver->pm &&
1654 + dev->driver->pm->suspend) {
1655 + host->is_otg = 1;
1656 retval = dev->driver->pm->suspend(dev);
1657 + }
1658 if (fsm->id)
1659 /* default-b */
1660 fsl_otg_drv_vbus(fsm, 0);
1661 @@ -539,8 +544,17 @@ int fsl_otg_start_gadget(struct otg_fsm
1662 dev = otg->gadget->dev.parent;
1663
1664 if (on) {
1665 - if (dev->driver->resume)
1666 + /* Delay gadget resume to synchronize between host and gadget
1667 + * drivers. Upon role-reversal host drv is shutdown by kernel
1668 + * worker thread. By the time host drv shuts down, controller
1669 + * gets programmed for gadget role. Shutting host drv after
1670 + * this results in controller getting reset, and it stops
1671 + * responding to otg events
1672 + */
1673 + if (dev->driver->resume) {
1674 + msleep(1000);
1675 dev->driver->resume(dev);
1676 + }
1677 } else {
1678 if (dev->driver->suspend)
1679 dev->driver->suspend(dev, otg_suspend_state);
1680 @@ -672,6 +686,10 @@ static void fsl_otg_event(struct work_st
1681 fsl_otg_start_host(fsm, 0);
1682 otg_drv_vbus(fsm, 0);
1683 fsl_otg_start_gadget(fsm, 1);
1684 + } else {
1685 + fsl_otg_start_gadget(fsm, 0);
1686 + otg_drv_vbus(fsm, 1);
1687 + fsl_otg_start_host(fsm, 1);
1688 }
1689 }
1690
1691 @@ -724,6 +742,7 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1692 {
1693 struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
1694 struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
1695 + struct fsl_otg *otg_dev = dev_id;
1696 u32 otg_int_src, otg_sc;
1697
1698 otg_sc = fsl_readl(&usb_dr_regs->otgsc);
1699 @@ -753,18 +772,8 @@ irqreturn_t fsl_otg_isr(int irq, void *d
1700 otg->gadget->is_a_peripheral = !fsm->id;
1701 VDBG("ID int (ID is %d)\n", fsm->id);
1702
1703 - if (fsm->id) { /* switch to gadget */
1704 - schedule_delayed_work(
1705 - &((struct fsl_otg *)dev_id)->otg_event,
1706 - 100);
1707 - } else { /* switch to host */
1708 - cancel_delayed_work(&
1709 - ((struct fsl_otg *)dev_id)->
1710 - otg_event);
1711 - fsl_otg_start_gadget(fsm, 0);
1712 - otg_drv_vbus(fsm, 1);
1713 - fsl_otg_start_host(fsm, 1);
1714 - }
1715 + schedule_delayed_work(&otg_dev->otg_event, 100);
1716 +
1717 return IRQ_HANDLED;
1718 }
1719 }
1720 @@ -925,12 +934,32 @@ int usb_otg_start(struct platform_device
1721 temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
1722 switch (pdata->phy_mode) {
1723 case FSL_USB2_PHY_ULPI:
1724 + if (pdata->controller_ver) {
1725 + /* controller version 1.6 or above */
1726 + setbits32(&p_otg->dr_mem_map->control,
1727 + USB_CTRL_ULPI_PHY_CLK_SEL);
1728 + /*
1729 + * Due to controller issue of PHY_CLK_VALID in ULPI
1730 + * mode, we set USB_CTRL_USB_EN before checking
1731 + * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
1732 + */
1733 + clrsetbits_be32(&p_otg->dr_mem_map->control,
1734 + USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
1735 + }
1736 temp |= PORTSC_PTS_ULPI;
1737 break;
1738 case FSL_USB2_PHY_UTMI_WIDE:
1739 temp |= PORTSC_PTW_16BIT;
1740 /* fall through */
1741 case FSL_USB2_PHY_UTMI:
1742 + if (pdata->controller_ver) {
1743 + /* controller version 1.6 or above */
1744 + setbits32(&p_otg->dr_mem_map->control,
1745 + USB_CTRL_UTMI_PHY_EN);
1746 + /* Delay for UTMI PHY CLK to become stable - 10ms */
1747 + mdelay(FSL_UTMI_PHY_DLY);
1748 + }
1749 + setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
1750 temp |= PORTSC_PTS_UTMI;
1751 /* fall through */
1752 default:
1753 --- a/drivers/usb/phy/phy-fsl-usb.h
1754 +++ b/drivers/usb/phy/phy-fsl-usb.h
1755 @@ -199,6 +199,14 @@
1756 /* control Register Bit Masks */
1757 #define USB_CTRL_IOENB (0x1<<2)
1758 #define USB_CTRL_ULPI_INT0EN (0x1<<0)
1759 +#define USB_CTRL_WU_INT_EN (0x1<<1)
1760 +#define USB_CTRL_LINE_STATE_FILTER__EN (0x1<<3)
1761 +#define USB_CTRL_KEEP_OTG_ON (0x1<<4)
1762 +#define USB_CTRL_OTG_PORT (0x1<<5)
1763 +#define USB_CTRL_PLL_RESET (0x1<<8)
1764 +#define USB_CTRL_UTMI_PHY_EN (0x1<<9)
1765 +#define USB_CTRL_ULPI_PHY_CLK_SEL (0x1<<10)
1766 +#define USB_CTRL_PHY_CLK_VALID (0x1<<17)
1767
1768 /* BCSR5 */
1769 #define BCSR5_INT_USB (0x02)
1770 --- a/include/linux/usb.h
1771 +++ b/include/linux/usb.h
1772 @@ -362,6 +362,7 @@ struct usb_bus {
1773 * for control transfers?
1774 */
1775 u8 otg_port; /* 0, or number of OTG/HNP port */
1776 + unsigned is_otg:1; /* true when host is also otg */
1777 unsigned is_b_host:1; /* true during some HNP roleswitches */
1778 unsigned b_hnp_enable:1; /* OTG: did A-Host enable HNP? */
1779 unsigned no_stop_on_short:1; /*
1780 --- a/include/linux/usb/of.h
1781 +++ b/include/linux/usb/of.h
1782 @@ -11,6 +11,8 @@
1783 #include <linux/usb/otg.h>
1784 #include <linux/usb/phy.h>
1785
1786 +enum usb_dr_mode of_usb_get_dr_mode(struct device_node *np);
1787 +
1788 #if IS_ENABLED(CONFIG_OF)
1789 enum usb_dr_mode of_usb_get_dr_mode_by_phy(struct device_node *np, int arg0);
1790 bool of_usb_host_tpl_support(struct device_node *np);