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[openwrt/openwrt.git] / target / linux / layerscape / patches-5.4 / 701-net-0260-net-mscc-ocelot-publish-structure-definitions-to-inc.patch
1 From 417b5a156ca8ab4c986c9deacf58309ce4e09410 Mon Sep 17 00:00:00 2001
2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
3 Date: Thu, 14 Nov 2019 17:03:27 +0200
4 Subject: [PATCH] net: mscc: ocelot: publish structure definitions to
5 include/soc/mscc/ocelot.h
6
7 We will be registering another switch driver based on ocelot, which
8 lives under drivers/net/dsa.
9
10 Make sure the Felix DSA front-end has the necessary abstractions to
11 implement a new Ocelot driver instantiation. This includes the function
12 prototypes for implementing DSA callbacks.
13
14 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
15 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
16 Signed-off-by: David S. Miller <davem@davemloft.net>
17 ---
18 drivers/net/ethernet/mscc/ocelot.c | 78 +++---
19 drivers/net/ethernet/mscc/ocelot.h | 482 +--------------------------------
20 include/soc/mscc/ocelot.h | 539 +++++++++++++++++++++++++++++++++++++
21 3 files changed, 588 insertions(+), 511 deletions(-)
22 create mode 100644 include/soc/mscc/ocelot.h
23
24 --- a/drivers/net/ethernet/mscc/ocelot.c
25 +++ b/drivers/net/ethernet/mscc/ocelot.c
26 @@ -21,7 +21,6 @@
27 #include <net/netevent.h>
28 #include <net/rtnetlink.h>
29 #include <net/switchdev.h>
30 -#include <net/dsa.h>
31
32 #include "ocelot.h"
33 #include "ocelot_ace.h"
34 @@ -184,8 +183,8 @@ static void ocelot_vlan_mode(struct ocel
35 ocelot_write(ocelot, val, ANA_VLANMASK);
36 }
37
38 -static void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
39 - bool vlan_aware)
40 +void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
41 + bool vlan_aware)
42 {
43 struct ocelot_port *ocelot_port = ocelot->ports[port];
44 u32 val;
45 @@ -230,6 +229,7 @@ static void ocelot_port_vlan_filtering(s
46 REW_TAG_CFG_TAG_CFG_M,
47 REW_TAG_CFG, port);
48 }
49 +EXPORT_SYMBOL(ocelot_port_vlan_filtering);
50
51 static int ocelot_port_set_native_vlan(struct ocelot *ocelot, int port,
52 u16 vid)
53 @@ -267,8 +267,8 @@ static void ocelot_port_set_pvid(struct
54 ocelot_port->pvid = pvid;
55 }
56
57 -static int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
58 - bool untagged)
59 +int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
60 + bool untagged)
61 {
62 int ret;
63
64 @@ -291,6 +291,7 @@ static int ocelot_vlan_add(struct ocelot
65
66 return 0;
67 }
68 +EXPORT_SYMBOL(ocelot_vlan_add);
69
70 static int ocelot_vlan_vid_add(struct net_device *dev, u16 vid, bool pvid,
71 bool untagged)
72 @@ -312,7 +313,7 @@ static int ocelot_vlan_vid_add(struct ne
73 return 0;
74 }
75
76 -static int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
77 +int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid)
78 {
79 struct ocelot_port *ocelot_port = ocelot->ports[port];
80 int ret;
81 @@ -333,6 +334,7 @@ static int ocelot_vlan_del(struct ocelot
82
83 return 0;
84 }
85 +EXPORT_SYMBOL(ocelot_vlan_del);
86
87 static int ocelot_vlan_vid_del(struct net_device *dev, u16 vid)
88 {
89 @@ -404,8 +406,8 @@ static u16 ocelot_wm_enc(u16 value)
90 return value;
91 }
92
93 -static void ocelot_adjust_link(struct ocelot *ocelot, int port,
94 - struct phy_device *phydev)
95 +void ocelot_adjust_link(struct ocelot *ocelot, int port,
96 + struct phy_device *phydev)
97 {
98 struct ocelot_port *ocelot_port = ocelot->ports[port];
99 int speed, mode = 0;
100 @@ -471,6 +473,7 @@ static void ocelot_adjust_link(struct oc
101 SYS_MAC_FC_CFG, port);
102 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
103 }
104 +EXPORT_SYMBOL(ocelot_adjust_link);
105
106 static void ocelot_port_adjust_link(struct net_device *dev)
107 {
108 @@ -481,8 +484,8 @@ static void ocelot_port_adjust_link(stru
109 ocelot_adjust_link(ocelot, port, dev->phydev);
110 }
111
112 -static void ocelot_port_enable(struct ocelot *ocelot, int port,
113 - struct phy_device *phy)
114 +void ocelot_port_enable(struct ocelot *ocelot, int port,
115 + struct phy_device *phy)
116 {
117 /* Enable receiving frames on the port, and activate auto-learning of
118 * MAC addresses.
119 @@ -492,6 +495,7 @@ static void ocelot_port_enable(struct oc
120 ANA_PORT_PORT_CFG_PORTID_VAL(port),
121 ANA_PORT_PORT_CFG, port);
122 }
123 +EXPORT_SYMBOL(ocelot_port_enable);
124
125 static int ocelot_port_open(struct net_device *dev)
126 {
127 @@ -526,7 +530,7 @@ static int ocelot_port_open(struct net_d
128 return 0;
129 }
130
131 -static void ocelot_port_disable(struct ocelot *ocelot, int port)
132 +void ocelot_port_disable(struct ocelot *ocelot, int port)
133 {
134 struct ocelot_port *ocelot_port = ocelot->ports[port];
135
136 @@ -534,6 +538,7 @@ static void ocelot_port_disable(struct o
137 ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,
138 QSYS_SWITCH_PORT_MODE, port);
139 }
140 +EXPORT_SYMBOL(ocelot_port_disable);
141
142 static int ocelot_port_stop(struct net_device *dev)
143 {
144 @@ -790,9 +795,8 @@ static void ocelot_get_stats64(struct ne
145 stats->collisions = ocelot_read(ocelot, SYS_COUNT_TX_COLLISION);
146 }
147
148 -static int ocelot_fdb_add(struct ocelot *ocelot, int port,
149 - const unsigned char *addr, u16 vid,
150 - bool vlan_aware)
151 +int ocelot_fdb_add(struct ocelot *ocelot, int port,
152 + const unsigned char *addr, u16 vid, bool vlan_aware)
153 {
154 struct ocelot_port *ocelot_port = ocelot->ports[port];
155
156 @@ -812,6 +816,7 @@ static int ocelot_fdb_add(struct ocelot
157
158 return ocelot_mact_learn(ocelot, port, addr, vid, ENTRYTYPE_LOCKED);
159 }
160 +EXPORT_SYMBOL(ocelot_fdb_add);
161
162 static int ocelot_port_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
163 struct net_device *dev,
164 @@ -826,11 +831,12 @@ static int ocelot_port_fdb_add(struct nd
165 return ocelot_fdb_add(ocelot, port, addr, vid, priv->vlan_aware);
166 }
167
168 -static int ocelot_fdb_del(struct ocelot *ocelot, int port,
169 - const unsigned char *addr, u16 vid)
170 +int ocelot_fdb_del(struct ocelot *ocelot, int port,
171 + const unsigned char *addr, u16 vid)
172 {
173 return ocelot_mact_forget(ocelot, addr, vid);
174 }
175 +EXPORT_SYMBOL(ocelot_fdb_del);
176
177 static int ocelot_port_fdb_del(struct ndmsg *ndm, struct nlattr *tb[],
178 struct net_device *dev,
179 @@ -940,8 +946,8 @@ static int ocelot_mact_read(struct ocelo
180 return 0;
181 }
182
183 -static int ocelot_fdb_dump(struct ocelot *ocelot, int port,
184 - dsa_fdb_dump_cb_t *cb, void *data)
185 +int ocelot_fdb_dump(struct ocelot *ocelot, int port,
186 + dsa_fdb_dump_cb_t *cb, void *data)
187 {
188 int i, j;
189
190 @@ -973,6 +979,7 @@ static int ocelot_fdb_dump(struct ocelot
191
192 return 0;
193 }
194 +EXPORT_SYMBOL(ocelot_fdb_dump);
195
196 static int ocelot_port_fdb_dump(struct sk_buff *skb,
197 struct netlink_callback *cb,
198 @@ -1153,8 +1160,7 @@ static const struct net_device_ops ocelo
199 .ndo_do_ioctl = ocelot_ioctl,
200 };
201
202 -static void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset,
203 - u8 *data)
204 +void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data)
205 {
206 int i;
207
208 @@ -1165,6 +1171,7 @@ static void ocelot_get_strings(struct oc
209 memcpy(data + i * ETH_GSTRING_LEN, ocelot->stats_layout[i].name,
210 ETH_GSTRING_LEN);
211 }
212 +EXPORT_SYMBOL(ocelot_get_strings);
213
214 static void ocelot_port_get_strings(struct net_device *netdev, u32 sset,
215 u8 *data)
216 @@ -1216,7 +1223,7 @@ static void ocelot_check_stats_work(stru
217 OCELOT_STATS_CHECK_DELAY);
218 }
219
220 -static void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
221 +void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data)
222 {
223 int i;
224
225 @@ -1227,6 +1234,7 @@ static void ocelot_get_ethtool_stats(str
226 for (i = 0; i < ocelot->num_stats; i++)
227 *data++ = ocelot->stats[port * ocelot->num_stats + i];
228 }
229 +EXPORT_SYMBOL(ocelot_get_ethtool_stats);
230
231 static void ocelot_port_get_ethtool_stats(struct net_device *dev,
232 struct ethtool_stats *stats,
233 @@ -1239,13 +1247,14 @@ static void ocelot_port_get_ethtool_stat
234 ocelot_get_ethtool_stats(ocelot, port, data);
235 }
236
237 -static int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
238 +int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset)
239 {
240 if (sset != ETH_SS_STATS)
241 return -EOPNOTSUPP;
242
243 return ocelot->num_stats;
244 }
245 +EXPORT_SYMBOL(ocelot_get_sset_count);
246
247 static int ocelot_port_get_sset_count(struct net_device *dev, int sset)
248 {
249 @@ -1256,8 +1265,8 @@ static int ocelot_port_get_sset_count(st
250 return ocelot_get_sset_count(ocelot, port, sset);
251 }
252
253 -static int ocelot_get_ts_info(struct ocelot *ocelot, int port,
254 - struct ethtool_ts_info *info)
255 +int ocelot_get_ts_info(struct ocelot *ocelot, int port,
256 + struct ethtool_ts_info *info)
257 {
258 info->phc_index = ocelot->ptp_clock ?
259 ptp_clock_index(ocelot->ptp_clock) : -1;
260 @@ -1273,6 +1282,7 @@ static int ocelot_get_ts_info(struct oce
261
262 return 0;
263 }
264 +EXPORT_SYMBOL(ocelot_get_ts_info);
265
266 static int ocelot_port_get_ts_info(struct net_device *dev,
267 struct ethtool_ts_info *info)
268 @@ -1296,8 +1306,7 @@ static const struct ethtool_ops ocelot_e
269 .get_ts_info = ocelot_port_get_ts_info,
270 };
271
272 -static void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port,
273 - u8 state)
274 +void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state)
275 {
276 u32 port_cfg;
277 int p, i;
278 @@ -1358,6 +1367,7 @@ static void ocelot_bridge_stp_state_set(
279 }
280 }
281 }
282 +EXPORT_SYMBOL(ocelot_bridge_stp_state_set);
283
284 static void ocelot_port_attr_stp_state_set(struct ocelot *ocelot, int port,
285 struct switchdev_trans *trans,
286 @@ -1369,11 +1379,12 @@ static void ocelot_port_attr_stp_state_s
287 ocelot_bridge_stp_state_set(ocelot, port, state);
288 }
289
290 -static void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
291 +void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs)
292 {
293 ocelot_write(ocelot, ANA_AUTOAGE_AGE_PERIOD(msecs / 2),
294 ANA_AUTOAGE);
295 }
296 +EXPORT_SYMBOL(ocelot_set_ageing_time);
297
298 static void ocelot_port_attr_ageing_set(struct ocelot *ocelot, int port,
299 unsigned long ageing_clock_t)
300 @@ -1604,8 +1615,8 @@ static int ocelot_port_obj_del(struct ne
301 return ret;
302 }
303
304 -static int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
305 - struct net_device *bridge)
306 +int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
307 + struct net_device *bridge)
308 {
309 if (!ocelot->bridge_mask) {
310 ocelot->hw_bridge_dev = bridge;
311 @@ -1620,9 +1631,10 @@ static int ocelot_port_bridge_join(struc
312
313 return 0;
314 }
315 +EXPORT_SYMBOL(ocelot_port_bridge_join);
316
317 -static int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
318 - struct net_device *bridge)
319 +int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
320 + struct net_device *bridge)
321 {
322 ocelot->bridge_mask &= ~BIT(port);
323
324 @@ -1633,6 +1645,7 @@ static int ocelot_port_bridge_leave(stru
325 ocelot_port_set_pvid(ocelot, port, 0);
326 return ocelot_port_set_native_vlan(ocelot, port, 0);
327 }
328 +EXPORT_SYMBOL(ocelot_port_bridge_leave);
329
330 static void ocelot_set_aggr_pgids(struct ocelot *ocelot)
331 {
332 @@ -2123,7 +2136,7 @@ static void ocelot_port_set_mtu(struct o
333 ocelot_write(ocelot, ocelot_wm_enc(atop_wm), SYS_ATOP_TOT_CFG);
334 }
335
336 -static void ocelot_init_port(struct ocelot *ocelot, int port)
337 +void ocelot_init_port(struct ocelot *ocelot, int port)
338 {
339 struct ocelot_port *ocelot_port = ocelot->ports[port];
340
341 @@ -2170,6 +2183,7 @@ static void ocelot_init_port(struct ocel
342 /* Enable vcap lookups */
343 ocelot_vcap_enable(ocelot, port);
344 }
345 +EXPORT_SYMBOL(ocelot_init_port);
346
347 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
348 void __iomem *regs,
349 --- a/drivers/net/ethernet/mscc/ocelot.h
350 +++ b/drivers/net/ethernet/mscc/ocelot.h
351 @@ -18,6 +18,7 @@
352 #include <linux/ptp_clock_kernel.h>
353 #include <linux/regmap.h>
354
355 +#include <soc/mscc/ocelot.h>
356 #include "ocelot_ana.h"
357 #include "ocelot_dev.h"
358 #include "ocelot_qsys.h"
359 @@ -52,376 +53,6 @@ struct frame_info {
360 u32 timestamp; /* rew_val */
361 };
362
363 -#define IFH_INJ_BYPASS BIT(31)
364 -#define IFH_INJ_POP_CNT_DISABLE (3 << 28)
365 -
366 -#define IFH_TAG_TYPE_C 0
367 -#define IFH_TAG_TYPE_S 1
368 -
369 -#define IFH_REW_OP_NOOP 0x0
370 -#define IFH_REW_OP_DSCP 0x1
371 -#define IFH_REW_OP_ONE_STEP_PTP 0x2
372 -#define IFH_REW_OP_TWO_STEP_PTP 0x3
373 -#define IFH_REW_OP_ORIGIN_PTP 0x5
374 -
375 -#define OCELOT_TAG_LEN 16
376 -#define OCELOT_SHORT_PREFIX_LEN 4
377 -#define OCELOT_LONG_PREFIX_LEN 16
378 -
379 -#define OCELOT_SPEED_2500 0
380 -#define OCELOT_SPEED_1000 1
381 -#define OCELOT_SPEED_100 2
382 -#define OCELOT_SPEED_10 3
383 -
384 -#define TARGET_OFFSET 24
385 -#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
386 -#define REG(reg, offset) [reg & REG_MASK] = offset
387 -
388 -enum ocelot_target {
389 - ANA = 1,
390 - QS,
391 - QSYS,
392 - REW,
393 - SYS,
394 - S2,
395 - HSIO,
396 - PTP,
397 - TARGET_MAX,
398 -};
399 -
400 -enum ocelot_reg {
401 - ANA_ADVLEARN = ANA << TARGET_OFFSET,
402 - ANA_VLANMASK,
403 - ANA_PORT_B_DOMAIN,
404 - ANA_ANAGEFIL,
405 - ANA_ANEVENTS,
406 - ANA_STORMLIMIT_BURST,
407 - ANA_STORMLIMIT_CFG,
408 - ANA_ISOLATED_PORTS,
409 - ANA_COMMUNITY_PORTS,
410 - ANA_AUTOAGE,
411 - ANA_MACTOPTIONS,
412 - ANA_LEARNDISC,
413 - ANA_AGENCTRL,
414 - ANA_MIRRORPORTS,
415 - ANA_EMIRRORPORTS,
416 - ANA_FLOODING,
417 - ANA_FLOODING_IPMC,
418 - ANA_SFLOW_CFG,
419 - ANA_PORT_MODE,
420 - ANA_CUT_THRU_CFG,
421 - ANA_PGID_PGID,
422 - ANA_TABLES_ANMOVED,
423 - ANA_TABLES_MACHDATA,
424 - ANA_TABLES_MACLDATA,
425 - ANA_TABLES_STREAMDATA,
426 - ANA_TABLES_MACACCESS,
427 - ANA_TABLES_MACTINDX,
428 - ANA_TABLES_VLANACCESS,
429 - ANA_TABLES_VLANTIDX,
430 - ANA_TABLES_ISDXACCESS,
431 - ANA_TABLES_ISDXTIDX,
432 - ANA_TABLES_ENTRYLIM,
433 - ANA_TABLES_PTP_ID_HIGH,
434 - ANA_TABLES_PTP_ID_LOW,
435 - ANA_TABLES_STREAMACCESS,
436 - ANA_TABLES_STREAMTIDX,
437 - ANA_TABLES_SEQ_HISTORY,
438 - ANA_TABLES_SEQ_MASK,
439 - ANA_TABLES_SFID_MASK,
440 - ANA_TABLES_SFIDACCESS,
441 - ANA_TABLES_SFIDTIDX,
442 - ANA_MSTI_STATE,
443 - ANA_OAM_UPM_LM_CNT,
444 - ANA_SG_ACCESS_CTRL,
445 - ANA_SG_CONFIG_REG_1,
446 - ANA_SG_CONFIG_REG_2,
447 - ANA_SG_CONFIG_REG_3,
448 - ANA_SG_CONFIG_REG_4,
449 - ANA_SG_CONFIG_REG_5,
450 - ANA_SG_GCL_GS_CONFIG,
451 - ANA_SG_GCL_TI_CONFIG,
452 - ANA_SG_STATUS_REG_1,
453 - ANA_SG_STATUS_REG_2,
454 - ANA_SG_STATUS_REG_3,
455 - ANA_PORT_VLAN_CFG,
456 - ANA_PORT_DROP_CFG,
457 - ANA_PORT_QOS_CFG,
458 - ANA_PORT_VCAP_CFG,
459 - ANA_PORT_VCAP_S1_KEY_CFG,
460 - ANA_PORT_VCAP_S2_CFG,
461 - ANA_PORT_PCP_DEI_MAP,
462 - ANA_PORT_CPU_FWD_CFG,
463 - ANA_PORT_CPU_FWD_BPDU_CFG,
464 - ANA_PORT_CPU_FWD_GARP_CFG,
465 - ANA_PORT_CPU_FWD_CCM_CFG,
466 - ANA_PORT_PORT_CFG,
467 - ANA_PORT_POL_CFG,
468 - ANA_PORT_PTP_CFG,
469 - ANA_PORT_PTP_DLY1_CFG,
470 - ANA_PORT_PTP_DLY2_CFG,
471 - ANA_PORT_SFID_CFG,
472 - ANA_PFC_PFC_CFG,
473 - ANA_PFC_PFC_TIMER,
474 - ANA_IPT_OAM_MEP_CFG,
475 - ANA_IPT_IPT,
476 - ANA_PPT_PPT,
477 - ANA_FID_MAP_FID_MAP,
478 - ANA_AGGR_CFG,
479 - ANA_CPUQ_CFG,
480 - ANA_CPUQ_CFG2,
481 - ANA_CPUQ_8021_CFG,
482 - ANA_DSCP_CFG,
483 - ANA_DSCP_REWR_CFG,
484 - ANA_VCAP_RNG_TYPE_CFG,
485 - ANA_VCAP_RNG_VAL_CFG,
486 - ANA_VRAP_CFG,
487 - ANA_VRAP_HDR_DATA,
488 - ANA_VRAP_HDR_MASK,
489 - ANA_DISCARD_CFG,
490 - ANA_FID_CFG,
491 - ANA_POL_PIR_CFG,
492 - ANA_POL_CIR_CFG,
493 - ANA_POL_MODE_CFG,
494 - ANA_POL_PIR_STATE,
495 - ANA_POL_CIR_STATE,
496 - ANA_POL_STATE,
497 - ANA_POL_FLOWC,
498 - ANA_POL_HYST,
499 - ANA_POL_MISC_CFG,
500 - QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
501 - QS_XTR_RD,
502 - QS_XTR_FRM_PRUNING,
503 - QS_XTR_FLUSH,
504 - QS_XTR_DATA_PRESENT,
505 - QS_XTR_CFG,
506 - QS_INJ_GRP_CFG,
507 - QS_INJ_WR,
508 - QS_INJ_CTRL,
509 - QS_INJ_STATUS,
510 - QS_INJ_ERR,
511 - QS_INH_DBG,
512 - QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
513 - QSYS_SWITCH_PORT_MODE,
514 - QSYS_STAT_CNT_CFG,
515 - QSYS_EEE_CFG,
516 - QSYS_EEE_THRES,
517 - QSYS_IGR_NO_SHARING,
518 - QSYS_EGR_NO_SHARING,
519 - QSYS_SW_STATUS,
520 - QSYS_EXT_CPU_CFG,
521 - QSYS_PAD_CFG,
522 - QSYS_CPU_GROUP_MAP,
523 - QSYS_QMAP,
524 - QSYS_ISDX_SGRP,
525 - QSYS_TIMED_FRAME_ENTRY,
526 - QSYS_TFRM_MISC,
527 - QSYS_TFRM_PORT_DLY,
528 - QSYS_TFRM_TIMER_CFG_1,
529 - QSYS_TFRM_TIMER_CFG_2,
530 - QSYS_TFRM_TIMER_CFG_3,
531 - QSYS_TFRM_TIMER_CFG_4,
532 - QSYS_TFRM_TIMER_CFG_5,
533 - QSYS_TFRM_TIMER_CFG_6,
534 - QSYS_TFRM_TIMER_CFG_7,
535 - QSYS_TFRM_TIMER_CFG_8,
536 - QSYS_RED_PROFILE,
537 - QSYS_RES_QOS_MODE,
538 - QSYS_RES_CFG,
539 - QSYS_RES_STAT,
540 - QSYS_EGR_DROP_MODE,
541 - QSYS_EQ_CTRL,
542 - QSYS_EVENTS_CORE,
543 - QSYS_QMAXSDU_CFG_0,
544 - QSYS_QMAXSDU_CFG_1,
545 - QSYS_QMAXSDU_CFG_2,
546 - QSYS_QMAXSDU_CFG_3,
547 - QSYS_QMAXSDU_CFG_4,
548 - QSYS_QMAXSDU_CFG_5,
549 - QSYS_QMAXSDU_CFG_6,
550 - QSYS_QMAXSDU_CFG_7,
551 - QSYS_PREEMPTION_CFG,
552 - QSYS_CIR_CFG,
553 - QSYS_EIR_CFG,
554 - QSYS_SE_CFG,
555 - QSYS_SE_DWRR_CFG,
556 - QSYS_SE_CONNECT,
557 - QSYS_SE_DLB_SENSE,
558 - QSYS_CIR_STATE,
559 - QSYS_EIR_STATE,
560 - QSYS_SE_STATE,
561 - QSYS_HSCH_MISC_CFG,
562 - QSYS_TAG_CONFIG,
563 - QSYS_TAS_PARAM_CFG_CTRL,
564 - QSYS_PORT_MAX_SDU,
565 - QSYS_PARAM_CFG_REG_1,
566 - QSYS_PARAM_CFG_REG_2,
567 - QSYS_PARAM_CFG_REG_3,
568 - QSYS_PARAM_CFG_REG_4,
569 - QSYS_PARAM_CFG_REG_5,
570 - QSYS_GCL_CFG_REG_1,
571 - QSYS_GCL_CFG_REG_2,
572 - QSYS_PARAM_STATUS_REG_1,
573 - QSYS_PARAM_STATUS_REG_2,
574 - QSYS_PARAM_STATUS_REG_3,
575 - QSYS_PARAM_STATUS_REG_4,
576 - QSYS_PARAM_STATUS_REG_5,
577 - QSYS_PARAM_STATUS_REG_6,
578 - QSYS_PARAM_STATUS_REG_7,
579 - QSYS_PARAM_STATUS_REG_8,
580 - QSYS_PARAM_STATUS_REG_9,
581 - QSYS_GCL_STATUS_REG_1,
582 - QSYS_GCL_STATUS_REG_2,
583 - REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
584 - REW_TAG_CFG,
585 - REW_PORT_CFG,
586 - REW_DSCP_CFG,
587 - REW_PCP_DEI_QOS_MAP_CFG,
588 - REW_PTP_CFG,
589 - REW_PTP_DLY1_CFG,
590 - REW_RED_TAG_CFG,
591 - REW_DSCP_REMAP_DP1_CFG,
592 - REW_DSCP_REMAP_CFG,
593 - REW_STAT_CFG,
594 - REW_REW_STICKY,
595 - REW_PPT,
596 - SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
597 - SYS_COUNT_RX_UNICAST,
598 - SYS_COUNT_RX_MULTICAST,
599 - SYS_COUNT_RX_BROADCAST,
600 - SYS_COUNT_RX_SHORTS,
601 - SYS_COUNT_RX_FRAGMENTS,
602 - SYS_COUNT_RX_JABBERS,
603 - SYS_COUNT_RX_CRC_ALIGN_ERRS,
604 - SYS_COUNT_RX_SYM_ERRS,
605 - SYS_COUNT_RX_64,
606 - SYS_COUNT_RX_65_127,
607 - SYS_COUNT_RX_128_255,
608 - SYS_COUNT_RX_256_1023,
609 - SYS_COUNT_RX_1024_1526,
610 - SYS_COUNT_RX_1527_MAX,
611 - SYS_COUNT_RX_PAUSE,
612 - SYS_COUNT_RX_CONTROL,
613 - SYS_COUNT_RX_LONGS,
614 - SYS_COUNT_RX_CLASSIFIED_DROPS,
615 - SYS_COUNT_TX_OCTETS,
616 - SYS_COUNT_TX_UNICAST,
617 - SYS_COUNT_TX_MULTICAST,
618 - SYS_COUNT_TX_BROADCAST,
619 - SYS_COUNT_TX_COLLISION,
620 - SYS_COUNT_TX_DROPS,
621 - SYS_COUNT_TX_PAUSE,
622 - SYS_COUNT_TX_64,
623 - SYS_COUNT_TX_65_127,
624 - SYS_COUNT_TX_128_511,
625 - SYS_COUNT_TX_512_1023,
626 - SYS_COUNT_TX_1024_1526,
627 - SYS_COUNT_TX_1527_MAX,
628 - SYS_COUNT_TX_AGING,
629 - SYS_RESET_CFG,
630 - SYS_SR_ETYPE_CFG,
631 - SYS_VLAN_ETYPE_CFG,
632 - SYS_PORT_MODE,
633 - SYS_FRONT_PORT_MODE,
634 - SYS_FRM_AGING,
635 - SYS_STAT_CFG,
636 - SYS_SW_STATUS,
637 - SYS_MISC_CFG,
638 - SYS_REW_MAC_HIGH_CFG,
639 - SYS_REW_MAC_LOW_CFG,
640 - SYS_TIMESTAMP_OFFSET,
641 - SYS_CMID,
642 - SYS_PAUSE_CFG,
643 - SYS_PAUSE_TOT_CFG,
644 - SYS_ATOP,
645 - SYS_ATOP_TOT_CFG,
646 - SYS_MAC_FC_CFG,
647 - SYS_MMGT,
648 - SYS_MMGT_FAST,
649 - SYS_EVENTS_DIF,
650 - SYS_EVENTS_CORE,
651 - SYS_CNT,
652 - SYS_PTP_STATUS,
653 - SYS_PTP_TXSTAMP,
654 - SYS_PTP_NXT,
655 - SYS_PTP_CFG,
656 - SYS_RAM_INIT,
657 - SYS_CM_ADDR,
658 - SYS_CM_DATA_WR,
659 - SYS_CM_DATA_RD,
660 - SYS_CM_OP,
661 - SYS_CM_DATA,
662 - S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
663 - S2_CORE_MV_CFG,
664 - S2_CACHE_ENTRY_DAT,
665 - S2_CACHE_MASK_DAT,
666 - S2_CACHE_ACTION_DAT,
667 - S2_CACHE_CNT_DAT,
668 - S2_CACHE_TG_DAT,
669 - PTP_PIN_CFG = PTP << TARGET_OFFSET,
670 - PTP_PIN_TOD_SEC_MSB,
671 - PTP_PIN_TOD_SEC_LSB,
672 - PTP_PIN_TOD_NSEC,
673 - PTP_CFG_MISC,
674 - PTP_CLK_CFG_ADJ_CFG,
675 - PTP_CLK_CFG_ADJ_FREQ,
676 -};
677 -
678 -enum ocelot_regfield {
679 - ANA_ADVLEARN_VLAN_CHK,
680 - ANA_ADVLEARN_LEARN_MIRROR,
681 - ANA_ANEVENTS_FLOOD_DISCARD,
682 - ANA_ANEVENTS_MSTI_DROP,
683 - ANA_ANEVENTS_ACLKILL,
684 - ANA_ANEVENTS_ACLUSED,
685 - ANA_ANEVENTS_AUTOAGE,
686 - ANA_ANEVENTS_VS2TTL1,
687 - ANA_ANEVENTS_STORM_DROP,
688 - ANA_ANEVENTS_LEARN_DROP,
689 - ANA_ANEVENTS_AGED_ENTRY,
690 - ANA_ANEVENTS_CPU_LEARN_FAILED,
691 - ANA_ANEVENTS_AUTO_LEARN_FAILED,
692 - ANA_ANEVENTS_LEARN_REMOVE,
693 - ANA_ANEVENTS_AUTO_LEARNED,
694 - ANA_ANEVENTS_AUTO_MOVED,
695 - ANA_ANEVENTS_DROPPED,
696 - ANA_ANEVENTS_CLASSIFIED_DROP,
697 - ANA_ANEVENTS_CLASSIFIED_COPY,
698 - ANA_ANEVENTS_VLAN_DISCARD,
699 - ANA_ANEVENTS_FWD_DISCARD,
700 - ANA_ANEVENTS_MULTICAST_FLOOD,
701 - ANA_ANEVENTS_UNICAST_FLOOD,
702 - ANA_ANEVENTS_DEST_KNOWN,
703 - ANA_ANEVENTS_BUCKET3_MATCH,
704 - ANA_ANEVENTS_BUCKET2_MATCH,
705 - ANA_ANEVENTS_BUCKET1_MATCH,
706 - ANA_ANEVENTS_BUCKET0_MATCH,
707 - ANA_ANEVENTS_CPU_OPERATION,
708 - ANA_ANEVENTS_DMAC_LOOKUP,
709 - ANA_ANEVENTS_SMAC_LOOKUP,
710 - ANA_ANEVENTS_SEQ_GEN_ERR_0,
711 - ANA_ANEVENTS_SEQ_GEN_ERR_1,
712 - ANA_TABLES_MACACCESS_B_DOM,
713 - ANA_TABLES_MACTINDX_BUCKET,
714 - ANA_TABLES_MACTINDX_M_INDEX,
715 - QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
716 - QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
717 - QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
718 - QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
719 - QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
720 - SYS_RESET_CFG_CORE_ENA,
721 - SYS_RESET_CFG_MEM_ENA,
722 - SYS_RESET_CFG_MEM_INIT,
723 - REGFIELD_MAX
724 -};
725 -
726 -enum ocelot_clk_pins {
727 - ALT_PPS_PIN = 1,
728 - EXT_CLK_PIN,
729 - ALT_LDST_PIN,
730 - TOD_ACC_PIN
731 -};
732 -
733 struct ocelot_multicast {
734 struct list_head list;
735 unsigned char addr[ETH_ALEN];
736 @@ -429,88 +60,6 @@ struct ocelot_multicast {
737 u16 ports;
738 };
739
740 -enum ocelot_tag_prefix {
741 - OCELOT_TAG_PREFIX_DISABLED = 0,
742 - OCELOT_TAG_PREFIX_NONE,
743 - OCELOT_TAG_PREFIX_SHORT,
744 - OCELOT_TAG_PREFIX_LONG,
745 -};
746 -
747 -struct ocelot_port;
748 -struct ocelot;
749 -
750 -struct ocelot_stat_layout {
751 - u32 offset;
752 - char name[ETH_GSTRING_LEN];
753 -};
754 -
755 -struct ocelot_ops {
756 - void (*pcs_init)(struct ocelot *ocelot, int port);
757 - int (*reset)(struct ocelot *ocelot);
758 -};
759 -
760 -struct ocelot {
761 - const struct ocelot_ops *ops;
762 - struct device *dev;
763 -
764 - struct regmap *targets[TARGET_MAX];
765 - struct regmap_field *regfields[REGFIELD_MAX];
766 - const u32 *const *map;
767 - const struct ocelot_stat_layout *stats_layout;
768 - unsigned int num_stats;
769 -
770 - u8 base_mac[ETH_ALEN];
771 -
772 - struct net_device *hw_bridge_dev;
773 - u16 bridge_mask;
774 - u16 bridge_fwd_mask;
775 -
776 - struct workqueue_struct *ocelot_owq;
777 -
778 - int shared_queue_sz;
779 -
780 - u8 num_phys_ports;
781 - u8 num_cpu_ports;
782 - u8 cpu;
783 - struct ocelot_port **ports;
784 -
785 - u32 *lags;
786 -
787 - /* Keep track of the vlan port masks */
788 - u32 vlan_mask[VLAN_N_VID];
789 -
790 - struct list_head multicast;
791 -
792 - /* Workqueue to check statistics for overflow with its lock */
793 - struct mutex stats_lock;
794 - u64 *stats;
795 - struct delayed_work stats_work;
796 - struct workqueue_struct *stats_queue;
797 -
798 - u8 ptp:1;
799 - struct ptp_clock *ptp_clock;
800 - struct ptp_clock_info ptp_info;
801 - struct hwtstamp_config hwtstamp_config;
802 - struct mutex ptp_lock; /* Protects the PTP interface state */
803 - spinlock_t ptp_clock_lock; /* Protects the PTP clock */
804 -};
805 -
806 -struct ocelot_port {
807 - struct ocelot *ocelot;
808 -
809 - void __iomem *regs;
810 -
811 - /* Ingress default VLAN (pvid) */
812 - u16 pvid;
813 -
814 - /* Egress default VLAN (vid) */
815 - u16 vid;
816 -
817 - u8 ptp_cmd;
818 - struct list_head skbs;
819 - u8 ts_id;
820 -};
821 -
822 struct ocelot_port_private {
823 struct ocelot_port port;
824 struct net_device *dev;
825 @@ -531,37 +80,12 @@ struct ocelot_skb {
826 u8 id;
827 };
828
829 -u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
830 -#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
831 -#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
832 -#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
833 -#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
834 -
835 -void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
836 -#define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
837 -#define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
838 -#define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
839 -#define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
840 -
841 -void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
842 - u32 offset);
843 -#define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
844 -#define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
845 -#define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
846 -#define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
847 -
848 u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
849 void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
850
851 -int ocelot_regfields_init(struct ocelot *ocelot,
852 - const struct reg_field *const regfields);
853 -struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
854 -
855 #define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
856 #define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
857
858 -int ocelot_init(struct ocelot *ocelot);
859 -void ocelot_deinit(struct ocelot *ocelot);
860 int ocelot_chip_init(struct ocelot *ocelot, const struct ocelot_ops *ops);
861 int ocelot_probe_port(struct ocelot *ocelot, u8 port,
862 void __iomem *regs,
863 @@ -575,7 +99,7 @@ extern struct notifier_block ocelot_netd
864 extern struct notifier_block ocelot_switchdev_nb;
865 extern struct notifier_block ocelot_switchdev_blocking_nb;
866
867 -int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
868 -void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts);
869 +#define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))
870 +#define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))
871
872 #endif
873 --- /dev/null
874 +++ b/include/soc/mscc/ocelot.h
875 @@ -0,0 +1,539 @@
876 +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
877 +/* Copyright (c) 2017 Microsemi Corporation
878 + */
879 +
880 +#ifndef _SOC_MSCC_OCELOT_H
881 +#define _SOC_MSCC_OCELOT_H
882 +
883 +#include <linux/ptp_clock_kernel.h>
884 +#include <linux/net_tstamp.h>
885 +#include <linux/if_vlan.h>
886 +#include <linux/regmap.h>
887 +#include <net/dsa.h>
888 +
889 +#define IFH_INJ_BYPASS BIT(31)
890 +#define IFH_INJ_POP_CNT_DISABLE (3 << 28)
891 +
892 +#define IFH_TAG_TYPE_C 0
893 +#define IFH_TAG_TYPE_S 1
894 +
895 +#define IFH_REW_OP_NOOP 0x0
896 +#define IFH_REW_OP_DSCP 0x1
897 +#define IFH_REW_OP_ONE_STEP_PTP 0x2
898 +#define IFH_REW_OP_TWO_STEP_PTP 0x3
899 +#define IFH_REW_OP_ORIGIN_PTP 0x5
900 +
901 +#define OCELOT_TAG_LEN 16
902 +#define OCELOT_SHORT_PREFIX_LEN 4
903 +#define OCELOT_LONG_PREFIX_LEN 16
904 +
905 +#define OCELOT_SPEED_2500 0
906 +#define OCELOT_SPEED_1000 1
907 +#define OCELOT_SPEED_100 2
908 +#define OCELOT_SPEED_10 3
909 +
910 +#define TARGET_OFFSET 24
911 +#define REG_MASK GENMASK(TARGET_OFFSET - 1, 0)
912 +#define REG(reg, offset) [reg & REG_MASK] = offset
913 +
914 +#define REG_RESERVED_ADDR 0xffffffff
915 +#define REG_RESERVED(reg) REG(reg, REG_RESERVED_ADDR)
916 +
917 +enum ocelot_target {
918 + ANA = 1,
919 + QS,
920 + QSYS,
921 + REW,
922 + SYS,
923 + S2,
924 + HSIO,
925 + PTP,
926 + GCB,
927 + TARGET_MAX,
928 +};
929 +
930 +enum ocelot_reg {
931 + ANA_ADVLEARN = ANA << TARGET_OFFSET,
932 + ANA_VLANMASK,
933 + ANA_PORT_B_DOMAIN,
934 + ANA_ANAGEFIL,
935 + ANA_ANEVENTS,
936 + ANA_STORMLIMIT_BURST,
937 + ANA_STORMLIMIT_CFG,
938 + ANA_ISOLATED_PORTS,
939 + ANA_COMMUNITY_PORTS,
940 + ANA_AUTOAGE,
941 + ANA_MACTOPTIONS,
942 + ANA_LEARNDISC,
943 + ANA_AGENCTRL,
944 + ANA_MIRRORPORTS,
945 + ANA_EMIRRORPORTS,
946 + ANA_FLOODING,
947 + ANA_FLOODING_IPMC,
948 + ANA_SFLOW_CFG,
949 + ANA_PORT_MODE,
950 + ANA_CUT_THRU_CFG,
951 + ANA_PGID_PGID,
952 + ANA_TABLES_ANMOVED,
953 + ANA_TABLES_MACHDATA,
954 + ANA_TABLES_MACLDATA,
955 + ANA_TABLES_STREAMDATA,
956 + ANA_TABLES_MACACCESS,
957 + ANA_TABLES_MACTINDX,
958 + ANA_TABLES_VLANACCESS,
959 + ANA_TABLES_VLANTIDX,
960 + ANA_TABLES_ISDXACCESS,
961 + ANA_TABLES_ISDXTIDX,
962 + ANA_TABLES_ENTRYLIM,
963 + ANA_TABLES_PTP_ID_HIGH,
964 + ANA_TABLES_PTP_ID_LOW,
965 + ANA_TABLES_STREAMACCESS,
966 + ANA_TABLES_STREAMTIDX,
967 + ANA_TABLES_SEQ_HISTORY,
968 + ANA_TABLES_SEQ_MASK,
969 + ANA_TABLES_SFID_MASK,
970 + ANA_TABLES_SFIDACCESS,
971 + ANA_TABLES_SFIDTIDX,
972 + ANA_MSTI_STATE,
973 + ANA_OAM_UPM_LM_CNT,
974 + ANA_SG_ACCESS_CTRL,
975 + ANA_SG_CONFIG_REG_1,
976 + ANA_SG_CONFIG_REG_2,
977 + ANA_SG_CONFIG_REG_3,
978 + ANA_SG_CONFIG_REG_4,
979 + ANA_SG_CONFIG_REG_5,
980 + ANA_SG_GCL_GS_CONFIG,
981 + ANA_SG_GCL_TI_CONFIG,
982 + ANA_SG_STATUS_REG_1,
983 + ANA_SG_STATUS_REG_2,
984 + ANA_SG_STATUS_REG_3,
985 + ANA_PORT_VLAN_CFG,
986 + ANA_PORT_DROP_CFG,
987 + ANA_PORT_QOS_CFG,
988 + ANA_PORT_VCAP_CFG,
989 + ANA_PORT_VCAP_S1_KEY_CFG,
990 + ANA_PORT_VCAP_S2_CFG,
991 + ANA_PORT_PCP_DEI_MAP,
992 + ANA_PORT_CPU_FWD_CFG,
993 + ANA_PORT_CPU_FWD_BPDU_CFG,
994 + ANA_PORT_CPU_FWD_GARP_CFG,
995 + ANA_PORT_CPU_FWD_CCM_CFG,
996 + ANA_PORT_PORT_CFG,
997 + ANA_PORT_POL_CFG,
998 + ANA_PORT_PTP_CFG,
999 + ANA_PORT_PTP_DLY1_CFG,
1000 + ANA_PORT_PTP_DLY2_CFG,
1001 + ANA_PORT_SFID_CFG,
1002 + ANA_PFC_PFC_CFG,
1003 + ANA_PFC_PFC_TIMER,
1004 + ANA_IPT_OAM_MEP_CFG,
1005 + ANA_IPT_IPT,
1006 + ANA_PPT_PPT,
1007 + ANA_FID_MAP_FID_MAP,
1008 + ANA_AGGR_CFG,
1009 + ANA_CPUQ_CFG,
1010 + ANA_CPUQ_CFG2,
1011 + ANA_CPUQ_8021_CFG,
1012 + ANA_DSCP_CFG,
1013 + ANA_DSCP_REWR_CFG,
1014 + ANA_VCAP_RNG_TYPE_CFG,
1015 + ANA_VCAP_RNG_VAL_CFG,
1016 + ANA_VRAP_CFG,
1017 + ANA_VRAP_HDR_DATA,
1018 + ANA_VRAP_HDR_MASK,
1019 + ANA_DISCARD_CFG,
1020 + ANA_FID_CFG,
1021 + ANA_POL_PIR_CFG,
1022 + ANA_POL_CIR_CFG,
1023 + ANA_POL_MODE_CFG,
1024 + ANA_POL_PIR_STATE,
1025 + ANA_POL_CIR_STATE,
1026 + ANA_POL_STATE,
1027 + ANA_POL_FLOWC,
1028 + ANA_POL_HYST,
1029 + ANA_POL_MISC_CFG,
1030 + QS_XTR_GRP_CFG = QS << TARGET_OFFSET,
1031 + QS_XTR_RD,
1032 + QS_XTR_FRM_PRUNING,
1033 + QS_XTR_FLUSH,
1034 + QS_XTR_DATA_PRESENT,
1035 + QS_XTR_CFG,
1036 + QS_INJ_GRP_CFG,
1037 + QS_INJ_WR,
1038 + QS_INJ_CTRL,
1039 + QS_INJ_STATUS,
1040 + QS_INJ_ERR,
1041 + QS_INH_DBG,
1042 + QSYS_PORT_MODE = QSYS << TARGET_OFFSET,
1043 + QSYS_SWITCH_PORT_MODE,
1044 + QSYS_STAT_CNT_CFG,
1045 + QSYS_EEE_CFG,
1046 + QSYS_EEE_THRES,
1047 + QSYS_IGR_NO_SHARING,
1048 + QSYS_EGR_NO_SHARING,
1049 + QSYS_SW_STATUS,
1050 + QSYS_EXT_CPU_CFG,
1051 + QSYS_PAD_CFG,
1052 + QSYS_CPU_GROUP_MAP,
1053 + QSYS_QMAP,
1054 + QSYS_ISDX_SGRP,
1055 + QSYS_TIMED_FRAME_ENTRY,
1056 + QSYS_TFRM_MISC,
1057 + QSYS_TFRM_PORT_DLY,
1058 + QSYS_TFRM_TIMER_CFG_1,
1059 + QSYS_TFRM_TIMER_CFG_2,
1060 + QSYS_TFRM_TIMER_CFG_3,
1061 + QSYS_TFRM_TIMER_CFG_4,
1062 + QSYS_TFRM_TIMER_CFG_5,
1063 + QSYS_TFRM_TIMER_CFG_6,
1064 + QSYS_TFRM_TIMER_CFG_7,
1065 + QSYS_TFRM_TIMER_CFG_8,
1066 + QSYS_RED_PROFILE,
1067 + QSYS_RES_QOS_MODE,
1068 + QSYS_RES_CFG,
1069 + QSYS_RES_STAT,
1070 + QSYS_EGR_DROP_MODE,
1071 + QSYS_EQ_CTRL,
1072 + QSYS_EVENTS_CORE,
1073 + QSYS_QMAXSDU_CFG_0,
1074 + QSYS_QMAXSDU_CFG_1,
1075 + QSYS_QMAXSDU_CFG_2,
1076 + QSYS_QMAXSDU_CFG_3,
1077 + QSYS_QMAXSDU_CFG_4,
1078 + QSYS_QMAXSDU_CFG_5,
1079 + QSYS_QMAXSDU_CFG_6,
1080 + QSYS_QMAXSDU_CFG_7,
1081 + QSYS_PREEMPTION_CFG,
1082 + QSYS_CIR_CFG,
1083 + QSYS_EIR_CFG,
1084 + QSYS_SE_CFG,
1085 + QSYS_SE_DWRR_CFG,
1086 + QSYS_SE_CONNECT,
1087 + QSYS_SE_DLB_SENSE,
1088 + QSYS_CIR_STATE,
1089 + QSYS_EIR_STATE,
1090 + QSYS_SE_STATE,
1091 + QSYS_HSCH_MISC_CFG,
1092 + QSYS_TAG_CONFIG,
1093 + QSYS_TAS_PARAM_CFG_CTRL,
1094 + QSYS_PORT_MAX_SDU,
1095 + QSYS_PARAM_CFG_REG_1,
1096 + QSYS_PARAM_CFG_REG_2,
1097 + QSYS_PARAM_CFG_REG_3,
1098 + QSYS_PARAM_CFG_REG_4,
1099 + QSYS_PARAM_CFG_REG_5,
1100 + QSYS_GCL_CFG_REG_1,
1101 + QSYS_GCL_CFG_REG_2,
1102 + QSYS_PARAM_STATUS_REG_1,
1103 + QSYS_PARAM_STATUS_REG_2,
1104 + QSYS_PARAM_STATUS_REG_3,
1105 + QSYS_PARAM_STATUS_REG_4,
1106 + QSYS_PARAM_STATUS_REG_5,
1107 + QSYS_PARAM_STATUS_REG_6,
1108 + QSYS_PARAM_STATUS_REG_7,
1109 + QSYS_PARAM_STATUS_REG_8,
1110 + QSYS_PARAM_STATUS_REG_9,
1111 + QSYS_GCL_STATUS_REG_1,
1112 + QSYS_GCL_STATUS_REG_2,
1113 + REW_PORT_VLAN_CFG = REW << TARGET_OFFSET,
1114 + REW_TAG_CFG,
1115 + REW_PORT_CFG,
1116 + REW_DSCP_CFG,
1117 + REW_PCP_DEI_QOS_MAP_CFG,
1118 + REW_PTP_CFG,
1119 + REW_PTP_DLY1_CFG,
1120 + REW_RED_TAG_CFG,
1121 + REW_DSCP_REMAP_DP1_CFG,
1122 + REW_DSCP_REMAP_CFG,
1123 + REW_STAT_CFG,
1124 + REW_REW_STICKY,
1125 + REW_PPT,
1126 + SYS_COUNT_RX_OCTETS = SYS << TARGET_OFFSET,
1127 + SYS_COUNT_RX_UNICAST,
1128 + SYS_COUNT_RX_MULTICAST,
1129 + SYS_COUNT_RX_BROADCAST,
1130 + SYS_COUNT_RX_SHORTS,
1131 + SYS_COUNT_RX_FRAGMENTS,
1132 + SYS_COUNT_RX_JABBERS,
1133 + SYS_COUNT_RX_CRC_ALIGN_ERRS,
1134 + SYS_COUNT_RX_SYM_ERRS,
1135 + SYS_COUNT_RX_64,
1136 + SYS_COUNT_RX_65_127,
1137 + SYS_COUNT_RX_128_255,
1138 + SYS_COUNT_RX_256_1023,
1139 + SYS_COUNT_RX_1024_1526,
1140 + SYS_COUNT_RX_1527_MAX,
1141 + SYS_COUNT_RX_PAUSE,
1142 + SYS_COUNT_RX_CONTROL,
1143 + SYS_COUNT_RX_LONGS,
1144 + SYS_COUNT_RX_CLASSIFIED_DROPS,
1145 + SYS_COUNT_TX_OCTETS,
1146 + SYS_COUNT_TX_UNICAST,
1147 + SYS_COUNT_TX_MULTICAST,
1148 + SYS_COUNT_TX_BROADCAST,
1149 + SYS_COUNT_TX_COLLISION,
1150 + SYS_COUNT_TX_DROPS,
1151 + SYS_COUNT_TX_PAUSE,
1152 + SYS_COUNT_TX_64,
1153 + SYS_COUNT_TX_65_127,
1154 + SYS_COUNT_TX_128_511,
1155 + SYS_COUNT_TX_512_1023,
1156 + SYS_COUNT_TX_1024_1526,
1157 + SYS_COUNT_TX_1527_MAX,
1158 + SYS_COUNT_TX_AGING,
1159 + SYS_RESET_CFG,
1160 + SYS_SR_ETYPE_CFG,
1161 + SYS_VLAN_ETYPE_CFG,
1162 + SYS_PORT_MODE,
1163 + SYS_FRONT_PORT_MODE,
1164 + SYS_FRM_AGING,
1165 + SYS_STAT_CFG,
1166 + SYS_SW_STATUS,
1167 + SYS_MISC_CFG,
1168 + SYS_REW_MAC_HIGH_CFG,
1169 + SYS_REW_MAC_LOW_CFG,
1170 + SYS_TIMESTAMP_OFFSET,
1171 + SYS_CMID,
1172 + SYS_PAUSE_CFG,
1173 + SYS_PAUSE_TOT_CFG,
1174 + SYS_ATOP,
1175 + SYS_ATOP_TOT_CFG,
1176 + SYS_MAC_FC_CFG,
1177 + SYS_MMGT,
1178 + SYS_MMGT_FAST,
1179 + SYS_EVENTS_DIF,
1180 + SYS_EVENTS_CORE,
1181 + SYS_CNT,
1182 + SYS_PTP_STATUS,
1183 + SYS_PTP_TXSTAMP,
1184 + SYS_PTP_NXT,
1185 + SYS_PTP_CFG,
1186 + SYS_RAM_INIT,
1187 + SYS_CM_ADDR,
1188 + SYS_CM_DATA_WR,
1189 + SYS_CM_DATA_RD,
1190 + SYS_CM_OP,
1191 + SYS_CM_DATA,
1192 + S2_CORE_UPDATE_CTRL = S2 << TARGET_OFFSET,
1193 + S2_CORE_MV_CFG,
1194 + S2_CACHE_ENTRY_DAT,
1195 + S2_CACHE_MASK_DAT,
1196 + S2_CACHE_ACTION_DAT,
1197 + S2_CACHE_CNT_DAT,
1198 + S2_CACHE_TG_DAT,
1199 + PTP_PIN_CFG = PTP << TARGET_OFFSET,
1200 + PTP_PIN_TOD_SEC_MSB,
1201 + PTP_PIN_TOD_SEC_LSB,
1202 + PTP_PIN_TOD_NSEC,
1203 + PTP_CFG_MISC,
1204 + PTP_CLK_CFG_ADJ_CFG,
1205 + PTP_CLK_CFG_ADJ_FREQ,
1206 + GCB_SOFT_RST = GCB << TARGET_OFFSET,
1207 +};
1208 +
1209 +enum ocelot_regfield {
1210 + ANA_ADVLEARN_VLAN_CHK,
1211 + ANA_ADVLEARN_LEARN_MIRROR,
1212 + ANA_ANEVENTS_FLOOD_DISCARD,
1213 + ANA_ANEVENTS_MSTI_DROP,
1214 + ANA_ANEVENTS_ACLKILL,
1215 + ANA_ANEVENTS_ACLUSED,
1216 + ANA_ANEVENTS_AUTOAGE,
1217 + ANA_ANEVENTS_VS2TTL1,
1218 + ANA_ANEVENTS_STORM_DROP,
1219 + ANA_ANEVENTS_LEARN_DROP,
1220 + ANA_ANEVENTS_AGED_ENTRY,
1221 + ANA_ANEVENTS_CPU_LEARN_FAILED,
1222 + ANA_ANEVENTS_AUTO_LEARN_FAILED,
1223 + ANA_ANEVENTS_LEARN_REMOVE,
1224 + ANA_ANEVENTS_AUTO_LEARNED,
1225 + ANA_ANEVENTS_AUTO_MOVED,
1226 + ANA_ANEVENTS_DROPPED,
1227 + ANA_ANEVENTS_CLASSIFIED_DROP,
1228 + ANA_ANEVENTS_CLASSIFIED_COPY,
1229 + ANA_ANEVENTS_VLAN_DISCARD,
1230 + ANA_ANEVENTS_FWD_DISCARD,
1231 + ANA_ANEVENTS_MULTICAST_FLOOD,
1232 + ANA_ANEVENTS_UNICAST_FLOOD,
1233 + ANA_ANEVENTS_DEST_KNOWN,
1234 + ANA_ANEVENTS_BUCKET3_MATCH,
1235 + ANA_ANEVENTS_BUCKET2_MATCH,
1236 + ANA_ANEVENTS_BUCKET1_MATCH,
1237 + ANA_ANEVENTS_BUCKET0_MATCH,
1238 + ANA_ANEVENTS_CPU_OPERATION,
1239 + ANA_ANEVENTS_DMAC_LOOKUP,
1240 + ANA_ANEVENTS_SMAC_LOOKUP,
1241 + ANA_ANEVENTS_SEQ_GEN_ERR_0,
1242 + ANA_ANEVENTS_SEQ_GEN_ERR_1,
1243 + ANA_TABLES_MACACCESS_B_DOM,
1244 + ANA_TABLES_MACTINDX_BUCKET,
1245 + ANA_TABLES_MACTINDX_M_INDEX,
1246 + QSYS_TIMED_FRAME_ENTRY_TFRM_VLD,
1247 + QSYS_TIMED_FRAME_ENTRY_TFRM_FP,
1248 + QSYS_TIMED_FRAME_ENTRY_TFRM_PORTNO,
1249 + QSYS_TIMED_FRAME_ENTRY_TFRM_TM_SEL,
1250 + QSYS_TIMED_FRAME_ENTRY_TFRM_TM_T,
1251 + SYS_RESET_CFG_CORE_ENA,
1252 + SYS_RESET_CFG_MEM_ENA,
1253 + SYS_RESET_CFG_MEM_INIT,
1254 + GCB_SOFT_RST_SWC_RST,
1255 + REGFIELD_MAX
1256 +};
1257 +
1258 +enum ocelot_clk_pins {
1259 + ALT_PPS_PIN = 1,
1260 + EXT_CLK_PIN,
1261 + ALT_LDST_PIN,
1262 + TOD_ACC_PIN
1263 +};
1264 +
1265 +struct ocelot_stat_layout {
1266 + u32 offset;
1267 + char name[ETH_GSTRING_LEN];
1268 +};
1269 +
1270 +enum ocelot_tag_prefix {
1271 + OCELOT_TAG_PREFIX_DISABLED = 0,
1272 + OCELOT_TAG_PREFIX_NONE,
1273 + OCELOT_TAG_PREFIX_SHORT,
1274 + OCELOT_TAG_PREFIX_LONG,
1275 +};
1276 +
1277 +struct ocelot;
1278 +
1279 +struct ocelot_ops {
1280 + void (*pcs_init)(struct ocelot *ocelot, int port);
1281 + int (*reset)(struct ocelot *ocelot);
1282 +};
1283 +
1284 +struct ocelot_port {
1285 + struct ocelot *ocelot;
1286 +
1287 + void __iomem *regs;
1288 +
1289 + /* Ingress default VLAN (pvid) */
1290 + u16 pvid;
1291 +
1292 + /* Egress default VLAN (vid) */
1293 + u16 vid;
1294 +
1295 + u8 ptp_cmd;
1296 + struct list_head skbs;
1297 + u8 ts_id;
1298 +};
1299 +
1300 +struct ocelot {
1301 + struct device *dev;
1302 +
1303 + const struct ocelot_ops *ops;
1304 + struct regmap *targets[TARGET_MAX];
1305 + struct regmap_field *regfields[REGFIELD_MAX];
1306 + const u32 *const *map;
1307 + const struct ocelot_stat_layout *stats_layout;
1308 + unsigned int num_stats;
1309 +
1310 + int shared_queue_sz;
1311 +
1312 + struct net_device *hw_bridge_dev;
1313 + u16 bridge_mask;
1314 + u16 bridge_fwd_mask;
1315 +
1316 + struct ocelot_port **ports;
1317 +
1318 + u8 base_mac[ETH_ALEN];
1319 +
1320 + /* Keep track of the vlan port masks */
1321 + u32 vlan_mask[VLAN_N_VID];
1322 +
1323 + u8 num_phys_ports;
1324 + u8 num_cpu_ports;
1325 + u8 cpu;
1326 +
1327 + u32 *lags;
1328 +
1329 + struct list_head multicast;
1330 +
1331 + /* Workqueue to check statistics for overflow with its lock */
1332 + struct mutex stats_lock;
1333 + u64 *stats;
1334 + struct delayed_work stats_work;
1335 + struct workqueue_struct *stats_queue;
1336 +
1337 + u8 ptp:1;
1338 + struct ptp_clock *ptp_clock;
1339 + struct ptp_clock_info ptp_info;
1340 + struct hwtstamp_config hwtstamp_config;
1341 + /* Protects the PTP interface state */
1342 + struct mutex ptp_lock;
1343 + /* Protects the PTP clock */
1344 + spinlock_t ptp_clock_lock;
1345 +
1346 + void (*port_pcs_init)(struct ocelot_port *port);
1347 +};
1348 +
1349 +#define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
1350 +#define ocelot_read_gix(ocelot, reg, gi) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi))
1351 +#define ocelot_read_rix(ocelot, reg, ri) __ocelot_read_ix(ocelot, reg, reg##_RSZ * (ri))
1352 +#define ocelot_read(ocelot, reg) __ocelot_read_ix(ocelot, reg, 0)
1353 +
1354 +#define ocelot_write_ix(ocelot, val, reg, gi, ri) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
1355 +#define ocelot_write_gix(ocelot, val, reg, gi) __ocelot_write_ix(ocelot, val, reg, reg##_GSZ * (gi))
1356 +#define ocelot_write_rix(ocelot, val, reg, ri) __ocelot_write_ix(ocelot, val, reg, reg##_RSZ * (ri))
1357 +#define ocelot_write(ocelot, val, reg) __ocelot_write_ix(ocelot, val, reg, 0)
1358 +
1359 +#define ocelot_rmw_ix(ocelot, val, m, reg, gi, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
1360 +#define ocelot_rmw_gix(ocelot, val, m, reg, gi) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_GSZ * (gi))
1361 +#define ocelot_rmw_rix(ocelot, val, m, reg, ri) __ocelot_rmw_ix(ocelot, val, m, reg, reg##_RSZ * (ri))
1362 +#define ocelot_rmw(ocelot, val, m, reg) __ocelot_rmw_ix(ocelot, val, m, reg, 0)
1363 +
1364 +/* I/O */
1365 +u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);
1366 +void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);
1367 +u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset);
1368 +void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset);
1369 +void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
1370 + u32 offset);
1371 +
1372 +/* Hardware initialization */
1373 +int ocelot_regfields_init(struct ocelot *ocelot,
1374 + const struct reg_field *const regfields);
1375 +struct regmap *ocelot_regmap_init(struct ocelot *ocelot, struct resource *res);
1376 +void ocelot_set_cpu_port(struct ocelot *ocelot, int cpu,
1377 + enum ocelot_tag_prefix injection,
1378 + enum ocelot_tag_prefix extraction);
1379 +int ocelot_init(struct ocelot *ocelot);
1380 +void ocelot_deinit(struct ocelot *ocelot);
1381 +void ocelot_init_port(struct ocelot *ocelot, int port);
1382 +
1383 +/* DSA callbacks */
1384 +void ocelot_port_enable(struct ocelot *ocelot, int port,
1385 + struct phy_device *phy);
1386 +void ocelot_port_disable(struct ocelot *ocelot, int port);
1387 +void ocelot_get_strings(struct ocelot *ocelot, int port, u32 sset, u8 *data);
1388 +void ocelot_get_ethtool_stats(struct ocelot *ocelot, int port, u64 *data);
1389 +int ocelot_get_sset_count(struct ocelot *ocelot, int port, int sset);
1390 +int ocelot_get_ts_info(struct ocelot *ocelot, int port,
1391 + struct ethtool_ts_info *info);
1392 +void ocelot_set_ageing_time(struct ocelot *ocelot, unsigned int msecs);
1393 +void ocelot_adjust_link(struct ocelot *ocelot, int port,
1394 + struct phy_device *phydev);
1395 +void ocelot_port_vlan_filtering(struct ocelot *ocelot, int port,
1396 + bool vlan_aware);
1397 +void ocelot_bridge_stp_state_set(struct ocelot *ocelot, int port, u8 state);
1398 +int ocelot_port_bridge_join(struct ocelot *ocelot, int port,
1399 + struct net_device *bridge);
1400 +int ocelot_port_bridge_leave(struct ocelot *ocelot, int port,
1401 + struct net_device *bridge);
1402 +int ocelot_fdb_dump(struct ocelot *ocelot, int port,
1403 + dsa_fdb_dump_cb_t *cb, void *data);
1404 +int ocelot_fdb_add(struct ocelot *ocelot, int port,
1405 + const unsigned char *addr, u16 vid, bool vlan_aware);
1406 +int ocelot_fdb_del(struct ocelot *ocelot, int port,
1407 + const unsigned char *addr, u16 vid);
1408 +int ocelot_vlan_add(struct ocelot *ocelot, int port, u16 vid, bool pvid,
1409 + bool untagged);
1410 +int ocelot_vlan_del(struct ocelot *ocelot, int port, u16 vid);
1411 +int ocelot_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts);
1412 +void ocelot_get_hwtimestamp(struct ocelot *ocelot, struct timespec64 *ts);
1413 +
1414 +#endif
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