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kernel: bump 5.4 to 5.4.85
[openwrt/openwrt.git] / target / linux / layerscape / patches-5.4 / 701-net-0261-net-mscc-ocelot-publish-ocelot_sys.h-to-include-soc-.patch
1 From 53069d6527fc1d2709d559206cdbf0d7357954b7 Mon Sep 17 00:00:00 2001
2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
3 Date: Thu, 14 Nov 2019 17:03:28 +0200
4 Subject: [PATCH] net: mscc: ocelot: publish ocelot_sys.h to include/soc/mscc
5
6 The Felix DSA driver needs to write to SYS_RAM_INIT_RAM_INIT for its own
7 chip initialization process.
8
9 Also update the MAINTAINERS file such that the headers exported by the
10 ocelot driver are under the same maintainers' umbrella as the driver
11 itself.
12
13 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
14 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
15 Signed-off-by: David S. Miller <davem@davemloft.net>
16 ---
17 MAINTAINERS | 1 +
18 drivers/net/ethernet/mscc/ocelot.h | 2 +-
19 drivers/net/ethernet/mscc/ocelot_sys.h | 144 ---------------------------------
20 include/soc/mscc/ocelot_sys.h | 144 +++++++++++++++++++++++++++++++++
21 4 files changed, 146 insertions(+), 145 deletions(-)
22 delete mode 100644 drivers/net/ethernet/mscc/ocelot_sys.h
23 create mode 100644 include/soc/mscc/ocelot_sys.h
24
25 --- a/MAINTAINERS
26 +++ b/MAINTAINERS
27 @@ -10825,6 +10825,7 @@ M: Microchip Linux Driver Support <UNGLi
28 L: netdev@vger.kernel.org
29 S: Supported
30 F: drivers/net/ethernet/mscc/
31 +F: include/soc/mscc/ocelot*
32
33 MICROSOFT SURFACE PRO 3 BUTTON DRIVER
34 M: Chen Yu <yu.c.chen@intel.com>
35 --- a/drivers/net/ethernet/mscc/ocelot.h
36 +++ b/drivers/net/ethernet/mscc/ocelot.h
37 @@ -18,12 +18,12 @@
38 #include <linux/ptp_clock_kernel.h>
39 #include <linux/regmap.h>
40
41 +#include <soc/mscc/ocelot_sys.h>
42 #include <soc/mscc/ocelot.h>
43 #include "ocelot_ana.h"
44 #include "ocelot_dev.h"
45 #include "ocelot_qsys.h"
46 #include "ocelot_rew.h"
47 -#include "ocelot_sys.h"
48 #include "ocelot_qs.h"
49 #include "ocelot_tc.h"
50 #include "ocelot_ptp.h"
51 --- a/drivers/net/ethernet/mscc/ocelot_sys.h
52 +++ /dev/null
53 @@ -1,144 +0,0 @@
54 -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
55 -/*
56 - * Microsemi Ocelot Switch driver
57 - *
58 - * Copyright (c) 2017 Microsemi Corporation
59 - */
60 -
61 -#ifndef _MSCC_OCELOT_SYS_H_
62 -#define _MSCC_OCELOT_SYS_H_
63 -
64 -#define SYS_COUNT_RX_OCTETS_RSZ 0x4
65 -
66 -#define SYS_COUNT_TX_OCTETS_RSZ 0x4
67 -
68 -#define SYS_PORT_MODE_RSZ 0x4
69 -
70 -#define SYS_PORT_MODE_DATA_WO_TS(x) (((x) << 5) & GENMASK(6, 5))
71 -#define SYS_PORT_MODE_DATA_WO_TS_M GENMASK(6, 5)
72 -#define SYS_PORT_MODE_DATA_WO_TS_X(x) (((x) & GENMASK(6, 5)) >> 5)
73 -#define SYS_PORT_MODE_INCL_INJ_HDR(x) (((x) << 3) & GENMASK(4, 3))
74 -#define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3)
75 -#define SYS_PORT_MODE_INCL_INJ_HDR_X(x) (((x) & GENMASK(4, 3)) >> 3)
76 -#define SYS_PORT_MODE_INCL_XTR_HDR(x) (((x) << 1) & GENMASK(2, 1))
77 -#define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1)
78 -#define SYS_PORT_MODE_INCL_XTR_HDR_X(x) (((x) & GENMASK(2, 1)) >> 1)
79 -#define SYS_PORT_MODE_INJ_HDR_ERR BIT(0)
80 -
81 -#define SYS_FRONT_PORT_MODE_RSZ 0x4
82 -
83 -#define SYS_FRONT_PORT_MODE_HDX_MODE BIT(0)
84 -
85 -#define SYS_FRM_AGING_AGE_TX_ENA BIT(20)
86 -#define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
87 -#define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
88 -
89 -#define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10))
90 -#define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
91 -#define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10)
92 -#define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0))
93 -#define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
94 -
95 -#define SYS_SW_STATUS_RSZ 0x4
96 -
97 -#define SYS_SW_STATUS_PORT_RX_PAUSED BIT(0)
98 -
99 -#define SYS_MISC_CFG_PTP_RSRV_CLR BIT(1)
100 -#define SYS_MISC_CFG_PTP_DIS_NEG_RO BIT(0)
101 -
102 -#define SYS_REW_MAC_HIGH_CFG_RSZ 0x4
103 -
104 -#define SYS_REW_MAC_LOW_CFG_RSZ 0x4
105 -
106 -#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))
107 -#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
108 -#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6)
109 -#define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x) ((x) & GENMASK(5, 0))
110 -#define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0)
111 -
112 -#define SYS_PAUSE_CFG_RSZ 0x4
113 -
114 -#define SYS_PAUSE_CFG_PAUSE_START(x) (((x) << 10) & GENMASK(18, 10))
115 -#define SYS_PAUSE_CFG_PAUSE_START_M GENMASK(18, 10)
116 -#define SYS_PAUSE_CFG_PAUSE_START_X(x) (((x) & GENMASK(18, 10)) >> 10)
117 -#define SYS_PAUSE_CFG_PAUSE_STOP(x) (((x) << 1) & GENMASK(9, 1))
118 -#define SYS_PAUSE_CFG_PAUSE_STOP_M GENMASK(9, 1)
119 -#define SYS_PAUSE_CFG_PAUSE_STOP_X(x) (((x) & GENMASK(9, 1)) >> 1)
120 -#define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
121 -
122 -#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x) (((x) << 9) & GENMASK(17, 9))
123 -#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9)
124 -#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x) (((x) & GENMASK(17, 9)) >> 9)
125 -#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x) ((x) & GENMASK(8, 0))
126 -#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0)
127 -
128 -#define SYS_ATOP_RSZ 0x4
129 -
130 -#define SYS_MAC_FC_CFG_RSZ 0x4
131 -
132 -#define SYS_MAC_FC_CFG_FC_LINK_SPEED(x) (((x) << 26) & GENMASK(27, 26))
133 -#define SYS_MAC_FC_CFG_FC_LINK_SPEED_M GENMASK(27, 26)
134 -#define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x) (((x) & GENMASK(27, 26)) >> 26)
135 -#define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x) (((x) << 20) & GENMASK(25, 20))
136 -#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M GENMASK(25, 20)
137 -#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x) (((x) & GENMASK(25, 20)) >> 20)
138 -#define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18)
139 -#define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17)
140 -#define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16)
141 -#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x) ((x) & GENMASK(15, 0))
142 -#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M GENMASK(15, 0)
143 -
144 -#define SYS_MMGT_RELCNT(x) (((x) << 16) & GENMASK(31, 16))
145 -#define SYS_MMGT_RELCNT_M GENMASK(31, 16)
146 -#define SYS_MMGT_RELCNT_X(x) (((x) & GENMASK(31, 16)) >> 16)
147 -#define SYS_MMGT_FREECNT(x) ((x) & GENMASK(15, 0))
148 -#define SYS_MMGT_FREECNT_M GENMASK(15, 0)
149 -
150 -#define SYS_MMGT_FAST_FREEVLD(x) (((x) << 4) & GENMASK(7, 4))
151 -#define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4)
152 -#define SYS_MMGT_FAST_FREEVLD_X(x) (((x) & GENMASK(7, 4)) >> 4)
153 -#define SYS_MMGT_FAST_RELVLD(x) ((x) & GENMASK(3, 0))
154 -#define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0)
155 -
156 -#define SYS_EVENTS_DIF_RSZ 0x4
157 -
158 -#define SYS_EVENTS_DIF_EV_DRX(x) (((x) << 6) & GENMASK(8, 6))
159 -#define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6)
160 -#define SYS_EVENTS_DIF_EV_DRX_X(x) (((x) & GENMASK(8, 6)) >> 6)
161 -#define SYS_EVENTS_DIF_EV_DTX(x) ((x) & GENMASK(5, 0))
162 -#define SYS_EVENTS_DIF_EV_DTX_M GENMASK(5, 0)
163 -
164 -#define SYS_EVENTS_CORE_EV_FWR BIT(2)
165 -#define SYS_EVENTS_CORE_EV_ANA(x) ((x) & GENMASK(1, 0))
166 -#define SYS_EVENTS_CORE_EV_ANA_M GENMASK(1, 0)
167 -
168 -#define SYS_CNT_GSZ 0x4
169 -
170 -#define SYS_PTP_STATUS_PTP_TXSTAMP_OAM BIT(29)
171 -#define SYS_PTP_STATUS_PTP_OVFL BIT(28)
172 -#define SYS_PTP_STATUS_PTP_MESS_VLD BIT(27)
173 -#define SYS_PTP_STATUS_PTP_MESS_ID(x) (((x) << 21) & GENMASK(26, 21))
174 -#define SYS_PTP_STATUS_PTP_MESS_ID_M GENMASK(26, 21)
175 -#define SYS_PTP_STATUS_PTP_MESS_ID_X(x) (((x) & GENMASK(26, 21)) >> 21)
176 -#define SYS_PTP_STATUS_PTP_MESS_TXPORT(x) (((x) << 16) & GENMASK(20, 16))
177 -#define SYS_PTP_STATUS_PTP_MESS_TXPORT_M GENMASK(20, 16)
178 -#define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x) (((x) & GENMASK(20, 16)) >> 16)
179 -#define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x) ((x) & GENMASK(15, 0))
180 -#define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M GENMASK(15, 0)
181 -
182 -#define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x) ((x) & GENMASK(29, 0))
183 -#define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M GENMASK(29, 0)
184 -#define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC BIT(31)
185 -
186 -#define SYS_PTP_NXT_PTP_NXT BIT(0)
187 -
188 -#define SYS_PTP_CFG_PTP_STAMP_WID(x) (((x) << 2) & GENMASK(7, 2))
189 -#define SYS_PTP_CFG_PTP_STAMP_WID_M GENMASK(7, 2)
190 -#define SYS_PTP_CFG_PTP_STAMP_WID_X(x) (((x) & GENMASK(7, 2)) >> 2)
191 -#define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x) ((x) & GENMASK(1, 0))
192 -#define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M GENMASK(1, 0)
193 -
194 -#define SYS_RAM_INIT_RAM_INIT BIT(1)
195 -#define SYS_RAM_INIT_RAM_CFG_HOOK BIT(0)
196 -
197 -#endif
198 --- /dev/null
199 +++ b/include/soc/mscc/ocelot_sys.h
200 @@ -0,0 +1,144 @@
201 +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
202 +/*
203 + * Microsemi Ocelot Switch driver
204 + *
205 + * Copyright (c) 2017 Microsemi Corporation
206 + */
207 +
208 +#ifndef _MSCC_OCELOT_SYS_H_
209 +#define _MSCC_OCELOT_SYS_H_
210 +
211 +#define SYS_COUNT_RX_OCTETS_RSZ 0x4
212 +
213 +#define SYS_COUNT_TX_OCTETS_RSZ 0x4
214 +
215 +#define SYS_PORT_MODE_RSZ 0x4
216 +
217 +#define SYS_PORT_MODE_DATA_WO_TS(x) (((x) << 5) & GENMASK(6, 5))
218 +#define SYS_PORT_MODE_DATA_WO_TS_M GENMASK(6, 5)
219 +#define SYS_PORT_MODE_DATA_WO_TS_X(x) (((x) & GENMASK(6, 5)) >> 5)
220 +#define SYS_PORT_MODE_INCL_INJ_HDR(x) (((x) << 3) & GENMASK(4, 3))
221 +#define SYS_PORT_MODE_INCL_INJ_HDR_M GENMASK(4, 3)
222 +#define SYS_PORT_MODE_INCL_INJ_HDR_X(x) (((x) & GENMASK(4, 3)) >> 3)
223 +#define SYS_PORT_MODE_INCL_XTR_HDR(x) (((x) << 1) & GENMASK(2, 1))
224 +#define SYS_PORT_MODE_INCL_XTR_HDR_M GENMASK(2, 1)
225 +#define SYS_PORT_MODE_INCL_XTR_HDR_X(x) (((x) & GENMASK(2, 1)) >> 1)
226 +#define SYS_PORT_MODE_INJ_HDR_ERR BIT(0)
227 +
228 +#define SYS_FRONT_PORT_MODE_RSZ 0x4
229 +
230 +#define SYS_FRONT_PORT_MODE_HDX_MODE BIT(0)
231 +
232 +#define SYS_FRM_AGING_AGE_TX_ENA BIT(20)
233 +#define SYS_FRM_AGING_MAX_AGE(x) ((x) & GENMASK(19, 0))
234 +#define SYS_FRM_AGING_MAX_AGE_M GENMASK(19, 0)
235 +
236 +#define SYS_STAT_CFG_STAT_CLEAR_SHOT(x) (((x) << 10) & GENMASK(16, 10))
237 +#define SYS_STAT_CFG_STAT_CLEAR_SHOT_M GENMASK(16, 10)
238 +#define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x) (((x) & GENMASK(16, 10)) >> 10)
239 +#define SYS_STAT_CFG_STAT_VIEW(x) ((x) & GENMASK(9, 0))
240 +#define SYS_STAT_CFG_STAT_VIEW_M GENMASK(9, 0)
241 +
242 +#define SYS_SW_STATUS_RSZ 0x4
243 +
244 +#define SYS_SW_STATUS_PORT_RX_PAUSED BIT(0)
245 +
246 +#define SYS_MISC_CFG_PTP_RSRV_CLR BIT(1)
247 +#define SYS_MISC_CFG_PTP_DIS_NEG_RO BIT(0)
248 +
249 +#define SYS_REW_MAC_HIGH_CFG_RSZ 0x4
250 +
251 +#define SYS_REW_MAC_LOW_CFG_RSZ 0x4
252 +
253 +#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x) (((x) << 6) & GENMASK(21, 6))
254 +#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M GENMASK(21, 6)
255 +#define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x) (((x) & GENMASK(21, 6)) >> 6)
256 +#define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x) ((x) & GENMASK(5, 0))
257 +#define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M GENMASK(5, 0)
258 +
259 +#define SYS_PAUSE_CFG_RSZ 0x4
260 +
261 +#define SYS_PAUSE_CFG_PAUSE_START(x) (((x) << 10) & GENMASK(18, 10))
262 +#define SYS_PAUSE_CFG_PAUSE_START_M GENMASK(18, 10)
263 +#define SYS_PAUSE_CFG_PAUSE_START_X(x) (((x) & GENMASK(18, 10)) >> 10)
264 +#define SYS_PAUSE_CFG_PAUSE_STOP(x) (((x) << 1) & GENMASK(9, 1))
265 +#define SYS_PAUSE_CFG_PAUSE_STOP_M GENMASK(9, 1)
266 +#define SYS_PAUSE_CFG_PAUSE_STOP_X(x) (((x) & GENMASK(9, 1)) >> 1)
267 +#define SYS_PAUSE_CFG_PAUSE_ENA BIT(0)
268 +
269 +#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x) (((x) << 9) & GENMASK(17, 9))
270 +#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M GENMASK(17, 9)
271 +#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x) (((x) & GENMASK(17, 9)) >> 9)
272 +#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x) ((x) & GENMASK(8, 0))
273 +#define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M GENMASK(8, 0)
274 +
275 +#define SYS_ATOP_RSZ 0x4
276 +
277 +#define SYS_MAC_FC_CFG_RSZ 0x4
278 +
279 +#define SYS_MAC_FC_CFG_FC_LINK_SPEED(x) (((x) << 26) & GENMASK(27, 26))
280 +#define SYS_MAC_FC_CFG_FC_LINK_SPEED_M GENMASK(27, 26)
281 +#define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x) (((x) & GENMASK(27, 26)) >> 26)
282 +#define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x) (((x) << 20) & GENMASK(25, 20))
283 +#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M GENMASK(25, 20)
284 +#define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x) (((x) & GENMASK(25, 20)) >> 20)
285 +#define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18)
286 +#define SYS_MAC_FC_CFG_TX_FC_ENA BIT(17)
287 +#define SYS_MAC_FC_CFG_RX_FC_ENA BIT(16)
288 +#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x) ((x) & GENMASK(15, 0))
289 +#define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M GENMASK(15, 0)
290 +
291 +#define SYS_MMGT_RELCNT(x) (((x) << 16) & GENMASK(31, 16))
292 +#define SYS_MMGT_RELCNT_M GENMASK(31, 16)
293 +#define SYS_MMGT_RELCNT_X(x) (((x) & GENMASK(31, 16)) >> 16)
294 +#define SYS_MMGT_FREECNT(x) ((x) & GENMASK(15, 0))
295 +#define SYS_MMGT_FREECNT_M GENMASK(15, 0)
296 +
297 +#define SYS_MMGT_FAST_FREEVLD(x) (((x) << 4) & GENMASK(7, 4))
298 +#define SYS_MMGT_FAST_FREEVLD_M GENMASK(7, 4)
299 +#define SYS_MMGT_FAST_FREEVLD_X(x) (((x) & GENMASK(7, 4)) >> 4)
300 +#define SYS_MMGT_FAST_RELVLD(x) ((x) & GENMASK(3, 0))
301 +#define SYS_MMGT_FAST_RELVLD_M GENMASK(3, 0)
302 +
303 +#define SYS_EVENTS_DIF_RSZ 0x4
304 +
305 +#define SYS_EVENTS_DIF_EV_DRX(x) (((x) << 6) & GENMASK(8, 6))
306 +#define SYS_EVENTS_DIF_EV_DRX_M GENMASK(8, 6)
307 +#define SYS_EVENTS_DIF_EV_DRX_X(x) (((x) & GENMASK(8, 6)) >> 6)
308 +#define SYS_EVENTS_DIF_EV_DTX(x) ((x) & GENMASK(5, 0))
309 +#define SYS_EVENTS_DIF_EV_DTX_M GENMASK(5, 0)
310 +
311 +#define SYS_EVENTS_CORE_EV_FWR BIT(2)
312 +#define SYS_EVENTS_CORE_EV_ANA(x) ((x) & GENMASK(1, 0))
313 +#define SYS_EVENTS_CORE_EV_ANA_M GENMASK(1, 0)
314 +
315 +#define SYS_CNT_GSZ 0x4
316 +
317 +#define SYS_PTP_STATUS_PTP_TXSTAMP_OAM BIT(29)
318 +#define SYS_PTP_STATUS_PTP_OVFL BIT(28)
319 +#define SYS_PTP_STATUS_PTP_MESS_VLD BIT(27)
320 +#define SYS_PTP_STATUS_PTP_MESS_ID(x) (((x) << 21) & GENMASK(26, 21))
321 +#define SYS_PTP_STATUS_PTP_MESS_ID_M GENMASK(26, 21)
322 +#define SYS_PTP_STATUS_PTP_MESS_ID_X(x) (((x) & GENMASK(26, 21)) >> 21)
323 +#define SYS_PTP_STATUS_PTP_MESS_TXPORT(x) (((x) << 16) & GENMASK(20, 16))
324 +#define SYS_PTP_STATUS_PTP_MESS_TXPORT_M GENMASK(20, 16)
325 +#define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x) (((x) & GENMASK(20, 16)) >> 16)
326 +#define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x) ((x) & GENMASK(15, 0))
327 +#define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M GENMASK(15, 0)
328 +
329 +#define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x) ((x) & GENMASK(29, 0))
330 +#define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M GENMASK(29, 0)
331 +#define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC BIT(31)
332 +
333 +#define SYS_PTP_NXT_PTP_NXT BIT(0)
334 +
335 +#define SYS_PTP_CFG_PTP_STAMP_WID(x) (((x) << 2) & GENMASK(7, 2))
336 +#define SYS_PTP_CFG_PTP_STAMP_WID_M GENMASK(7, 2)
337 +#define SYS_PTP_CFG_PTP_STAMP_WID_X(x) (((x) & GENMASK(7, 2)) >> 2)
338 +#define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x) ((x) & GENMASK(1, 0))
339 +#define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M GENMASK(1, 0)
340 +
341 +#define SYS_RAM_INIT_RAM_INIT BIT(1)
342 +#define SYS_RAM_INIT_RAM_CFG_HOOK BIT(0)
343 +
344 +#endif
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