target/linux/mcs814x/files-3.18/arch/arm/mach-mcs814x/irq.c

   1 /*
   2  * Moschip MCS814x generic interrupt controller routines
   3  *
   4  * Copyright (C) 2012, Florian Fainelli <florian@openwrt.org>
   5  *
   6  * Licensed under the GPLv2
   7  */
   8 #include <linux/init.h>
   9 #include <linux/irq.h>
  10 #include <linux/io.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <linux/irqdomain.h>
  14
  15 #include <asm/exception.h>
  16 #include <asm/mach/irq.h>
  17 #include <mach/mcs814x.h>
  18
  19 static void __iomem *mcs814x_intc_base;
  20
  21 static void __init mcs814x_alloc_gc(void __iomem *base, unsigned int irq_start,
  22                                         unsigned int num)
  23 {
  24         struct irq_chip_generic *gc;
  25         struct irq_chip_type *ct;
  26
  27         gc = irq_alloc_generic_chip("mcs814x-intc", 1,
  28                         irq_start, base, handle_level_irq);
  29         if (!gc)
  30                 panic("unable to allocate generic irq chip");
  31
  32         ct = gc->chip_types;
  33         ct->chip.irq_ack = irq_gc_unmask_enable_reg;
  34         ct->chip.irq_mask = irq_gc_mask_clr_bit;
  35         ct->chip.irq_unmask = irq_gc_mask_set_bit;
  36         ct->regs.mask = MCS814X_IRQ_MASK;
  37         ct->regs.enable = MCS814X_IRQ_ICR;
  38
  39         irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
  40                 IRQ_NOREQUEST, 0);
  41
  42         /* Clear all interrupts */
  43         writel_relaxed(0xffffffff, base + MCS814X_IRQ_ICR);
  44 }
  45
  46 asmlinkage void __exception_irq_entry mcs814x_handle_irq(struct pt_regs *regs)
  47 {
  48         u32 status, irq;
  49
  50         do {
  51                 /* read the status register */
  52                 status = __raw_readl(mcs814x_intc_base + MCS814X_IRQ_STS0);
  53                 if (!status)
  54                         break;
  55
  56                 irq = ffs(status) - 1;
  57                 status |= (1 << irq);
  58                 /* clear the interrupt */
  59                 __raw_writel(status, mcs814x_intc_base + MCS814X_IRQ_STS0);
  60                 /* call the generic handler */
  61                 handle_IRQ(irq, regs);
  62
  63         } while (1);
  64 }
  65
  66 static const struct of_device_id mcs814x_intc_ids[] = {
  67         { .compatible = "moschip,mcs814x-intc" },
  68         { /* sentinel */ },
  69 };
  70
  71 void __init mcs814x_of_irq_init(void)
  72 {
  73         struct device_node *np;
  74
  75         np = of_find_matching_node(NULL, mcs814x_intc_ids);
  76         if (!np)
  77                 panic("unable to find compatible intc node in dtb\n");
  78
  79         mcs814x_intc_base = of_iomap(np, 0);
  80         if (!mcs814x_intc_base)
  81                 panic("unable to map intc cpu registers\n");
  82
  83         irq_domain_add_simple(np, 32, 0, &irq_generic_chip_ops, NULL);
  84
  85         of_node_put(np);
  86
  87         mcs814x_alloc_gc(mcs814x_intc_base, 0, 32);
  88 }
  89