target/linux/mediatek/dts/mt7986a-asus-tuf-ax4200.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7986a.dtsi"
   9
  10 / {
  11         model = "ASUS TUF-AX4200";
  12         compatible = "asus,tuf-ax4200", "mediatek,mt7986a";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 led-boot = &led_system;
  17                 led-failsafe = &led_system;
  18                 led-running = &led_system;
  19                 led-upgrade = &led_system;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24                 bootargs-override = "ubi.mtd=UBI_DEV";
  25         };
  26
  27         memory {
  28                 reg = <0 0x40000000 0 0x20000000>;
  29         };
  30
  31         keys {
  32                 compatible = "gpio-keys";
  33
  34                 reset {
  35                         label = "reset";
  36                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  37                         linux,code = <KEY_RESTART>;
  38                 };
  39
  40                 mesh {
  41                         label = "wps";
  42                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  43                         linux,code = <KEY_WPS_BUTTON>;
  44                 };
  45         };
  46
  47         leds {
  48                 compatible = "gpio-leds";
  49
  50                 wlan24 {
  51                         label = "white:wlan24";
  52                         gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
  53                         linux,default-trigger = "phy0tpt";
  54                 };
  55
  56                 wlan5 {
  57                         label = "white:wlan5";
  58                         gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
  59                         linux,default-trigger = "phy1tpt";
  60                 };
  61
  62                 led_system: system {
  63                         label = "white:system";
  64                         gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
  65                 };
  66
  67                 wan-red {
  68                         label = "red:wan";
  69                         gpios = <&pio 12 GPIO_ACTIVE_LOW>;
  70                 };
  71         };
  72
  73         reg_3p3v: regulator-3p3v {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "fixed-3.3V";
  76                 regulator-min-microvolt = <3300000>;
  77                 regulator-max-microvolt = <3300000>;
  78                 regulator-boot-on;
  79                 regulator-always-on;
  80         };
  81
  82         reg_5v: regulator-5v {
  83                 compatible = "regulator-fixed";
  84                 regulator-name = "fixed-5V";
  85                 regulator-min-microvolt = <5000000>;
  86                 regulator-max-microvolt = <5000000>;
  87                 regulator-boot-on;
  88                 regulator-always-on;
  89         };
  90 };
  91
  92 &eth {
  93         status = "okay";
  94
  95         gmac0: mac@0 {
  96                 /* LAN */
  97                 compatible = "mediatek,eth-mac";
  98                 reg = <0>;
  99                 phy-mode = "2500base-x";
 100
 101                 fixed-link {
 102                         speed = <2500>;
 103                         full-duplex;
 104                         pause;
 105                 };
 106         };
 107
 108         gmac1: mac@1 {
 109                 /* WAN */
 110                 compatible = "mediatek,eth-mac";
 111                 reg = <1>;
 112                 phy-mode = "2500base-x";
 113                 phy-handle = <&phy6>;
 114         };
 115
 116         mdio: mdio-bus {
 117                 #address-cells = <1>;
 118                 #size-cells = <0>;
 119         };
 120 };
 121
 122 &mdio {
 123         phy6: phy@6 {
 124                 compatible = "ethernet-phy-ieee802.3-c45";
 125                 reg = <6>;
 126
 127                 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 128                 reset-assert-us = <10000>;
 129                 reset-deassert-us = <10000>;
 130
 131                 /* LED0: CONN (WAN white) */
 132                 mxl,led-config = <0x00f0 0x0 0x0 0x0>;
 133         };
 134
 135         switch: switch@0 {
 136                 compatible = "mediatek,mt7531";
 137                 reg = <31>;
 138
 139                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
 140                 reset-assert-us = <10000>;
 141                 reset-deassert-us = <10000>;
 142         };
 143 };
 144
 145 &pio {
 146         spi_flash_pins: spi-flash-pins-33-to-38 {
 147                 mux {
 148                         function = "spi";
 149                         groups = "spi0", "spi0_wp_hold";
 150                 };
 151                 conf-pu {
 152                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 153                         drive-strength = <8>;
 154                         mediatek,pull-up-adv = <0>; /* bias-disable */
 155                 };
 156                 conf-pd {
 157                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 158                         drive-strength = <8>;
 159                         mediatek,pull-down-adv = <0>; /* bias-disable */
 160                 };
 161         };
 162
 163         wf_2g_5g_pins: wf_2g_5g-pins {
 164                 mux {
 165                         function = "wifi";
 166                         groups = "wf_2g", "wf_5g";
 167                 };
 168                 conf {
 169                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 170                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 171                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 172                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 173                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 174                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 175                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 176                         drive-strength = <4>;
 177                 };
 178         };
 179
 180         wf_dbdc_pins: wf-dbdc-pins {
 181                 mux {
 182                         function = "wifi";
 183                         groups = "wf_dbdc";
 184                 };
 185                 conf {
 186                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 187                                 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 188                                 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 189                                 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 190                                 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 191                                 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 192                                 "WF1_TOP_CLK", "WF1_TOP_DATA";
 193                         drive-strength = <4>;
 194                 };
 195         };
 196 };
 197
 198 &spi0 {
 199         pinctrl-names = "default";
 200         pinctrl-0 = <&spi_flash_pins>;
 201         status = "okay";
 202
 203         spi_nand_flash: flash@0 {
 204                 compatible = "spi-nand";
 205                 #address-cells = <1>;
 206                 #size-cells = <1>;
 207                 reg = <0>;
 208
 209                 spi-max-frequency = <20000000>;
 210                 spi-tx-buswidth = <4>;
 211                 spi-rx-buswidth = <4>;
 212
 213                 partitions: partitions {
 214                         compatible = "fixed-partitions";
 215                         #address-cells = <1>;
 216                         #size-cells = <1>;
 217
 218                         partition@0 {
 219                                 label = "bootloader";
 220                                 reg = <0x0 0x400000>;
 221                                 read-only;
 222                         };
 223
 224                         partition@400000 {
 225                                 label = "UBI_DEV";
 226                                 reg = <0x400000 0xfc00000>;
 227                         };
 228                 };
 229         };
 230 };
 231
 232 &switch {
 233         ports {
 234                 #address-cells = <1>;
 235                 #size-cells = <0>;
 236
 237                 port@1 {
 238                         reg = <1>;
 239                         label = "lan1";
 240                 };
 241
 242                 port@2 {
 243                         reg = <2>;
 244                         label = "lan2";
 245                 };
 246
 247                 port@3 {
 248                         reg = <3>;
 249                         label = "lan3";
 250                 };
 251
 252                 port@4 {
 253                         reg = <4>;
 254                         label = "lan4";
 255                 };
 256
 257                 port@6 {
 258                         reg = <6>;
 259                         label = "cpu";
 260                         ethernet = <&gmac0>;
 261                         phy-mode = "2500base-x";
 262
 263                         fixed-link {
 264                                 speed = <2500>;
 265                                 full-duplex;
 266                                 pause;
 267                         };
 268                 };
 269         };
 270
 271         mdio {
 272                 #address-cells = <1>;
 273                 #size-cells = <0>;
 274
 275                 phy@1 {
 276                         reg = <1>;
 277
 278                         mediatek,led-config = <
 279                                 0x21 0x8009 /* BASIC_CTRL */
 280                                 0x22 0x0c00 /* ON_DURATION */
 281                                 0x23 0x1400 /* BLINK_DURATION */
 282                                 0x24 0x8000 /* LED0_ON_CTRL */
 283                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 284                                 0x26 0xc007 /* LED1_ON_CTRL */
 285                                 0x27 0x003f /* LED1_BLINK_CTRL */
 286                         >;
 287                 };
 288
 289                 phy@2 {
 290                         reg = <2>;
 291
 292                         mediatek,led-config = <
 293                                 0x21 0x8009 /* BASIC_CTRL */
 294                                 0x22 0x0c00 /* ON_DURATION */
 295                                 0x23 0x1400 /* BLINK_DURATION */
 296                                 0x24 0x8000 /* LED0_ON_CTRL */
 297                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 298                                 0x26 0xc007 /* LED1_ON_CTRL */
 299                                 0x27 0x003f /* LED1_BLINK_CTRL */
 300                         >;
 301                 };
 302
 303                 phy@3 {
 304                         reg = <3>;
 305
 306                         mediatek,led-config = <
 307                                 0x21 0x8009 /* BASIC_CTRL */
 308                                 0x22 0x0c00 /* ON_DURATION */
 309                                 0x23 0x1400 /* BLINK_DURATION */
 310                                 0x24 0x8000 /* LED0_ON_CTRL */
 311                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 312                                 0x26 0xc007 /* LED1_ON_CTRL */
 313                                 0x27 0x003f /* LED1_BLINK_CTRL */
 314                         >;
 315                 };
 316
 317                 phy@4 {
 318                         reg = <4>;
 319
 320                         mediatek,led-config = <
 321                                 0x21 0x8009 /* BASIC_CTRL */
 322                                 0x22 0x0c00 /* ON_DURATION */
 323                                 0x23 0x1400 /* BLINK_DURATION */
 324                                 0x24 0x8000 /* LED0_ON_CTRL */
 325                                 0x25 0x0000 /* LED0_BLINK_CTRL */
 326                                 0x26 0xc007 /* LED1_ON_CTRL */
 327                                 0x27 0x003f /* LED1_BLINK_CTRL */
 328                         >;
 329                 };
 330         };
 331 };
 332
 333 &wmac {
 334         status = "okay";
 335         pinctrl-names = "default", "dbdc";
 336         pinctrl-0 = <&wf_2g_5g_pins>;
 337         pinctrl-1 = <&wf_dbdc_pins>;
 338 };
 339
 340 &uart0 {
 341         status = "okay";
 342 };
 343
 344 &ssusb {
 345         vusb33-supply = <&reg_3p3v>;
 346         vbus-supply = <&reg_5v>;
 347         status = "okay";
 348 };
 349
 350 &usb_phy {
 351         status = "okay";
 352 };